From 4096fa397b195a6ef82e48a74deaa8dd026d8a41 Mon Sep 17 00:00:00 2001
From: Damien George <damien.p.george@gmail.com>
Date: Tue, 16 Jul 2019 14:46:31 +1000
Subject: [PATCH] stm32/powerctrlboot: Increase SYSCLK to 32MHz for L0 MCUs.
---
ports/stm32/powerctrlboot.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/ports/stm32/powerctrlboot.c b/ports/stm32/powerctrlboot.c
index e320cc4db..de7c9d88a 100644
--- a/ports/stm32/powerctrlboot.c
+++ b/ports/stm32/powerctrlboot.c
@@ -82,11 +82,21 @@ void SystemClock_Config(void) {
// Enable power control peripheral
__HAL_RCC_PWR_CLK_ENABLE();
- // Use the 16MHz internal oscillator
+ // Set flash latency to 1 because SYSCLK > 16MHz
+ FLASH->ACR |= FLASH_ACR_LATENCY;
+
+ // Enable the 16MHz internal oscillator
RCC->CR |= RCC_CR_HSION;
while (!(RCC->CR & RCC_CR_HSIRDY)) {
}
- const uint32_t sysclk_src = 1;
+
+ // Use HSI16 and the PLL to get a 32MHz SYSCLK
+ RCC->CFGR = 1 << RCC_CFGR_PLLDIV_Pos | 1 << RCC_CFGR_PLLMUL_Pos;
+ RCC->CR |= RCC_CR_PLLON;
+ while (!(RCC->CR & RCC_CR_PLLRDY)) {
+ // Wait for PLL to lock
+ }
+ const uint32_t sysclk_src = 3;
// Select SYSCLK source
RCC->CFGR |= sysclk_src << RCC_CFGR_SW_Pos;
--
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