![]() |
MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
|
Instruction Cache 0 Protection Register. More...
Macros | |
#define | MXC_F_RPU_ICACHE0_DMA0ACN_POS 0 |
ICACHE0_DMA0ACN Position. | |
#define | MXC_F_RPU_ICACHE0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_DMA0ACN_POS)) |
ICACHE0_DMA0ACN Mask. | |
#define | MXC_F_RPU_ICACHE0_DMA1ACN_POS 1 |
ICACHE0_DMA1ACN Position. | |
#define | MXC_F_RPU_ICACHE0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_DMA1ACN_POS)) |
ICACHE0_DMA1ACN Mask. | |
#define | MXC_F_RPU_ICACHE0_USBACN_POS 2 |
ICACHE0_USBACN Position. | |
#define | MXC_F_RPU_ICACHE0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_USBACN_POS)) |
ICACHE0_USBACN Mask. | |
#define | MXC_F_RPU_ICACHE0_SYS0ACN_POS 3 |
ICACHE0_SYS0ACN Position. | |
#define | MXC_F_RPU_ICACHE0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SYS0ACN_POS)) |
ICACHE0_SYS0ACN Mask. | |
#define | MXC_F_RPU_ICACHE0_SYS1ACN_POS 4 |
ICACHE0_SYS1ACN Position. | |
#define | MXC_F_RPU_ICACHE0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SYS1ACN_POS)) |
ICACHE0_SYS1ACN Mask. | |
#define | MXC_F_RPU_ICACHE0_SDMADACN_POS 5 |
ICACHE0_SDMADACN Position. | |
#define | MXC_F_RPU_ICACHE0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SDMADACN_POS)) |
ICACHE0_SDMADACN Mask. | |
#define | MXC_F_RPU_ICACHE0_SDMAIACN_POS 6 |
ICACHE0_SDMAIACN Position. | |
#define | MXC_F_RPU_ICACHE0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SDMAIACN_POS)) |
ICACHE0_SDMAIACN Mask. | |
#define | MXC_F_RPU_ICACHE0_CRYPTOACN_POS 7 |
ICACHE0_CRYPTOACN Position. | |
#define | MXC_F_RPU_ICACHE0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_CRYPTOACN_POS)) |
ICACHE0_CRYPTOACN Mask. | |
#define | MXC_F_RPU_ICACHE0_SDIOACN_POS 8 |
ICACHE0_SDIOACN Position. | |
#define | MXC_F_RPU_ICACHE0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SDIOACN_POS)) |
ICACHE0_SDIOACN Mask. | |