![]() |
MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
|
SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address. More...
Macros | |
#define | MXC_R_SDHC_SDMA ((uint32_t)0x00000000UL) |
Offset from SDHC Base Address: 0x0000 | |
#define | MXC_R_SDHC_BLK_SIZE ((uint32_t)0x00000004UL) |
Offset from SDHC Base Address: 0x0004 | |
#define | MXC_R_SDHC_BLK_CNT ((uint32_t)0x00000006UL) |
Offset from SDHC Base Address: 0x0006 | |
#define | MXC_R_SDHC_ARG_1 ((uint32_t)0x00000008UL) |
Offset from SDHC Base Address: 0x0008 | |
#define | MXC_R_SDHC_TRANS ((uint32_t)0x0000000CUL) |
Offset from SDHC Base Address: 0x000C | |
#define | MXC_R_SDHC_CMD ((uint32_t)0x0000000EUL) |
Offset from SDHC Base Address: 0x000E | |
#define | MXC_R_SDHC_RESP ((uint32_t)0x00000010UL) |
Offset from SDHC Base Address: 0x0010 | |
#define | MXC_R_SDHC_BUFFER ((uint32_t)0x00000020UL) |
Offset from SDHC Base Address: 0x0020 | |
#define | MXC_R_SDHC_PRESENT ((uint32_t)0x00000024UL) |
Offset from SDHC Base Address: 0x0024 | |
#define | MXC_R_SDHC_HOST_CN_1 ((uint32_t)0x00000028UL) |
Offset from SDHC Base Address: 0x0028 | |
#define | MXC_R_SDHC_PWR ((uint32_t)0x00000029UL) |
Offset from SDHC Base Address: 0x0029 | |
#define | MXC_R_SDHC_BLK_GAP ((uint32_t)0x0000002AUL) |
Offset from SDHC Base Address: 0x002A | |
#define | MXC_R_SDHC_WAKEUP ((uint32_t)0x0000002BUL) |
Offset from SDHC Base Address: 0x002B | |
#define | MXC_R_SDHC_CLK_CN ((uint32_t)0x0000002CUL) |
Offset from SDHC Base Address: 0x002C | |
#define | MXC_R_SDHC_TO ((uint32_t)0x0000002EUL) |
Offset from SDHC Base Address: 0x002E | |
#define | MXC_R_SDHC_SW_RESET ((uint32_t)0x0000002FUL) |
Offset from SDHC Base Address: 0x002F | |
#define | MXC_R_SDHC_INT_STAT ((uint32_t)0x00000030UL) |
Offset from SDHC Base Address: 0x0030 | |
#define | MXC_R_SDHC_ER_INT_STAT ((uint32_t)0x00000032UL) |
Offset from SDHC Base Address: 0x0032 | |
#define | MXC_R_SDHC_INT_EN ((uint32_t)0x00000034UL) |
Offset from SDHC Base Address: 0x0034 | |
#define | MXC_R_SDHC_ER_INT_EN ((uint32_t)0x00000036UL) |
Offset from SDHC Base Address: 0x0036 | |
#define | MXC_R_SDHC_INT_SIGNAL ((uint32_t)0x00000038UL) |
Offset from SDHC Base Address: 0x0038 | |
#define | MXC_R_SDHC_ER_INT_SIGNAL ((uint32_t)0x0000003AUL) |
Offset from SDHC Base Address: 0x003A | |
#define | MXC_R_SDHC_AUTO_CMD_ER ((uint32_t)0x0000003CUL) |
Offset from SDHC Base Address: 0x003C | |
#define | MXC_R_SDHC_HOST_CN_2 ((uint32_t)0x0000003EUL) |
Offset from SDHC Base Address: 0x003E | |
#define | MXC_R_SDHC_CFG_0 ((uint32_t)0x00000040UL) |
Offset from SDHC Base Address: 0x0040 | |
#define | MXC_R_SDHC_CFG_1 ((uint32_t)0x00000044UL) |
Offset from SDHC Base Address: 0x0044 | |
#define | MXC_R_SDHC_MAX_CURR_CFG ((uint32_t)0x00000048UL) |
Offset from SDHC Base Address: 0x0048 | |
#define | MXC_R_SDHC_FORCE_CMD ((uint32_t)0x00000050UL) |
Offset from SDHC Base Address: 0x0050 | |
#define | MXC_R_SDHC_FORCE_EVENT_INT_STAT ((uint32_t)0x00000052UL) |
Offset from SDHC Base Address: 0x0052 | |
#define | MXC_R_SDHC_ADMA_ER ((uint32_t)0x00000054UL) |
Offset from SDHC Base Address: 0x0054 | |
#define | MXC_R_SDHC_ADMA_ADDR_0 ((uint32_t)0x00000058UL) |
Offset from SDHC Base Address: 0x0058 | |
#define | MXC_R_SDHC_ADMA_ADDR_1 ((uint32_t)0x0000005CUL) |
Offset from SDHC Base Address: 0x005C | |
#define | MXC_R_SDHC_PRESET_0 ((uint32_t)0x00000060UL) |
Offset from SDHC Base Address: 0x0060 | |
#define | MXC_R_SDHC_PRESET_1 ((uint32_t)0x00000062UL) |
Offset from SDHC Base Address: 0x0062 | |
#define | MXC_R_SDHC_PRESET_2 ((uint32_t)0x00000064UL) |
Offset from SDHC Base Address: 0x0064 | |
#define | MXC_R_SDHC_PRESET_3 ((uint32_t)0x00000066UL) |
Offset from SDHC Base Address: 0x0066 | |
#define | MXC_R_SDHC_PRESET_4 ((uint32_t)0x00000068UL) |
Offset from SDHC Base Address: 0x0068 | |
#define | MXC_R_SDHC_PRESET_5 ((uint32_t)0x0000006AUL) |
Offset from SDHC Base Address: 0x006A | |
#define | MXC_R_SDHC_PRESET_6 ((uint32_t)0x0000006CUL) |
Offset from SDHC Base Address: 0x006C | |
#define | MXC_R_SDHC_PRESET_7 ((uint32_t)0x0000006EUL) |
Offset from SDHC Base Address: 0x006E | |
#define | MXC_R_SDHC_SHARED_BUS ((uint32_t)0x000000E0UL) |
Offset from SDHC Base Address: 0x00E0 | |
#define | MXC_R_SDHC_SLOT_INT ((uint32_t)0x000000FCUL) |
Offset from SDHC Base Address: 0x00FC | |
#define | MXC_R_SDHC_HOST_CN_VER ((uint32_t)0x000000FEUL) |
Offset from SDHC Base Address: 0x00FE | |