50 #if defined (__ICCARM__) 51 #pragma system_include 54 #if defined (__CC_ARM) 65 #define __I volatile const 71 #define __R volatile const 106 __R uint32_t rsv_0x44;
118 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) 119 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) 120 #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) 121 #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) 122 #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) 123 #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) 124 #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) 125 #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) 126 #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) 127 #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) 128 #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) 129 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) 130 #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) 131 #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) 132 #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) 133 #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) 134 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) 135 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) 136 #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x0000004CUL) 145 #define MXC_F_I2C_CTRL_I2C_EN_POS 0 146 #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) 148 #define MXC_F_I2C_CTRL_MST_POS 1 149 #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) 151 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 152 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) 154 #define MXC_F_I2C_CTRL_RX_MODE_POS 3 155 #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) 157 #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 158 #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) 160 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 161 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) 163 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 164 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) 166 #define MXC_F_I2C_CTRL_SCL_POS 8 167 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) 169 #define MXC_F_I2C_CTRL_SDA_POS 9 170 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) 172 #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 173 #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) 175 #define MXC_F_I2C_CTRL_READ_POS 11 176 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) 178 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 179 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) 181 #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 182 #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) 184 #define MXC_F_I2C_CTRL_HS_MODE_POS 15 185 #define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) 195 #define MXC_F_I2C_STATUS_BUS_POS 0 196 #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) 198 #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 199 #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) 201 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 202 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) 204 #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 205 #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) 207 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 208 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) 210 #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 211 #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) 213 #define MXC_F_I2C_STATUS_STATUS_POS 8 214 #define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) 215 #define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) 216 #define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) 217 #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) 218 #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) 219 #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) 220 #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) 221 #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) 222 #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) 223 #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) 224 #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) 225 #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) 226 #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) 227 #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) 228 #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) 229 #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) 230 #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) 231 #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) 232 #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) 233 #define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) 234 #define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) 235 #define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) 236 #define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) 237 #define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) 238 #define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) 239 #define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) 240 #define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) 241 #define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) 242 #define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) 243 #define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) 244 #define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) 254 #define MXC_F_I2C_INT_FL0_DONE_POS 0 255 #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) 257 #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 258 #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) 260 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 261 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) 263 #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 264 #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) 266 #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 267 #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) 269 #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 270 #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) 272 #define MXC_F_I2C_INT_FL0_STOP_POS 6 273 #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) 275 #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 276 #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) 278 #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 279 #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) 281 #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 282 #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) 284 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 285 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) 287 #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 288 #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) 290 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 291 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) 293 #define MXC_F_I2C_INT_FL0_START_ER_POS 13 294 #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) 296 #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 297 #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) 299 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 300 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) 310 #define MXC_F_I2C_INT_EN0_DONE_POS 0 311 #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) 313 #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 314 #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) 316 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 317 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) 319 #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 320 #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) 322 #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 323 #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) 325 #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 326 #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) 328 #define MXC_F_I2C_INT_EN0_STOP_POS 6 329 #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) 331 #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 332 #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) 334 #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 335 #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) 337 #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 338 #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) 340 #define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 341 #define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) 343 #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 344 #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) 346 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 347 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) 349 #define MXC_F_I2C_INT_EN0_START_ER_POS 13 350 #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) 352 #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 353 #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) 355 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 356 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) 366 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 367 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) 369 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 370 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) 380 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 381 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) 383 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 384 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) 394 #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 395 #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) 397 #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 398 #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) 408 #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 409 #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) 411 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 412 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) 414 #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 415 #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) 425 #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 426 #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) 428 #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 429 #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) 439 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 440 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) 442 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 443 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) 445 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 446 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) 448 #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 449 #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) 459 #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 460 #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) 462 #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 463 #define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) 465 #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 466 #define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) 476 #define MXC_F_I2C_FIFO_DATA_POS 0 477 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) 487 #define MXC_F_I2C_MASTER_CTRL_START_POS 0 488 #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) 490 #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 491 #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) 493 #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 494 #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) 496 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 497 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) 499 #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 500 #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) 502 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 503 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) 513 #define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 514 #define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) 524 #define MXC_F_I2C_CLK_HI_CKH_POS 0 525 #define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) 535 #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 536 #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) 538 #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 539 #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) 549 #define MXC_F_I2C_TIMEOUT_TO_POS 0 550 #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) 560 #define MXC_F_I2C_DMA_TX_EN_POS 0 561 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) 563 #define MXC_F_I2C_DMA_RX_EN_POS 1 564 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) 574 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 575 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) 577 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 578 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) 580 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 581 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) 583 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 584 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) __IO uint32_t int_en0
0x0C: I2C INT_EN0 Register
Definition: i2c_regs.h:92
__IO uint32_t master_ctrl
0x30: I2C MASTER_CTRL Register
Definition: i2c_regs.h:101
__IO uint32_t hs_clk
0x3C: I2C HS_CLK Register
Definition: i2c_regs.h:104
__IO uint32_t dma
0x48: I2C DMA Register
Definition: i2c_regs.h:107
__IO uint32_t int_fl0
0x08: I2C INT_FL0 Register
Definition: i2c_regs.h:91
__IO uint32_t fifo_len
0x18: I2C FIFO_LEN Register
Definition: i2c_regs.h:95
__IO uint32_t rx_ctrl1
0x20: I2C RX_CTRL1 Register
Definition: i2c_regs.h:97
__IO uint32_t clk_hi
0x38: I2C CLK_HI Register
Definition: i2c_regs.h:103
__IO uint32_t status
0x04: I2C STATUS Register
Definition: i2c_regs.h:90
__IO uint32_t fifo
0x2C: I2C FIFO Register
Definition: i2c_regs.h:100
__IO uint32_t rx_ctrl0
0x1C: I2C RX_CTRL0 Register
Definition: i2c_regs.h:96
__IO uint32_t slave_addr
0x4C: I2C SLAVE_ADDR Register
Definition: i2c_regs.h:108
__IO uint32_t timeout
0x40: I2C TIMEOUT Register
Definition: i2c_regs.h:105
Structure type to access the I2C Registers.
Definition: i2c_regs.h:88
__IO uint32_t tx_ctrl1
0x28: I2C TX_CTRL1 Register
Definition: i2c_regs.h:99
__IO uint32_t ctrl
0x00: I2C CTRL Register
Definition: i2c_regs.h:89
__IO uint32_t clk_lo
0x34: I2C CLK_LO Register
Definition: i2c_regs.h:102
__IO uint32_t int_fl1
0x10: I2C INT_FL1 Register
Definition: i2c_regs.h:93
__IO uint32_t tx_ctrl0
0x24: I2C TX_CTRL0 Register
Definition: i2c_regs.h:98
__IO uint32_t int_en1
0x14: I2C INT_EN1 Register
Definition: i2c_regs.h:94