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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Crypto Control Register. More...
Macros | |
#define | MXC_F_TPU_CTRL_RST_POS 0 |
CTRL_RST Position. | |
#define | MXC_F_TPU_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RST_POS)) |
CTRL_RST Mask. | |
#define | MXC_F_TPU_CTRL_INTR_POS 1 |
CTRL_INTR Position. | |
#define | MXC_F_TPU_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_INTR_POS)) |
CTRL_INTR Mask. | |
#define | MXC_F_TPU_CTRL_SRC_POS 2 |
CTRL_SRC Position. | |
#define | MXC_F_TPU_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_SRC_POS)) |
CTRL_SRC Mask. | |
#define | MXC_F_TPU_CTRL_BSO_POS 4 |
CTRL_BSO Position. | |
#define | MXC_F_TPU_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSO_POS)) |
CTRL_BSO Mask. | |
#define | MXC_F_TPU_CTRL_BSI_POS 5 |
CTRL_BSI Position. | |
#define | MXC_F_TPU_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSI_POS)) |
CTRL_BSI Mask. | |
#define | MXC_F_TPU_CTRL_WAIT_EN_POS 6 |
CTRL_WAIT_EN Position. | |
#define | MXC_F_TPU_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_EN_POS)) |
CTRL_WAIT_EN Mask. | |
#define | MXC_F_TPU_CTRL_WAIT_POL_POS 7 |
CTRL_WAIT_POL Position. | |
#define | MXC_F_TPU_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_POL_POS)) |
CTRL_WAIT_POL Mask. | |
#define | MXC_F_TPU_CTRL_WRSRC_POS 8 |
CTRL_WRSRC Position. | |
#define | MXC_F_TPU_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_WRSRC_POS)) |
CTRL_WRSRC Mask. | |
#define | MXC_V_TPU_CTRL_WRSRC_NONE ((uint32_t)0x0UL) |
CTRL_WRSRC_NONE Value. | |
#define | MXC_S_TPU_CTRL_WRSRC_NONE (MXC_V_TPU_CTRL_WRSRC_NONE << MXC_F_TPU_CTRL_WRSRC_POS) |
CTRL_WRSRC_NONE Setting. | |
#define | MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) |
CTRL_WRSRC_CIPHEROUTPUT Value. | |
#define | MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CTRL_WRSRC_POS) |
CTRL_WRSRC_CIPHEROUTPUT Setting. | |
#define | MXC_V_TPU_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) |
CTRL_WRSRC_READFIFO Value. | |
#define | MXC_S_TPU_CTRL_WRSRC_READFIFO (MXC_V_TPU_CTRL_WRSRC_READFIFO << MXC_F_TPU_CTRL_WRSRC_POS) |
CTRL_WRSRC_READFIFO Setting. | |
#define | MXC_F_TPU_CTRL_RDSRC_POS 10 |
CTRL_RDSRC Position. | |
#define | MXC_F_TPU_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_RDSRC_POS)) |
CTRL_RDSRC Mask. | |
#define | MXC_V_TPU_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) |
CTRL_RDSRC_DMADISABLED Value. | |
#define | MXC_S_TPU_CTRL_RDSRC_DMADISABLED (MXC_V_TPU_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CTRL_RDSRC_POS) |
CTRL_RDSRC_DMADISABLED Setting. | |
#define | MXC_V_TPU_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) |
CTRL_RDSRC_DMAORAPB Value. | |
#define | MXC_S_TPU_CTRL_RDSRC_DMAORAPB (MXC_V_TPU_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CTRL_RDSRC_POS) |
CTRL_RDSRC_DMAORAPB Setting. | |
#define | MXC_V_TPU_CTRL_RDSRC_RNG ((uint32_t)0x2UL) |
CTRL_RDSRC_RNG Value. | |
#define | MXC_S_TPU_CTRL_RDSRC_RNG (MXC_V_TPU_CTRL_RDSRC_RNG << MXC_F_TPU_CTRL_RDSRC_POS) |
CTRL_RDSRC_RNG Setting. | |
#define | MXC_F_TPU_CTRL_FLAG_MODE_POS 14 |
CTRL_FLAG_MODE Position. | |
#define | MXC_F_TPU_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_FLAG_MODE_POS)) |
CTRL_FLAG_MODE Mask. | |
#define | MXC_F_TPU_CTRL_DMADNEMSK_POS 15 |
CTRL_DMADNEMSK Position. | |
#define | MXC_F_TPU_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMADNEMSK_POS)) |
CTRL_DMADNEMSK Mask. | |
#define | MXC_F_TPU_CTRL_DMA_DONE_POS 24 |
CTRL_DMA_DONE Position. | |
#define | MXC_F_TPU_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMA_DONE_POS)) |
CTRL_DMA_DONE Mask. | |
#define | MXC_F_TPU_CTRL_GLS_DONE_POS 25 |
CTRL_GLS_DONE Position. | |
#define | MXC_F_TPU_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_GLS_DONE_POS)) |
CTRL_GLS_DONE Mask. | |
#define | MXC_F_TPU_CTRL_HSH_DONE_POS 26 |
CTRL_HSH_DONE Position. | |
#define | MXC_F_TPU_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_HSH_DONE_POS)) |
CTRL_HSH_DONE Mask. | |
#define | MXC_F_TPU_CTRL_CPH_DONE_POS 27 |
CTRL_CPH_DONE Position. | |
#define | MXC_F_TPU_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_CPH_DONE_POS)) |
CTRL_CPH_DONE Mask. | |
#define | MXC_F_TPU_CTRL_MAA_DONE_POS 28 |
CTRL_MAA_DONE Position. | |
#define | MXC_F_TPU_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_MAA_DONE_POS)) |
CTRL_MAA_DONE Mask. | |
#define | MXC_F_TPU_CTRL_ERR_POS 29 |
CTRL_ERR Position. | |
#define | MXC_F_TPU_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_ERR_POS)) |
CTRL_ERR Mask. | |
#define | MXC_F_TPU_CTRL_RDY_POS 30 |
CTRL_RDY Position. | |
#define | MXC_F_TPU_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RDY_POS)) |
CTRL_RDY Mask. | |
#define | MXC_F_TPU_CTRL_DONE_POS 31 |
CTRL_DONE Position. | |
#define | MXC_F_TPU_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DONE_POS)) |
CTRL_DONE Mask. | |