MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation
max32665.h
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32  * $Date: 2019-04-26 16:05:18 -0500 (Fri, 26 Apr 2019) $
33  * $Revision: 42983 $
34  *
35  ******************************************************************************/
36 
37 #ifndef _MAX32665_REGS_H_
38 #define _MAX32665_REGS_H_
39 
40 #ifndef TARGET_NUM
41 #define TARGET_NUM 32665
42 #endif
43 
44 #define MXC_NUMCORES 2
45 
46 #include <stdint.h>
47 
48 #ifndef FALSE
49 #define FALSE (0)
50 #endif
51 
52 #ifndef TRUE
53 #define TRUE (1)
54 #endif
55 
56 #if !defined ( __GNUC__ )
57  #define CMSIS_VECTAB_VIRTUAL
58  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
59 #endif
60 
61 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
62 #if defined ( __GNUC__ )
63 
64 #define __weak __attribute__((weak))
65 
66 #elif defined ( __CC_ARM)
67 
68 #define inline __inline
69 #pragma anon_unions
70 
71 #endif
72 
73 typedef enum {
74  NonMaskableInt_IRQn = -14,
75  HardFault_IRQn = -13,
76  MemoryManagement_IRQn = -12,
77  BusFault_IRQn = -11,
78  UsageFault_IRQn = -10,
79  SVCall_IRQn = -5,
80  DebugMonitor_IRQn = -4,
81  PendSV_IRQn = -2,
82  SysTick_IRQn = -1,
83 
84  /* Device-specific interrupt sources (external to ARM core) */
85  /* table entry number */
86  /* |||| */
87  /* |||| table offset address */
88  /* vvvv vvvvvv */
89 
90  PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
91  WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
92  USB_IRQn, /* 0x12 0x0048 18: USB */
93  RTC_IRQn, /* 0x13 0x004C 19: RTC */
94  TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
95  TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
96  TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
97  TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
98  TMR3_IRQn, /* 0x18 0x0060 24: Timer 3*/
99  TMR4_IRQn, /* 0x19 0x0064 25: Timer 4*/
100  TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
101  RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
102  RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
103  I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
104  UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
105  UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
106  SPI17Y1_IRQn, /* 0x20 0x0080 32: SPI17Y1 */
107  SPI17Y2_IRQn, /* 0x21 0x0084 33: SPI17Y2 */
108  RSV18_IRQn, /* 0x22 0x0088 34: Reserved */
109  RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
110  ADC_IRQn, /* 0x24 0x0090 36: ADC */
111  RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
112  RSV22_IRQn, /* 0x26 0x0098 38: Reserved */
113  FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
114  GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
115  GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */
116  RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */
117  TPU_IRQn, /* 0x2B 0x00AC 43: Crypto */
118  DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
119  DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
120  DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
121  DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
122  RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
123  RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
124  UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
125  RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */
126  I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
127  RSV36_IRQn, /* 0x35 0x00D4 53: Reserved */
128  SPIXFC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */
129  BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */
130  BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */
131  BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */
132  BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */
133  BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/
134  BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/
135  BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */
136  BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */
137  BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */
138  BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */
139  BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */
140  BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */
141  BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/
142  BTLE_IQ_DATA_VALID_IRQn,/* 0x44 0x0110 68: BTLE IQ Data Valid */
143  WUT_IRQn, /* 0x45 0x0114 69: WUT Wakeup */
144  GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
145  RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
146  SPI17Y0_IRQn, /* 0x48 0x0120 72: SPI17Y0 AHB*/
147  WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
148  RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */
149  PT_IRQn, /* 0x4B 0x012C 75: Pulse train */
150  SDMA_IRQn, /* 0x4C 0x0130 76: Smart DMA 0 */
151  RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
152  I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
153  RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
154  RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
155  RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
156  SDHC_IRQn, /* 0x52 0x0148 82: SDIO/SDHC */
157  OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */
158  DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
159  DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
160  DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
161  DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
162  DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
163  DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
164  DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
165  DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
166  DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */
167  DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */
168  DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */
169  DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */
170  USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */
171  WDT2_IRQn, /* 0x61 0x0184 97: Watchdog Timer 2 */
172  ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
173  DVS_IRQn, /* 0x63 0x018C 99: DVS Controller */
174  SIMO_IRQn, /* 0x64 0x0190 100: SIMO Controller */
175  RPU_IRQn, /* 0x65 0x0194 101: RPU */
176  AUDIO_IRQn, /* 0x66 0x0198 102: Audio subsystem */
177  FLC1_IRQn, /* 0x67 0x019C 103: Flash Control 1 */
178  UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
179  UART4_IRQn, /* 0x69 0x01A4 105: UART 4 */
180  UART5_IRQn, /* 0x6A 0x01A8 106: UART 5 */
181  CameraIF_IRQn, /* 0x6B 0x01AC 107: Camera IF */
182  I3C_IRQn, /* 0x6C 0x01B0 108: I3C */
183  HTMR0_IRQn, /* 0x6D 0x01B4 109: HTimer0 */
184  HTMR1_IRQn, /* 0x6E 0x01B8 110: HTimer1 */
185  MXC_IRQ_EXT_COUNT
186 } IRQn_Type;
187 
188 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
189 
190 
191 /* ================================================================================ */
192 /* ================ Processor and Core Peripheral Section ================ */
193 /* ================================================================================ */
194 
195 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
196 #define __CM4_REV 0x0100
197 #define __MPU_PRESENT 1
198 #define __NVIC_PRIO_BITS 3
199 #define __Vendor_SysTickConfig 0
200 #define __FPU_PRESENT 1
202 #ifndef __CROSSWORKS
203 #include <core_cm4.h>
204 #else
205 #include "max32665_sdma.h"
206 #endif
207 
208 #include "system_max32665.h"
211 /* ================================================================================ */
212 /* ================== Device Specific Memory Section ================== */
213 /* ================================================================================ */
214 
215 #define MXC_ROM_MEM_BASE 0x00000000UL
216 #define MXC_ROM_MEM_SIZE 0x00020000UL
217 #define MXC_XIP_MEM_BASE 0x08000000UL
218 #define MXC_XIP_MEM_SIZE 0x08000000UL
219 #define MXC_FLASH0_MEM_BASE 0x10000000UL
220 #define MXC_FLASH1_MEM_BASE 0x10080000UL
221 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
222 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
223 #define MXC_FLASH_MEM_SIZE 0x00080000UL
224 #define MXC_INFO0_MEM_BASE 0x10800000UL
225 #define MXC_INFO1_MEM_BASE 0x10804000UL
226 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
227 #define MXC_INFO_MEM_SIZE 0x00004000UL
228 #define MXC_SRAM_MEM_BASE 0x20000000UL
229 #define MXC_SRAM_MEM_SIZE 0x0008C000UL
230 #define MXC_XIP_DATA_MEM_BASE 0x80000000UL
231 #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
232 
233 /* ================================================================================ */
234 /* ================ Device Specific Peripheral Section ================ */
235 /* ================================================================================ */
236 
237 /*
238  Base addresses and configuration settings for all MAX32665 peripheral modules.
239 */
240 
241 /******************************************************************************/
242 /* Global control */
243 #define MXC_BASE_GCR ((uint32_t)0x40000000UL)
244 #define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
245 
246 /******************************************************************************/
247 /* Non-battery backed SI Registers */
248 #define MXC_BASE_SIR ((uint32_t)0x40000400UL)
249 #define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
250 
251 /******************************************************************************/
252 /* Non-battery backed Function Control */
253 #define MXC_BASE_FCR ((uint32_t)0x40000800UL)
254 #define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR)
255 
256 /******************************************************************************/
257 /* Trust Protection Unit */
258 #define MXC_BASE_TPU ((uint32_t)0x40001000UL)
259 #define MXC_TPU ((mxc_tpu_regs_t*)MXC_BASE_TPU)
260 
261 /******************************************************************************/
262 /* Watchdog */
263 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
264 #define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
265 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
266 #define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
267 #define MXC_BASE_WDT2 ((uint32_t)0x40003800UL)
268 #define MXC_WDT2 ((mxc_wdt_regs_t*)MXC_BASE_WDT2)
269 
270 /******************************************************************************/
271 /* Security Monitor */
272 #define MXC_BASE_SMON ((uint32_t)0x40004000UL)
273 #define MXC_SMON ((mxc_smon_regs_t*)MXC_BASE_SMON)
274 
275 
276 /******************************************************************************/
277 /* SIMO */
278 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL)
279 #define MXC_SIMO ((mxc_simo_regs_t*)MXC_BASE_SIMO)
280 
281 
282 /******************************************************************************/
283 /* DVS*/
284 #define MXC_BASE_DVS ((uint32_t)0x40004800UL)
285 #define MXC_DVS ((mxc_dvs_regs_t*)MXC_BASE_DVS)
286 
287 
288 /******************************************************************************/
289 /* Security Monitor */
290 #define MXC_BASE_SMON ((uint32_t)0x40004000UL)
291 #define MXC_SMON ((mxc_smon_regs_t*)MXC_BASE_SMON)
292 
293 /******************************************************************************/
294 /* Real Time Clock */
295 #define MXC_BASE_RTC ((uint32_t)0x40006000UL)
296 #define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
297 
298 /******************************************************************************/
299 /* Wakeup Timer */
300 #define MXC_BASE_WUT ((uint32_t)0x40006400UL)
301 #define MXC_WUT ((mxc_wut_regs_t*)MXC_BASE_WUT)
302 
303 
304 /******************************************************************************/
305 /* Power Sequencer */
306 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
307 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
308 /******************************************************************************/
309 /* Power Sequencer */
310 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
311 #define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR)
312 
313 /******************************************************************************/
314 /* GPIO */
315 #define MXC_CFG_GPIO_INSTANCES (2)
316 #define MXC_CFG_GPIO_PINS_PORT (32)
317 
318 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
319 #define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
320 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
321 #define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
322 
323 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
324  (p) == MXC_GPIO1 ? 1 : -1)
325 
326 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
327  (i) == 1 ? MXC_GPIO1 : 0)
328 
329 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
330  (i) == 1 ? GPIO1_IRQn : (IRQn_Type) 0)
331 
332 /******************************************************************************/
333 /* Timer */
334 #define MXC_CFG_TMR_INSTANCES (6)
335 
336 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
337 #define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
338 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
339 #define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
340 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
341 #define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
342 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
343 #define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
344 #define MXC_BASE_TMR4 ((uint32_t)0x40014000UL)
345 #define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
346 #define MXC_BASE_TMR5 ((uint32_t)0x40015000UL)
347 #define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
348 
349 #define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
350  (i) == 1 ? TMR1_IRQn : \
351  (i) == 2 ? TMR2_IRQn : \
352  (i) == 3 ? TMR3_IRQn : \
353  (i) == 4 ? TMR4_IRQn : \
354  (i) == 5 ? TMR5_IRQn : 0)
355 
356 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
357  (i) == 1 ? MXC_BASE_TMR1 : \
358  (i) == 2 ? MXC_BASE_TMR2 : \
359  (i) == 3 ? MXC_BASE_TMR3 : \
360  (i) == 4 ? MXC_BASE_TMR4 : \
361  (i) == 5 ? MXC_BASE_TMR5 : 0)
362 
363 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
364  (i) == 1 ? MXC_TMR1 : \
365  (i) == 2 ? MXC_TMR2 : \
366  (i) == 3 ? MXC_TMR3 : \
367  (i) == 4 ? MXC_TMR4 : \
368  (i) == 5 ? MXC_TMR5 : 0)
369 
370 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
371  (p) == MXC_TMR1 ? 1 : \
372  (p) == MXC_TMR2 ? 2 : \
373  (p) == MXC_TMR3 ? 3 : \
374  (p) == MXC_TMR4 ? 4 : \
375  (p) == MXC_TMR5 ? 5 : -1)
376 
377 /******************************************************************************/
378 /* High Speed Timer */
379 #define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL)
380 #define MXC_HTMR0 ((mxc_htmr_regs_t*)MXC_BASE_HTMR0)
381 #define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL)
382 #define MXC_HTMR1 ((mxc_htmr_regs_t*)MXC_BASE_HTMR1)
383 
384 
385 /******************************************************************************/
386 /* I2C */
387 #define MXC_I2C_INSTANCES (3)
388 
389 #define MXC_BASE_I2C0_BUS0 ((uint32_t)0x4001D000UL)
390 #define MXC_I2C0_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS0)
391 #define MXC_BASE_I2C1_BUS0 ((uint32_t)0x4001E000UL)
392 #define MXC_I2C1_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS0)
393 #define MXC_BASE_I2C2_BUS0 ((uint32_t)0x4001F000UL)
394 #define MXC_I2C2_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS0)
395 
396 #define MXC_BASE_I2C0_BUS1 ((uint32_t)0x4011D000UL)
397 #define MXC_I2C0_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS1)
398 #define MXC_BASE_I2C1_BUS1 ((uint32_t)0x4011E000UL)
399 #define MXC_I2C1_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS1)
400 #define MXC_BASE_I2C2_BUS1 ((uint32_t)0x4011F000UL)
401 #define MXC_I2C2_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS1)
402 
403 
404 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0x0 ? I2C0_IRQn : \
405  (i) == 0x1 ? I2C1_IRQn : \
406  (i) == 0x2 ? I2C2_IRQn : \
407  (i) == 0x8000 ? I2C0_IRQn : \
408  (i) == 0x8001 ? I2C1_IRQn : \
409  (i) == 0x8002 ? I2C2_IRQn : 0)
410 
411 #define MXC_I2C_GET_BASE(i) ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 : \
412  (i) == 0x1 ? MXC_BASE_I2C1_BUS0 : \
413  (i) == 0x2 ? MXC_BASE_I2C2_BUS0 : \
414  (i) == 0x8000 ? MXC_BASE_I2C0_BUS1 : \
415  (i) == 0x8001 ? MXC_BASE_I2C1_BUS1 : \
416  (i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : 0)
417 
418 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0_BUS0 ? 0x0 : \
419  (p) == MXC_I2C1_BUS0 ? 0x1 : \
420  (p) == MXC_I2C2_BUS0 ? 0x2 : \
421  (p) == MXC_I2C0_BUS1 ? 0x8000 : \
422  (p) == MXC_I2C1_BUS1 ? 0x8001 : \
423  (p) == MXC_I2C2_BUS1 ? 0x8002 : -1)
424 
425 #define MXC_I2C_GET_I2C(p) ((p) == 0x0 ? MXC_I2C0_BUS0 : \
426  (p) == 0x1 ? MXC_I2C1_BUS0 : \
427  (p) == 0x2 ? MXC_I2C2_BUS0 : \
428  (p) == 0x8000 ? MXC_I2C0_BUS1 : \
429  (p) == 0x8001 ? MXC_I2C1_BUS1 : \
430  (p) == 0x8002? MXC_I2C2_BUS1 : 0)
431 #define MXC_I2C_FIFO_DEPTH (8)
432 
433 /******************************************************************************/
434 /* SPI Execute in Place */
435 #define MXC_BASE_SPIXF ((uint32_t)0x40026000UL)
436 #define MXC_SPIXF ((mxc_spixf_regs_t*)MXC_BASE_SPIXF)
437 
438 #define MXC_BASE_SPIXF_FIFO ((uint32_t)0x400BC000UL)
439 #define MXC_SPIXF_FIFO ((mxc_spixf_fifo_regs_t*)MXC_BASE_SPIXF_FIFO)
440 /******************************************************************************/
441 /* SPI Execute in Place Master */
442 
443 #define MXC_CFG_SPIXFC_FIFO_DEPTH (16)
444 
445 #define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL)
446 #define MXC_SPIXFC ((mxc_spixfc_regs_t*)MXC_BASE_SPIXFC)
447 
448 /******************************************************************************/
449 /* DMA */
450 #define MXC_DMA_CHANNELS (16)
451 #define MXC_DMA_INSTANCES (2)
452 
453 #define MXC_BASE_DMA0 ((uint32_t)0x40028000UL)
454 #define MXC_DMA0 ((mxc_dma_regs_t*)MXC_BASE_DMA0)
455 #define MXC_BASE_DMA1 ((uint32_t)0x40035000UL)
456 #define MXC_DMA1 ((mxc_dma_regs_t*)MXC_BASE_DMA1)
457 
458 // TODO: remove this when creating drivers to accept two instance of these.
459 #define MXC_DMA MXC_DMA0
460 
461 #define MXC_DMA_GET_BASE(i) ((i) == 0 ? MXC_BASE_DMA0 : \
462  (i) == 1 ? MXC_BASE_DMA1 : 0)
463 
464 #define MXC_DMA_GET_DMA(i) ((i) == 0 ? MXC_DMA0 : \
465  (i) == 1 ? MXC_DMA1 : 0)
466 
467 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : \
468  (p) == MXC_DMA1 ? 1 : -1)
469 /******************************************************************************/
470 /* FLC */
471 #define MXC_FLC_INSTANCES (2)
472 
473 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
474 #define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0)
475 #define MXC_BASE_FLC1 ((uint32_t)0x40029400UL)
476 #define MXC_FLC1 ((mxc_flc_regs_t*)MXC_BASE_FLC1)
477 
478 // TODO: remove this when creating drivers to accept two instance of these.
479 // #define MXC_FLC MXC_FLC0
480 
481 
482 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : \
483  (i) == 1 ? FLC1_IRQn :0)
484 
485 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : \
486  (i) == 1 ? MXC_BASE_FLC1 : 0)
487 
488 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : \
489  (i) == 1 ? MXC_FLC1 : 0)
490 
491 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : \
492  (p) == MXC_FLC1 ? 1 : -1)
493 /******************************************************************************/
494 /* Instruction Cache */
495 #define MXC_ICC_INSTANCES (2)
496 
497 #define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
498 #define MXC_ICC0 ((mxc_icc_regs_t*)MXC_BASE_ICC0)
499 #define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL)
500 #define MXC_ICC1 ((mxc_icc_regs_t*)MXC_BASE_ICC1)
501 
502 // TODO: remove this when creating drivers to accept two instance of these.
503 #define MXC_ICC MXC_ICC0
504 
505 
506 #define MXC_ICC_GET_BASE(i) ((i) == 0 ? MXC_BASE_ICC0 : \
507  (i) == 1 ? MXC_BASE_ICC1 : 0)
508 
509 #define MXC_ICC_GET_ICC(i) ((i) == 0 ? MXC_ICC0 : \
510  (i) == 1 ? MXC_ICC1 : 0)
511 
512 #define MXC_ICC_GET_IDX(p) ((p) == MXC_ICC0 ? 0 : \
513  (p) == MXC_ICC1 ? 1 : -1)
514 /******************************************************************************/
515 /* Instruction Cache XIP */
516 #define MXC_BASE_ICX ((uint32_t)0x4002F000UL)
517 #define MXC_ICX ((mxc_icc_regs_t*)MXC_BASE_ICX)
518 
519 /******************************************************************************/
520 /* Data Cache */
521 #define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
522 #define MXC_EMCC ((mxc_emcc_regs_t*)MXC_BASE_EMCC)
523 
524 /******************************************************************************/
525 /* ADC */
526 #define MXC_BASE_ADC ((uint32_t)0x40034000UL)
527 #define MXC_ADC ((mxc_adc_regs_t*)MXC_BASE_ADC)
528 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz
529 
530 /******************************************************************************/
531 /* USB */
532 #define MXC_BASE_USBHS ((uint32_t)0x400B1000UL)
533 #define MXC_USBHS ((mxc_usbhs_regs_t*)MXC_BASE_USBHS)
534 #define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */
535 #define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */
536 #define MXC_USBHS_MAX_PACKET 512
537 
538 /******************************************************************************/
539 /* Smart DMA */
540 #define MXC_BASE_SDMA ((uint32_t)0x40036000UL)
541 #define MXC_SDMA ((mxc_sdma_regs_t*)MXC_BASE_SDMA)
542 
543 /******************************************************************************/
544 /* SPI XIP Data */
545 #define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL)
546 #define MXC_SPIXR ((mxc_spixr_regs_t*)MXC_BASE_SPIXR)
547 
548 /*******************************************************************************/
549 /* Pulse Train Generation */
550 
551 #define MXC_CFG_PT_INSTANCES (16)
552 
553 #define MXC_BASE_PTG_BUS0 ((uint32_t)0x4003C000UL)
554 #define MXC_PTG_BUS0 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0)
555 #define MXC_BASE_PT0_BUS0 ((uint32_t)0x4003C020UL)
556 #define MXC_PT0_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0)
557 #define MXC_BASE_PT1_BUS0 ((uint32_t)0x4003C040UL)
558 #define MXC_PT1_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0)
559 #define MXC_BASE_PT2_BUS0 ((uint32_t)0x4003C060UL)
560 #define MXC_PT2_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0)
561 #define MXC_BASE_PT3_BUS0 ((uint32_t)0x4003C080UL)
562 #define MXC_PT3_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0)
563 #define MXC_BASE_PT4_BUS0 ((uint32_t)0x4003C0A0UL)
564 #define MXC_PT4_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0)
565 #define MXC_BASE_PT5_BUS0 ((uint32_t)0x4003C0C0UL)
566 #define MXC_PT5_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0)
567 #define MXC_BASE_PT6_BUS0 ((uint32_t)0x4003C0E0UL)
568 #define MXC_PT6_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0)
569 #define MXC_BASE_PT7_BUS0 ((uint32_t)0x4003C100UL)
570 #define MXC_PT7_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0)
571 #define MXC_BASE_PT8_BUS0 ((uint32_t)0x4003C120UL)
572 #define MXC_PT8_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0)
573 #define MXC_BASE_PT9_BUS0 ((uint32_t)0x4003C140UL)
574 #define MXC_PT9_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0)
575 #define MXC_BASE_PT10_BUS0 ((uint32_t)0x4003C160UL)
576 #define MXC_PT10_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0)
577 #define MXC_BASE_PT11_BUS0 ((uint32_t)0x4003C180UL)
578 #define MXC_PT11_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0)
579 #define MXC_BASE_PT12_BUS0 ((uint32_t)0x4003C1A0UL)
580 #define MXC_PT12_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0)
581 #define MXC_BASE_PT13_BUS0 ((uint32_t)0x4003C1C0UL)
582 #define MXC_PT13_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0)
583 #define MXC_BASE_PT14_BUS0 ((uint32_t)0x4003C1E0UL)
584 #define MXC_PT14_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0)
585 #define MXC_BASE_PT15_BUS0 ((uint32_t)0x4003C200UL)
586 #define MXC_PT15_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0)
587 
588 
589 #define MXC_BASE_PTG_BUS1 ((uint32_t)0x4013C000UL)
590 #define MXC_PTG_BUS1 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1)
591 #define MXC_BASE_PT0_BUS1 ((uint32_t)0x4013C020UL)
592 #define MXC_PT0_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1)
593 #define MXC_BASE_PT1_BUS1 ((uint32_t)0x4013C040UL)
594 #define MXC_PT1_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1)
595 #define MXC_BASE_PT2_BUS1 ((uint32_t)0x4013C060UL)
596 #define MXC_PT2_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1)
597 #define MXC_BASE_PT3_BUS1 ((uint32_t)0x4013C080UL)
598 #define MXC_PT3_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1)
599 #define MXC_BASE_PT4_BUS1 ((uint32_t)0x4013C0A0UL)
600 #define MXC_PT4_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1)
601 #define MXC_BASE_PT5_BUS1 ((uint32_t)0x4013C0C0UL)
602 #define MXC_PT5_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1)
603 #define MXC_BASE_PT6_BUS1 ((uint32_t)0x4013C0E0UL)
604 #define MXC_PT6_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1)
605 #define MXC_BASE_PT7_BUS1 ((uint32_t)0x4013C100UL)
606 #define MXC_PT7_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1)
607 #define MXC_BASE_PT8_BUS1 ((uint32_t)0x4013C120UL)
608 #define MXC_PT8_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1)
609 #define MXC_BASE_PT9_BUS1 ((uint32_t)0x4013C140UL)
610 #define MXC_PT9_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1)
611 #define MXC_BASE_PT10_BUS1 ((uint32_t)0x4013C160UL)
612 #define MXC_PT10_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1)
613 #define MXC_BASE_PT11_BUS1 ((uint32_t)0x4013C180UL)
614 #define MXC_PT11_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1)
615 #define MXC_BASE_PT12_BUS1 ((uint32_t)0x4013C1A0UL)
616 #define MXC_PT12_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1)
617 #define MXC_BASE_PT13_BUS1 ((uint32_t)0x4013C1C0UL)
618 #define MXC_PT13_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1)
619 #define MXC_BASE_PT14_BUS1 ((uint32_t)0x4013C1E0UL)
620 #define MXC_PT14_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1)
621 #define MXC_BASE_PT15_BUS1 ((uint32_t)0x4013C200UL)
622 #define MXC_PT15_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1)
623 
624 #define MXC_PT_GET_BASE(i) ((i) == 0x0 ? MXC_BASE_PT0_BUS0 : \
625  (i) == 0x1 ? MXC_BASE_PT1_BUS0 : \
626  (i) == 0x2 ? MXC_BASE_PT2_BUS0 : \
627  (i) == 0x3 ? MXC_BASE_PT3_BUS0 : \
628  (i) == 0x4 ? MXC_BASE_PT4_BUS0 : \
629  (i) == 0x5 ? MXC_BASE_PT5_BUS0 : \
630  (i) == 0x6 ? MXC_BASE_PT6_BUS0 : \
631  (i) == 0x7 ? MXC_BASE_PT7_BUS0 : \
632  (i) == 0x8 ? MXC_BASE_PT8_BUS0 : \
633  (i) == 0x9 ? MXC_BASE_PT9_BUS0 : \
634  (i) == 0xA ? MXC_BASE_PT10_BUS0 : \
635  (i) == 0xB ? MXC_BASE_PT11_BUS0 : \
636  (i) == 0xC ? MXC_BASE_PT12_BUS0 : \
637  (i) == 0xD ? MXC_BASE_PT13_BUS0 : \
638  (i) == 0xE ? MXC_BASE_PT14_BUS0 : \
639  (i) == 0xF ? MXC_BASE_PT15_BUS0 : \
640  (i) == 0x8000 ? MXC_BASE_PT0_BUS1 : \
641  (i) == 0x8001 ? MXC_BASE_PT1_BUS1 : \
642  (i) == 0x8002 ? MXC_BASE_PT2_BUS1 : \
643  (i) == 0x8003 ? MXC_BASE_PT3_BUS1 : \
644  (i) == 0x8004 ? MXC_BASE_PT4_BUS1 : \
645  (i) == 0x8005 ? MXC_BASE_PT5_BUS1 : \
646  (i) == 0x8006 ? MXC_BASE_PT6_BUS1 : \
647  (i) == 0x8007 ? MXC_BASE_PT7_BUS1 : \
648  (i) == 0x8008 ? MXC_BASE_PT8_BUS1 : \
649  (i) == 0x8009 ? MXC_BASE_PT9_BUS1 : \
650  (i) == 0x800A ? MXC_BASE_PT10_BUS1 : \
651  (i) == 0x800B ? MXC_BASE_PT11_BUS1 : \
652  (i) == 0x800C ? MXC_BASE_PT12_BUS1 : \
653  (i) == 0x800D ? MXC_BASE_PT13_BUS1 : \
654  (i) == 0x800E ? MXC_BASE_PT14_BUS1 : \
655  (i) == 0x800F ? MXC_BASE_PT15_BUS1 : 0)
656 
657 #define MXC_PT_GET_PT(i) ((i) == 0x0 ? MXC_PT0_BUS0 : \
658  (i) == 0x1 ? MXC_PT1_BUS0 : \
659  (i) == 0x2 ? MXC_PT2_BUS0 : \
660  (i) == 0x3 ? MXC_PT3_BUS0 : \
661  (i) == 0x4 ? MXC_PT4_BUS0 : \
662  (i) == 0x5 ? MXC_PT5_BUS0 : \
663  (i) == 0x6 ? MXC_PT6_BUS0 : \
664  (i) == 0x7 ? MXC_PT7_BUS0 : \
665  (i) == 0x8 ? MXC_PT8_BUS0 : \
666  (i) == 0x9 ? MXC_PT9_BUS0 : \
667  (i) == 0xA ? MXC_PT10_BUS0 : \
668  (i) == 0xB ? MXC_PT11_BUS0 : \
669  (i) == 0xC ? MXC_PT12_BUS0 : \
670  (i) == 0xD ? MXC_PT13_BUS0 : \
671  (i) == 0xE ? MXC_PT14_BUS0 : \
672  (i) == 0xF ? MXC_PT15_BUS0 : \
673  (i) == 0x8000 ? MXC_PT0_BUS1 : \
674  (i) == 0x8001 ? MXC_PT1_BUS1 : \
675  (i) == 0x8002 ? MXC_PT2_BUS1 : \
676  (i) == 0x8003 ? MXC_PT3_BUS1 : \
677  (i) == 0x8004 ? MXC_PT4_BUS1 : \
678  (i) == 0x8005 ? MXC_PT5_BUS1 : \
679  (i) == 0x8006 ? MXC_PT6_BUS1 : \
680  (i) == 0x8007 ? MXC_PT7_BUS1 : \
681  (i) == 0x8008 ? MXC_PT8_BUS1 : \
682  (i) == 0x8009 ? MXC_PT9_BUS1 : \
683  (i) == 0x800A ? MXC_PT10_BUS1 : \
684  (i) == 0x800B ? MXC_PT11_BUS1 : \
685  (i) == 0x800C ? MXC_PT12_BUS1 : \
686  (i) == 0x800D ? MXC_PT13_BUS1 : \
687  (i) == 0x800E ? MXC_PT14_BUS1 : \
688  (i) == 0x800F ? MXC_PT15_BUS1 : 0)
689 
690 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0_BUS0 ? 0x0 : \
691  (p) == MXC_PT1_BUS0 ? 0x1 : \
692  (p) == MXC_PT2_BUS0 ? 0x2 : \
693  (p) == MXC_PT3_BUS0 ? 0x3 : \
694  (p) == MXC_PT4_BUS0 ? 0x4 : \
695  (p) == MXC_PT5_BUS0 ? 0x5 : \
696  (p) == MXC_PT6_BUS0 ? 0x6 : \
697  (p) == MXC_PT7_BUS0 ? 0x7 : \
698  (p) == MXC_PT8_BUS0 ? 0x8 : \
699  (p) == MXC_PT9_BUS0 ? 0x9 : \
700  (p) == MXC_PT10_BUS0 ? 0xA : \
701  (p) == MXC_PT11_BUS0 ? 0xB : \
702  (p) == MXC_PT12_BUS0 ? 0xC : \
703  (p) == MXC_PT13_BUS0 ? 0xD : \
704  (p) == MXC_PT14_BUS0 ? 0xE : \
705  (p) == MXC_PT15_BUS0 ? 0xF : \
706  (p) == MXC_PT0_BUS1 ? 0x8000 : \
707  (p) == MXC_PT1_BUS1 ? 0x8001 : \
708  (p) == MXC_PT2_BUS1 ? 0x8002 : \
709  (p) == MXC_PT3_BUS1 ? 0x8003 : \
710  (p) == MXC_PT4_BUS1 ? 0x8004 : \
711  (p) == MXC_PT5_BUS1 ? 0x8005 : \
712  (p) == MXC_PT6_BUS1 ? 0x8006 : \
713  (p) == MXC_PT7_BUS1 ? 0x8007 : \
714  (p) == MXC_PT8_BUS1 ? 0x8008 : \
715  (p) == MXC_PT9_BUS1 ? 0x8009 : \
716  (p) == MXC_PT10_BUS1 ? 0x800A : \
717  (p) == MXC_PT11_BUS1 ? 0x800B : \
718  (p) == MXC_PT12_BUS1 ? 0x800C : \
719  (p) == MXC_PT13_BUS1 ? 0x800D : \
720  (p) == MXC_PT14_BUS1 ? 0x800E : \
721  (p) == MXC_PT15_BUS1 ? 0x800F : -1)
722 
723 #define MXC_PT_GET_BUS(i) (((i) & 0x00100000UL)>>20)
724 
725 #define MXC_PTG_GET_PTG(i) (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 : \
726  MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0)
727 
728 /******************************************************************************/
729 /* One Wire Master */
730 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
731 #define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM)
732 
733 /******************************************************************************/
734 /* Semaphore */
735 #define MXC_CFG_SEMA_INSTANCES (8)
736 
737 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
738 #define MXC_SEMA ((mxc_sema_regs_t*)MXC_BASE_SEMA)
739 
740 /******************************************************************************/
741 /* UART / Serial Port Interface */
742 
743 #define MXC_UART_INSTANCES (3)
744 #define MXC_UART_FIFO_DEPTH (32)
745 
746 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
747 #define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
748 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
749 #define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
750 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
751 #define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2)
752 
753 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
754  (i) == 1 ? UART1_IRQn : \
755  (i) == 2 ? UART2_IRQn : 0)
756 
757 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
758  (i) == 1 ? MXC_BASE_UART1 : \
759  (i) == 2 ? MXC_BASE_UART2 : 0)
760 
761 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
762  (i) == 1 ? MXC_UART1 : \
763  (i) == 2 ? MXC_UART2 : 0)
764 
765 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
766  (p) == MXC_UART1 ? 1 : \
767  (p) == MXC_UART2 ? 2 : -1)
768 
769 /******************************************************************************/
770 /* SPI17Y */
771 
772 #define MXC_SPI17Y_INSTANCES (3)
773 #define MXC_SPI17Y_SS_INSTANCES (4)
774 #define MXC_SPI17Y_FIFO_DEPTH (32)
775 
776 #define MXC_BASE_SPI17Y0 ((uint32_t)0x400BE000UL)
777 #define MXC_SPI17Y0 ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y0)
778 #define MXC_BASE_SPI17Y1 ((uint32_t)0x40046000UL)
779 #define MXC_SPI17Y1 ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y1)
780 #define MXC_BASE_SPI17Y2 ((uint32_t)0x40047000UL)
781 #define MXC_SPI17Y2 ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y2)
782 
783 
784 #define MXC_SPI17Y_GET_IDX(p) ((p) == MXC_SPI17Y0 ? 0 : \
785  (p) == MXC_SPI17Y1 ? 1 : \
786  (p) == MXC_SPI17Y2 ? 2 : -1)
787 
788 #define MXC_SPI17Y_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI17Y0 : \
789  (i) == 1 ? MXC_BASE_SPI17Y1 : \
790  (i) == 2 ? MXC_BASE_SPI17Y2 : 0)
791 
792 #define MXC_SPI17Y_GET_SPI17Y(i) ((i) == 0 ? MXC_SPI17Y0 : \
793  (i) == 1 ? MXC_SPI17Y1 : \
794  (i) == 2 ? MXC_SPI17Y2 : 0)
795 
796 #define MXC_SPI17Y_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI17Y0_IRQn : \
797  (i) == 1 ? SPI17Y1_IRQn : \
798  (i) == 2 ? SPI17Y2_IRQn : 0)
799 
800 
801 /******************************************************************************/
802 /* TRNG */
803 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
804 #define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG)
805 
806 /******************************************************************************/
807 /* SDHC */
808 #define MXC_BASE_SDHC ((uint32_t)0x400B6000UL)
809 #define MXC_SDHC ((mxc_sdhc_regs_t*)MXC_BASE_SDHC)
810 
811 /******************************************************************************/
812 /* RPU */
813 #define MXC_BASE_RPU ((uint32_t)0x40002300UL)
814 #define MXC_RPU ((mxc_rpu_regs_t*)MXC_BASE_RPU)
815 #define MXC_RPU_NUM_BUS_MASTERS 9
816 
817 /******************************************************************************/
818 /* Audio Subsystem */
819 #define MXC_BASE_AUDIO ((uint32_t)0x4004C000UL)
820 #define MXC_AUDIO ((mxc_audio_regs_t*)MXC_BASE_AUDIO)
821 
822 /******************************************************************************/
823 /* Bluetooth Low Energy */
824 #define MXC_BASE_BTLE (0x40050000UL)
825 #define MXC_BTLE ((mxc_btle_regs_t*)MXC_BASE_BTLE)
826 #define MXC_BASE_BTLE_DBB_CTRL (MXC_BASE_BTLE + 0x1000)
827 #define MXC_BASE_BTLE_DBB_TX (MXC_BASE_BTLE + 0x2000)
828 #define MXC_BASE_BTLE_DBB_RX (MXC_BASE_BTLE + 0x3000)
829 #define MXC_BASE_BTLE_DBB_EXT_RFFE (MXC_BASE_BTLE + 0x8000)
830 
831 // Base address definitions needed for DBB register definitions in BTLE stack
832 #define DBB_CTRL_BASE MXC_BASE_BTLE_DBB_CTRL
833 #define DBB_TX_BASE MXC_BASE_BTLE_DBB_TX
834 #define DBB_RX_BASE MXC_BASE_BTLE_DBB_RX
835 #define DBB_EXT_RFFE_BASE MXC_BASE_BTLE_DBB_EXT_RFFE
836 
837 
838 /******************************************************************************/
839 /* Bit Shifting */
840 
841 #define MXC_F_BIT_0 (1 << 0)
842 #define MXC_F_BIT_1 (1 << 1)
843 #define MXC_F_BIT_2 (1 << 2)
844 #define MXC_F_BIT_3 (1 << 3)
845 #define MXC_F_BIT_4 (1 << 4)
846 #define MXC_F_BIT_5 (1 << 5)
847 #define MXC_F_BIT_6 (1 << 6)
848 #define MXC_F_BIT_7 (1 << 7)
849 #define MXC_F_BIT_8 (1 << 8)
850 #define MXC_F_BIT_9 (1 << 9)
851 #define MXC_F_BIT_10 (1 << 10)
852 #define MXC_F_BIT_11 (1 << 11)
853 #define MXC_F_BIT_12 (1 << 12)
854 #define MXC_F_BIT_13 (1 << 13)
855 #define MXC_F_BIT_14 (1 << 14)
856 #define MXC_F_BIT_15 (1 << 15)
857 #define MXC_F_BIT_16 (1 << 16)
858 #define MXC_F_BIT_17 (1 << 17)
859 #define MXC_F_BIT_18 (1 << 18)
860 #define MXC_F_BIT_19 (1 << 19)
861 #define MXC_F_BIT_20 (1 << 20)
862 #define MXC_F_BIT_21 (1 << 21)
863 #define MXC_F_BIT_22 (1 << 22)
864 #define MXC_F_BIT_23 (1 << 23)
865 #define MXC_F_BIT_24 (1 << 24)
866 #define MXC_F_BIT_25 (1 << 25)
867 #define MXC_F_BIT_26 (1 << 26)
868 #define MXC_F_BIT_27 (1 << 27)
869 #define MXC_F_BIT_28 (1 << 28)
870 #define MXC_F_BIT_29 (1 << 29)
871 #define MXC_F_BIT_30 (1 << 30)
872 #define MXC_F_BIT_31 (1 << 31)
873 
874 /******************************************************************************/
875 /* Bit Banding */
876 
877 
878 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
879  (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
880 
881 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
882 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
883 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
884 
885 #define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
886 
887 /******************************************************************************/
888 /* SCB CPACR */
889 
890 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
891 #define SCB_CPACR_CP10_Pos 20
892 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
893 #define SCB_CPACR_CP11_Pos 22
894 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
896 #endif /* _MAX32665_REGS_H_ */