47 #include "mxc_config.h" 64 RPU_DMA0_ALLOW = 0x01,
65 RPU_DMA1_ALLOW = 0x02,
67 RPU_SYS0_ALLOW = 0x08,
68 RPU_SYS1_ALLOW = 0x10,
69 RPU_SDMAD_ALLOW = 0x20,
70 RPU_SDMAI_ALLOW = 0x40,
71 RPU_CRYPTO_ALLOW = 0x80,
72 RPU_SDIO_ALLOW = 0x100
144 int RPU_Allow(rpu_device_t periph, uint32_t allow_mask);
153 int RPU_Disallow(rpu_device_t periph, uint32_t disallow_mask);
#define MXC_R_RPU_SDIO
Offset from RPU Base Address: 0x0B60
Definition: rpu_regs.h:267
#define MXC_R_RPU_BBCR
Offset from RPU Base Address: 0x006C
Definition: rpu_regs.h:227
#define MXC_R_RPU_SDHCCTRL
Offset from RPU Base Address: 0x0370
Definition: rpu_regs.h:253
#define MXC_R_RPU_BBSIR
Offset from RPU Base Address: 0x0054
Definition: rpu_regs.h:223
#define MXC_R_RPU_WDT1
Offset from RPU Base Address: 0x0034
Definition: rpu_regs.h:218
#define MXC_R_RPU_ICACHE1
Offset from RPU Base Address: 0x02A4
Definition: rpu_regs.h:247
#define MXC_R_RPU_I2C0
Offset from RPU Base Address: 0x01D0
Definition: rpu_regs.h:238
#define MXC_R_RPU_TMR1
Offset from RPU Base Address: 0x0110
Definition: rpu_regs.h:231
#define MXC_R_RPU_TMR5
Offset from RPU Base Address: 0x0150
Definition: rpu_regs.h:235
#define MXC_R_RPU_I2C1
Offset from RPU Base Address: 0x01E0
Definition: rpu_regs.h:239
#define MXC_R_RPU_WDT0
Offset from RPU Base Address: 0x0030
Definition: rpu_regs.h:217
#define MXC_R_RPU_DVS
Offset from RPU Base Address: 0x0048
Definition: rpu_regs.h:222
#define MXC_R_RPU_ICACHEXIP
Offset from RPU Base Address: 0x02F0
Definition: rpu_regs.h:248
#define MXC_R_RPU_GPIO1
Offset from RPU Base Address: 0x0090
Definition: rpu_regs.h:229
#define MXC_R_RPU_TMR2
Offset from RPU Base Address: 0x0120
Definition: rpu_regs.h:232
#define MXC_R_RPU_DCACHE
Offset from RPU Base Address: 0x0330
Definition: rpu_regs.h:249
#define MXC_R_RPU_FLC0
Offset from RPU Base Address: 0x0290
Definition: rpu_regs.h:244
#define MXC_R_RPU_AUDIO
Offset from RPU Base Address: 0x04C0
Definition: rpu_regs.h:263
#define MXC_R_RPU_WDT2
Offset from RPU Base Address: 0x0038
Definition: rpu_regs.h:219
#define MXC_R_RPU_SEMA
Offset from RPU Base Address: 0x03E0
Definition: rpu_regs.h:257
#define MXC_R_RPU_FCR
Offset from RPU Base Address: 0x0008
Definition: rpu_regs.h:215
#define MXC_R_RPU_RTC
Offset from RPU Base Address: 0x0060
Definition: rpu_regs.h:224
#define MXC_R_RPU_I2C2
Offset from RPU Base Address: 0x01F0
Definition: rpu_regs.h:240
#define MXC_R_RPU_PT
Offset from RPU Base Address: 0x03C0
Definition: rpu_regs.h:255
#define MXC_R_RPU_GPIO0
Offset from RPU Base Address: 0x0080
Definition: rpu_regs.h:228
#define MXC_R_RPU_FLC1
Offset from RPU Base Address: 0x0294
Definition: rpu_regs.h:245
#define MXC_R_RPU_BTLE
Offset from RPU Base Address: 0x0500
Definition: rpu_regs.h:265
#define MXC_R_RPU_QSPI0
Offset from RPU Base Address: 0x0BE0
Definition: rpu_regs.h:269
#define MXC_R_RPU_SPIXIPM
Offset from RPU Base Address: 0x0260
Definition: rpu_regs.h:241
#define MXC_R_RPU_HTIMER0
Offset from RPU Base Address: 0x01B0
Definition: rpu_regs.h:236
#define MXC_R_RPU_SIMO
Offset from RPU Base Address: 0x0044
Definition: rpu_regs.h:221
#define MXC_R_RPU_TMR3
Offset from RPU Base Address: 0x0130
Definition: rpu_regs.h:233
#define MXC_R_RPU_USBHS
Offset from RPU Base Address: 0x0B10
Definition: rpu_regs.h:266
#define MXC_R_RPU_TMR4
Offset from RPU Base Address: 0x0140
Definition: rpu_regs.h:234
int RPU_Disallow(rpu_device_t periph, uint32_t disallow_mask)
Disable access to peripherals restricted by the RPU This function must be called from handler (privil...
#define MXC_R_RPU_SPIXIPMC
Offset from RPU Base Address: 0x0270
Definition: rpu_regs.h:242
#define MXC_R_RPU_ICACHE0
Offset from RPU Base Address: 0x02A0
Definition: rpu_regs.h:246
#define MXC_R_RPU_PWRSEQ
Offset from RPU Base Address: 0x0068
Definition: rpu_regs.h:226
#define MXC_R_RPU_SDMA
Offset from RPU Base Address: 0x0360
Definition: rpu_regs.h:252
#define MXC_R_RPU_OWM
Offset from RPU Base Address: 0x03D0
Definition: rpu_regs.h:256
#define MXC_R_RPU_GCR
Offset from RPU Base Address: 0x0000
Definition: rpu_regs.h:213
#define MXC_R_RPU_CRYPTO
Offset from RPU Base Address: 0x000C
Definition: rpu_regs.h:216
#define MXC_R_RPU_UART2
Offset from RPU Base Address: 0x0440
Definition: rpu_regs.h:260
#define MXC_R_RPU_TMR0
Offset from RPU Base Address: 0x0100
Definition: rpu_regs.h:230
#define MXC_R_RPU_DMA1
Offset from RPU Base Address: 0x0350
Definition: rpu_regs.h:251
#define MXC_R_RPU_WUT
Offset from RPU Base Address: 0x0064
Definition: rpu_regs.h:225
#define MXC_R_RPU_DMA0
Offset from RPU Base Address: 0x0280
Definition: rpu_regs.h:243
#define MXC_R_RPU_SMON
Offset from RPU Base Address: 0x0040
Definition: rpu_regs.h:220
#define MXC_R_RPU_SPIXIPMFIFO
Offset from RPU Base Address: 0x0BC0
Definition: rpu_regs.h:268
int RPU_Allow(rpu_device_t periph, uint32_t allow_mask)
Enable access to peripherals restricted by the RPU This function must be called from handler (privile...
#define MXC_R_RPU_QSPI2
Offset from RPU Base Address: 0x0480
Definition: rpu_regs.h:262
#define MXC_R_RPU_HTIMER1
Offset from RPU Base Address: 0x01C0
Definition: rpu_regs.h:237
#define MXC_R_RPU_UART1
Offset from RPU Base Address: 0x0430
Definition: rpu_regs.h:259
#define MXC_R_RPU_TRNG
Offset from RPU Base Address: 0x04D0
Definition: rpu_regs.h:264
#define MXC_R_RPU_SIR
Offset from RPU Base Address: 0x0004
Definition: rpu_regs.h:214
#define MXC_R_RPU_SPID
Offset from RPU Base Address: 0x03A0
Definition: rpu_regs.h:254
#define MXC_R_RPU_QSPI1
Offset from RPU Base Address: 0x0460
Definition: rpu_regs.h:261
int RPU_IsAllowed(void)
Check to see if this process is running in handler mode.
#define MXC_R_RPU_ADC
Offset from RPU Base Address: 0x0340
Definition: rpu_regs.h:250
#define MXC_R_RPU_UART0
Offset from RPU Base Address: 0x0420
Definition: rpu_regs.h:258