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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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SRAM0 Protection Register. More...
Macros | |
#define | MXC_F_RPU_SRAM0_DMA0ACNR_POS 0 |
SRAM0_DMA0ACNR Position. | |
#define | MXC_F_RPU_SRAM0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA0ACNR_POS)) |
SRAM0_DMA0ACNR Mask. | |
#define | MXC_F_RPU_SRAM0_DMA0ACNW_POS 1 |
SRAM0_DMA0ACNW Position. | |
#define | MXC_F_RPU_SRAM0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA0ACNW_POS)) |
SRAM0_DMA0ACNW Mask. | |
#define | MXC_F_RPU_SRAM0_DMA1ACNR_POS 2 |
SRAM0_DMA1ACNR Position. | |
#define | MXC_F_RPU_SRAM0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA1ACNR_POS)) |
SRAM0_DMA1ACNR Mask. | |
#define | MXC_F_RPU_SRAM0_DMA1ACNW_POS 3 |
SRAM0_DMA1ACNW Position. | |
#define | MXC_F_RPU_SRAM0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA1ACNW_POS)) |
SRAM0_DMA1ACNW Mask. | |
#define | MXC_F_RPU_SRAM0_USBACNR_POS 4 |
SRAM0_USBACNR Position. | |
#define | MXC_F_RPU_SRAM0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_USBACNR_POS)) |
SRAM0_USBACNR Mask. | |
#define | MXC_F_RPU_SRAM0_USBACNW_POS 5 |
SRAM0_USBACNW Position. | |
#define | MXC_F_RPU_SRAM0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_USBACNW_POS)) |
SRAM0_USBACNW Mask. | |
#define | MXC_F_RPU_SRAM0_SYS0ACNR_POS 6 |
SRAM0_SYS0ACNR Position. | |
#define | MXC_F_RPU_SRAM0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS0ACNR_POS)) |
SRAM0_SYS0ACNR Mask. | |
#define | MXC_F_RPU_SRAM0_SYS0ACNW_POS 7 |
SRAM0_SYS0ACNW Position. | |
#define | MXC_F_RPU_SRAM0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS0ACNW_POS)) |
SRAM0_SYS0ACNW Mask. | |
#define | MXC_F_RPU_SRAM0_SYS1ACNR_POS 8 |
SRAM0_SYS1ACNR Position. | |
#define | MXC_F_RPU_SRAM0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS1ACNR_POS)) |
SRAM0_SYS1ACNR Mask. | |
#define | MXC_F_RPU_SRAM0_SYS1ACNW_POS 9 |
SRAM0_SYS1ACNW Position. | |
#define | MXC_F_RPU_SRAM0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS1ACNW_POS)) |
SRAM0_SYS1ACNW Mask. | |
#define | MXC_F_RPU_SRAM0_SDMADACNR_POS 10 |
SRAM0_SDMADACNR Position. | |
#define | MXC_F_RPU_SRAM0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMADACNR_POS)) |
SRAM0_SDMADACNR Mask. | |
#define | MXC_F_RPU_SRAM0_SDMADACNW_POS 11 |
SRAM0_SDMADACNW Position. | |
#define | MXC_F_RPU_SRAM0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMADACNW_POS)) |
SRAM0_SDMADACNW Mask. | |
#define | MXC_F_RPU_SRAM0_SDMAIACNR_POS 12 |
SRAM0_SDMAIACNR Position. | |
#define | MXC_F_RPU_SRAM0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMAIACNR_POS)) |
SRAM0_SDMAIACNR Mask. | |
#define | MXC_F_RPU_SRAM0_SDMAIACNW_POS 13 |
SRAM0_SDMAIACNW Position. | |
#define | MXC_F_RPU_SRAM0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMAIACNW_POS)) |
SRAM0_SDMAIACNW Mask. | |
#define | MXC_F_RPU_SRAM0_CRYPTOACNR_POS 14 |
SRAM0_CRYPTOACNR Position. | |
#define | MXC_F_RPU_SRAM0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_CRYPTOACNR_POS)) |
SRAM0_CRYPTOACNR Mask. | |
#define | MXC_F_RPU_SRAM0_CRYPTOACNW_POS 15 |
SRAM0_CRYPTOACNW Position. | |
#define | MXC_F_RPU_SRAM0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_CRYPTOACNW_POS)) |
SRAM0_CRYPTOACNW Mask. | |
#define | MXC_F_RPU_SRAM0_SDIOACNR_POS 16 |
SRAM0_SDIOACNR Position. | |
#define | MXC_F_RPU_SRAM0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDIOACNR_POS)) |
SRAM0_SDIOACNR Mask. | |
#define | MXC_F_RPU_SRAM0_SDIOACNW_POS 17 |
SRAM0_SDIOACNW Position. | |
#define | MXC_F_RPU_SRAM0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDIOACNW_POS)) |
SRAM0_SDIOACNW Mask. | |