MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation

Source Device Address. More...

Macros

#define MXC_F_DMA_SRC_ADDR_POS   0
 SRC_ADDR Position.
 
#define MXC_F_DMA_SRC_ADDR   ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS))
 SRC_ADDR Mask.
 

Detailed Description

If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD.