45 #include "mxc_config.h" 46 #include "uart_regs.h" 53 #include "sdhc_regs.h" 55 #include "spixfc_regs.h" 56 #include "spi17y_regs.h" 57 #include "htmr_regs.h" 67 SYS_RESET_DMA = MXC_F_GCR_RSTR0_DMA_POS,
68 SYS_RESET_WDT = MXC_F_GCR_RSTR0_WDT_POS,
69 SYS_RESET_GPIO0 = MXC_F_GCR_RSTR0_GPIO0_POS,
70 SYS_RESET_GPIO1 = MXC_F_GCR_RSTR0_GPIO1_POS,
71 SYS_RESET_TIMER0 = MXC_F_GCR_RSTR0_TIMER0_POS,
72 SYS_RESET_TIMER1 = MXC_F_GCR_RSTR0_TIMER1_POS,
73 SYS_RESET_TIMER2 = MXC_F_GCR_RSTR0_TIMER2_POS,
74 SYS_RESET_TIMER3 = MXC_F_GCR_RSTR0_TIMER3_POS,
75 SYS_RESET_TIMER4 = MXC_F_GCR_RSTR0_TIMER4_POS,
76 SYS_RESET_TIMER5 = MXC_F_GCR_RSTR0_TIMER5_POS,
77 SYS_RESET_UART0 = MXC_F_GCR_RSTR0_UART0_POS,
78 SYS_RESET_UART1 = MXC_F_GCR_RSTR0_UART1_POS,
79 SYS_RESET_SPI1 = MXC_F_GCR_RSTR0_SPI0_POS,
80 SYS_RESET_SPI2 = MXC_F_GCR_RSTR0_SPI1_POS,
81 SYS_RESET_I2C0 = MXC_F_GCR_RSTR0_I2C0_POS,
82 SYS_RESET_RTC = MXC_F_GCR_RSTR0_RTC_POS,
83 SYS_RESET_CRYPTO = MXC_F_GCR_RSTR0_CRYPTO_POS,
84 SYS_RESET_USB = MXC_F_GCR_RSTR0_USB_POS,
85 SYS_RESET_TRNG = MXC_F_GCR_RSTR0_TRNG_POS,
86 SYS_RESET_ADC = MXC_F_GCR_RSTR0_ADC_POS,
87 SYS_RESET_UART2 = MXC_F_GCR_RSTR0_UART2_POS,
88 SYS_RESET_SRST = MXC_F_GCR_RSTR0_SRST_POS,
89 SYS_RESET_PRST = MXC_F_GCR_RSTR0_PRST_POS,
90 SYS_RESET_SYSTEM = MXC_F_GCR_RSTR0_SYSTEM_POS,
92 SYS_RESET_I2C1 = (MXC_F_GCR_RSTR1_I2C1_POS + 32),
93 SYS_RESET_PT = (MXC_F_GCR_RSTR1_PT_POS + 32),
94 SYS_RESET_SPIXIP = (MXC_F_GCR_RSTR1_SPIXIP_POS + 32),
95 SYS_RESET_XSPIM = (MXC_F_GCR_RSTR1_XSPIM_POS + 32),
96 SYS_RESET_SDHC = (MXC_F_GCR_RSTR1_SDHC_POS + 32),
97 SYS_RESET_OWIRE = (MXC_F_GCR_RSTR1_OWIRE_POS + 32),
98 SYS_RESET_HTR0 = (MXC_F_GCR_RSTR1_HTMR0_POS + 32),
99 SYS_RESET_HTMR1 = (MXC_F_GCR_RSTR1_HTMR1_POS + 32),
100 SYS_RESET_WDT1 = (MXC_F_GCR_RSTR1_WDT1_POS + 32),
101 SYS_RESET_SPI0 = (MXC_F_GCR_RSTR1_QSPI0_AHB_POS + 32),
102 SYS_RESET_SPIXMEM = (MXC_F_GCR_RSTR1_SPIXMEM_POS + 32),
103 SYS_RESET_SMPHR = (MXC_F_GCR_RSTR1_SMPHR_POS + 32),
108 SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PERCKCN0_GPIO0D_POS,
109 SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PERCKCN0_GPIO1D_POS,
110 SYS_PERIPH_CLOCK_USB = MXC_F_GCR_PERCKCN0_USBD_POS,
111 SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PERCKCN0_DMAD_POS,
112 SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PERCKCN0_SPI0D_POS,
113 SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PERCKCN0_SPI1D_POS,
114 SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PERCKCN0_UART0D_POS,
115 SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PERCKCN0_UART1D_POS,
116 SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PERCKCN0_I2C0D_POS,
117 SYS_PERIPH_CLOCK_TPU = MXC_F_GCR_PERCKCN0_CRYPTOD_POS,
118 SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_T0D_POS,
119 SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_T1D_POS,
120 SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_T2D_POS,
121 SYS_PERIPH_CLOCK_T3 = MXC_F_GCR_PERCKCN0_T3D_POS,
122 SYS_PERIPH_CLOCK_T4 = MXC_F_GCR_PERCKCN0_T4D_POS,
123 SYS_PERIPH_CLOCK_T5 = MXC_F_GCR_PERCKCN0_T5D_POS,
124 SYS_PERIPH_CLOCK_ADC = MXC_F_GCR_PERCKCN0_ADCD_POS,
125 SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PERCKCN0_I2C1D_POS,
126 SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PERCKCN0_PTD_POS,
127 SYS_PERIPH_CLOCK_SPIXIP = MXC_F_GCR_PERCKCN0_SPIXIPD_POS,
128 SYS_PERIPH_CLOCK_SPIXFC = MXC_F_GCR_PERCKCN0_SPIMD_POS,
130 SYS_PERIPH_CLOCK_BTLE =(MXC_F_GCR_PERCKCN1_BTLED_POS + 32),
131 SYS_PERIPH_CLOCK_UART2 =(MXC_F_GCR_PERCKCN1_UART2D_POS + 32),
132 SYS_PERIPH_CLOCK_TRNG =(MXC_F_GCR_PERCKCN1_TRNGD_POS + 32),
133 SYS_PERIPH_CLOCK_SCACHE =(MXC_F_GCR_PERCKCN1_SCACHED_POS + 32),
134 SYS_PERIPH_CLOCK_SDMA =(MXC_F_GCR_PERCKCN1_SDMAD_POS + 32),
135 SYS_PERIPH_CLOCK_SMPHR =(MXC_F_GCR_PERCKCN1_SMPHRD_POS + 32),
136 SYS_PERIPH_CLOCK_SDHC =(MXC_F_GCR_PERCKCN1_SDHCD_POS + 32),
137 SYS_PERIPH_CLOCK_ICACHEXIP =(MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS + 32),
138 SYS_PERIPH_CLOCK_OWIRE =(MXC_F_GCR_PERCKCN1_OWIRED_POS + 32),
139 SYS_PERIPH_CLOCK_SPI0 =(MXC_F_GCR_PERCKCN1_SPI3D_POS + 32),
140 SYS_PERIPH_CLOCK_SPIXIPD =(MXC_F_GCR_PERCKCN1_SPIXIPDD_POS + 32),
141 SYS_PERIPH_CLOCK_DMA1 =(MXC_F_GCR_PERCKCN1_DMA1_POS + 32),
142 SYS_PERIPH_CLOCK_AUDIO =(MXC_F_GCR_PERCKCN1_AUDIO_POS + 32),
143 SYS_PERIPH_CLOCK_I2C2 =(MXC_F_GCR_PERCKCN1_I2C2_POS + 32),
144 SYS_PERIPH_CLOCK_HTMR0 =(MXC_F_GCR_PERCKCN1_HTMR0_POS + 32),
145 SYS_PERIPH_CLOCK_HTMR1 =(MXC_F_GCR_PERCKCN1_HTMR1_POS + 32),
146 SYS_PERIPH_CLOCK_WDT0 =(MXC_F_GCR_PERCKCN1_WDT0_POS + 32),
147 SYS_PERIPH_CLOCK_WDT1 =(MXC_F_GCR_PERCKCN1_WDT1_POS + 32),
148 SYS_PERIPH_CLOCK_WDT2 =(MXC_F_GCR_PERCKCN1_WDT2_POS + 32),
149 SYS_PERIPH_CLOCK_CPU1 =(MXC_F_GCR_PERCKCN1_CPU1_POS + 32),
150 } sys_periph_clock_t;
153 SYS_CLOCK_HIRC96 = MXC_V_GCR_CLKCN_CLKSEL_HIRC96,
154 SYS_CLOCK_HIRC8 = MXC_V_GCR_CLKCN_CLKSEL_HIRC8,
155 SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC,
156 SYS_CLOCK_XTAL32M = MXC_V_GCR_CLKCN_CLKSEL_XTAL32M,
157 SYS_CLOCK_LIRC8K = MXC_V_GCR_CLKCN_CLKSEL_LIRC8,
158 SYS_CLOCK_XTAL32K = MXC_V_GCR_CLKCN_CLKSEL_XTAL32K,
159 } sys_system_clock_t;
161 #define SYS_SCACHE_CLK 1 // Enable SCACHE CLK 162 #define SYS_CRYPTO_CLK 1 // Enable CRYPTO CLK 174 typedef void* sys_cfg_t;
201 typedef sys_cfg_t sys_cfg_i2c_t;
204 typedef sys_cfg_t sys_cfg_sdhc_t;
207 typedef sys_cfg_t sys_cfg_owm_t;
210 typedef sys_cfg_t sys_cfg_scache_t;
213 typedef sys_cfg_t sys_cfg_usbhs_t;
216 typedef sys_cfg_t sys_cfg_rtc_t;
219 typedef sys_cfg_t sys_cfg_tpu_t;
222 typedef sys_cfg_t sys_cfg_tmr_t;
225 typedef sys_cfg_t sys_cfg_adc_t;
228 typedef sys_cfg_t sys_cfg_flc_t;
231 typedef sys_cfg_t sys_cfg_trng_t;
234 typedef sys_cfg_t sys_cfg_spixfc_t;
240 typedef sys_cfg_t sys_cfg_ptg_t;
243 typedef sys_cfg_t sys_cfg_htmr_t;
246 typedef sys_cfg_t sys_cfg_sema_t;
249 typedef sys_cfg_t sys_cfg_wdt_t;
252 typedef unsigned int sys_pt_clk_scale;
261 int SYS_IsClockEnabled(sys_periph_clock_t clock);
267 void SYS_ClockDisable(sys_periph_clock_t clock);
273 void SYS_ClockEnable(sys_periph_clock_t clock);
279 void SYS_RTCClockEnable(sys_cfg_rtc_t *sys_cfg);
285 int SYS_RTCClockDisable(
void);
292 int SYS_ClockSourceEnable(sys_system_clock_t clock);
299 int SYS_ClockSourceDisable(sys_system_clock_t clock);
307 int SYS_Clock_Select(sys_system_clock_t clock,
mxc_tmr_regs_t* tmr);
332 int SYS_I2C_Init(
mxc_i2c_regs_t *i2c,
const sys_cfg_i2c_t* sys_cfg);
353 int SYS_PT_Config(
mxc_pt_regs_t *pt,
const sys_cfg_pt_t *cfg);
359 void SYS_PT_Init(
const sys_cfg_ptg_t* sys_cfg);
364 void SYS_PT_Shutdown(
void);
370 unsigned SYS_PT_GetFreq(
void);
380 void SYS_Flash_Operation(
void);
385 void SYS_Reset_Periph(sys_reset_t reset);
391 int SYS_SDHC_Init(
const sys_cfg_sdhc_t* sys_cfg);
397 int SYS_SDHC_Shutdown(
void);
403 int SYS_SEMA_Init(
const sys_cfg_sema_t* sys_cfg);
409 int SYS_SEMA_Shutdown(
void);
440 uint32_t SYS_OWM_Init(
const sys_cfg_owm_t* sys_cfg);
445 void SYS_OWM_Shutdown(
void);
451 uint32_t SYS_OWM_GetFreq(
void);
463 void SYS_SPIXR_Shutdown(
void);
469 void SYS_SCACHE_Init(
const sys_cfg_scache_t* sys_cfg);
474 void SYS_SCACHE_Shutdown(
void);
494 void SYS_RTC_SqwavInit(
const sys_cfg_rtc_t* sys_cfg);
501 int SYS_USBHS_Init(
const sys_cfg_usbhs_t* sys_cfg);
507 int SYS_USBHS_Shutdown(
void);
511 void SYS_DMA_Init(
void);
516 void SYS_DMA_Shutdown(
void);
522 int SYS_TMR_Init(
mxc_tmr_regs_t *tmr,
const sys_cfg_tmr_t* sys_cfg);
533 int SYS_TPU_Init(
const sys_cfg_tpu_t* sys_cfg);
538 int SYS_TPU_Shutdown(
void);
544 int SYS_ADC_Init(
const sys_cfg_adc_t* sys_cfg);
549 int SYS_ADC_Shutdown(
void);
554 int SYS_FLC_Init(
const sys_cfg_flc_t* sys_cfg);
573 int SYS_FLC_GetPhysicalAddress( uint32_t addr, uint32_t *result);
578 int SYS_FLC_Shutdown(
void);
584 int SYS_TRNG_Init(
const sys_cfg_trng_t* sys_cfg);
589 int SYS_TRNG_Shutdown(
void);
608 int SYS_WDT_Init(
mxc_wdt_regs_t *wdt,
const sys_cfg_wdt_t* sys_cfg);
Structure type for configuring a GPIO port.
Definition: gpio.h:138
Structure type to access the WDT Registers.
Definition: wdt_regs.h:88
UART Configuration Object.
Definition: mxc_sys.h:186
SPIXR Configuration Object.
Definition: mxc_sys.h:193
Structure type to access the HTMR Registers.
Definition: htmr_regs.h:88
int SYS_UART_Shutdown(mxc_uart_regs_t *uart)
System level shutdown for UART module.
SPI17Y Configuration Object.
Definition: mxc_sys.h:177
Structure type to access the UART Registers.
Definition: uart_regs.h:88
Structure type to access the I2C Registers.
Definition: i2c_regs.h:88
Structure type to access the FLC Registers.
Definition: flc_regs.h:88
Structure type to access the SPI17Y Registers.
Definition: spi17y_regs.h:88
Structure type to access the TMR Registers.
Definition: tmr_regs.h:88
Structure type to access the PT Registers.
Definition: pt_regs.h:88
Structure type to access the SPIXFC Registers.
Definition: spixfc_regs.h:88