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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. More...
Modules | |
Register Offsets | |
GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. | |
GPIO_EN | |
GPIO Function Enable Register. | |
GPIO_EN_SET | |
GPIO Set Function Enable Register. | |
GPIO_EN_CLR | |
GPIO Clear Function Enable Register. | |
GPIO_OUT_EN | |
GPIO Output Enable Register. | |
GPIO_OUT_EN_SET | |
GPIO Output Enable Set Function Enable Register. | |
GPIO_OUT_EN_CLR | |
GPIO Output Enable Clear Function Enable Register. | |
GPIO_OUT | |
GPIO Output Register. | |
GPIO_OUT_SET | |
GPIO Output Set. | |
GPIO_OUT_CLR | |
GPIO Output Clear. | |
GPIO_IN | |
GPIO Input Register. | |
GPIO_INT_MOD | |
GPIO Interrupt Mode Register. | |
GPIO_INT_POL | |
GPIO Interrupt Polarity Register. | |
GPIO_INT_EN | |
GPIO Interrupt Enable Register. | |
GPIO_INT_EN_SET | |
GPIO Interrupt Enable Set. | |
GPIO_INT_EN_CLR | |
GPIO Interrupt Enable Clear. | |
GPIO_INT_STAT | |
GPIO Interrupt Status Register. | |
GPIO_INT_CLR | |
GPIO Status Clear. | |
GPIO_WAKE_EN | |
GPIO Wake Enable Register. | |
GPIO_WAKE_EN_SET | |
GPIO Wake Enable Set. | |
GPIO_WAKE_EN_CLR | |
GPIO Wake Enable Clear. | |
GPIO_INT_DUAL_EDGE | |
GPIO Interrupt Dual Edge Mode Register. | |
GPIO_PAD_CFG1 | |
GPIO Input Mode Config 1. | |
GPIO_PAD_CFG2 | |
GPIO Input Mode Config 2. | |
GPIO_EN1 | |
GPIO Alternate Function Enable Register. | |
GPIO_EN1_SET | |
GPIO Alternate Function Set. | |
GPIO_EN1_CLR | |
GPIO Alternate Function Clear. | |
GPIO_EN2 | |
GPIO Alternate Function Enable Register. | |
GPIO_EN2_SET | |
GPIO Alternate Function 2 Set. | |
GPIO_EN2_CLR | |
GPIO Wake Alternate Function Clear. | |
GPIO_DS | |
GPIO Drive Strength Register. | |
GPIO_DS1 | |
GPIO Drive Strength 1 Register. | |
GPIO_PS | |
GPIO Pull Select Mode. | |
GPIO_VSSEL | |
GPIO Voltage Select. | |
Data Structures | |
struct | mxc_gpio_regs_t |
Structure type to access the GPIO Registers. More... | |
Individual I/O for each GPIO