40 #ifndef _PWRSEQ_REGS_H_ 41 #define _PWRSEQ_REGS_H_ 50 #if defined (__ICCARM__) 51 #pragma system_include 54 #if defined (__CC_ARM) 65 #define __I volatile const 71 #define __R volatile const 98 __R uint32_t rsv_0x24_0x2f[3];
101 __R uint32_t rsv_0x38_0x3f[2];
117 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) 118 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) 119 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) 120 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) 121 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) 122 #define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL) 123 #define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) 124 #define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL) 125 #define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) 126 #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) 127 #define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) 128 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) 129 #define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) 130 #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) 131 #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) 132 #define MXC_R_PWRSEQ_LPMCSTAT ((uint32_t)0x00000050UL) 133 #define MXC_R_PWRSEQ_LPMCREQ ((uint32_t)0x00000054UL) 142 #define MXC_F_PWRSEQ_LPCN_RAMRET_POS 0 143 #define MXC_F_PWRSEQ_LPCN_RAMRET ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS)) 144 #define MXC_V_PWRSEQ_LPCN_RAMRET_DIS ((uint32_t)0x0UL) 145 #define MXC_S_PWRSEQ_LPCN_RAMRET_DIS (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 146 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN1 ((uint32_t)0x1UL) 147 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN1 (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 148 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN2 ((uint32_t)0x2UL) 149 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN2 (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 150 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN3 ((uint32_t)0x3UL) 151 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN3 (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 153 #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 154 #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) 155 #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) 156 #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) 157 #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) 158 #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) 159 #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) 160 #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) 162 #define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6 163 #define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS)) 165 #define MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7 166 #define MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS)) 168 #define MXC_F_PWRSEQ_LPCN_RREGEN_POS 8 169 #define MXC_F_PWRSEQ_LPCN_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RREGEN_POS)) 171 #define MXC_F_PWRSEQ_LPCN_BCKGRND_POS 9 172 #define MXC_F_PWRSEQ_LPCN_BCKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) 174 #define MXC_F_PWRSEQ_LPCN_FWKM_POS 10 175 #define MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS)) 177 #define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 178 #define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) 180 #define MXC_F_PWRSEQ_LPCN_VDDCMD_POS 20 181 #define MXC_F_PWRSEQ_LPCN_VDDCMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDCMD_POS)) 183 #define MXC_F_PWRSEQ_LPCN_VRTCMD_POS 21 184 #define MXC_F_PWRSEQ_LPCN_VRTCMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRTCMD_POS)) 186 #define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22 187 #define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) 189 #define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23 190 #define MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) 192 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24 193 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) 195 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25 196 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) 198 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26 199 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) 201 #define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27 202 #define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) 213 #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS 0 214 #define MXC_F_PWRSEQ_LPWKST0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) 225 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 226 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) 236 #define MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS 0 237 #define MXC_F_PWRSEQ_LPPWST_USBLSWKST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS)) 239 #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS 2 240 #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS)) 242 #define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS 3 243 #define MXC_F_PWRSEQ_LPPWST_SDMAWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) 245 #define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS 16 246 #define MXC_F_PWRSEQ_LPPWST_BBMODEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) 256 #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS 0 257 #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS)) 259 #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS 2 260 #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS)) 262 #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS 3 263 #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) 273 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS 0 274 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) 276 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS 1 277 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) 279 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS 2 280 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) 282 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS 3 283 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) 285 #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS 4 286 #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS)) 288 #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS 5 289 #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) 291 #define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS 6 292 #define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS)) 294 #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS 7 295 #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) 297 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS 8 298 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) 300 #define MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS 9 301 #define MXC_F_PWRSEQ_LPMEMSD_SCACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS)) 303 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS 10 304 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) 306 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS 11 307 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS)) 309 #define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS 12 310 #define MXC_F_PWRSEQ_LPMEMSD_ROMSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS)) 312 #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS 13 313 #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS)) 315 #define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS 14 316 #define MXC_F_PWRSEQ_LPMEMSD_IC1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS)) 326 #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS 0 327 #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS)) 329 #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS 1 330 #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS)) 332 #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS 8 333 #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS)) 335 #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS 9 336 #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS)) 338 #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS 10 339 #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS)) 341 #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS 11 342 #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS)) __IO uint32_t lpwkst2
0x14: PWRSEQ LPWKST2 Register
Definition: pwrseq_regs.h:94
__IO uint32_t lpvddpd
0x44: PWRSEQ LPVDDPD Register
Definition: pwrseq_regs.h:103
__IO uint32_t lpmemsd
0x40: PWRSEQ LPMEMSD Register
Definition: pwrseq_regs.h:102
__IO uint32_t lpwken1
0x10: PWRSEQ LPWKEN1 Register
Definition: pwrseq_regs.h:93
__IO uint32_t lpmcreq
0x54: PWRSEQ LPMCREQ Register
Definition: pwrseq_regs.h:107
__IO uint32_t lppwen
0x34: PWRSEQ LPPWEN Register
Definition: pwrseq_regs.h:100
__IO uint32_t lpwken0
0x08: PWRSEQ LPWKEN0 Register
Definition: pwrseq_regs.h:91
__IO uint32_t lppwst
0x30: PWRSEQ LPPWST Register
Definition: pwrseq_regs.h:99
__IO uint32_t lpwken3
0x20: PWRSEQ LPWKEN3 Register
Definition: pwrseq_regs.h:97
__IO uint32_t lpwken2
0x18: PWRSEQ LPWKEN2 Register
Definition: pwrseq_regs.h:95
__IO uint32_t lpwkst0
0x04: PWRSEQ LPWKST0 Register
Definition: pwrseq_regs.h:90
__IO uint32_t gp0
0x48: PWRSEQ GP0 Register
Definition: pwrseq_regs.h:104
__IO uint32_t lpcn
0x00: PWRSEQ LPCN Register
Definition: pwrseq_regs.h:89
__IO uint32_t gp1
0x4C: PWRSEQ GP1 Register
Definition: pwrseq_regs.h:105
__IO uint32_t lpwkst1
0x0C: PWRSEQ LPWKST1 Register
Definition: pwrseq_regs.h:92
Structure type to access the PWRSEQ Registers.
Definition: pwrseq_regs.h:88
__IO uint32_t lpmcstat
0x50: PWRSEQ LPMCSTAT Register
Definition: pwrseq_regs.h:106
__IO uint32_t lpwkst3
0x1C: PWRSEQ LPWKST3 Register
Definition: pwrseq_regs.h:96