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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module. More...
Modules | |
Register Offsets | |
SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address. | |
SDHC_SDMA | |
SDMA System Address / Argument 2. | |
SDHC_BLK_SIZE | |
Block Size. | |
SDHC_BLK_CNT | |
Block Count. | |
SDHC_ARG_1 | |
Argument 1. | |
SDHC_TRANS | |
Transfer Mode. | |
SDHC_CMD | |
Command. | |
SDHC_RESP | |
Response 0 Register 0-15. | |
SDHC_BUFFER | |
Buffer Data Port. | |
SDHC_PRESENT | |
Present State. | |
SDHC_HOST_CN_1 | |
Host Control 1. | |
SDHC_PWR | |
Power Control. | |
SDHC_BLK_GAP | |
Block Gap Control. | |
SDHC_WAKEUP | |
Wakeup Control. | |
SDHC_CLK_CN | |
Clock Control. | |
SDHC_TO | |
Timeout Control. | |
SDHC_SW_RESET | |
Software Reset. | |
SDHC_INT_STAT | |
Normal Interrupt Status. | |
SDHC_ER_INT_STAT | |
Error Interrupt Status. | |
SDHC_INT_EN | |
Normal Interrupt Status Enable. | |
SDHC_ER_INT_EN | |
Error Interrupt Status Enable. | |
SDHC_INT_SIGNAL | |
Normal Interrupt Signal Enable. | |
SDHC_ER_INT_SIGNAL | |
Error Interrupt Signal Enable. | |
SDHC_AUTO_CMD_ER | |
Auto CMD Error Status. | |
SDHC_HOST_CN_2 | |
Host Control 2. | |
SDHC_CFG_0 | |
Capabilities 0-31. | |
SDHC_CFG_1 | |
Capabilities 32-63. | |
SDHC_MAX_CURR_CFG | |
Maximum Current Capabilities. | |
SDHC_FORCE_CMD | |
Force Event for Auto CMD Error Status. | |
SDHC_FORCE_EVENT_INT_STAT | |
Force Event for Error Interrupt Status. | |
SDHC_ADMA_ER | |
ADMA Error Status. | |
SDHC_ADMA_ADDR_0 | |
ADMA System Address 0-31. | |
SDHC_ADMA_ADDR_1 | |
ADMA System Address 32-63. | |
SDHC_PRESET_0 | |
Preset Value for Initialization. | |
SDHC_PRESET_1 | |
Preset Value for Default Speed. | |
SDHC_PRESET_2 | |
Preset Value for High Speed. | |
SDHC_PRESET_3 | |
Preset Value for SDR12. | |
SDHC_PRESET_4 | |
Preset Value for SDR25. | |
SDHC_PRESET_5 | |
Preset Value for SDR50. | |
SDHC_PRESET_6 | |
Preset Value for SDR104. | |
SDHC_PRESET_7 | |
Preset Value for DDR50. | |
SDHC_SLOT_INT | |
Slot Interrupt Status. | |
SDHC_HOST_CN_VER | |
Host Controller Version. | |
Data Structures | |
struct | mxc_sdhc_regs_t |
Structure type to access the SDHC Registers. More... | |
SDHC/SDIO Controller