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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Cipher Control Register. More...
Macros | |
#define | MXC_F_TPU_CIPHER_CTRL_ENC_POS 0 |
CIPHER_CTRL_ENC Position. | |
#define | MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS)) |
CIPHER_CTRL_ENC Mask. | |
#define | MXC_F_TPU_CIPHER_CTRL_KEY_POS 1 |
CIPHER_CTRL_KEY Position. | |
#define | MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS)) |
CIPHER_CTRL_KEY Mask. | |
#define | MXC_F_TPU_CIPHER_CTRL_SRC_POS 2 |
CIPHER_CTRL_SRC Position. | |
#define | MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS)) |
CIPHER_CTRL_SRC Mask. | |
#define | MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) |
CIPHER_CTRL_SRC_CIPHERKEY Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS) |
CIPHER_CTRL_SRC_CIPHERKEY Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) |
CIPHER_CTRL_SRC_REGFILE Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) |
CIPHER_CTRL_SRC_REGFILE Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) |
CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) |
CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting. | |
#define | MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4 |
CIPHER_CTRL_CIPHER Position. | |
#define | MXC_F_TPU_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) |
CIPHER_CTRL_CIPHER Mask. | |
#define | MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) |
CIPHER_CTRL_CIPHER_DIS Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) |
CIPHER_CTRL_CIPHER_DIS Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) |
CIPHER_CTRL_CIPHER_AES128 Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) |
CIPHER_CTRL_CIPHER_AES128 Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) |
CIPHER_CTRL_CIPHER_AES192 Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) |
CIPHER_CTRL_CIPHER_AES192 Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) |
CIPHER_CTRL_CIPHER_AES256 Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) |
CIPHER_CTRL_CIPHER_AES256 Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) |
CIPHER_CTRL_CIPHER_DES Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_CIPHER_DES (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) |
CIPHER_CTRL_CIPHER_DES Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) |
CIPHER_CTRL_CIPHER_TDES Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) |
CIPHER_CTRL_CIPHER_TDES Setting. | |
#define | MXC_F_TPU_CIPHER_CTRL_MODE_POS 8 |
CIPHER_CTRL_MODE Position. | |
#define | MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS)) |
CIPHER_CTRL_MODE Mask. | |
#define | MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) |
CIPHER_CTRL_MODE_ECB Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_MODE_ECB (MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
CIPHER_CTRL_MODE_ECB Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) |
CIPHER_CTRL_MODE_CBC Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_MODE_CBC (MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
CIPHER_CTRL_MODE_CBC Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) |
CIPHER_CTRL_MODE_CFB Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_MODE_CFB (MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
CIPHER_CTRL_MODE_CFB Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) |
CIPHER_CTRL_MODE_OFB Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_MODE_OFB (MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
CIPHER_CTRL_MODE_OFB Setting. | |
#define | MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) |
CIPHER_CTRL_MODE_CTR Value. | |
#define | MXC_S_TPU_CIPHER_CTRL_MODE_CTR (MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
CIPHER_CTRL_MODE_CTR Setting. | |