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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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QSPI1 Protection Register. More...
Macros | |
#define | MXC_F_RPU_QSPI1_DMA0ACN_POS 0 |
QSPI1_DMA0ACN Position. | |
#define | MXC_F_RPU_QSPI1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_DMA0ACN_POS)) |
QSPI1_DMA0ACN Mask. | |
#define | MXC_F_RPU_QSPI1_DMA1ACN_POS 1 |
QSPI1_DMA1ACN Position. | |
#define | MXC_F_RPU_QSPI1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_DMA1ACN_POS)) |
QSPI1_DMA1ACN Mask. | |
#define | MXC_F_RPU_QSPI1_USBACN_POS 2 |
QSPI1_USBACN Position. | |
#define | MXC_F_RPU_QSPI1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_USBACN_POS)) |
QSPI1_USBACN Mask. | |
#define | MXC_F_RPU_QSPI1_SYS0ACN_POS 3 |
QSPI1_SYS0ACN Position. | |
#define | MXC_F_RPU_QSPI1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SYS0ACN_POS)) |
QSPI1_SYS0ACN Mask. | |
#define | MXC_F_RPU_QSPI1_SYS1ACN_POS 4 |
QSPI1_SYS1ACN Position. | |
#define | MXC_F_RPU_QSPI1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SYS1ACN_POS)) |
QSPI1_SYS1ACN Mask. | |
#define | MXC_F_RPU_QSPI1_SDMADACN_POS 5 |
QSPI1_SDMADACN Position. | |
#define | MXC_F_RPU_QSPI1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SDMADACN_POS)) |
QSPI1_SDMADACN Mask. | |
#define | MXC_F_RPU_QSPI1_SDMAIACN_POS 6 |
QSPI1_SDMAIACN Position. | |
#define | MXC_F_RPU_QSPI1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SDMAIACN_POS)) |
QSPI1_SDMAIACN Mask. | |
#define | MXC_F_RPU_QSPI1_CRYPTOACN_POS 7 |
QSPI1_CRYPTOACN Position. | |
#define | MXC_F_RPU_QSPI1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_CRYPTOACN_POS)) |
QSPI1_CRYPTOACN Mask. | |
#define | MXC_F_RPU_QSPI1_SDIOACN_POS 8 |
QSPI1_SDIOACN Position. | |
#define | MXC_F_RPU_QSPI1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SDIOACN_POS)) |
QSPI1_SDIOACN Mask. | |