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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Capabilities 0-31. More...
Macros | |
#define | MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS 0 |
CFG_0_TO_CLK_FREQ Position. | |
#define | MXC_F_SDHC_CFG_0_TO_CLK_FREQ ((uint32_t)(0x3FUL << MXC_F_SDHC_CFG_0_TO_CLK_FREQ_POS)) |
CFG_0_TO_CLK_FREQ Mask. | |
#define | MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS 7 |
CFG_0_TO_CLK_UNIT Position. | |
#define | MXC_F_SDHC_CFG_0_TO_CLK_UNIT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_TO_CLK_UNIT_POS)) |
CFG_0_TO_CLK_UNIT Mask. | |
#define | MXC_F_SDHC_CFG_0_CLK_FREQ_POS 8 |
CFG_0_CLK_FREQ Position. | |
#define | MXC_F_SDHC_CFG_0_CLK_FREQ ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_0_CLK_FREQ_POS)) |
CFG_0_CLK_FREQ Mask. | |
#define | MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS 16 |
CFG_0_MAX_BLK_LEN Position. | |
#define | MXC_F_SDHC_CFG_0_MAX_BLK_LEN ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_MAX_BLK_LEN_POS)) |
CFG_0_MAX_BLK_LEN Mask. | |
#define | MXC_F_SDHC_CFG_0_BIT_8_POS 18 |
CFG_0_BIT_8 Position. | |
#define | MXC_F_SDHC_CFG_0_BIT_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_8_POS)) |
CFG_0_BIT_8 Mask. | |
#define | MXC_F_SDHC_CFG_0_ADMA2_POS 19 |
CFG_0_ADMA2 Position. | |
#define | MXC_F_SDHC_CFG_0_ADMA2 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ADMA2_POS)) |
CFG_0_ADMA2 Mask. | |
#define | MXC_F_SDHC_CFG_0_HS_POS 21 |
CFG_0_HS Position. | |
#define | MXC_F_SDHC_CFG_0_HS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_HS_POS)) |
CFG_0_HS Mask. | |
#define | MXC_F_SDHC_CFG_0_SDMA_POS 22 |
CFG_0_SDMA Position. | |
#define | MXC_F_SDHC_CFG_0_SDMA ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SDMA_POS)) |
CFG_0_SDMA Mask. | |
#define | MXC_F_SDHC_CFG_0_SUSPEND_POS 23 |
CFG_0_SUSPEND Position. | |
#define | MXC_F_SDHC_CFG_0_SUSPEND ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_SUSPEND_POS)) |
CFG_0_SUSPEND Mask. | |
#define | MXC_F_SDHC_CFG_0_V3_3_POS 24 |
CFG_0_V3_3 Position. | |
#define | MXC_F_SDHC_CFG_0_V3_3 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_3_POS)) |
CFG_0_V3_3 Mask. | |
#define | MXC_F_SDHC_CFG_0_V3_0_POS 25 |
CFG_0_V3_0 Position. | |
#define | MXC_F_SDHC_CFG_0_V3_0 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V3_0_POS)) |
CFG_0_V3_0 Mask. | |
#define | MXC_F_SDHC_CFG_0_V1_8_POS 26 |
CFG_0_V1_8 Position. | |
#define | MXC_F_SDHC_CFG_0_V1_8 ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_V1_8_POS)) |
CFG_0_V1_8 Mask. | |
#define | MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS 28 |
CFG_0_BIT_64_SYS_BUS Position. | |
#define | MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_BIT_64_SYS_BUS_POS)) |
CFG_0_BIT_64_SYS_BUS Mask. | |
#define | MXC_F_SDHC_CFG_0_ASYNC_INT_POS 29 |
CFG_0_ASYNC_INT Position. | |
#define | MXC_F_SDHC_CFG_0_ASYNC_INT ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_0_ASYNC_INT_POS)) |
CFG_0_ASYNC_INT Mask. | |
#define | MXC_F_SDHC_CFG_0_SLOT_TYPE_POS 30 |
CFG_0_SLOT_TYPE Position. | |
#define | MXC_F_SDHC_CFG_0_SLOT_TYPE ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_0_SLOT_TYPE_POS)) |
CFG_0_SLOT_TYPE Mask. | |