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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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RPU Peripheral Register Offsets from the RPU Base Peripheral Address. More...
Macros | |
#define | MXC_R_RPU_GCR ((uint32_t)0x00000000UL) |
Offset from RPU Base Address: 0x0000 | |
#define | MXC_R_RPU_SIR ((uint32_t)0x00000004UL) |
Offset from RPU Base Address: 0x0004 | |
#define | MXC_R_RPU_FCR ((uint32_t)0x00000008UL) |
Offset from RPU Base Address: 0x0008 | |
#define | MXC_R_RPU_CRYPTO ((uint32_t)0x0000000CUL) |
Offset from RPU Base Address: 0x000C | |
#define | MXC_R_RPU_WDT0 ((uint32_t)0x00000030UL) |
Offset from RPU Base Address: 0x0030 | |
#define | MXC_R_RPU_WDT1 ((uint32_t)0x00000034UL) |
Offset from RPU Base Address: 0x0034 | |
#define | MXC_R_RPU_WDT2 ((uint32_t)0x00000038UL) |
Offset from RPU Base Address: 0x0038 | |
#define | MXC_R_RPU_SMON ((uint32_t)0x00000040UL) |
Offset from RPU Base Address: 0x0040 | |
#define | MXC_R_RPU_SIMO ((uint32_t)0x00000044UL) |
Offset from RPU Base Address: 0x0044 | |
#define | MXC_R_RPU_DVS ((uint32_t)0x00000048UL) |
Offset from RPU Base Address: 0x0048 | |
#define | MXC_R_RPU_BBSIR ((uint32_t)0x00000054UL) |
Offset from RPU Base Address: 0x0054 | |
#define | MXC_R_RPU_RTC ((uint32_t)0x00000060UL) |
Offset from RPU Base Address: 0x0060 | |
#define | MXC_R_RPU_WUT ((uint32_t)0x00000064UL) |
Offset from RPU Base Address: 0x0064 | |
#define | MXC_R_RPU_PWRSEQ ((uint32_t)0x00000068UL) |
Offset from RPU Base Address: 0x0068 | |
#define | MXC_R_RPU_BBCR ((uint32_t)0x0000006CUL) |
Offset from RPU Base Address: 0x006C | |
#define | MXC_R_RPU_GPIO0 ((uint32_t)0x00000080UL) |
Offset from RPU Base Address: 0x0080 | |
#define | MXC_R_RPU_GPIO1 ((uint32_t)0x00000090UL) |
Offset from RPU Base Address: 0x0090 | |
#define | MXC_R_RPU_TMR0 ((uint32_t)0x00000100UL) |
Offset from RPU Base Address: 0x0100 | |
#define | MXC_R_RPU_TMR1 ((uint32_t)0x00000110UL) |
Offset from RPU Base Address: 0x0110 | |
#define | MXC_R_RPU_TMR2 ((uint32_t)0x00000120UL) |
Offset from RPU Base Address: 0x0120 | |
#define | MXC_R_RPU_TMR3 ((uint32_t)0x00000130UL) |
Offset from RPU Base Address: 0x0130 | |
#define | MXC_R_RPU_TMR4 ((uint32_t)0x00000140UL) |
Offset from RPU Base Address: 0x0140 | |
#define | MXC_R_RPU_TMR5 ((uint32_t)0x00000150UL) |
Offset from RPU Base Address: 0x0150 | |
#define | MXC_R_RPU_HTIMER0 ((uint32_t)0x000001B0UL) |
Offset from RPU Base Address: 0x01B0 | |
#define | MXC_R_RPU_HTIMER1 ((uint32_t)0x000001C0UL) |
Offset from RPU Base Address: 0x01C0 | |
#define | MXC_R_RPU_I2C0 ((uint32_t)0x000001D0UL) |
Offset from RPU Base Address: 0x01D0 | |
#define | MXC_R_RPU_I2C1 ((uint32_t)0x000001E0UL) |
Offset from RPU Base Address: 0x01E0 | |
#define | MXC_R_RPU_I2C2 ((uint32_t)0x000001F0UL) |
Offset from RPU Base Address: 0x01F0 | |
#define | MXC_R_RPU_SPIXIPM ((uint32_t)0x00000260UL) |
Offset from RPU Base Address: 0x0260 | |
#define | MXC_R_RPU_SPIXIPMC ((uint32_t)0x00000270UL) |
Offset from RPU Base Address: 0x0270 | |
#define | MXC_R_RPU_DMA0 ((uint32_t)0x00000280UL) |
Offset from RPU Base Address: 0x0280 | |
#define | MXC_R_RPU_FLC0 ((uint32_t)0x00000290UL) |
Offset from RPU Base Address: 0x0290 | |
#define | MXC_R_RPU_FLC1 ((uint32_t)0x00000294UL) |
Offset from RPU Base Address: 0x0294 | |
#define | MXC_R_RPU_ICACHE0 ((uint32_t)0x000002A0UL) |
Offset from RPU Base Address: 0x02A0 | |
#define | MXC_R_RPU_ICACHE1 ((uint32_t)0x000002A4UL) |
Offset from RPU Base Address: 0x02A4 | |
#define | MXC_R_RPU_ICACHEXIP ((uint32_t)0x000002F0UL) |
Offset from RPU Base Address: 0x02F0 | |
#define | MXC_R_RPU_DCACHE ((uint32_t)0x00000330UL) |
Offset from RPU Base Address: 0x0330 | |
#define | MXC_R_RPU_ADC ((uint32_t)0x00000340UL) |
Offset from RPU Base Address: 0x0340 | |
#define | MXC_R_RPU_DMA1 ((uint32_t)0x00000350UL) |
Offset from RPU Base Address: 0x0350 | |
#define | MXC_R_RPU_SDMA ((uint32_t)0x00000360UL) |
Offset from RPU Base Address: 0x0360 | |
#define | MXC_R_RPU_SDHCCTRL ((uint32_t)0x00000370UL) |
Offset from RPU Base Address: 0x0370 | |
#define | MXC_R_RPU_SPID ((uint32_t)0x000003A0UL) |
Offset from RPU Base Address: 0x03A0 | |
#define | MXC_R_RPU_PT ((uint32_t)0x000003C0UL) |
Offset from RPU Base Address: 0x03C0 | |
#define | MXC_R_RPU_OWM ((uint32_t)0x000003D0UL) |
Offset from RPU Base Address: 0x03D0 | |
#define | MXC_R_RPU_SEMA ((uint32_t)0x000003E0UL) |
Offset from RPU Base Address: 0x03E0 | |
#define | MXC_R_RPU_UART0 ((uint32_t)0x00000420UL) |
Offset from RPU Base Address: 0x0420 | |
#define | MXC_R_RPU_UART1 ((uint32_t)0x00000430UL) |
Offset from RPU Base Address: 0x0430 | |
#define | MXC_R_RPU_UART2 ((uint32_t)0x00000440UL) |
Offset from RPU Base Address: 0x0440 | |
#define | MXC_R_RPU_QSPI1 ((uint32_t)0x00000460UL) |
Offset from RPU Base Address: 0x0460 | |
#define | MXC_R_RPU_QSPI2 ((uint32_t)0x00000480UL) |
Offset from RPU Base Address: 0x0480 | |
#define | MXC_R_RPU_AUDIO ((uint32_t)0x000004C0UL) |
Offset from RPU Base Address: 0x04C0 | |
#define | MXC_R_RPU_TRNG ((uint32_t)0x000004D0UL) |
Offset from RPU Base Address: 0x04D0 | |
#define | MXC_R_RPU_BTLE ((uint32_t)0x00000500UL) |
Offset from RPU Base Address: 0x0500 | |
#define | MXC_R_RPU_USBHS ((uint32_t)0x00000B10UL) |
Offset from RPU Base Address: 0x0B10 | |
#define | MXC_R_RPU_SDIO ((uint32_t)0x00000B60UL) |
Offset from RPU Base Address: 0x0B60 | |
#define | MXC_R_RPU_SPIXIPMFIFO ((uint32_t)0x00000BC0UL) |
Offset from RPU Base Address: 0x0BC0 | |
#define | MXC_R_RPU_QSPI0 ((uint32_t)0x00000BE0UL) |
Offset from RPU Base Address: 0x0BE0 | |
#define | MXC_R_RPU_SRAM0 ((uint32_t)0x00000F00UL) |
Offset from RPU Base Address: 0x0F00 | |
#define | MXC_R_RPU_SRAM1 ((uint32_t)0x00000F10UL) |
Offset from RPU Base Address: 0x0F10 | |
#define | MXC_R_RPU_SRAM2 ((uint32_t)0x00000F20UL) |
Offset from RPU Base Address: 0x0F20 | |
#define | MXC_R_RPU_SRAM3 ((uint32_t)0x00000F30UL) |
Offset from RPU Base Address: 0x0F30 | |
#define | MXC_R_RPU_SRAM4 ((uint32_t)0x00000F40UL) |
Offset from RPU Base Address: 0x0F40 | |
#define | MXC_R_RPU_SRAM5 ((uint32_t)0x00000F50UL) |
Offset from RPU Base Address: 0x0F50 | |
#define | MXC_R_RPU_SRAM6 ((uint32_t)0x00000F60UL) |
Offset from RPU Base Address: 0x0F60 | |