MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation

Low Power Memory Shutdown Control. More...

Macros

#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS   0
 LPMEMSD_SRAM0SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS))
 LPMEMSD_SRAM0SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS   1
 LPMEMSD_SRAM1SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS))
 LPMEMSD_SRAM1SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS   2
 LPMEMSD_SRAM2SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS))
 LPMEMSD_SRAM2SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS   3
 LPMEMSD_SRAM3SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS))
 LPMEMSD_SRAM3SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS   4
 LPMEMSD_SRAM4SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS))
 LPMEMSD_SRAM4SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS   5
 LPMEMSD_SRAM5SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS))
 LPMEMSD_SRAM5SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS   6
 LPMEMSD_SRAM6SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS))
 LPMEMSD_SRAM6SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS   7
 LPMEMSD_ICACHESD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS))
 LPMEMSD_ICACHESD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS   8
 LPMEMSD_ICACHEXIPSD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS))
 LPMEMSD_ICACHEXIPSD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS   9
 LPMEMSD_SCACHESD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_SCACHESD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS))
 LPMEMSD_SCACHESD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS   10
 LPMEMSD_CRYPTOSD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS))
 LPMEMSD_CRYPTOSD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS   11
 LPMEMSD_USBFIFOSD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS))
 LPMEMSD_USBFIFOSD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS   12
 LPMEMSD_ROMSD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_ROMSD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS))
 LPMEMSD_ROMSD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS   13
 LPMEMSD_ROM1SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_ROM1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS))
 LPMEMSD_ROM1SD Mask.
 
#define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS   14
 LPMEMSD_IC1SD Position.
 
#define MXC_F_PWRSEQ_LPMEMSD_IC1SD   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS))
 LPMEMSD_IC1SD Mask.
 

Detailed Description