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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Semaphores Protection Register. More...
Macros | |
#define | MXC_F_RPU_SEMA_DMA0ACN_POS 0 |
SEMA_DMA0ACN Position. | |
#define | MXC_F_RPU_SEMA_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_DMA0ACN_POS)) |
SEMA_DMA0ACN Mask. | |
#define | MXC_F_RPU_SEMA_DMA1ACN_POS 1 |
SEMA_DMA1ACN Position. | |
#define | MXC_F_RPU_SEMA_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_DMA1ACN_POS)) |
SEMA_DMA1ACN Mask. | |
#define | MXC_F_RPU_SEMA_USBACN_POS 2 |
SEMA_USBACN Position. | |
#define | MXC_F_RPU_SEMA_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_USBACN_POS)) |
SEMA_USBACN Mask. | |
#define | MXC_F_RPU_SEMA_SYS0ACN_POS 3 |
SEMA_SYS0ACN Position. | |
#define | MXC_F_RPU_SEMA_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SYS0ACN_POS)) |
SEMA_SYS0ACN Mask. | |
#define | MXC_F_RPU_SEMA_SYS1ACN_POS 4 |
SEMA_SYS1ACN Position. | |
#define | MXC_F_RPU_SEMA_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SYS1ACN_POS)) |
SEMA_SYS1ACN Mask. | |
#define | MXC_F_RPU_SEMA_SDMADACN_POS 5 |
SEMA_SDMADACN Position. | |
#define | MXC_F_RPU_SEMA_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SDMADACN_POS)) |
SEMA_SDMADACN Mask. | |
#define | MXC_F_RPU_SEMA_SDMAIACN_POS 6 |
SEMA_SDMAIACN Position. | |
#define | MXC_F_RPU_SEMA_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SDMAIACN_POS)) |
SEMA_SDMAIACN Mask. | |
#define | MXC_F_RPU_SEMA_CRYPTOACN_POS 7 |
SEMA_CRYPTOACN Position. | |
#define | MXC_F_RPU_SEMA_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_CRYPTOACN_POS)) |
SEMA_CRYPTOACN Mask. | |
#define | MXC_F_RPU_SEMA_SDIOACN_POS 8 |
SEMA_SDIOACN Position. | |
#define | MXC_F_RPU_SEMA_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SEMA_SDIOACN_POS)) |
SEMA_SDIOACN Mask. | |