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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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ADC Control. More...
Macros | |
#define | MXC_F_ADC_CTRL_START_POS 0 |
CTRL_START Position. | |
#define | MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) |
CTRL_START Mask. | |
#define | MXC_F_ADC_CTRL_PWR_POS 1 |
CTRL_PWR Position. | |
#define | MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) |
CTRL_PWR Mask. | |
#define | MXC_F_ADC_CTRL_REFBUF_PWR_POS 3 |
CTRL_REFBUF_PWR Position. | |
#define | MXC_F_ADC_CTRL_REFBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REFBUF_PWR_POS)) |
CTRL_REFBUF_PWR Mask. | |
#define | MXC_F_ADC_CTRL_REF_SEL_POS 4 |
CTRL_REF_SEL Position. | |
#define | MXC_F_ADC_CTRL_REF_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SEL_POS)) |
CTRL_REF_SEL Mask. | |
#define | MXC_F_ADC_CTRL_REF_SCALE_POS 8 |
CTRL_REF_SCALE Position. | |
#define | MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) |
CTRL_REF_SCALE Mask. | |
#define | MXC_F_ADC_CTRL_SCALE_POS 9 |
CTRL_SCALE Position. | |
#define | MXC_F_ADC_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_SCALE_POS)) |
CTRL_SCALE Mask. | |
#define | MXC_F_ADC_CTRL_CLK_EN_POS 11 |
CTRL_CLK_EN Position. | |
#define | MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) |
CTRL_CLK_EN Mask. | |
#define | MXC_F_ADC_CTRL_CH_SEL_POS 12 |
CTRL_CH_SEL Position. | |
#define | MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL_CH_SEL_POS)) |
CTRL_CH_SEL Mask. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) |
CTRL_CH_SEL_AIN0 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN0 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) |
CTRL_CH_SEL_AIN1 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN1 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) |
CTRL_CH_SEL_AIN2 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN2 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) |
CTRL_CH_SEL_AIN3 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN3 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) |
CTRL_CH_SEL_AIN4 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN4 (MXC_V_ADC_CTRL_CH_SEL_AIN4 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN4 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) |
CTRL_CH_SEL_AIN5 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN5 (MXC_V_ADC_CTRL_CH_SEL_AIN5 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN5 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) |
CTRL_CH_SEL_AIN6 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN6 (MXC_V_ADC_CTRL_CH_SEL_AIN6 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN6 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) |
CTRL_CH_SEL_AIN7 Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_AIN7 (MXC_V_ADC_CTRL_CH_SEL_AIN7 << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_AIN7 Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) |
CTRL_CH_SEL_VCOREA Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VCOREA (MXC_V_ADC_CTRL_CH_SEL_VCOREA << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VCOREA Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) |
CTRL_CH_SEL_VCOREB Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VCOREB (MXC_V_ADC_CTRL_CH_SEL_VCOREB << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VCOREB Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) |
CTRL_CH_SEL_VRXOUT Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VRXOUT Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) |
CTRL_CH_SEL_VTXOUT Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VTXOUT Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) |
CTRL_CH_SEL_VDDA Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VDDA Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) |
CTRL_CH_SEL_VDDB Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VDDB (MXC_V_ADC_CTRL_CH_SEL_VDDB << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VDDB Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) |
CTRL_CH_SEL_VDDIO Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VDDIO (MXC_V_ADC_CTRL_CH_SEL_VDDIO << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VDDIO Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) |
CTRL_CH_SEL_VDDIOH Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VDDIOH Setting. | |
#define | MXC_V_ADC_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) |
CTRL_CH_SEL_VREGI Value. | |
#define | MXC_S_ADC_CTRL_CH_SEL_VREGI (MXC_V_ADC_CTRL_CH_SEL_VREGI << MXC_F_ADC_CTRL_CH_SEL_POS) |
CTRL_CH_SEL_VREGI Setting. | |
#define | MXC_F_ADC_CTRL_ADC_DIVSEL_POS 17 |
CTRL_ADC_DIVSEL Position. | |
#define | MXC_F_ADC_CTRL_ADC_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_CTRL_ADC_DIVSEL_POS)) |
CTRL_ADC_DIVSEL Mask. | |
#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV1 ((uint32_t)0x0UL) |
CTRL_ADC_DIVSEL_DIV1 Value. | |
#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV1 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV1 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
CTRL_ADC_DIVSEL_DIV1 Setting. | |
#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV2 ((uint32_t)0x1UL) |
CTRL_ADC_DIVSEL_DIV2 Value. | |
#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV2 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV2 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
CTRL_ADC_DIVSEL_DIV2 Setting. | |
#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV3 ((uint32_t)0x2UL) |
CTRL_ADC_DIVSEL_DIV3 Value. | |
#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV3 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV3 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
CTRL_ADC_DIVSEL_DIV3 Setting. | |
#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV4 ((uint32_t)0x3UL) |
CTRL_ADC_DIVSEL_DIV4 Value. | |
#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV4 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV4 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
CTRL_ADC_DIVSEL_DIV4 Setting. | |
#define | MXC_F_ADC_CTRL_DATA_ALIGN_POS 20 |
CTRL_DATA_ALIGN Position. | |
#define | MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) |
CTRL_DATA_ALIGN Mask. | |