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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Register for reading and clearing interrupt flags. More...
Macros | |
#define | MXC_F_SPI17Y_INT_FL_TX_THRESH_POS 0 |
INT_FL_TX_THRESH Position. | |
#define | MXC_F_SPI17Y_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_THRESH_POS)) |
INT_FL_TX_THRESH Mask. | |
#define | MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS 1 |
INT_FL_TX_EMPTY Position. | |
#define | MXC_F_SPI17Y_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_EMPTY_POS)) |
INT_FL_TX_EMPTY Mask. | |
#define | MXC_F_SPI17Y_INT_FL_RX_THRESH_POS 2 |
INT_FL_RX_THRESH Position. | |
#define | MXC_F_SPI17Y_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_THRESH_POS)) |
INT_FL_RX_THRESH Mask. | |
#define | MXC_F_SPI17Y_INT_FL_RX_FULL_POS 3 |
INT_FL_RX_FULL Position. | |
#define | MXC_F_SPI17Y_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_FULL_POS)) |
INT_FL_RX_FULL Mask. | |
#define | MXC_F_SPI17Y_INT_FL_SSA_POS 4 |
INT_FL_SSA Position. | |
#define | MXC_F_SPI17Y_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSA_POS)) |
INT_FL_SSA Mask. | |
#define | MXC_F_SPI17Y_INT_FL_SSD_POS 5 |
INT_FL_SSD Position. | |
#define | MXC_F_SPI17Y_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_SSD_POS)) |
INT_FL_SSD Mask. | |
#define | MXC_F_SPI17Y_INT_FL_FAULT_POS 8 |
INT_FL_FAULT Position. | |
#define | MXC_F_SPI17Y_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_FAULT_POS)) |
INT_FL_FAULT Mask. | |
#define | MXC_F_SPI17Y_INT_FL_ABORT_POS 9 |
INT_FL_ABORT Position. | |
#define | MXC_F_SPI17Y_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_ABORT_POS)) |
INT_FL_ABORT Mask. | |
#define | MXC_F_SPI17Y_INT_FL_M_DONE_POS 11 |
INT_FL_M_DONE Position. | |
#define | MXC_F_SPI17Y_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_M_DONE_POS)) |
INT_FL_M_DONE Mask. | |
#define | MXC_F_SPI17Y_INT_FL_TX_OVR_POS 12 |
INT_FL_TX_OVR Position. | |
#define | MXC_F_SPI17Y_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_OVR_POS)) |
INT_FL_TX_OVR Mask. | |
#define | MXC_F_SPI17Y_INT_FL_TX_UND_POS 13 |
INT_FL_TX_UND Position. | |
#define | MXC_F_SPI17Y_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_TX_UND_POS)) |
INT_FL_TX_UND Mask. | |
#define | MXC_F_SPI17Y_INT_FL_RX_OVR_POS 14 |
INT_FL_RX_OVR Position. | |
#define | MXC_F_SPI17Y_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_OVR_POS)) |
INT_FL_RX_OVR Mask. | |
#define | MXC_F_SPI17Y_INT_FL_RX_UND_POS 15 |
INT_FL_RX_UND Position. | |
#define | MXC_F_SPI17Y_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI17Y_INT_FL_RX_UND_POS)) |
INT_FL_RX_UND Mask. | |
All bits are write 1 to clear.