LED Board Support API | |
▼MX25 SPI Multi-I/O Flash Memory Driver | |
MX25 SPI Command Definitions | |
Push button driver board support | |
▼Analog To Digital Converter (ADC) | |
►ADC_Registers | Registers, Bit Masks and Bit Positions for the ADC Peripheral Module |
Register Offsets | ADC Peripheral Register Offsets from the ADC Base Peripheral Address |
ADC_CTRL | ADC Control |
ADC_STATUS | ADC Status |
ADC_DATA | ADC Output Data |
ADC_INTR | ADC Interrupt Control Register |
ADC_LIMIT | ADC Limit |
▼Trust Protection Unit | |
►TPU_Registers | Registers, Bit Masks and Bit Positions for the TPU Peripheral Module |
Register Offsets | TPU Peripheral Register Offsets from the TPU Base Peripheral Address |
TPU_CTRL | Crypto Control Register |
TPU_CIPHER_CTRL | Cipher Control Register |
TPU_HASH_CTRL | HASH Control Register |
TPU_CRC_CTRL | CRC Control Register |
TPU_DMA_SRC | Crypto DMA Source Address |
TPU_DMA_DEST | Crypto DMA Destination Address |
TPU_DMA_CNT | Crypto DMA Byte Count |
TPU_MAA_CTRL | MAA Control Register |
TPU_DIN | Crypto Data Input |
TPU_DOUT | Crypto Data Output |
TPU_CRC_POLY | CRC Polynomial |
TPU_CRC_VAL | CRC Value |
TPU_CRC_PRNG | Pseudo Random Value |
TPU_HAM_ECC | Hamming ECC Register |
TPU_CIPHER_INIT | Initial Vector |
TPU_CIPHER_KEY | Cipher Key |
TPU_HASH_DIGEST | This register holds the calculated hash value |
TPU_HASH_MSG_SZ | Message Size |
TPU_MAA_MAWS | MAA Word Size |
AES and DES | |
Cyclic Redundancy Check (CRC) | |
HASH | |
Modular Arithmetic Accelerator (MAA) | |
▼Direct Memory Access (DMA) | |
►DMA_Registers | Registers, Bit Masks and Bit Positions for the DMA Peripheral Module |
Register Offsets | DMA Peripheral Register Offsets from the DMA Base Peripheral Address |
DMA_CN | DMA Control Register |
DMA_INTR | DMA Interrupt Register |
DMA_CFG | DMA Channel Configuration Register |
DMA_ST | DMA Channel Status Register |
DMA_SRC | Source Device Address |
DMA_DST | Destination Device Address |
DMA_CNT | DMA Counter |
DMA_SRC_RLD | Source Address Reload Value |
DMA_DST_RLD | Destination Address Reload Value |
DMA_CNT_RLD | DMA Channel Count Reload Register |
▼External Memory Cache Controller (EMCC) | |
►EMCC_Registers | Registers, Bit Masks and Bit Positions for the EMCC Peripheral Module |
Register Offsets | EMCC Peripheral Register Offsets from the EMCC Base Peripheral Address |
EMCC_CACHE_ID | Cache ID Register |
EMCC_MEMCFG | Memory Configuration Register |
EMCC_CACHE_CTRL | Cache Control and Status Register |
EMCC_INVALIDATE | Invalidate All Cache Contents |
▼Flash Controller (FLC) | |
►FLC_Registers | Registers, Bit Masks and Bit Positions for the FLC Peripheral Module |
Register Offsets | FLC Peripheral Register Offsets from the FLC Base Peripheral Address |
FLC_ADDR | Flash Write Address |
FLC_CLKDIV | Flash Clock Divide |
FLC_CN | Flash Control Register |
FLC_INTR | Flash Interrupt Register |
FLC_DATA | Flash Write Data |
FLC_ACNTL | Access Control Register |
▼General-Purpose Input/Output (GPIO) | |
►Port and Pin Definitions | |
Port Definitions | |
Pin Definitions | |
►GPIO_Registers | Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module |
Register Offsets | GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address |
GPIO_EN | GPIO Function Enable Register |
GPIO_EN_SET | GPIO Set Function Enable Register |
GPIO_EN_CLR | GPIO Clear Function Enable Register |
GPIO_OUT_EN | GPIO Output Enable Register |
GPIO_OUT_EN_SET | GPIO Output Enable Set Function Enable Register |
GPIO_OUT_EN_CLR | GPIO Output Enable Clear Function Enable Register |
GPIO_OUT | GPIO Output Register |
GPIO_OUT_SET | GPIO Output Set |
GPIO_OUT_CLR | GPIO Output Clear |
GPIO_IN | GPIO Input Register |
GPIO_INT_MOD | GPIO Interrupt Mode Register |
GPIO_INT_POL | GPIO Interrupt Polarity Register |
GPIO_INT_EN | GPIO Interrupt Enable Register |
GPIO_INT_EN_SET | GPIO Interrupt Enable Set |
GPIO_INT_EN_CLR | GPIO Interrupt Enable Clear |
GPIO_INT_STAT | GPIO Interrupt Status Register |
GPIO_INT_CLR | GPIO Status Clear |
GPIO_WAKE_EN | GPIO Wake Enable Register |
GPIO_WAKE_EN_SET | GPIO Wake Enable Set |
GPIO_WAKE_EN_CLR | GPIO Wake Enable Clear |
GPIO_INT_DUAL_EDGE | GPIO Interrupt Dual Edge Mode Register |
GPIO_PAD_CFG1 | GPIO Input Mode Config 1 |
GPIO_PAD_CFG2 | GPIO Input Mode Config 2 |
GPIO_EN1 | GPIO Alternate Function Enable Register |
GPIO_EN1_SET | GPIO Alternate Function Set |
GPIO_EN1_CLR | GPIO Alternate Function Clear |
GPIO_EN2 | GPIO Alternate Function Enable Register |
GPIO_EN2_SET | GPIO Alternate Function 2 Set |
GPIO_EN2_CLR | GPIO Wake Alternate Function Clear |
GPIO_DS | GPIO Drive Strength Register |
GPIO_DS1 | GPIO Drive Strength 1 Register |
GPIO_PS | GPIO Pull Select Mode |
GPIO_VSSEL | GPIO Voltage Select |
▼HTMR | |
►HTMR_Registers | Registers, Bit Masks and Bit Positions for the HTMR Peripheral Module |
Register Offsets | HTMR Peripheral Register Offsets from the HTMR Base Peripheral Address |
HTMR_SSEC | HTimer Short Interval Counter |
HTMR_RAS | Long Interval Alarm |
HTMR_RSSA | HTimer Short Interval Alarm |
HTMR_CTRL | HTimer Control Register |
▼I2C | |
►I2C_Registers | Registers, Bit Masks and Bit Positions for the I2C Peripheral Module |
Register Offsets | I2C Peripheral Register Offsets from the I2C Base Peripheral Address |
I2C_CTRL | Control Register0 |
I2C_STATUS | Status Register |
I2C_INT_FL0 | Interrupt Status Register |
I2C_INT_EN0 | Interrupt Enable Register |
I2C_INT_FL1 | Interrupt Status Register 1 |
I2C_INT_EN1 | Interrupt Staus Register 1 |
I2C_FIFO_LEN | FIFO Configuration Register |
I2C_RX_CTRL0 | Receive Control Register 0 |
I2C_RX_CTRL1 | Receive Control Register 1 |
I2C_TX_CTRL0 | Transmit Control Register 0 |
I2C_TX_CTRL1 | Transmit Control Register 1 |
I2C_FIFO | Data Register |
I2C_MASTER_CTRL | Master Control Register |
I2C_CLK_LO | Clock Low Register |
I2C_CLK_HI | Clock high Register |
I2C_HS_CLK | HS-Mode Clock Control Register |
I2C_TIMEOUT | Timeout Register |
I2C_DMA | DMA Register |
I2C_SLAVE_ADDR | Slave Address Register |
▼ICC_Registers | Registers, Bit Masks and Bit Positions for the ICC Peripheral Module |
Register Offsets | ICC Peripheral Register Offsets from the ICC Base Peripheral Address |
ICC_CACHE_ID | Cache ID Register |
ICC_MEMCFG | Memory Configuration Register |
ICC_CACHE_CTRL | Cache Control and Status Register |
▼Low Power (Power Sequencer) | |
►PWRSEQ_Registers | Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module |
Register Offsets | PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address |
PWRSEQ_LPCN | Low Power Control Register |
PWRSEQ_LPWKST0 | Low Power I/O Wakeup Status Register 0 |
PWRSEQ_LPWKEN0 | Low Power I/O Wakeup Enable Register 0 |
PWRSEQ_LPPWST | Low Power Peripheral Wakeup Status Register |
PWRSEQ_LPPWEN | Low Power Peripheral Wakeup Enable Register |
PWRSEQ_LPMEMSD | Low Power Memory Shutdown Control |
PWRSEQ_LPVDDPD | Low Power VDD Domain Power Down Control |
▼1-Wire Master (OWM) | |
►OWM_Registers | Registers, Bit Masks and Bit Positions for the OWM Peripheral Module |
Register Offsets | OWM Peripheral Register Offsets from the OWM Base Peripheral Address |
OWM_CFG | 1-Wire Master Configuration |
OWM_CLK_DIV_1US | 1-Wire Master Clock Divisor |
OWM_CTRL_STAT | 1-Wire Master Control/Status |
OWM_DATA | 1-Wire Master Data Buffer |
OWM_INTFL | 1-Wire Master Interrupt Flags |
OWM_INTEN | 1-Wire Master Interrupt Enables |
▼Pulse Train Engine (PT) | This is the high level API for the pulse train engine |
►PT_Registers | Registers, Bit Masks and Bit Positions for the PT Peripheral Module |
Register Offsets | PT Peripheral Register Offsets from the PT Base Peripheral Address |
PT_RATE_LENGTH | Pulse Train Configuration |
PT_LOOP | Pulse Train Loop Count |
PT_RESTART | Pulse Train Auto-Restart Configuration |
▼Resource Protection Unit | |
►RPU_Registers | Registers, Bit Masks and Bit Positions for the RPU Peripheral Module |
Register Offsets | RPU Peripheral Register Offsets from the RPU Base Peripheral Address |
RPU_GCR | GCR Protection Register |
RPU_SIR | SIR Protection Register |
RPU_FCR | FCR Protection Register |
RPU_CRYPTO | Crypto Protection Register |
RPU_WDT0 | Watchdog 0 Protection Register |
RPU_WDT1 | Watchdog 1 Protection Register |
RPU_WDT2 | Watchdog 2 Protection Register |
RPU_SMON | SMON Protection Register |
RPU_SIMO | SIMO Protection Register |
RPU_DVS | DVS Protection Register |
RPU_BBSIR | BBSIR Protection Register |
RPU_RTC | RTC Protection Register |
RPU_WUT | Wakeup Timer Protection Register |
RPU_PWRSEQ | Power Sequencer Protection Register |
RPU_BBCR | BBCR Protection Register |
RPU_GPIO0 | GPIO0 Protection Register |
RPU_GPIO1 | GPIO1 Protection Register |
RPU_TMR0 | TMR0 Protection Register |
RPU_TMR1 | TMR1 Protection Register |
RPU_TMR2 | TMR2 Protection Register |
RPU_TMR3 | TMR3 Protection Register |
RPU_TMR4 | TMR4 Protection Register |
RPU_TMR5 | TMR5 Protection Register |
RPU_HTIMER0 | HTimer0 Protection Register |
RPU_HTIMER1 | HTimer1 Protection Register |
RPU_I2C0 | I2C0 Protection Register |
RPU_I2C1 | I2C1 Protection Register |
RPU_I2C2 | I2C2 Protection Register |
RPU_SPIXIPM | SPI-XIP Master Protection Register |
RPU_SPIXIPMC | SPI-XIP Master Controller Protection Register |
RPU_DMA0 | DMA0 Protection Register |
RPU_FLC0 | Flash 0 Protection Register |
RPU_FLC1 | Flash 1 Protection Register |
RPU_ICACHE0 | Instruction Cache 0 Protection Register |
RPU_ICACHE1 | Instruction Cache 1 Protection Register |
RPU_ICACHEXIP | Instruction Cache XIP Protection Register |
RPU_DCACHE | Data Cache Controller Protection Register |
RPU_ADC | ADC Protection Register |
RPU_DMA1 | DMA1 Protection Register |
RPU_SDMA | SDMA Protection Register |
RPU_SDHCCTRL | SDHC Controller Protection Register |
RPU_SPID | SPI Data Controller Protection Register |
RPU_PT | Pulse Train Protection Register |
RPU_OWM | One Wire Master Protection Register |
RPU_SEMA | Semaphores Protection Register |
RPU_UART0 | UART0 Protection Register |
RPU_UART1 | UART1 Protection Register |
RPU_UART2 | UART2 Protection Register |
RPU_QSPI1 | QSPI1 Protection Register |
RPU_QSPI2 | QSPI2 Protection Register |
RPU_AUDIO | Audio Subsystem Protection Register |
RPU_TRNG | TRNG Protection Register |
RPU_BTLE | BTLE Registers Protection Register |
RPU_USBHS | USBHS Protection Register |
RPU_SDIO | SDIO Protection Register |
RPU_SPIXIPMFIFO | SPI XIP Master FIFO Protection Register |
RPU_QSPI0 | QSPI0 Protection Register |
RPU_SRAM0 | SRAM0 Protection Register |
RPU_SRAM1 | SRAM1 Protection Register |
RPU_SRAM2 | SRAM2 Protection Register |
RPU_SRAM3 | SRAM3 Protection Register |
RPU_SRAM4 | SRAM4 Protection Register |
RPU_SRAM5 | SRAM5 Protection Register |
RPU_SRAM6 | SRAM6 Protection Register |
▼RTC | |
►RTC_Registers | Registers, Bit Masks and Bit Positions for the RTC Peripheral Module |
Register Offsets | RTC Peripheral Register Offsets from the RTC Base Peripheral Address |
RTC_SSEC | RTC Sub-second Counter |
RTC_RAS | Time-of-day Alarm |
RTC_RSSA | RTC sub-second alarm |
RTC_CTRL | RTC Control Register |
RTC_TRIM | RTC Trim Register |
RTC_OSCCTRL | RTC Oscillator Control Register |
▼Secure Digital High Capacity (SDHC) | |
►SDHC_Registers | Registers, Bit Masks and Bit Positions for the SDHC Peripheral Module |
Register Offsets | SDHC Peripheral Register Offsets from the SDHC Base Peripheral Address |
SDHC_SDMA | SDMA System Address / Argument 2 |
SDHC_BLK_SIZE | Block Size |
SDHC_BLK_CNT | Block Count |
SDHC_ARG_1 | Argument 1 |
SDHC_TRANS | Transfer Mode |
SDHC_CMD | Command |
SDHC_RESP | Response 0 Register 0-15 |
SDHC_BUFFER | Buffer Data Port |
SDHC_PRESENT | Present State |
SDHC_HOST_CN_1 | Host Control 1 |
SDHC_PWR | Power Control |
SDHC_BLK_GAP | Block Gap Control |
SDHC_WAKEUP | Wakeup Control |
SDHC_CLK_CN | Clock Control |
SDHC_TO | Timeout Control |
SDHC_SW_RESET | Software Reset |
SDHC_INT_STAT | Normal Interrupt Status |
SDHC_ER_INT_STAT | Error Interrupt Status |
SDHC_INT_EN | Normal Interrupt Status Enable |
SDHC_ER_INT_EN | Error Interrupt Status Enable |
SDHC_INT_SIGNAL | Normal Interrupt Signal Enable |
SDHC_ER_INT_SIGNAL | Error Interrupt Signal Enable |
SDHC_AUTO_CMD_ER | Auto CMD Error Status |
SDHC_HOST_CN_2 | Host Control 2 |
SDHC_CFG_0 | Capabilities 0-31 |
SDHC_CFG_1 | Capabilities 32-63 |
SDHC_MAX_CURR_CFG | Maximum Current Capabilities |
SDHC_FORCE_CMD | Force Event for Auto CMD Error Status |
SDHC_FORCE_EVENT_INT_STAT | Force Event for Error Interrupt Status |
SDHC_ADMA_ER | ADMA Error Status |
SDHC_ADMA_ADDR_0 | ADMA System Address 0-31 |
SDHC_ADMA_ADDR_1 | ADMA System Address 32-63 |
SDHC_PRESET_0 | Preset Value for Initialization |
SDHC_PRESET_1 | Preset Value for Default Speed |
SDHC_PRESET_2 | Preset Value for High Speed |
SDHC_PRESET_3 | Preset Value for SDR12 |
SDHC_PRESET_4 | Preset Value for SDR25 |
SDHC_PRESET_5 | Preset Value for SDR50 |
SDHC_PRESET_6 | Preset Value for SDR104 |
SDHC_PRESET_7 | Preset Value for DDR50 |
SDHC_SLOT_INT | Slot Interrupt Status |
SDHC_HOST_CN_VER | Host Controller Version |
Sdhc_async | Callback function type used in asynchronous SDHC communications requests |
▼Semaphore (SEMA) | |
►SEMA_Registers | Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module |
Register Offsets | SEMA Peripheral Register Offsets from the SEMA Base Peripheral Address |
SEMA_SEMAPHORES | Read to test and set, returns prior value |
SEMA_STATUS | Semaphore status bits |
▼SPI | |
►SPI17Y | |
►SPI17Y_Registers | Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module |
Register Offsets | SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address |
SPI17Y_DATA32 | Register for reading and writing the FIFO |
SPI17Y_DATA16 | Register for reading and writing the FIFO |
SPI17Y_DATA8 | Register for reading and writing the FIFO |
SPI17Y_CTRL0 | Register for controlling SPI peripheral |
SPI17Y_CTRL1 | Register for controlling SPI peripheral |
SPI17Y_CTRL2 | Register for controlling SPI peripheral |
SPI17Y_SS_TIME | Register for controlling SPI peripheral/Slave Select Timing |
SPI17Y_CLK_CFG | Register for controlling SPI clock rate |
SPI17Y_DMA | Register for controlling DMA |
SPI17Y_INT_FL | Register for reading and clearing interrupt flags |
SPI17Y_INT_EN | Register for enabling interrupts |
SPI17Y_WAKE_FL | Register for wake up flags |
SPI17Y_WAKE_EN | Register for wake up enable |
SPI17Y_STAT | SPI Status register |
Spi_async | Callback function type used in asynchronous SPI Master communication requests |
▼SPI External Flash (SPIXF) | |
►SPIXF_Registers | Registers, Bit Masks and Bit Positions for the SPIXF Peripheral Module |
Register Offsets | SPIXF Peripheral Register Offsets from the SPIXF Base Peripheral Address |
SPIXF_CFG | SPIX Configuration Register |
SPIXF_FETCH_CTRL | SPIX Fetch Control Register |
SPIXF_MODE_CTRL | SPIX Mode Control Register |
SPIXF_MODE_DATA | SPIX Mode Data Register |
SPIXF_SCLK_FB_CTRL | SPIX Feedback Control Register |
SPIXF_IO_CTRL | SPIX IO Control Register |
SPIXF_MEMSECCN | SPIX Memory Security Control Register |
▼SPI External Flash Controller (SPIXFC) | |
►SPIXFC_Registers | Registers, Bit Masks and Bit Positions for the SPIXFC Peripheral Module |
Register Offsets | SPIXFC Peripheral Register Offsets from the SPIXFC Base Peripheral Address |
SPIXFC_CONFIG | Configuration Register |
SPIXFC_SS_POL | SPIX Controller Slave Select Polarity Register |
SPIXFC_GEN_CTRL | SPIX Controller General Controller Register |
SPIXFC_FIFO_CTRL | SPIX Controller FIFO Control and Status Register |
SPIXFC_SPCTRL | SPIX Controller Special Control Register |
SPIXFC_INTFL | SPIX Controller Interrupt Status Register |
SPIXFC_INTEN | SPIX Controller Interrupt Enable Register |
▼SPI External Ram (SPIXR) | |
►SPIXR_Registers | Registers, Bit Masks and Bit Positions for the SPIXR Peripheral Module |
Register Offsets | SPIXR Peripheral Register Offsets from the SPIXR Base Peripheral Address |
SPIXR_DATA32 | Register for reading and writing the FIFO |
SPIXR_DATA16 | Register for reading and writing the FIFO |
SPIXR_DATA8 | Register for reading and writing the FIFO |
SPIXR_CTRL1 | Register for controlling SPI peripheral |
SPIXR_CTRL2 | Register for controlling SPI peripheral |
SPIXR_CTRL3 | Register for controlling SPI peripheral |
SPIXR_CTRL4 | Register for controlling SPI peripheral |
SPIXR_BRG_CTRL | Register for controlling SPI clock rate |
SPIXR_I2S_CTRL | Register for controlling I2C mode |
SPIXR_DMA | Register for controlling DMA |
SPIXR_IRQ | Register for reading and clearing interrupt flags |
SPIXR_IRQE | Register for enabling interrupts |
SPIXR_WAKE | Register for wake up flags |
SPIXR_WAKEE | Register for wake up enable |
SPIXR_STAT | SPI Status register |
SPIXR_XMEM_CTRL | Register to control external memory |
▼Timer (TMR) | |
►TMR_Registers | Registers, Bit Masks and Bit Positions for the TMR Peripheral Module |
Register Offsets | TMR Peripheral Register Offsets from the TMR Base Peripheral Address |
TMR_INTR | Clear Interrupt |
TMR_CN | Timer Control Register |
TMR_NOLCMP | Timer Non-Overlapping Compare Register |
Timer Utility Functions | |
▼TRNG_Registers | Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module |
Register Offsets | TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address |
TRNG_CN | TRNG Control Register |
TRNG_ST | Data |
TRNG_DATA | Data |
▼UART | |
►UART_Registers | Registers, Bit Masks and Bit Positions for the UART Peripheral Module |
Register Offsets | UART Peripheral Register Offsets from the UART Base Peripheral Address |
UART_CTRL | Control Register |
UART_THRESH_CTRL | Threshold Control register |
UART_STATUS | Status Register |
UART_INT_EN | Interrupt Enable Register |
UART_INT_FL | Interrupt Status Flags |
UART_BAUD0 | Baud rate register |
UART_BAUD1 | Baud rate register |
UART_FIFO | FIFO Data buffer |
UART_DMA | DMA Configuration |
UART_TX_FIFO | Transmit FIFO Status register |
▼Watchdog Timer (WDT) | |
►WDT_Registers | Registers, Bit Masks and Bit Positions for the WDT Peripheral Module |
Register Offsets | WDT Peripheral Register Offsets from the WDT Base Peripheral Address |
WDT_CTRL | Watchdog Timer Control Register |
WDT_RST | Watchdog Timer Reset Register |
Error Codes | A list of common error codes used by the API |
Exclusive Access Locks | Lock functions to obtain and release a variable for exclusive access |
Delay Utility Functions | Asynchronous delay routines based on the SysTick Timer |
Assertion Checks for Debugging | Assertion checks for debugging |