MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation

Registers, Bit Masks and Bit Positions for the TPU Peripheral Module. More...

Modules

 Register Offsets
 TPU Peripheral Register Offsets from the TPU Base Peripheral Address.
 
 TPU_CTRL
 Crypto Control Register.
 
 TPU_CIPHER_CTRL
 Cipher Control Register.
 
 TPU_HASH_CTRL
 HASH Control Register.
 
 TPU_CRC_CTRL
 CRC Control Register.
 
 TPU_DMA_SRC
 Crypto DMA Source Address.
 
 TPU_DMA_DEST
 Crypto DMA Destination Address.
 
 TPU_DMA_CNT
 Crypto DMA Byte Count.
 
 TPU_MAA_CTRL
 MAA Control Register.
 
 TPU_DIN
 Crypto Data Input.
 
 TPU_DOUT
 Crypto Data Output.
 
 TPU_CRC_POLY
 CRC Polynomial.
 
 TPU_CRC_VAL
 CRC Value.
 
 TPU_CRC_PRNG
 Pseudo Random Value.
 
 TPU_HAM_ECC
 Hamming ECC Register.
 
 TPU_CIPHER_INIT
 Initial Vector.
 
 TPU_CIPHER_KEY
 Cipher Key.
 
 TPU_HASH_DIGEST
 This register holds the calculated hash value.
 
 TPU_HASH_MSG_SZ
 Message Size.
 
 TPU_MAA_MAWS
 MAA Word Size.
 

Data Structures

struct  mxc_tpu_regs_t
 Structure type to access the TPU Registers. More...
 

Detailed Description

The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms.