enum | rpu_allow_t {
RPU_DMA0_ALLOW = 0x01,
RPU_DMA1_ALLOW = 0x02,
RPU_USB_ALLOW = 0x04,
RPU_SYS0_ALLOW = 0x08,
RPU_SYS1_ALLOW = 0x10,
RPU_SDMAD_ALLOW = 0x20,
RPU_SDMAI_ALLOW = 0x40,
RPU_CRYPTO_ALLOW = 0x80,
RPU_SDIO_ALLOW = 0x100
} |
enum | rpu_device_t {
RPU_GCR = MXC_R_RPU_GCR,
RPU_FLC0 = MXC_R_RPU_FLC0,
RPU_SDHCCTRL = MXC_R_RPU_SDHCCTRL,
RPU_SIR = MXC_R_RPU_SIR,
RPU_FCR = MXC_R_RPU_FCR,
RPU_CRYPTO = MXC_R_RPU_CRYPTO,
RPU_WDT0 = MXC_R_RPU_WDT0,
RPU_WDT1 = MXC_R_RPU_WDT1,
RPU_WDT2 = MXC_R_RPU_WDT2,
RPU_SMON = MXC_R_RPU_SMON,
RPU_SIMO = MXC_R_RPU_SIMO,
RPU_DVS = MXC_R_RPU_DVS,
RPU_BBSIR = MXC_R_RPU_BBSIR,
RPU_RTC = MXC_R_RPU_RTC,
RPU_WUT = MXC_R_RPU_WUT,
RPU_PWRSEQ = MXC_R_RPU_PWRSEQ,
RPU_BBCR = MXC_R_RPU_BBCR,
RPU_GPIO0 = MXC_R_RPU_GPIO0,
RPU_GPIO1 = MXC_R_RPU_GPIO1,
RPU_TMR0 = MXC_R_RPU_TMR0,
RPU_TMR1 = MXC_R_RPU_TMR1,
RPU_TMR2 = MXC_R_RPU_TMR2,
RPU_TMR3 = MXC_R_RPU_TMR3,
RPU_TMR4 = MXC_R_RPU_TMR4,
RPU_TMR5 = MXC_R_RPU_TMR5,
RPU_HTIMER0 = MXC_R_RPU_HTIMER0,
RPU_HTIMER1 = MXC_R_RPU_HTIMER1,
RPU_I2C0 = MXC_R_RPU_I2C0,
RPU_I2C1 = MXC_R_RPU_I2C1,
RPU_I2C2 = MXC_R_RPU_I2C2,
RPU_SPIXIPM = MXC_R_RPU_SPIXIPM,
RPU_SPIXIPMC = MXC_R_RPU_SPIXIPMC,
RPU_DMA0 = MXC_R_RPU_DMA0,
RPU_FLC1 = MXC_R_RPU_FLC1,
RPU_ICACHE0 = MXC_R_RPU_ICACHE0,
RPU_ICACHE1 = MXC_R_RPU_ICACHE1,
RPU_ICACHEXIP = MXC_R_RPU_ICACHEXIP,
RPU_DCACHE = MXC_R_RPU_DCACHE,
RPU_ADC = MXC_R_RPU_ADC,
RPU_DMA1 = MXC_R_RPU_DMA1,
RPU_SDMA = MXC_R_RPU_SDMA,
RPU_SPID = MXC_R_RPU_SPID,
RPU_PT = MXC_R_RPU_PT,
RPU_OWM = MXC_R_RPU_OWM,
RPU_SEMA = MXC_R_RPU_SEMA,
RPU_UART0 = MXC_R_RPU_UART0,
RPU_UART1 = MXC_R_RPU_UART1,
RPU_UART2 = MXC_R_RPU_UART2,
RPU_QSPI1 = MXC_R_RPU_QSPI1,
RPU_QSPI2 = MXC_R_RPU_QSPI2,
RPU_AUDIO = MXC_R_RPU_AUDIO,
RPU_TRNG = MXC_R_RPU_TRNG,
RPU_BTLE = MXC_R_RPU_BTLE,
RPU_USBHS = MXC_R_RPU_USBHS,
RPU_SDIO = MXC_R_RPU_SDIO,
RPU_SPIXIPMFIFO = MXC_R_RPU_SPIXIPMFIFO,
RPU_QSPI0 = MXC_R_RPU_QSPI0
} |