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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Registers, Bit Masks and Bit Positions for the SPI17Y Peripheral Module. More...
Modules | |
Register Offsets | |
SPI17Y Peripheral Register Offsets from the SPI17Y Base Peripheral Address. | |
SPI17Y_DATA32 | |
Register for reading and writing the FIFO. | |
SPI17Y_DATA16 | |
Register for reading and writing the FIFO. | |
SPI17Y_DATA8 | |
Register for reading and writing the FIFO. | |
SPI17Y_CTRL0 | |
Register for controlling SPI peripheral. | |
SPI17Y_CTRL1 | |
Register for controlling SPI peripheral. | |
SPI17Y_CTRL2 | |
Register for controlling SPI peripheral. | |
SPI17Y_SS_TIME | |
Register for controlling SPI peripheral/Slave Select Timing. | |
SPI17Y_CLK_CFG | |
Register for controlling SPI clock rate. | |
SPI17Y_DMA | |
Register for controlling DMA. | |
SPI17Y_INT_FL | |
Register for reading and clearing interrupt flags. | |
SPI17Y_INT_EN | |
Register for enabling interrupts. | |
SPI17Y_WAKE_FL | |
Register for wake up flags. | |
SPI17Y_WAKE_EN | |
Register for wake up enable. | |
SPI17Y_STAT | |
SPI Status register. | |
Data Structures | |
struct | mxc_spi17y_regs_t |
Structure type to access the SPI17Y Registers. More... | |
SPI peripheral.