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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Flash Clock Divide. More...
Macros | |
#define | MXC_F_FLC_CLKDIV_CLKDIV_POS 0 |
CLKDIV_CLKDIV Position. | |
#define | MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) |
CLKDIV_CLKDIV Mask. | |
The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller.