MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation

Register for reading and clearing interrupt flags. More...

Macros

#define MXC_F_SPIXR_IRQ_TX_THRESH_POS   0
 IRQ_TX_THRESH Position.
 
#define MXC_F_SPIXR_IRQ_TX_THRESH   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_THRESH_POS))
 IRQ_TX_THRESH Mask.
 
#define MXC_F_SPIXR_IRQ_TX_EMPTY_POS   1
 IRQ_TX_EMPTY Position.
 
#define MXC_F_SPIXR_IRQ_TX_EMPTY   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_EMPTY_POS))
 IRQ_TX_EMPTY Mask.
 
#define MXC_F_SPIXR_IRQ_RX_THRESH_POS   2
 IRQ_RX_THRESH Position.
 
#define MXC_F_SPIXR_IRQ_RX_THRESH   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_THRESH_POS))
 IRQ_RX_THRESH Mask.
 
#define MXC_F_SPIXR_IRQ_RX_FULL_POS   3
 IRQ_RX_FULL Position.
 
#define MXC_F_SPIXR_IRQ_RX_FULL   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_FULL_POS))
 IRQ_RX_FULL Mask.
 
#define MXC_F_SPIXR_IRQ_SSA_POS   4
 IRQ_SSA Position.
 
#define MXC_F_SPIXR_IRQ_SSA   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SSA_POS))
 IRQ_SSA Mask.
 
#define MXC_F_SPIXR_IRQ_SSD_POS   5
 IRQ_SSD Position.
 
#define MXC_F_SPIXR_IRQ_SSD   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SSD_POS))
 IRQ_SSD Mask.
 
#define MXC_F_SPIXR_IRQ_FAULT_POS   8
 IRQ_FAULT Position.
 
#define MXC_F_SPIXR_IRQ_FAULT   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_FAULT_POS))
 IRQ_FAULT Mask.
 
#define MXC_F_SPIXR_IRQ_ABORT_POS   9
 IRQ_ABORT Position.
 
#define MXC_F_SPIXR_IRQ_ABORT   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_ABORT_POS))
 IRQ_ABORT Mask.
 
#define MXC_F_SPIXR_IRQ_TIMEOUT_POS   10
 IRQ_TIMEOUT Position.
 
#define MXC_F_SPIXR_IRQ_TIMEOUT   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TIMEOUT_POS))
 IRQ_TIMEOUT Mask.
 
#define MXC_F_SPIXR_IRQ_M_DONE_POS   11
 IRQ_M_DONE Position.
 
#define MXC_F_SPIXR_IRQ_M_DONE   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_M_DONE_POS))
 IRQ_M_DONE Mask.
 
#define MXC_F_SPIXR_IRQ_TX_OVR_POS   12
 IRQ_TX_OVR Position.
 
#define MXC_F_SPIXR_IRQ_TX_OVR   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_OVR_POS))
 IRQ_TX_OVR Mask.
 
#define MXC_F_SPIXR_IRQ_TX_UND_POS   13
 IRQ_TX_UND Position.
 
#define MXC_F_SPIXR_IRQ_TX_UND   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_UND_POS))
 IRQ_TX_UND Mask.
 
#define MXC_F_SPIXR_IRQ_RX_OVR_POS   14
 IRQ_RX_OVR Position.
 
#define MXC_F_SPIXR_IRQ_RX_OVR   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_OVR_POS))
 IRQ_RX_OVR Mask.
 
#define MXC_F_SPIXR_IRQ_RX_UND_POS   15
 IRQ_RX_UND Position.
 
#define MXC_F_SPIXR_IRQ_RX_UND   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_UND_POS))
 IRQ_RX_UND Mask.
 
#define MXC_F_SPIXR_IRQ_SR0A_POS   16
 IRQ_SR0A Position.
 
#define MXC_F_SPIXR_IRQ_SR0A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR0A_POS))
 IRQ_SR0A Mask.
 
#define MXC_F_SPIXR_IRQ_SR1A_POS   17
 IRQ_SR1A Position.
 
#define MXC_F_SPIXR_IRQ_SR1A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR1A_POS))
 IRQ_SR1A Mask.
 
#define MXC_F_SPIXR_IRQ_SR2A_POS   18
 IRQ_SR2A Position.
 
#define MXC_F_SPIXR_IRQ_SR2A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR2A_POS))
 IRQ_SR2A Mask.
 
#define MXC_F_SPIXR_IRQ_SR3A_POS   19
 IRQ_SR3A Position.
 
#define MXC_F_SPIXR_IRQ_SR3A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR3A_POS))
 IRQ_SR3A Mask.
 
#define MXC_F_SPIXR_IRQ_SR4A_POS   20
 IRQ_SR4A Position.
 
#define MXC_F_SPIXR_IRQ_SR4A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR4A_POS))
 IRQ_SR4A Mask.
 
#define MXC_F_SPIXR_IRQ_SR5A_POS   21
 IRQ_SR5A Position.
 
#define MXC_F_SPIXR_IRQ_SR5A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR5A_POS))
 IRQ_SR5A Mask.
 
#define MXC_F_SPIXR_IRQ_SR6A_POS   22
 IRQ_SR6A Position.
 
#define MXC_F_SPIXR_IRQ_SR6A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR6A_POS))
 IRQ_SR6A Mask.
 
#define MXC_F_SPIXR_IRQ_SR7A_POS   23
 IRQ_SR7A Position.
 
#define MXC_F_SPIXR_IRQ_SR7A   ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR7A_POS))
 IRQ_SR7A Mask.
 

Detailed Description

All bits are write 1 to clear.