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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Register for enabling interrupts. More...
Macros | |
#define | MXC_F_SPIXR_IRQE_TX_THRESH_POS 0 |
IRQE_TX_THRESH Position. | |
#define | MXC_F_SPIXR_IRQE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_THRESH_POS)) |
IRQE_TX_THRESH Mask. | |
#define | MXC_F_SPIXR_IRQE_TX_EMPTY_POS 1 |
IRQE_TX_EMPTY Position. | |
#define | MXC_F_SPIXR_IRQE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_EMPTY_POS)) |
IRQE_TX_EMPTY Mask. | |
#define | MXC_F_SPIXR_IRQE_RX_THRESH_POS 2 |
IRQE_RX_THRESH Position. | |
#define | MXC_F_SPIXR_IRQE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_THRESH_POS)) |
IRQE_RX_THRESH Mask. | |
#define | MXC_F_SPIXR_IRQE_RX_FULL_POS 3 |
IRQE_RX_FULL Position. | |
#define | MXC_F_SPIXR_IRQE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_FULL_POS)) |
IRQE_RX_FULL Mask. | |
#define | MXC_F_SPIXR_IRQE_SSA_POS 4 |
IRQE_SSA Position. | |
#define | MXC_F_SPIXR_IRQE_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SSA_POS)) |
IRQE_SSA Mask. | |
#define | MXC_F_SPIXR_IRQE_SSD_POS 5 |
IRQE_SSD Position. | |
#define | MXC_F_SPIXR_IRQE_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SSD_POS)) |
IRQE_SSD Mask. | |
#define | MXC_F_SPIXR_IRQE_FAULT_POS 8 |
IRQE_FAULT Position. | |
#define | MXC_F_SPIXR_IRQE_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_FAULT_POS)) |
IRQE_FAULT Mask. | |
#define | MXC_F_SPIXR_IRQE_ABORT_POS 9 |
IRQE_ABORT Position. | |
#define | MXC_F_SPIXR_IRQE_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_ABORT_POS)) |
IRQE_ABORT Mask. | |
#define | MXC_F_SPIXR_IRQE_TIMEOUT_POS 10 |
IRQE_TIMEOUT Position. | |
#define | MXC_F_SPIXR_IRQE_TIMEOUT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TIMEOUT_POS)) |
IRQE_TIMEOUT Mask. | |
#define | MXC_F_SPIXR_IRQE_M_DONE_POS 11 |
IRQE_M_DONE Position. | |
#define | MXC_F_SPIXR_IRQE_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_M_DONE_POS)) |
IRQE_M_DONE Mask. | |
#define | MXC_F_SPIXR_IRQE_TX_OVR_POS 12 |
IRQE_TX_OVR Position. | |
#define | MXC_F_SPIXR_IRQE_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_OVR_POS)) |
IRQE_TX_OVR Mask. | |
#define | MXC_F_SPIXR_IRQE_TX_UND_POS 13 |
IRQE_TX_UND Position. | |
#define | MXC_F_SPIXR_IRQE_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_UND_POS)) |
IRQE_TX_UND Mask. | |
#define | MXC_F_SPIXR_IRQE_RX_OVR_POS 14 |
IRQE_RX_OVR Position. | |
#define | MXC_F_SPIXR_IRQE_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_OVR_POS)) |
IRQE_RX_OVR Mask. | |
#define | MXC_F_SPIXR_IRQE_RX_UND_POS 15 |
IRQE_RX_UND Position. | |
#define | MXC_F_SPIXR_IRQE_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_UND_POS)) |
IRQE_RX_UND Mask. | |
#define | MXC_F_SPIXR_IRQE_SR0A_POS 16 |
IRQE_SR0A Position. | |
#define | MXC_F_SPIXR_IRQE_SR0A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR0A_POS)) |
IRQE_SR0A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR1A_POS 17 |
IRQE_SR1A Position. | |
#define | MXC_F_SPIXR_IRQE_SR1A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR1A_POS)) |
IRQE_SR1A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR2A_POS 18 |
IRQE_SR2A Position. | |
#define | MXC_F_SPIXR_IRQE_SR2A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR2A_POS)) |
IRQE_SR2A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR3A_POS 19 |
IRQE_SR3A Position. | |
#define | MXC_F_SPIXR_IRQE_SR3A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR3A_POS)) |
IRQE_SR3A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR4A_POS 20 |
IRQE_SR4A Position. | |
#define | MXC_F_SPIXR_IRQE_SR4A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR4A_POS)) |
IRQE_SR4A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR5A_POS 21 |
IRQE_SR5A Position. | |
#define | MXC_F_SPIXR_IRQE_SR5A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR5A_POS)) |
IRQE_SR5A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR6A_POS 22 |
IRQE_SR6A Position. | |
#define | MXC_F_SPIXR_IRQE_SR6A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR6A_POS)) |
IRQE_SR6A Mask. | |
#define | MXC_F_SPIXR_IRQE_SR7A_POS 23 |
IRQE_SR7A Position. | |
#define | MXC_F_SPIXR_IRQE_SR7A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR7A_POS)) |
IRQE_SR7A Mask. | |