MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation

TPU Peripheral Register Offsets from the TPU Base Peripheral Address. More...

Macros

#define MXC_R_TPU_CTRL   ((uint32_t)0x00000000UL)
 Offset from TPU Base Address: 0x0000
 
#define MXC_R_TPU_CIPHER_CTRL   ((uint32_t)0x00000004UL)
 Offset from TPU Base Address: 0x0004
 
#define MXC_R_TPU_HASH_CTRL   ((uint32_t)0x00000008UL)
 Offset from TPU Base Address: 0x0008
 
#define MXC_R_TPU_CRC_CTRL   ((uint32_t)0x0000000CUL)
 Offset from TPU Base Address: 0x000C
 
#define MXC_R_TPU_DMA_SRC   ((uint32_t)0x00000010UL)
 Offset from TPU Base Address: 0x0010
 
#define MXC_R_TPU_DMA_DEST   ((uint32_t)0x00000014UL)
 Offset from TPU Base Address: 0x0014
 
#define MXC_R_TPU_DMA_CNT   ((uint32_t)0x00000018UL)
 Offset from TPU Base Address: 0x0018
 
#define MXC_R_TPU_MAA_CTRL   ((uint32_t)0x0000001CUL)
 Offset from TPU Base Address: 0x001C
 
#define MXC_R_TPU_DIN   ((uint32_t)0x00000020UL)
 Offset from TPU Base Address: 0x0020
 
#define MXC_R_TPU_DOUT   ((uint32_t)0x00000030UL)
 Offset from TPU Base Address: 0x0030
 
#define MXC_R_TPU_CRC_POLY   ((uint32_t)0x00000040UL)
 Offset from TPU Base Address: 0x0040
 
#define MXC_R_TPU_CRC_VAL   ((uint32_t)0x00000044UL)
 Offset from TPU Base Address: 0x0044
 
#define MXC_R_TPU_CRC_PRNG   ((uint32_t)0x00000048UL)
 Offset from TPU Base Address: 0x0048
 
#define MXC_R_TPU_HAM_ECC   ((uint32_t)0x0000004CUL)
 Offset from TPU Base Address: 0x004C
 
#define MXC_R_TPU_CIPHER_INIT   ((uint32_t)0x00000050UL)
 Offset from TPU Base Address: 0x0050
 
#define MXC_R_TPU_CIPHER_KEY   ((uint32_t)0x00000060UL)
 Offset from TPU Base Address: 0x0060
 
#define MXC_R_TPU_HASH_DIGEST   ((uint32_t)0x00000080UL)
 Offset from TPU Base Address: 0x0080
 
#define MXC_R_TPU_HASH_MSG_SZ   ((uint32_t)0x000000C0UL)
 Offset from TPU Base Address: 0x00C0
 
#define MXC_R_TPU_MAA_MAWS   ((uint32_t)0x000000D0UL)
 Offset from TPU Base Address: 0x00D0
 

Detailed Description