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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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SRAM5 Protection Register. More...
Macros | |
#define | MXC_F_RPU_SRAM5_DMA0ACNR_POS 0 |
SRAM5_DMA0ACNR Position. | |
#define | MXC_F_RPU_SRAM5_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA0ACNR_POS)) |
SRAM5_DMA0ACNR Mask. | |
#define | MXC_F_RPU_SRAM5_DMA0ACNW_POS 1 |
SRAM5_DMA0ACNW Position. | |
#define | MXC_F_RPU_SRAM5_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA0ACNW_POS)) |
SRAM5_DMA0ACNW Mask. | |
#define | MXC_F_RPU_SRAM5_DMA1ACNR_POS 2 |
SRAM5_DMA1ACNR Position. | |
#define | MXC_F_RPU_SRAM5_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA1ACNR_POS)) |
SRAM5_DMA1ACNR Mask. | |
#define | MXC_F_RPU_SRAM5_DMA1ACNW_POS 3 |
SRAM5_DMA1ACNW Position. | |
#define | MXC_F_RPU_SRAM5_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA1ACNW_POS)) |
SRAM5_DMA1ACNW Mask. | |
#define | MXC_F_RPU_SRAM5_USBACNR_POS 4 |
SRAM5_USBACNR Position. | |
#define | MXC_F_RPU_SRAM5_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_USBACNR_POS)) |
SRAM5_USBACNR Mask. | |
#define | MXC_F_RPU_SRAM5_USBACNW_POS 5 |
SRAM5_USBACNW Position. | |
#define | MXC_F_RPU_SRAM5_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_USBACNW_POS)) |
SRAM5_USBACNW Mask. | |
#define | MXC_F_RPU_SRAM5_SYS0ACNR_POS 6 |
SRAM5_SYS0ACNR Position. | |
#define | MXC_F_RPU_SRAM5_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS0ACNR_POS)) |
SRAM5_SYS0ACNR Mask. | |
#define | MXC_F_RPU_SRAM5_SYS0ACNW_POS 7 |
SRAM5_SYS0ACNW Position. | |
#define | MXC_F_RPU_SRAM5_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS0ACNW_POS)) |
SRAM5_SYS0ACNW Mask. | |
#define | MXC_F_RPU_SRAM5_SYS1ACNR_POS 8 |
SRAM5_SYS1ACNR Position. | |
#define | MXC_F_RPU_SRAM5_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS1ACNR_POS)) |
SRAM5_SYS1ACNR Mask. | |
#define | MXC_F_RPU_SRAM5_SYS1ACNW_POS 9 |
SRAM5_SYS1ACNW Position. | |
#define | MXC_F_RPU_SRAM5_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS1ACNW_POS)) |
SRAM5_SYS1ACNW Mask. | |
#define | MXC_F_RPU_SRAM5_SDMADACNR_POS 10 |
SRAM5_SDMADACNR Position. | |
#define | MXC_F_RPU_SRAM5_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMADACNR_POS)) |
SRAM5_SDMADACNR Mask. | |
#define | MXC_F_RPU_SRAM5_SDMADACNW_POS 11 |
SRAM5_SDMADACNW Position. | |
#define | MXC_F_RPU_SRAM5_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMADACNW_POS)) |
SRAM5_SDMADACNW Mask. | |
#define | MXC_F_RPU_SRAM5_SDMAIACNR_POS 12 |
SRAM5_SDMAIACNR Position. | |
#define | MXC_F_RPU_SRAM5_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMAIACNR_POS)) |
SRAM5_SDMAIACNR Mask. | |
#define | MXC_F_RPU_SRAM5_SDMAIACNW_POS 13 |
SRAM5_SDMAIACNW Position. | |
#define | MXC_F_RPU_SRAM5_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMAIACNW_POS)) |
SRAM5_SDMAIACNW Mask. | |
#define | MXC_F_RPU_SRAM5_CRYPTOACNR_POS 14 |
SRAM5_CRYPTOACNR Position. | |
#define | MXC_F_RPU_SRAM5_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_CRYPTOACNR_POS)) |
SRAM5_CRYPTOACNR Mask. | |
#define | MXC_F_RPU_SRAM5_CRYPTOACNW_POS 15 |
SRAM5_CRYPTOACNW Position. | |
#define | MXC_F_RPU_SRAM5_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_CRYPTOACNW_POS)) |
SRAM5_CRYPTOACNW Mask. | |
#define | MXC_F_RPU_SRAM5_SDIOACNR_POS 16 |
SRAM5_SDIOACNR Position. | |
#define | MXC_F_RPU_SRAM5_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDIOACNR_POS)) |
SRAM5_SDIOACNR Mask. | |
#define | MXC_F_RPU_SRAM5_SDIOACNW_POS 17 |
SRAM5_SDIOACNW Position. | |
#define | MXC_F_RPU_SRAM5_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDIOACNW_POS)) |
SRAM5_SDIOACNW Mask. | |