![]() |
MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
|
BBSIR Protection Register. More...
Macros | |
#define | MXC_F_RPU_BBSIR_DMA0ACN_POS 0 |
BBSIR_DMA0ACN Position. | |
#define | MXC_F_RPU_BBSIR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_DMA0ACN_POS)) |
BBSIR_DMA0ACN Mask. | |
#define | MXC_F_RPU_BBSIR_DMA1ACN_POS 1 |
BBSIR_DMA1ACN Position. | |
#define | MXC_F_RPU_BBSIR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_DMA1ACN_POS)) |
BBSIR_DMA1ACN Mask. | |
#define | MXC_F_RPU_BBSIR_USBACN_POS 2 |
BBSIR_USBACN Position. | |
#define | MXC_F_RPU_BBSIR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_USBACN_POS)) |
BBSIR_USBACN Mask. | |
#define | MXC_F_RPU_BBSIR_SYS0ACN_POS 3 |
BBSIR_SYS0ACN Position. | |
#define | MXC_F_RPU_BBSIR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SYS0ACN_POS)) |
BBSIR_SYS0ACN Mask. | |
#define | MXC_F_RPU_BBSIR_SYS1ACN_POS 4 |
BBSIR_SYS1ACN Position. | |
#define | MXC_F_RPU_BBSIR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SYS1ACN_POS)) |
BBSIR_SYS1ACN Mask. | |
#define | MXC_F_RPU_BBSIR_SDMADACN_POS 5 |
BBSIR_SDMADACN Position. | |
#define | MXC_F_RPU_BBSIR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SDMADACN_POS)) |
BBSIR_SDMADACN Mask. | |
#define | MXC_F_RPU_BBSIR_SDMAIACN_POS 6 |
BBSIR_SDMAIACN Position. | |
#define | MXC_F_RPU_BBSIR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SDMAIACN_POS)) |
BBSIR_SDMAIACN Mask. | |
#define | MXC_F_RPU_BBSIR_CRYPTOACN_POS 7 |
BBSIR_CRYPTOACN Position. | |
#define | MXC_F_RPU_BBSIR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_CRYPTOACN_POS)) |
BBSIR_CRYPTOACN Mask. | |
#define | MXC_F_RPU_BBSIR_SDIOACN_POS 8 |
BBSIR_SDIOACN Position. | |
#define | MXC_F_RPU_BBSIR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_BBSIR_SDIOACN_POS)) |
BBSIR_SDIOACN Mask. | |