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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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DMA Control Register. More...
Macros | |
#define | MXC_F_DMA_CN_CH0_IEN_POS 0 |
CN_CH0_IEN Position. | |
#define | MXC_F_DMA_CN_CH0_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH0_IEN_POS)) |
CN_CH0_IEN Mask. | |
#define | MXC_F_DMA_CN_CH1_IEN_POS 1 |
CN_CH1_IEN Position. | |
#define | MXC_F_DMA_CN_CH1_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH1_IEN_POS)) |
CN_CH1_IEN Mask. | |
#define | MXC_F_DMA_CN_CH2_IEN_POS 2 |
CN_CH2_IEN Position. | |
#define | MXC_F_DMA_CN_CH2_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH2_IEN_POS)) |
CN_CH2_IEN Mask. | |
#define | MXC_F_DMA_CN_CH3_IEN_POS 3 |
CN_CH3_IEN Position. | |
#define | MXC_F_DMA_CN_CH3_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH3_IEN_POS)) |
CN_CH3_IEN Mask. | |
#define | MXC_F_DMA_CN_CH4_IEN_POS 4 |
CN_CH4_IEN Position. | |
#define | MXC_F_DMA_CN_CH4_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH4_IEN_POS)) |
CN_CH4_IEN Mask. | |
#define | MXC_F_DMA_CN_CH5_IEN_POS 5 |
CN_CH5_IEN Position. | |
#define | MXC_F_DMA_CN_CH5_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH5_IEN_POS)) |
CN_CH5_IEN Mask. | |
#define | MXC_F_DMA_CN_CH6_IEN_POS 6 |
CN_CH6_IEN Position. | |
#define | MXC_F_DMA_CN_CH6_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH6_IEN_POS)) |
CN_CH6_IEN Mask. | |
#define | MXC_F_DMA_CN_CH7_IEN_POS 7 |
CN_CH7_IEN Position. | |
#define | MXC_F_DMA_CN_CH7_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH7_IEN_POS)) |
CN_CH7_IEN Mask. | |
#define | MXC_F_DMA_CN_CH8_IEN_POS 8 |
CN_CH8_IEN Position. | |
#define | MXC_F_DMA_CN_CH8_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH8_IEN_POS)) |
CN_CH8_IEN Mask. | |
#define | MXC_F_DMA_CN_CH9_IEN_POS 9 |
CN_CH9_IEN Position. | |
#define | MXC_F_DMA_CN_CH9_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH9_IEN_POS)) |
CN_CH9_IEN Mask. | |
#define | MXC_F_DMA_CN_CH10_IEN_POS 10 |
CN_CH10_IEN Position. | |
#define | MXC_F_DMA_CN_CH10_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH10_IEN_POS)) |
CN_CH10_IEN Mask. | |
#define | MXC_F_DMA_CN_CH11_IEN_POS 11 |
CN_CH11_IEN Position. | |
#define | MXC_F_DMA_CN_CH11_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH11_IEN_POS)) |
CN_CH11_IEN Mask. | |
#define | MXC_F_DMA_CN_CH12_IEN_POS 12 |
CN_CH12_IEN Position. | |
#define | MXC_F_DMA_CN_CH12_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH12_IEN_POS)) |
CN_CH12_IEN Mask. | |
#define | MXC_F_DMA_CN_CH13_IEN_POS 13 |
CN_CH13_IEN Position. | |
#define | MXC_F_DMA_CN_CH13_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH13_IEN_POS)) |
CN_CH13_IEN Mask. | |
#define | MXC_F_DMA_CN_CH14_IEN_POS 14 |
CN_CH14_IEN Position. | |
#define | MXC_F_DMA_CN_CH14_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH14_IEN_POS)) |
CN_CH14_IEN Mask. | |
#define | MXC_F_DMA_CN_CH15_IEN_POS 15 |
CN_CH15_IEN Position. | |
#define | MXC_F_DMA_CN_CH15_IEN ((uint32_t)(0x1UL << MXC_F_DMA_CN_CH15_IEN_POS)) |
CN_CH15_IEN Mask. | |