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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. More...
Macros | |
#define | MXC_R_GPIO_EN ((uint32_t)0x00000000UL) |
Offset from GPIO Base Address: 0x0000 | |
#define | MXC_R_GPIO_EN_SET ((uint32_t)0x00000004UL) |
Offset from GPIO Base Address: 0x0004 | |
#define | MXC_R_GPIO_EN_CLR ((uint32_t)0x00000008UL) |
Offset from GPIO Base Address: 0x0008 | |
#define | MXC_R_GPIO_OUT_EN ((uint32_t)0x0000000CUL) |
Offset from GPIO Base Address: 0x000C | |
#define | MXC_R_GPIO_OUT_EN_SET ((uint32_t)0x00000010UL) |
Offset from GPIO Base Address: 0x0010 | |
#define | MXC_R_GPIO_OUT_EN_CLR ((uint32_t)0x00000014UL) |
Offset from GPIO Base Address: 0x0014 | |
#define | MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) |
Offset from GPIO Base Address: 0x0018 | |
#define | MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) |
Offset from GPIO Base Address: 0x001C | |
#define | MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) |
Offset from GPIO Base Address: 0x0020 | |
#define | MXC_R_GPIO_IN ((uint32_t)0x00000024UL) |
Offset from GPIO Base Address: 0x0024 | |
#define | MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) |
Offset from GPIO Base Address: 0x0028 | |
#define | MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) |
Offset from GPIO Base Address: 0x002C | |
#define | MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) |
Offset from GPIO Base Address: 0x0034 | |
#define | MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) |
Offset from GPIO Base Address: 0x0038 | |
#define | MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) |
Offset from GPIO Base Address: 0x003C | |
#define | MXC_R_GPIO_INT_STAT ((uint32_t)0x00000040UL) |
Offset from GPIO Base Address: 0x0040 | |
#define | MXC_R_GPIO_INT_CLR ((uint32_t)0x00000048UL) |
Offset from GPIO Base Address: 0x0048 | |
#define | MXC_R_GPIO_WAKE_EN ((uint32_t)0x0000004CUL) |
Offset from GPIO Base Address: 0x004C | |
#define | MXC_R_GPIO_WAKE_EN_SET ((uint32_t)0x00000050UL) |
Offset from GPIO Base Address: 0x0050 | |
#define | MXC_R_GPIO_WAKE_EN_CLR ((uint32_t)0x00000054UL) |
Offset from GPIO Base Address: 0x0054 | |
#define | MXC_R_GPIO_INT_DUAL_EDGE ((uint32_t)0x0000005CUL) |
Offset from GPIO Base Address: 0x005C | |
#define | MXC_R_GPIO_PAD_CFG1 ((uint32_t)0x00000060UL) |
Offset from GPIO Base Address: 0x0060 | |
#define | MXC_R_GPIO_PAD_CFG2 ((uint32_t)0x00000064UL) |
Offset from GPIO Base Address: 0x0064 | |
#define | MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) |
Offset from GPIO Base Address: 0x0068 | |
#define | MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) |
Offset from GPIO Base Address: 0x006C | |
#define | MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) |
Offset from GPIO Base Address: 0x0070 | |
#define | MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) |
Offset from GPIO Base Address: 0x0074 | |
#define | MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) |
Offset from GPIO Base Address: 0x0078 | |
#define | MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) |
Offset from GPIO Base Address: 0x007C | |
#define | MXC_R_GPIO_IS ((uint32_t)0x000000A8UL) |
Offset from GPIO Base Address: 0x00A8 | |
#define | MXC_R_GPIO_SR ((uint32_t)0x000000ACUL) |
Offset from GPIO Base Address: 0x00AC | |
#define | MXC_R_GPIO_DS ((uint32_t)0x000000B0UL) |
Offset from GPIO Base Address: 0x00B0 | |
#define | MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) |
Offset from GPIO Base Address: 0x00B4 | |
#define | MXC_R_GPIO_PS ((uint32_t)0x000000B8UL) |
Offset from GPIO Base Address: 0x00B8 | |
#define | MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) |
Offset from GPIO Base Address: 0x00C0 | |