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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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DMA Channel Configuration Register. More...
Macros | |
#define | MXC_F_DMA_CFG_CHEN_POS 0 |
CFG_CHEN Position. | |
#define | MXC_F_DMA_CFG_CHEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHEN_POS)) |
CFG_CHEN Mask. | |
#define | MXC_F_DMA_CFG_RLDEN_POS 1 |
CFG_RLDEN Position. | |
#define | MXC_F_DMA_CFG_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_RLDEN_POS)) |
CFG_RLDEN Mask. | |
#define | MXC_F_DMA_CFG_PRI_POS 2 |
CFG_PRI Position. | |
#define | MXC_F_DMA_CFG_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PRI_POS)) |
CFG_PRI Mask. | |
#define | MXC_V_DMA_CFG_PRI_HIGH ((uint32_t)0x0UL) |
CFG_PRI_HIGH Value. | |
#define | MXC_S_DMA_CFG_PRI_HIGH (MXC_V_DMA_CFG_PRI_HIGH << MXC_F_DMA_CFG_PRI_POS) |
CFG_PRI_HIGH Setting. | |
#define | MXC_V_DMA_CFG_PRI_MEDHIGH ((uint32_t)0x1UL) |
CFG_PRI_MEDHIGH Value. | |
#define | MXC_S_DMA_CFG_PRI_MEDHIGH (MXC_V_DMA_CFG_PRI_MEDHIGH << MXC_F_DMA_CFG_PRI_POS) |
CFG_PRI_MEDHIGH Setting. | |
#define | MXC_V_DMA_CFG_PRI_MEDLOW ((uint32_t)0x2UL) |
CFG_PRI_MEDLOW Value. | |
#define | MXC_S_DMA_CFG_PRI_MEDLOW (MXC_V_DMA_CFG_PRI_MEDLOW << MXC_F_DMA_CFG_PRI_POS) |
CFG_PRI_MEDLOW Setting. | |
#define | MXC_V_DMA_CFG_PRI_LOW ((uint32_t)0x3UL) |
CFG_PRI_LOW Value. | |
#define | MXC_S_DMA_CFG_PRI_LOW (MXC_V_DMA_CFG_PRI_LOW << MXC_F_DMA_CFG_PRI_POS) |
CFG_PRI_LOW Setting. | |
#define | MXC_F_DMA_CFG_REQSEL_POS 4 |
CFG_REQSEL Position. | |
#define | MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) |
CFG_REQSEL Mask. | |
#define | MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) |
CFG_REQSEL_MEMTOMEM Value. | |
#define | MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_MEMTOMEM Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) |
CFG_REQSEL_SPI0RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI0RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) |
CFG_REQSEL_SPI1RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI1RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x3UL) |
CFG_REQSEL_SPI2RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI2RX (MXC_V_DMA_CFG_REQSEL_SPI2RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI2RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) |
CFG_REQSEL_UART0RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_UART0RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) |
CFG_REQSEL_UART1RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_UART1RX (MXC_V_DMA_CFG_REQSEL_UART1RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_UART1RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_I2C0RX ((uint32_t)0x7UL) |
CFG_REQSEL_I2C0RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_I2C0RX (MXC_V_DMA_CFG_REQSEL_I2C0RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_I2C0RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_I2C1RX ((uint32_t)0x8UL) |
CFG_REQSEL_I2C1RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_I2C1RX (MXC_V_DMA_CFG_REQSEL_I2C1RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_I2C1RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_ADC ((uint32_t)0x9UL) |
CFG_REQSEL_ADC Value. | |
#define | MXC_S_DMA_CFG_REQSEL_ADC (MXC_V_DMA_CFG_REQSEL_ADC << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_ADC Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_UART2RX ((uint32_t)0xEUL) |
CFG_REQSEL_UART2RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_UART2RX (MXC_V_DMA_CFG_REQSEL_UART2RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_UART2RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI3RX ((uint32_t)0xFUL) |
CFG_REQSEL_SPI3RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI3RX (MXC_V_DMA_CFG_REQSEL_SPI3RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI3RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX ((uint32_t)0x10UL) |
CFG_REQSEL_SPI_MSS0RX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX (MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI_MSS0RX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP1 ((uint32_t)0x11UL) |
CFG_REQSEL_USBRXEP1 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP1 (MXC_V_DMA_CFG_REQSEL_USBRXEP1 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP1 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP2 ((uint32_t)0x12UL) |
CFG_REQSEL_USBRXEP2 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP2 (MXC_V_DMA_CFG_REQSEL_USBRXEP2 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP2 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP3 ((uint32_t)0x13UL) |
CFG_REQSEL_USBRXEP3 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP3 (MXC_V_DMA_CFG_REQSEL_USBRXEP3 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP3 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP4 ((uint32_t)0x14UL) |
CFG_REQSEL_USBRXEP4 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP4 (MXC_V_DMA_CFG_REQSEL_USBRXEP4 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP4 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP5 ((uint32_t)0x15UL) |
CFG_REQSEL_USBRXEP5 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP5 (MXC_V_DMA_CFG_REQSEL_USBRXEP5 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP5 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP6 ((uint32_t)0x16UL) |
CFG_REQSEL_USBRXEP6 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP6 (MXC_V_DMA_CFG_REQSEL_USBRXEP6 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP6 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP7 ((uint32_t)0x17UL) |
CFG_REQSEL_USBRXEP7 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP7 (MXC_V_DMA_CFG_REQSEL_USBRXEP7 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP7 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP8 ((uint32_t)0x18UL) |
CFG_REQSEL_USBRXEP8 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP8 (MXC_V_DMA_CFG_REQSEL_USBRXEP8 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP8 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP9 ((uint32_t)0x19UL) |
CFG_REQSEL_USBRXEP9 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP9 (MXC_V_DMA_CFG_REQSEL_USBRXEP9 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP9 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP10 ((uint32_t)0x1AUL) |
CFG_REQSEL_USBRXEP10 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP10 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP10 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBRXEP11 ((uint32_t)0x1BUL) |
CFG_REQSEL_USBRXEP11 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBRXEP11 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBRXEP11 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) |
CFG_REQSEL_SPI0TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI0TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) |
CFG_REQSEL_SPI1TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI1TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x23UL) |
CFG_REQSEL_SPI2TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI2TX (MXC_V_DMA_CFG_REQSEL_SPI2TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI2TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) |
CFG_REQSEL_UART0TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_UART0TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) |
CFG_REQSEL_UART1TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_UART1TX (MXC_V_DMA_CFG_REQSEL_UART1TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_UART1TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_I2C0TX ((uint32_t)0x27UL) |
CFG_REQSEL_I2C0TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_I2C0TX (MXC_V_DMA_CFG_REQSEL_I2C0TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_I2C0TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_I2C1TX ((uint32_t)0x28UL) |
CFG_REQSEL_I2C1TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_I2C1TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_UART2TX ((uint32_t)0x2EUL) |
CFG_REQSEL_UART2TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_UART2TX (MXC_V_DMA_CFG_REQSEL_UART2TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_UART2TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI3TX ((uint32_t)0x2FUL) |
CFG_REQSEL_SPI3TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI3TX (MXC_V_DMA_CFG_REQSEL_SPI3TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI3TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX ((uint32_t)0x30UL) |
CFG_REQSEL_SPI_MSS0TX Value. | |
#define | MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX (MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_SPI_MSS0TX Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP1 ((uint32_t)0x31UL) |
CFG_REQSEL_USBTXEP1 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP1 (MXC_V_DMA_CFG_REQSEL_USBTXEP1 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP1 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP2 ((uint32_t)0x32UL) |
CFG_REQSEL_USBTXEP2 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP2 (MXC_V_DMA_CFG_REQSEL_USBTXEP2 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP2 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP3 ((uint32_t)0x33UL) |
CFG_REQSEL_USBTXEP3 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP3 (MXC_V_DMA_CFG_REQSEL_USBTXEP3 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP3 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP4 ((uint32_t)0x34UL) |
CFG_REQSEL_USBTXEP4 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP4 (MXC_V_DMA_CFG_REQSEL_USBTXEP4 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP4 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP5 ((uint32_t)0x35UL) |
CFG_REQSEL_USBTXEP5 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP5 (MXC_V_DMA_CFG_REQSEL_USBTXEP5 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP5 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP6 ((uint32_t)0x36UL) |
CFG_REQSEL_USBTXEP6 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP6 (MXC_V_DMA_CFG_REQSEL_USBTXEP6 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP6 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP7 ((uint32_t)0x37UL) |
CFG_REQSEL_USBTXEP7 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP7 (MXC_V_DMA_CFG_REQSEL_USBTXEP7 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP7 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP8 ((uint32_t)0x38UL) |
CFG_REQSEL_USBTXEP8 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP8 (MXC_V_DMA_CFG_REQSEL_USBTXEP8 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP8 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP9 ((uint32_t)0x39UL) |
CFG_REQSEL_USBTXEP9 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP9 (MXC_V_DMA_CFG_REQSEL_USBTXEP9 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP9 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP10 ((uint32_t)0x3AUL) |
CFG_REQSEL_USBTXEP10 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP10 (MXC_V_DMA_CFG_REQSEL_USBTXEP10 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP10 Setting. | |
#define | MXC_V_DMA_CFG_REQSEL_USBTXEP11 ((uint32_t)0x3BUL) |
CFG_REQSEL_USBTXEP11 Value. | |
#define | MXC_S_DMA_CFG_REQSEL_USBTXEP11 (MXC_V_DMA_CFG_REQSEL_USBTXEP11 << MXC_F_DMA_CFG_REQSEL_POS) |
CFG_REQSEL_USBTXEP11 Setting. | |
#define | MXC_F_DMA_CFG_REQWAIT_POS 10 |
CFG_REQWAIT Position. | |
#define | MXC_F_DMA_CFG_REQWAIT ((uint32_t)(0x1UL << MXC_F_DMA_CFG_REQWAIT_POS)) |
CFG_REQWAIT Mask. | |
#define | MXC_F_DMA_CFG_TOSEL_POS 11 |
CFG_TOSEL Position. | |
#define | MXC_F_DMA_CFG_TOSEL ((uint32_t)(0x7UL << MXC_F_DMA_CFG_TOSEL_POS)) |
CFG_TOSEL Mask. | |
#define | MXC_V_DMA_CFG_TOSEL_TO4 ((uint32_t)0x0UL) |
CFG_TOSEL_TO4 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO4 (MXC_V_DMA_CFG_TOSEL_TO4 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO4 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO8 ((uint32_t)0x1UL) |
CFG_TOSEL_TO8 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO8 (MXC_V_DMA_CFG_TOSEL_TO8 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO8 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO16 ((uint32_t)0x2UL) |
CFG_TOSEL_TO16 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO16 (MXC_V_DMA_CFG_TOSEL_TO16 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO16 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO32 ((uint32_t)0x3UL) |
CFG_TOSEL_TO32 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO32 (MXC_V_DMA_CFG_TOSEL_TO32 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO32 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO64 ((uint32_t)0x4UL) |
CFG_TOSEL_TO64 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO64 (MXC_V_DMA_CFG_TOSEL_TO64 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO64 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO128 ((uint32_t)0x5UL) |
CFG_TOSEL_TO128 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO128 (MXC_V_DMA_CFG_TOSEL_TO128 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO128 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO256 ((uint32_t)0x6UL) |
CFG_TOSEL_TO256 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO256 (MXC_V_DMA_CFG_TOSEL_TO256 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO256 Setting. | |
#define | MXC_V_DMA_CFG_TOSEL_TO512 ((uint32_t)0x7UL) |
CFG_TOSEL_TO512 Value. | |
#define | MXC_S_DMA_CFG_TOSEL_TO512 (MXC_V_DMA_CFG_TOSEL_TO512 << MXC_F_DMA_CFG_TOSEL_POS) |
CFG_TOSEL_TO512 Setting. | |
#define | MXC_F_DMA_CFG_PSSEL_POS 14 |
CFG_PSSEL Position. | |
#define | MXC_F_DMA_CFG_PSSEL ((uint32_t)(0x3UL << MXC_F_DMA_CFG_PSSEL_POS)) |
CFG_PSSEL Mask. | |
#define | MXC_V_DMA_CFG_PSSEL_DIS ((uint32_t)0x0UL) |
CFG_PSSEL_DIS Value. | |
#define | MXC_S_DMA_CFG_PSSEL_DIS (MXC_V_DMA_CFG_PSSEL_DIS << MXC_F_DMA_CFG_PSSEL_POS) |
CFG_PSSEL_DIS Setting. | |
#define | MXC_V_DMA_CFG_PSSEL_DIV256 ((uint32_t)0x1UL) |
CFG_PSSEL_DIV256 Value. | |
#define | MXC_S_DMA_CFG_PSSEL_DIV256 (MXC_V_DMA_CFG_PSSEL_DIV256 << MXC_F_DMA_CFG_PSSEL_POS) |
CFG_PSSEL_DIV256 Setting. | |
#define | MXC_V_DMA_CFG_PSSEL_DIV64K ((uint32_t)0x2UL) |
CFG_PSSEL_DIV64K Value. | |
#define | MXC_S_DMA_CFG_PSSEL_DIV64K (MXC_V_DMA_CFG_PSSEL_DIV64K << MXC_F_DMA_CFG_PSSEL_POS) |
CFG_PSSEL_DIV64K Setting. | |
#define | MXC_V_DMA_CFG_PSSEL_DIV16M ((uint32_t)0x3UL) |
CFG_PSSEL_DIV16M Value. | |
#define | MXC_S_DMA_CFG_PSSEL_DIV16M (MXC_V_DMA_CFG_PSSEL_DIV16M << MXC_F_DMA_CFG_PSSEL_POS) |
CFG_PSSEL_DIV16M Setting. | |
#define | MXC_F_DMA_CFG_SRCWD_POS 16 |
CFG_SRCWD Position. | |
#define | MXC_F_DMA_CFG_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_SRCWD_POS)) |
CFG_SRCWD Mask. | |
#define | MXC_V_DMA_CFG_SRCWD_BYTE ((uint32_t)0x0UL) |
CFG_SRCWD_BYTE Value. | |
#define | MXC_S_DMA_CFG_SRCWD_BYTE (MXC_V_DMA_CFG_SRCWD_BYTE << MXC_F_DMA_CFG_SRCWD_POS) |
CFG_SRCWD_BYTE Setting. | |
#define | MXC_V_DMA_CFG_SRCWD_HALFWORD ((uint32_t)0x1UL) |
CFG_SRCWD_HALFWORD Value. | |
#define | MXC_S_DMA_CFG_SRCWD_HALFWORD (MXC_V_DMA_CFG_SRCWD_HALFWORD << MXC_F_DMA_CFG_SRCWD_POS) |
CFG_SRCWD_HALFWORD Setting. | |
#define | MXC_V_DMA_CFG_SRCWD_WORD ((uint32_t)0x2UL) |
CFG_SRCWD_WORD Value. | |
#define | MXC_S_DMA_CFG_SRCWD_WORD (MXC_V_DMA_CFG_SRCWD_WORD << MXC_F_DMA_CFG_SRCWD_POS) |
CFG_SRCWD_WORD Setting. | |
#define | MXC_F_DMA_CFG_SRCINC_POS 18 |
CFG_SRCINC Position. | |
#define | MXC_F_DMA_CFG_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_SRCINC_POS)) |
CFG_SRCINC Mask. | |
#define | MXC_F_DMA_CFG_DSTWD_POS 20 |
CFG_DSTWD Position. | |
#define | MXC_F_DMA_CFG_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CFG_DSTWD_POS)) |
CFG_DSTWD Mask. | |
#define | MXC_V_DMA_CFG_DSTWD_BYTE ((uint32_t)0x0UL) |
CFG_DSTWD_BYTE Value. | |
#define | MXC_S_DMA_CFG_DSTWD_BYTE (MXC_V_DMA_CFG_DSTWD_BYTE << MXC_F_DMA_CFG_DSTWD_POS) |
CFG_DSTWD_BYTE Setting. | |
#define | MXC_V_DMA_CFG_DSTWD_HALFWORD ((uint32_t)0x1UL) |
CFG_DSTWD_HALFWORD Value. | |
#define | MXC_S_DMA_CFG_DSTWD_HALFWORD (MXC_V_DMA_CFG_DSTWD_HALFWORD << MXC_F_DMA_CFG_DSTWD_POS) |
CFG_DSTWD_HALFWORD Setting. | |
#define | MXC_V_DMA_CFG_DSTWD_WORD ((uint32_t)0x2UL) |
CFG_DSTWD_WORD Value. | |
#define | MXC_S_DMA_CFG_DSTWD_WORD (MXC_V_DMA_CFG_DSTWD_WORD << MXC_F_DMA_CFG_DSTWD_POS) |
CFG_DSTWD_WORD Setting. | |
#define | MXC_F_DMA_CFG_DSTINC_POS 22 |
CFG_DSTINC Position. | |
#define | MXC_F_DMA_CFG_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CFG_DSTINC_POS)) |
CFG_DSTINC Mask. | |
#define | MXC_F_DMA_CFG_BRST_POS 24 |
CFG_BRST Position. | |
#define | MXC_F_DMA_CFG_BRST ((uint32_t)(0x1FUL << MXC_F_DMA_CFG_BRST_POS)) |
CFG_BRST Mask. | |
#define | MXC_F_DMA_CFG_CHDIEN_POS 30 |
CFG_CHDIEN Position. | |
#define | MXC_F_DMA_CFG_CHDIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CHDIEN_POS)) |
CFG_CHDIEN Mask. | |
#define | MXC_F_DMA_CFG_CTZIEN_POS 31 |
CFG_CTZIEN Position. | |
#define | MXC_F_DMA_CFG_CTZIEN ((uint32_t)(0x1UL << MXC_F_DMA_CFG_CTZIEN_POS)) |
CFG_CTZIEN Mask. | |