MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation

QSPI2 Protection Register. More...

Macros

#define MXC_F_RPU_QSPI2_DMA0ACN_POS   0
 QSPI2_DMA0ACN Position.
 
#define MXC_F_RPU_QSPI2_DMA0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_DMA0ACN_POS))
 QSPI2_DMA0ACN Mask.
 
#define MXC_F_RPU_QSPI2_DMA1ACN_POS   1
 QSPI2_DMA1ACN Position.
 
#define MXC_F_RPU_QSPI2_DMA1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_DMA1ACN_POS))
 QSPI2_DMA1ACN Mask.
 
#define MXC_F_RPU_QSPI2_USBACN_POS   2
 QSPI2_USBACN Position.
 
#define MXC_F_RPU_QSPI2_USBACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_USBACN_POS))
 QSPI2_USBACN Mask.
 
#define MXC_F_RPU_QSPI2_SYS0ACN_POS   3
 QSPI2_SYS0ACN Position.
 
#define MXC_F_RPU_QSPI2_SYS0ACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SYS0ACN_POS))
 QSPI2_SYS0ACN Mask.
 
#define MXC_F_RPU_QSPI2_SYS1ACN_POS   4
 QSPI2_SYS1ACN Position.
 
#define MXC_F_RPU_QSPI2_SYS1ACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SYS1ACN_POS))
 QSPI2_SYS1ACN Mask.
 
#define MXC_F_RPU_QSPI2_SDMADACN_POS   5
 QSPI2_SDMADACN Position.
 
#define MXC_F_RPU_QSPI2_SDMADACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SDMADACN_POS))
 QSPI2_SDMADACN Mask.
 
#define MXC_F_RPU_QSPI2_SDMAIACN_POS   6
 QSPI2_SDMAIACN Position.
 
#define MXC_F_RPU_QSPI2_SDMAIACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SDMAIACN_POS))
 QSPI2_SDMAIACN Mask.
 
#define MXC_F_RPU_QSPI2_CRYPTOACN_POS   7
 QSPI2_CRYPTOACN Position.
 
#define MXC_F_RPU_QSPI2_CRYPTOACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_CRYPTOACN_POS))
 QSPI2_CRYPTOACN Mask.
 
#define MXC_F_RPU_QSPI2_SDIOACN_POS   8
 QSPI2_SDIOACN Position.
 
#define MXC_F_RPU_QSPI2_SDIOACN   ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SDIOACN_POS))
 QSPI2_SDIOACN Mask.
 

Detailed Description