diff --git a/lib/sdk/Documentation/html/dma_8h_source.html b/lib/sdk/Documentation/html/dma_8h_source.html
index cd7908103c4234889688667bee146315ef096abe..0a602c4de20edcc545cf0b6661a91076e4442279 100644
--- a/lib/sdk/Documentation/html/dma_8h_source.html
+++ b/lib/sdk/Documentation/html/dma_8h_source.html
@@ -79,7 +79,7 @@ $(document).ready(function(){initNavTree('dma_8h_source.html','');});
 <div class="ttc" id="group__DMA__CFG_html_ga419ba3c18269073c520cd8ff317c7fc2"><div class="ttname"><a href="group__DMA__CFG.html#ga419ba3c18269073c520cd8ff317c7fc2">MXC_S_DMA_CFG_REQSEL_USBRXEP5</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_USBRXEP5</div><div class="ttdoc">CFG_REQSEL_USBRXEP5 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:296</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408abeec80c93a1c67928600e7faccabaeda"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408abeec80c93a1c67928600e7faccabaeda">DMA_REQSEL_SPI1RX</a></div><div class="ttdoc">SPI1 Receive DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:75</div></div>
 <div class="ttc" id="group__dma_html_gga63f28310491d665df0ad9a99dc22a77fac8cf6ef78512bdaad9bd21bf3cb2bbea"><div class="ttname"><a href="group__dma.html#gga63f28310491d665df0ad9a99dc22a77fac8cf6ef78512bdaad9bd21bf3cb2bbea">DMA_PRIO_HIGH</a></div><div class="ttdoc">High Priority. </div><div class="ttdef"><b>Definition:</b> dma.h:65</div></div>
-<div class="ttc" id="group__DMA__CFG_html_gae14d1d9ad0b5bc476ae30fb75eedb000"><div class="ttname"><a href="group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000">MXC_S_DMA_CFG_REQSEL_SPI0TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI0TX</div><div class="ttdoc">CFG_REQSEL_SPI0TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:310</div></div>
+<div class="ttc" id="group__DMA__CFG_html_gae14d1d9ad0b5bc476ae30fb75eedb000"><div class="ttname"><a href="group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000">MXC_S_DMA_CFG_REQSEL_SPI0TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI0TX</div><div class="ttdoc">CFG_REQSEL_SPI0TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:326</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gabbaaea47d5c7476b05b82fee78270f8e"><div class="ttname"><a href="group__DMA__CFG.html#gabbaaea47d5c7476b05b82fee78270f8e">MXC_V_DMA_CFG_SRCWD_WORD</a></div><div class="ttdeci">#define MXC_V_DMA_CFG_SRCWD_WORD</div><div class="ttdoc">CFG_SRCWD_WORD Value. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:391</div></div>
 <div class="ttc" id="group__dma_html_ggabdc20369150b453e75a9560fad63ab9aaf7ebfffdc12244311ce0670376f5c59f"><div class="ttname"><a href="group__dma.html#ggabdc20369150b453e75a9560fad63ab9aaf7ebfffdc12244311ce0670376f5c59f">DMA_PRESCALE_DISABLE</a></div><div class="ttdoc">Prescaler disabled. </div><div class="ttdef"><b>Definition:</b> dma.h:121</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gac4b209297fe9fee806e1ea1286cf5001"><div class="ttname"><a href="group__DMA__CFG.html#gac4b209297fe9fee806e1ea1286cf5001">MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX</div><div class="ttdoc">CFG_REQSEL_SPI_MSS0TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:328</div></div>
@@ -103,16 +103,16 @@ $(document).ready(function(){initNavTree('dma_8h_source.html','');});
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a2a637ee49124fa935d4311e9bc0af141"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a2a637ee49124fa935d4311e9bc0af141">DMA_REQSEL_SPI3TX</a></div><div class="ttdoc">SPI3 Transmit DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:104</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gaf5feeb1d958b25d1aca32e333f8ecb2b"><div class="ttname"><a href="group__DMA__CFG.html#gaf5feeb1d958b25d1aca32e333f8ecb2b">MXC_S_DMA_CFG_REQSEL_USBTXEP10</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_USBTXEP10</div><div class="ttdoc">CFG_REQSEL_USBTXEP10 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:348</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gac9cb6e4074715c6ae1900ec0dc133464"><div class="ttname"><a href="group__DMA__CFG.html#gac9cb6e4074715c6ae1900ec0dc133464">MXC_S_DMA_CFG_REQSEL_I2C0RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_I2C0RX</div><div class="ttdoc">CFG_REQSEL_I2C0RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:276</div></div>
-<div class="ttc" id="group__DMA__CFG_html_ga41434e3a003ef48bae78988373094f8b"><div class="ttname"><a href="group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b">MXC_S_DMA_CFG_REQSEL_SPI3TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI3TX</div><div class="ttdoc">CFG_REQSEL_SPI3TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:326</div></div>
+<div class="ttc" id="group__DMA__CFG_html_ga41434e3a003ef48bae78988373094f8b"><div class="ttname"><a href="group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b">MXC_S_DMA_CFG_REQSEL_SPI3TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI3TX</div><div class="ttdoc">CFG_REQSEL_SPI3TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:314</div></div>
 <div class="ttc" id="structmxc__dma__ch__regs__t_html"><div class="ttname"><a href="structmxc__dma__ch__regs__t.html">mxc_dma_ch_regs_t</a></div><div class="ttdoc">Structure type to access the DMA Registers. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:88</div></div>
 <div class="ttc" id="group__dma_html_gabdc20369150b453e75a9560fad63ab9a"><div class="ttname"><a href="group__dma.html#gabdc20369150b453e75a9560fad63ab9a">dma_prescale_t</a></div><div class="ttdeci">dma_prescale_t</div><div class="ttdoc">Enumeration for the DMA prescaler. </div><div class="ttdef"><b>Definition:</b> dma.h:120</div></div>
-<div class="ttc" id="group__DMA__CFG_html_ga94a9fbd8bb720eb2b6e289a80eca1a9a"><div class="ttname"><a href="group__DMA__CFG.html#ga94a9fbd8bb720eb2b6e289a80eca1a9a">MXC_S_DMA_CFG_REQSEL_SPI0RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI0RX</div><div class="ttdoc">CFG_REQSEL_SPI0RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:266</div></div>
+<div class="ttc" id="group__DMA__CFG_html_ga94a9fbd8bb720eb2b6e289a80eca1a9a"><div class="ttname"><a href="group__DMA__CFG.html#ga94a9fbd8bb720eb2b6e289a80eca1a9a">MXC_S_DMA_CFG_REQSEL_SPI0RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI0RX</div><div class="ttdoc">CFG_REQSEL_SPI0RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:284</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408ab1aec33d0aeb324231903d2f64cd9290"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408ab1aec33d0aeb324231903d2f64cd9290">DMA_REQSEL_I2C1RX</a></div><div class="ttdoc">I2C1 Receive DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:80</div></div>
 <div class="ttc" id="group__DMA__CFG_html_ga83b6321725f03daa527979b86d2d7fea"><div class="ttname"><a href="group__DMA__CFG.html#ga83b6321725f03daa527979b86d2d7fea">MXC_S_DMA_CFG_REQSEL_UART0RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_UART0RX</div><div class="ttdoc">CFG_REQSEL_UART0RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:272</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gaa94c4c24fc99b4d5bee38f5726950333"><div class="ttname"><a href="group__DMA__CFG.html#gaa94c4c24fc99b4d5bee38f5726950333">MXC_S_DMA_CFG_REQSEL_USBRXEP2</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_USBRXEP2</div><div class="ttdoc">CFG_REQSEL_USBRXEP2 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:290</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408ae883e8f89356b468471a8fff1947395a"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408ae883e8f89356b468471a8fff1947395a">DMA_REQSEL_UART0TX</a></div><div class="ttdoc">UART0 Transmit DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:99</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a6ea6c67b1f02c7b6abc11fddecf4ccf0"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a6ea6c67b1f02c7b6abc11fddecf4ccf0">DMA_REQSEL_SPI0TX</a></div><div class="ttdoc">SPI0 Transmit DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:96</div></div>
-<div class="ttc" id="group__DMA__CFG_html_ga2ca72c3d3e653d28c8862e1e1e73ae16"><div class="ttname"><a href="group__DMA__CFG.html#ga2ca72c3d3e653d28c8862e1e1e73ae16">MXC_S_DMA_CFG_REQSEL_SPI1RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI1RX</div><div class="ttdoc">CFG_REQSEL_SPI1RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:268</div></div>
+<div class="ttc" id="group__DMA__CFG_html_ga2ca72c3d3e653d28c8862e1e1e73ae16"><div class="ttname"><a href="group__DMA__CFG.html#ga2ca72c3d3e653d28c8862e1e1e73ae16">MXC_S_DMA_CFG_REQSEL_SPI1RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI1RX</div><div class="ttdoc">CFG_REQSEL_SPI1RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:266</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408add5be883d51e370d04134b9838c0a9c4"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408add5be883d51e370d04134b9838c0a9c4">DMA_REQSEL_SPI3RX</a></div><div class="ttdoc">SPI3 Receive DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:83</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a7bfad1b5f3c5da7fea79a810bc7d92bf"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a7bfad1b5f3c5da7fea79a810bc7d92bf">DMA_REQSEL_USBRXEP11</a></div><div class="ttdoc">USB Receive Endpoint 11 DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:95</div></div>
 <div class="ttc" id="group__DMA__CFG_html_ga945246e090f5da1fb54792f3378b8084"><div class="ttname"><a href="group__DMA__CFG.html#ga945246e090f5da1fb54792f3378b8084">MXC_S_DMA_CFG_TOSEL_TO32</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_TOSEL_TO32</div><div class="ttdoc">CFG_TOSEL_TO32 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:364</div></div>
@@ -136,10 +136,10 @@ $(document).ready(function(){initNavTree('dma_8h_source.html','');});
 <div class="ttc" id="group__DMA__CFG_html_ga2c51b0b043738b1f2b1c1df0feceaf93"><div class="ttname"><a href="group__DMA__CFG.html#ga2c51b0b043738b1f2b1c1df0feceaf93">MXC_S_DMA_CFG_PSSEL_DIV16M</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_PSSEL_DIV16M</div><div class="ttdoc">CFG_PSSEL_DIV16M Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:383</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gac80c461e8265c7576b3bf8ba7eeffee4"><div class="ttname"><a href="group__DMA__CFG.html#gac80c461e8265c7576b3bf8ba7eeffee4">MXC_S_DMA_CFG_REQSEL_USBRXEP3</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_USBRXEP3</div><div class="ttdoc">CFG_REQSEL_USBRXEP3 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:292</div></div>
 <div class="ttc" id="group__dma_html_gga6898fefb607e1b17c9371a257fd6c62da6617d79a5707efdfb1ae4b38149de5d4"><div class="ttname"><a href="group__dma.html#gga6898fefb607e1b17c9371a257fd6c62da6617d79a5707efdfb1ae4b38149de5d4">DMA_WIDTH_WORD</a></div><div class="ttdoc">DMA transfer in 32-bit words. </div><div class="ttdef"><b>Definition:</b> dma.h:146</div></div>
-<div class="ttc" id="group__DMA__CFG_html_ga59a0cdb0d780752093a04132d3aa80d3"><div class="ttname"><a href="group__DMA__CFG.html#ga59a0cdb0d780752093a04132d3aa80d3">MXC_S_DMA_CFG_REQSEL_SPI1TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI1TX</div><div class="ttdoc">CFG_REQSEL_SPI1TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:312</div></div>
+<div class="ttc" id="group__DMA__CFG_html_ga59a0cdb0d780752093a04132d3aa80d3"><div class="ttname"><a href="group__DMA__CFG.html#ga59a0cdb0d780752093a04132d3aa80d3">MXC_S_DMA_CFG_REQSEL_SPI1TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI1TX</div><div class="ttdoc">CFG_REQSEL_SPI1TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:310</div></div>
 <div class="ttc" id="group__dma_html_ga6898fefb607e1b17c9371a257fd6c62d"><div class="ttname"><a href="group__dma.html#ga6898fefb607e1b17c9371a257fd6c62d">dma_width_t</a></div><div class="ttdeci">dma_width_t</div><div class="ttdoc">DMA transfer data width. </div><div class="ttdef"><b>Definition:</b> dma.h:140</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a833d7259f8abbb014bc8ce2a33406366"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a833d7259f8abbb014bc8ce2a33406366">DMA_REQSEL_USBRXEP1</a></div><div class="ttdoc">USB Receive Endpoint 1 DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:85</div></div>
-<div class="ttc" id="group__DMA__CFG_html_gacfbe66e9428a311fde3b6879c60da6b0"><div class="ttname"><a href="group__DMA__CFG.html#gacfbe66e9428a311fde3b6879c60da6b0">MXC_S_DMA_CFG_REQSEL_SPI2RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI2RX</div><div class="ttdoc">CFG_REQSEL_SPI2RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:270</div></div>
+<div class="ttc" id="group__DMA__CFG_html_gacfbe66e9428a311fde3b6879c60da6b0"><div class="ttname"><a href="group__DMA__CFG.html#gacfbe66e9428a311fde3b6879c60da6b0">MXC_S_DMA_CFG_REQSEL_SPI2RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI2RX</div><div class="ttdoc">CFG_REQSEL_SPI2RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:268</div></div>
 <div class="ttc" id="group__DMA__CFG_html_ga24cae5e873707512474e80daa1a83d0f"><div class="ttname"><a href="group__DMA__CFG.html#ga24cae5e873707512474e80daa1a83d0f">MXC_S_DMA_CFG_REQSEL_UART1TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_UART1TX</div><div class="ttdoc">CFG_REQSEL_UART1TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:318</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a638b88e1779105dbe62a992383f7c004"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a638b88e1779105dbe62a992383f7c004">DMA_REQSEL_USBRXEP5</a></div><div class="ttdoc">USB Receive Endpoint 5 DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:89</div></div>
 <div class="ttc" id="group__DMA__CFG_html_ga3adb094f786f489adb93e9d182163a89"><div class="ttname"><a href="group__DMA__CFG.html#ga3adb094f786f489adb93e9d182163a89">MXC_S_DMA_CFG_TOSEL_TO16</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_TOSEL_TO16</div><div class="ttdoc">CFG_TOSEL_TO16 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:362</div></div>
@@ -185,7 +185,7 @@ $(document).ready(function(){initNavTree('dma_8h_source.html','');});
 <div class="ttc" id="group__DMA__CFG_html_gadf1da5f6f88cc60476e345ad0f4cb984"><div class="ttname"><a href="group__DMA__CFG.html#gadf1da5f6f88cc60476e345ad0f4cb984">MXC_S_DMA_CFG_REQSEL_I2C1TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_I2C1TX</div><div class="ttdoc">CFG_REQSEL_I2C1TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:322</div></div>
 <div class="ttc" id="group__DMA__CFG_html_ga73e07ad27c6e0f6859b3765c81a9a59f"><div class="ttname"><a href="group__DMA__CFG.html#ga73e07ad27c6e0f6859b3765c81a9a59f">MXC_S_DMA_CFG_REQSEL_USBRXEP11</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_USBRXEP11</div><div class="ttdoc">CFG_REQSEL_USBRXEP11 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:308</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408ac1cb96bb9bf8c2205d978ec59c3e0251"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408ac1cb96bb9bf8c2205d978ec59c3e0251">DMA_REQSEL_SPI_MSS0RX</a></div><div class="ttdoc">I2S Receive DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:84</div></div>
-<div class="ttc" id="group__DMA__CFG_html_gaf131253bf03e1bb7e63198431f0ff639"><div class="ttname"><a href="group__DMA__CFG.html#gaf131253bf03e1bb7e63198431f0ff639">MXC_S_DMA_CFG_REQSEL_SPI3RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI3RX</div><div class="ttdoc">CFG_REQSEL_SPI3RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:284</div></div>
+<div class="ttc" id="group__DMA__CFG_html_gaf131253bf03e1bb7e63198431f0ff639"><div class="ttname"><a href="group__DMA__CFG.html#gaf131253bf03e1bb7e63198431f0ff639">MXC_S_DMA_CFG_REQSEL_SPI3RX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI3RX</div><div class="ttdoc">CFG_REQSEL_SPI3RX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:270</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a06f099106181e0a36b0e3ddca00fd807"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a06f099106181e0a36b0e3ddca00fd807">DMA_REQSEL_I2C0TX</a></div><div class="ttdoc">I2C0 Transmit DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:101</div></div>
 <div class="ttc" id="group__dma_html_ggaf4c2df18735a743030345f350119c3d4a5673e85aa449e259b51e49b4bb2632a8"><div class="ttname"><a href="group__dma.html#ggaf4c2df18735a743030345f350119c3d4a5673e85aa449e259b51e49b4bb2632a8">DMA_TIMEOUT_32_CLK</a></div><div class="ttdoc">DMA timeout of 32 clocks. </div><div class="ttdef"><b>Definition:</b> dma.h:132</div></div>
 <div class="ttc" id="group__DMA__CFG_html_gae3dac96e9661c9dd79398ecd317a326b"><div class="ttname"><a href="group__DMA__CFG.html#gae3dac96e9661c9dd79398ecd317a326b">MXC_V_DMA_CFG_SRCWD_HALFWORD</a></div><div class="ttdeci">#define MXC_V_DMA_CFG_SRCWD_HALFWORD</div><div class="ttdoc">CFG_SRCWD_HALFWORD Value. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:389</div></div>
@@ -203,7 +203,7 @@ $(document).ready(function(){initNavTree('dma_8h_source.html','');});
 <div class="ttc" id="group__dma_html_ga0aaac740cb64a4dcb6765822121f7535"><div class="ttname"><a href="group__dma.html#ga0aaac740cb64a4dcb6765822121f7535">DMA_Start</a></div><div class="ttdeci">int DMA_Start(int ch)</div><div class="ttdoc">Start transfer. </div></div>
 <div class="ttc" id="group__DMA__CFG_html_ga22cd21918e4ce20fc8690c334c63b0c8"><div class="ttname"><a href="group__DMA__CFG.html#ga22cd21918e4ce20fc8690c334c63b0c8">MXC_S_DMA_CFG_REQSEL_USBTXEP2</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_USBTXEP2</div><div class="ttdoc">CFG_REQSEL_USBTXEP2 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:332</div></div>
 <div class="ttc" id="group__dma_html_ga84cf72d84bc90d178a0d5cbb895baec8"><div class="ttname"><a href="group__dma.html#ga84cf72d84bc90d178a0d5cbb895baec8">DMA_Init</a></div><div class="ttdeci">int DMA_Init(void)</div><div class="ttdoc">Initialize DMA resources. </div></div>
-<div class="ttc" id="group__DMA__CFG_html_gad3a1d6b9f0161f5cd633fd04a3817226"><div class="ttname"><a href="group__DMA__CFG.html#gad3a1d6b9f0161f5cd633fd04a3817226">MXC_S_DMA_CFG_REQSEL_SPI2TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI2TX</div><div class="ttdoc">CFG_REQSEL_SPI2TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:314</div></div>
+<div class="ttc" id="group__DMA__CFG_html_gad3a1d6b9f0161f5cd633fd04a3817226"><div class="ttname"><a href="group__DMA__CFG.html#gad3a1d6b9f0161f5cd633fd04a3817226">MXC_S_DMA_CFG_REQSEL_SPI2TX</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_REQSEL_SPI2TX</div><div class="ttdoc">CFG_REQSEL_SPI2TX Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:312</div></div>
 <div class="ttc" id="group__dma_html_ga7db638ec18ae5a4a328788e75ac3737f"><div class="ttname"><a href="group__dma.html#ga7db638ec18ae5a4a328788e75ac3737f">DMA_SetCallback</a></div><div class="ttdeci">int DMA_SetCallback(int ch, void(*callback)(int, int))</div><div class="ttdoc">Set channel interrupt callback. </div></div>
 <div class="ttc" id="group__DMA__CFG_html_gacb9ce2dab8569c1614027d388634ddbe"><div class="ttname"><a href="group__DMA__CFG.html#gacb9ce2dab8569c1614027d388634ddbe">MXC_S_DMA_CFG_TOSEL_TO64</a></div><div class="ttdeci">#define MXC_S_DMA_CFG_TOSEL_TO64</div><div class="ttdoc">CFG_TOSEL_TO64 Setting. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:366</div></div>
 <div class="ttc" id="group__dma_html_ggafa41a68d2bce30908687b8eb949c9408a65155976ed71ff0cf558e53365921652"><div class="ttname"><a href="group__dma.html#ggafa41a68d2bce30908687b8eb949c9408a65155976ed71ff0cf558e53365921652">DMA_REQSEL_USBRXEP7</a></div><div class="ttdoc">USB Receive Endpoint 7 DMA Request Selection. </div><div class="ttdef"><b>Definition:</b> dma.h:91</div></div>
diff --git a/lib/sdk/Documentation/html/dma__regs_8h_source.html b/lib/sdk/Documentation/html/dma__regs_8h_source.html
index 98f5a77444e6c3ebf6c6223796d6b5127bbbc133..c2ab59d805478f2fa0de1044e94f2aa96266f9e9 100644
--- a/lib/sdk/Documentation/html/dma__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/dma__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('dma__regs_8h_source.html','');});
 <div class="title">dma_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _DMA_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _DMA_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__dma__ch__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__dma__ch__regs__t.html#aefc8f81c40663db67ab4c6a2001cf205">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__dma__ch__regs__t.html#aefc8f81c40663db67ab4c6a2001cf205">cfg</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__dma__ch__regs__t.html#ad5413cbd6fba1e24f8443936ae9145e0">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__dma__ch__regs__t.html#ad5413cbd6fba1e24f8443936ae9145e0">st</a>;                   </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__dma__ch__regs__t.html#a892f57a64656deca7c61e76fc5806423">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__dma__ch__regs__t.html#a892f57a64656deca7c61e76fc5806423">src</a>;                  </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__dma__ch__regs__t.html#a1a7e35c8c34af54704b10fc27dc0266d">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__dma__ch__regs__t.html#a1a7e35c8c34af54704b10fc27dc0266d">dst</a>; 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   __IO uint32_t <a class="code" href="structmxc__dma__ch__regs__t.html#adf30fd26a788d6185c69c4e1ad2eac3b">cnt_rld</a>;              </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;} <a class="code" href="structmxc__dma__ch__regs__t.html">mxc_dma_ch_regs_t</a>;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__dma__regs__t.html">   99</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__dma__regs__t.html#a21e1cfb0af372e336277034eccefcb1a">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__dma__regs__t.html#a21e1cfb0af372e336277034eccefcb1a">cn</a>;                   </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__dma__regs__t.html#ab05350b16da1326ab852e1f047fee80e">  101</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__dma__regs__t.html#ab05350b16da1326ab852e1f047fee80e">intr</a>;                 </div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;    __R  uint32_t rsv_0x8_0xff[62];</div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__dma__regs__t.html#a27780f59e82ed35bce90a36944664c6c">  103</a></span>&#160;    __IO <a class="code" href="structmxc__dma__ch__regs__t.html">mxc_dma_ch_regs_t</a>    ch[8];    </div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;} <a class="code" href="structmxc__dma__regs__t.html">mxc_dma_regs_t</a>;</div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;</div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;<span class="comment">/* Register offsets for module DMA */</span></div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga7e32848dfdff3e710b017ededb95b48c">  113</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_CFG                      ((uint32_t)0x00000100UL) </span></div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga3ddaeee114356d585d13ca819f8c2081">  114</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_ST                       ((uint32_t)0x00000104UL) </span></div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga4b4502e44af59c89e9aa834bc736e143">  115</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_SRC                      ((uint32_t)0x00000108UL) </span></div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga742141dd814b737c959514ea099c0bd9">  116</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_DST                      ((uint32_t)0x0000010CUL) </span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#gae08079176f6556b87bff7b702832a7a0">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_CNT                      ((uint32_t)0x00000110UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga1808779440fa7f7f742495c4624e1c2c">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_SRC_RLD                  ((uint32_t)0x00000114UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga5abf5185f9050582c2080a8f35730da5">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_DST_RLD                  ((uint32_t)0x00000118UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga4ea54e1e2896512ffd804babe7d11f16">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_CNT_RLD                  ((uint32_t)0x0000011CUL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#gae2c33964cfa27a2401a1f74a9e656ecf">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_CN                       ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga6a782aec41819f3977692718c2bc38b9">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_INTR                     ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__DMA__Register__Offsets.html#ga22f69dc6133d81efa7c37da456cc5d90">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_DMA_CH                       ((uint32_t)0x00000100UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga0d48022b670db60fb47295ae53a5ed6a">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH0_IEN_POS                       0 </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga2fa43dcc66e28ddcb3492c0d14418c0e">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH0_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH0_IEN_POS)) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gacbc8d96f1b88c791f8cb77afc75dfa98">  135</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH1_IEN_POS                       1 </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga917d01cea603dda759124c9c6c9851a2">  136</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH1_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH1_IEN_POS)) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gadbd5dd353f49dbe7fcc9ea95f2871769">  138</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH2_IEN_POS                       2 </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga293c515505c1657e6fda4c8652427128">  139</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH2_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH2_IEN_POS)) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga457b73cb88fbd075a8af3731feb8014d">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH3_IEN_POS                       3 </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga6246140775b36041cb3dd8e94c04580c">  142</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH3_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH3_IEN_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaff45133c027b287b1f64e8c570b6be73">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH4_IEN_POS                       4 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga8c14181a489bb391330caba5da58f135">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH4_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH4_IEN_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gafd2e33adf2d00c0717d288f4cc41e0d2">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH5_IEN_POS                       5 </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gad71c0eeb98ba75df7071189accca3e95">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH5_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH5_IEN_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gabb41f0db418d78d13d58b708781e8151">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH6_IEN_POS                       6 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gadaee65afe92d1a253e4301a3ae4e6c78">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH6_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH6_IEN_POS)) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga4a4678eeb3ce1f591d07e42b501a0cfe">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH7_IEN_POS                       7 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaa04622eeb0d62b3149bc3ffcf24ed171">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH7_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH7_IEN_POS)) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga0f3947db3bbe7818a359d4f2841da5bf">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH8_IEN_POS                       8 </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaa0793a949fcfe137311c38c8e1e452fc">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH8_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH8_IEN_POS)) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gadc3f00825c640bf298d00962c7874381">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH9_IEN_POS                       9 </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga0a2f82a3f811b2d42b6aa8cb2a268990">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH9_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH9_IEN_POS)) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga2c03660a4c36656b70d783ba56a99828">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH10_IEN_POS                      10 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga293dd9af543756d19ecc7123bc6e28d4">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH10_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH10_IEN_POS)) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga94dc253feb04cc1194f18a8b52d1539d">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH11_IEN_POS                      11 </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga1efc732ea74cc0673c1a7380ef36414c">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH11_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH11_IEN_POS)) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaea3dd5c62a1213b7ae660e63d2c2b006">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH12_IEN_POS                      12 </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga38776061a14cf64251fe16e4dfad6c49">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH12_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH12_IEN_POS)) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gace0fd55cd838afe0a52a4fefe8b339b6">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH13_IEN_POS                      13 </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga396b5e16d9c58e4e87b0cdad1125c365">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH13_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH13_IEN_POS)) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga19adf9265edc475caa9d3f1a963884fe">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH14_IEN_POS                      14 </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaaff0a2d7b6ceb70a648f3aca3b8abb9e">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH14_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH14_IEN_POS)) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga6c5874bee4e18238c9f4f9bde46ee860">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH15_IEN_POS                      15 </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaa72823e410849805c86175a6daa45e3c">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH15_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH15_IEN_POS)) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga57b288d992d1d92f75c4cccac1c3cbaf">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH0_IPEND_POS                   0 </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga89f23258e3d69615ae8c343bc6fa5ce7">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH0_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH0_IPEND_POS)) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga7c79ef9b04caa86bb4fff9d5ac1ee889">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH1_IPEND_POS                   1 </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga09c03353d3f53840b968e8a725eb9b54">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH1_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH1_IPEND_POS)) </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gae4d2a765f372651876ea0852d6ca5be1">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH2_IPEND_POS                   2 </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga0022fa66237e4e625ece19f8a6b9d795">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH2_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH2_IPEND_POS)) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gac58ff1fe84266baba9d4d6ab18d5690d">  197</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH3_IPEND_POS                   3 </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga6ca2a671d5915cb5dc297f9b810ad704">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH3_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH3_IPEND_POS)) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga92a274d388492d89a8dbac1c92777d38">  200</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH4_IPEND_POS                   4 </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gaf6584c1d63d0761e790ab5649aeaa58f">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH4_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH4_IPEND_POS)) </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gab41f19a54b983e142c64546f07eff94e">  203</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH5_IPEND_POS                   5 </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga6cb03ad810963e17a39260f111821677">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH5_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH5_IPEND_POS)) </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga26cd70a7d36c39fd8450011c171b5be8">  206</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH6_IPEND_POS                   6 </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga5d7a2e3e28821d3bcb40b4678a4caece">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH6_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH6_IPEND_POS)) </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga438e25eccbc6bc58a704672376074297">  209</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH7_IPEND_POS                   7 </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gaa8fcfea2d98e3cc5989e7ba08efc66af">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH7_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH7_IPEND_POS)) </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga15b217f6bf29a8f31c1553bf42b306cd">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH8_IPEND_POS                   8 </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga189ccfd95375ff10b36a9045f5e6aac5">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH8_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH8_IPEND_POS)) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga68fcb6d800e48feb464e8e7c46c84b5b">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH9_IPEND_POS                   9 </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga4f372d4dea6652da4341e2b4673da9a2">  216</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH9_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH9_IPEND_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gab59de7f3592c2ac8b3bcf4068a4ab891">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH10_IPEND_POS                  10 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga7c907db9dc7111989dd01d8f2d6ba3b2">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH10_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH10_IPEND_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga31d236eb1226390cb3517e12189a6a7a">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH11_IPEND_POS                  11 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga61b10f79c2c80d1af6d701b413224850">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH11_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH11_IPEND_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gac2d8a83e68b16fba9cd89ca589360a8e">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH12_IPEND_POS                  12 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga3c41a714c951e2c3301b1f19ea7ff57c">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH12_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH12_IPEND_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga396ddec1bfa54bbdbddabeae7b3c1010">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH13_IPEND_POS                  13 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gafc4e738aad3bef7e85d2d416b5469046">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH13_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH13_IPEND_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga0960a66936967afaab6ba663f7f31c6c">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH14_IPEND_POS                  14 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga03187088c5b74dd5e43039bc4eb021a0">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH14_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH14_IPEND_POS)) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gabadc997a9d6c1a530a834933c3f705c2">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH15_IPEND_POS                  15 </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga63868190062f637557c23e2de0218cae">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH15_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH15_IPEND_POS)) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gad8788d2be626779c965bd8edae4c2057">  244</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHEN_POS                         0 </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabb9215341b86b5bd08d00c83a5f17cbf">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHEN                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_CHEN_POS)) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4aef700763abb52f9b5ce089c6e118e4">  247</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_RLDEN_POS                        1 </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadf5c7b670153984d28e858b6375c6135">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_RLDEN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_RLDEN_POS)) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga8d3eae53922e0c21fb29e4ef8ee2c90c">  250</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PRI_POS                          2 </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab1c2846d4535cd0319ef23599cb16f6f">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PRI                              ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_PRI_POS)) </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaec995470f08943883e5f60f83163ca8d">  252</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_HIGH                         ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2c6b67059a94cb9e63438faa10e18908">  253</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_HIGH                         (MXC_V_DMA_CFG_PRI_HIGH &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacd9a18766517306801ff34d4ebf819f7">  254</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_MEDHIGH                      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2bd08149d46a3d823b60468fd2250293">  255</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_MEDHIGH                      (MXC_V_DMA_CFG_PRI_MEDHIGH &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga55cbadab3b8fd40edf267c1b39fd0bd1">  256</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_MEDLOW                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaacadb81a6a1ef7fb7aabcc92f6df1a2f">  257</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_MEDLOW                       (MXC_V_DMA_CFG_PRI_MEDLOW &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1b5f0a12fb6b444edfae225dfb6e7bdf">  258</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_LOW                          ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga52b9e89b113d30ee7fee1aceecd4619f">  259</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_LOW                          (MXC_V_DMA_CFG_PRI_LOW &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga03b16149181424405cc14cc5aacc6a6b">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQSEL_POS                       4 </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaddaf5defb97d4587fafb78575d40e037">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQSEL                           ((uint32_t)(0x3FUL &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS)) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga008c60c169b71e7075e95e7f1aa422c3">  263</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM                  ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaab33bbc5b4fcb13a55cdb8e716b2df95">  264</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM                  (MXC_V_DMA_CFG_REQSEL_MEMTOMEM &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaec6de3f265bcfedfbd8c650c4c43ecd0">  265</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI0RX                    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga94a9fbd8bb720eb2b6e289a80eca1a9a">  266</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI0RX                    (MXC_V_DMA_CFG_REQSEL_SPI0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga090233ebbf1ab67f94bf3427b81087e8">  267</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI1RX                    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2ca72c3d3e653d28c8862e1e1e73ae16">  268</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI1RX                    (MXC_V_DMA_CFG_REQSEL_SPI1RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga48dc9d5a7aba7592f779ed9667201a28">  269</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI2RX                    ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacfbe66e9428a311fde3b6879c60da6b0">  270</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI2RX                    (MXC_V_DMA_CFG_REQSEL_SPI2RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3a3b5f284123dcfbd2e6752db69b93bd">  271</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART0RX                   ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga83b6321725f03daa527979b86d2d7fea">  272</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART0RX                   (MXC_V_DMA_CFG_REQSEL_UART0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaac9f95327aec4a7e10609f4e06e3e408">  273</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART1RX                   ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga9dc214dee46338800b770bd8d436c09e">  274</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART1RX                   (MXC_V_DMA_CFG_REQSEL_UART1RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf67b9c1b93435eeb839fbb713bbc28ef">  275</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C0RX                    ((uint32_t)0x7UL) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac9cb6e4074715c6ae1900ec0dc133464">  276</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C0RX                    (MXC_V_DMA_CFG_REQSEL_I2C0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab33e5862e5a84f60181576793cee3543">  277</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C1RX                    ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa871e9c25f06854c77f4a13ef72c4868">  278</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C1RX                    (MXC_V_DMA_CFG_REQSEL_I2C1RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaada7a5a00bab0a0d540b4690d5789ea3">  279</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_ADC                       ((uint32_t)0x9UL) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gace9660a09dc239db5fbcc19a2eff1a5d">  280</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_ADC                       (MXC_V_DMA_CFG_REQSEL_ADC &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga32fa58a44707ec0dc04c2475ede271b3">  281</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART2RX                   ((uint32_t)0xEUL) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga558829f658022cdc489bd0906227752a">  282</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART2RX                   (MXC_V_DMA_CFG_REQSEL_UART2RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4449ecef8d439c68653316c9dbb92456">  283</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI3RX                    ((uint32_t)0xFUL) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf131253bf03e1bb7e63198431f0ff639">  284</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI3RX                    (MXC_V_DMA_CFG_REQSEL_SPI3RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4890f1dff25f80855704fe86b8d173ac">  285</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX                ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga625831734be28d96e7bcc8090acbe3b8">  286</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX                (MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga5e7f98d000749aaf98ff3e2ed272978c">  287</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP1                  ((uint32_t)0x11UL) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc5b39f84758ac7b43c7e8c127eeab46">  288</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP1                  (MXC_V_DMA_CFG_REQSEL_USBRXEP1 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga50c86e65c8303114b72558ec25623448">  289</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP2                  ((uint32_t)0x12UL) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa94c4c24fc99b4d5bee38f5726950333">  290</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP2                  (MXC_V_DMA_CFG_REQSEL_USBRXEP2 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga7cda6e10d7f60961f46dc0d387e293f4">  291</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP3                  ((uint32_t)0x13UL) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac80c461e8265c7576b3bf8ba7eeffee4">  292</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP3                  (MXC_V_DMA_CFG_REQSEL_USBRXEP3 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3a74c1bf70decd47173fc13bb7317a47">  293</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP4                  ((uint32_t)0x14UL) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga655204beb229c26ccc3809e1edaa7361">  294</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP4                  (MXC_V_DMA_CFG_REQSEL_USBRXEP4 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa5e45fafd8e34b7bedf68276e94dc022">  295</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP5                  ((uint32_t)0x15UL) </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga419ba3c18269073c520cd8ff317c7fc2">  296</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP5                  (MXC_V_DMA_CFG_REQSEL_USBRXEP5 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa40064aedd82461156cafea9f28b5637">  297</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP6                  ((uint32_t)0x16UL) </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6330761be59ddfd7836bfd815ac81573">  298</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP6                  (MXC_V_DMA_CFG_REQSEL_USBRXEP6 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga85a962ed68cc2038972e562ad704fe52">  299</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP7                  ((uint32_t)0x17UL) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga856ddf760786a7a1d85340989b85d90b">  300</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP7                  (MXC_V_DMA_CFG_REQSEL_USBRXEP7 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc358244c44c42e8a390eca2e39420a0">  301</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP8                  ((uint32_t)0x18UL) </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1487a02e09dbbb6df355a74776596f72">  302</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP8                  (MXC_V_DMA_CFG_REQSEL_USBRXEP8 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga76611849a0724ef4c0a61c53c10a58b9">  303</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP9                  ((uint32_t)0x19UL) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac404cca1dac17794e20bfd25655b2443">  304</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP9                  (MXC_V_DMA_CFG_REQSEL_USBRXEP9 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga80e5a07e525c8358ec6800a604b4f3cd">  305</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP10                 ((uint32_t)0x1AUL) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga17fca0704d673883615813c0e436a486">  306</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP10                 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga63855563f74194b2702f36722169c667">  307</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP11                 ((uint32_t)0x1BUL) </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga73e07ad27c6e0f6859b3765c81a9a59f">  308</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP11                 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab57be50928424427440ae1550e458610">  309</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI0TX                    ((uint32_t)0x21UL) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000">  310</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI0TX                    (MXC_V_DMA_CFG_REQSEL_SPI0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2063a26c093bfe3699134a9a3defa403">  311</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI1TX                    ((uint32_t)0x22UL) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga59a0cdb0d780752093a04132d3aa80d3">  312</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI1TX                    (MXC_V_DMA_CFG_REQSEL_SPI1TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabe3ae057abab200af7f84e92cc0d55c4">  313</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI2TX                    ((uint32_t)0x23UL) </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gad3a1d6b9f0161f5cd633fd04a3817226">  314</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI2TX                    (MXC_V_DMA_CFG_REQSEL_SPI2TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6f7d5538511de9c21714d8a8f4b84a4b">  315</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART0TX                   ((uint32_t)0x24UL) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6b454bf5654872a6b0954865dfdedc4d">  316</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART0TX                   (MXC_V_DMA_CFG_REQSEL_UART0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2dbc01d93a93b32b8f3befbad23b3917">  317</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART1TX                   ((uint32_t)0x25UL) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga24cae5e873707512474e80daa1a83d0f">  318</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART1TX                   (MXC_V_DMA_CFG_REQSEL_UART1TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc396c3a0fcec0fdca843d1babac1f94">  319</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C0TX                    ((uint32_t)0x27UL) </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga19ccddaaec7f5d15362c3331c1901411">  320</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C0TX                    (MXC_V_DMA_CFG_REQSEL_I2C0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadd56f4442caac4bd7bb09552519c882b">  321</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C1TX                    ((uint32_t)0x28UL) </span></div><div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadf1da5f6f88cc60476e345ad0f4cb984">  322</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C1TX                    (MXC_V_DMA_CFG_REQSEL_I2C1TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf66d145949474eba9cf18275aa12fa40">  323</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART2TX                   ((uint32_t)0x2EUL) </span></div><div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gafbd3c8451764f125184213be8adedc95">  324</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART2TX                   (MXC_V_DMA_CFG_REQSEL_UART2TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga69cb063b48ef0fd41b6bd7db7aae9def">  325</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI3TX                    ((uint32_t)0x2FUL) </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b">  326</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI3TX                    (MXC_V_DMA_CFG_REQSEL_SPI3TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga387dae08cef4a75de7a2fcd15642d54d">  327</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX                ((uint32_t)0x30UL) </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac4b209297fe9fee806e1ea1286cf5001">  328</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX                (MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga54e9b247505edf08571690565b72b647">  329</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP1                  ((uint32_t)0x31UL) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gad954469358987e3d3dc0c78356cee783">  330</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP1                  (MXC_V_DMA_CFG_REQSEL_USBTXEP1 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaae3c21f2a013c9c427c1fa637b743a9f">  331</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP2                  ((uint32_t)0x32UL) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga22cd21918e4ce20fc8690c334c63b0c8">  332</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP2                  (MXC_V_DMA_CFG_REQSEL_USBTXEP2 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga66523c77b67a8b01e3c00aa0622b2850">  333</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP3                  ((uint32_t)0x33UL) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3255788a83195bb2d0f1a4e37f47cdb0">  334</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP3                  (MXC_V_DMA_CFG_REQSEL_USBTXEP3 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacdf5ab8392e256af13bc4049194b4152">  335</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP4                  ((uint32_t)0x34UL) </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga515ceb7d26504984b1ca229cec786b22">  336</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP4                  (MXC_V_DMA_CFG_REQSEL_USBTXEP4 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf556c7996dd6f76c06ebdcb429ebd04d">  337</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP5                  ((uint32_t)0x35UL) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa1c6cad4dfb0766726238cf29cda1509">  338</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP5                  (MXC_V_DMA_CFG_REQSEL_USBTXEP5 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga59c9157cdefab9916214f981d7058f09">  339</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP6                  ((uint32_t)0x36UL) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga854bd263d54bee8622305ea0cd65ed44">  340</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP6                  (MXC_V_DMA_CFG_REQSEL_USBTXEP6 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga7d8a74e28a64c4e6377ea6ecc7423790">  341</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP7                  ((uint32_t)0x37UL) </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga51288c54b6422d7775d84780efbe757a">  342</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP7                  (MXC_V_DMA_CFG_REQSEL_USBTXEP7 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf9fe56970c382913244f4d39eb8c012f">  343</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP8                  ((uint32_t)0x38UL) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6c3f75da4dceae47af0ff9bea6dd9a10">  344</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP8                  (MXC_V_DMA_CFG_REQSEL_USBTXEP8 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga0721eb0d6e0c54ae9a31d59f07f04b32">  345</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP9                  ((uint32_t)0x39UL) </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga691bc44c837e4c3f0bee6d6d1fc9b13d">  346</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP9                  (MXC_V_DMA_CFG_REQSEL_USBTXEP9 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00347"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac4633e78570f85d2afbe5f30ae0f0c15">  347</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP10                 ((uint32_t)0x3AUL) </span></div><div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf5feeb1d958b25d1aca32e333f8ecb2b">  348</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP10                 (MXC_V_DMA_CFG_REQSEL_USBTXEP10 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga526b7edb52a69d3d920f2a018fc01a1f">  349</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP11                 ((uint32_t)0x3BUL) </span></div><div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga30d56f29d9829264795b6086ed591973">  350</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP11                 (MXC_V_DMA_CFG_REQSEL_USBTXEP11 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga89fc4a96f38da5ecd1023ec972eb3baf">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQWAIT_POS                      10 </span></div><div class="line"><a name="l00353"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga91987cb8e9ba16fb16e1736e0d00463b">  353</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQWAIT                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_REQWAIT_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga68560874214b251d0705821d105d40e8">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_TOSEL_POS                        11 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga82b8a26be3bdd6a424e72693df35e07a">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_TOSEL                            ((uint32_t)(0x7UL &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS)) </span></div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga15b35265b7f5af2945e502d69f840c93">  357</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO4                        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa65a8e6e9a47f8baaf48bfbe30e857e5">  358</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO4                        (MXC_V_DMA_CFG_TOSEL_TO4 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga32ca288d8df91355807a352234f8fe6b">  359</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO8                        ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab37cd6e6aab4352f55c6bf2b7c8ebf8c">  360</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO8                        (MXC_V_DMA_CFG_TOSEL_TO8 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3bfc3ba550e5ad6096e518aa2eb49b17">  361</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO16                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3adb094f786f489adb93e9d182163a89">  362</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO16                       (MXC_V_DMA_CFG_TOSEL_TO16 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab278c7ae0475ca7ee04891fdde01bc89">  363</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO32                       ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga945246e090f5da1fb54792f3378b8084">  364</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO32                       (MXC_V_DMA_CFG_TOSEL_TO32 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac4ee36e08c1cf6669c0c86babaaf3236">  365</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO64                       ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacb9ce2dab8569c1614027d388634ddbe">  366</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO64                       (MXC_V_DMA_CFG_TOSEL_TO64 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaaa64e15a23c5f9428a335cdaaa3276fd">  367</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO128                      ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1b0df84d9dd17d90b7aae0e5d9fc17cb">  368</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO128                      (MXC_V_DMA_CFG_TOSEL_TO128 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga8b0b811ed8e654f9b5c01649fd5f7222">  369</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO256                      ((uint32_t)0x6UL) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa8881ab56ad4bb8c7fa593a75aef23a8">  370</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO256                      (MXC_V_DMA_CFG_TOSEL_TO256 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc276290f72d8f30f56798ed096b5eb8">  371</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO512                      ((uint32_t)0x7UL) </span></div><div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga7a52b4d7b63f05aa7f40d473e402909a">  372</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO512                      (MXC_V_DMA_CFG_TOSEL_TO512 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga36f6611f1b51448654cbfc34fa09625e">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PSSEL_POS                        14 </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac6a613169c808ae7e321df9766f73774">  375</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PSSEL                            ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga9e2e528c615634cd3cbe4a42aaab8d99">  376</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIS                        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae8500e02648065503cb8d0724f64439f">  377</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIS                        (MXC_V_DMA_CFG_PSSEL_DIS &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga73bfd76f65f1253eb5932e546e12917d">  378</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIV256                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab33e7b4da545b54e51bdd8e37bf31a1f">  379</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIV256                     (MXC_V_DMA_CFG_PSSEL_DIV256 &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabcee969c3d08fd3fb01ad2aff3ea3ac0">  380</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIV64K                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga81c828d319077f1a3e4740ea14bd29c5">  381</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIV64K                     (MXC_V_DMA_CFG_PSSEL_DIV64K &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2a8e4ce350752be63a899c7fd950e759">  382</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIV16M                     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2c51b0b043738b1f2b1c1df0feceaf93">  383</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIV16M                     (MXC_V_DMA_CFG_PSSEL_DIV16M &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae72cce35caa6cf5c5b64f42ce2d33d9c">  385</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCWD_POS                        16 </span></div><div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga8542857f944797e85d8b808e1d77ed80">  386</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCWD                            ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS)) </span></div><div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3495e30108a57dcf2d6b7c3e60f516f1">  387</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_SRCWD_BYTE                       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab89ad10788611110f80df88e2555b464">  388</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_SRCWD_BYTE                       (MXC_V_DMA_CFG_SRCWD_BYTE &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS) </span></div><div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae3dac96e9661c9dd79398ecd317a326b">  389</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_SRCWD_HALFWORD                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac8ec688df9a7d8cda25bea18bc7d6e8c">  390</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_SRCWD_HALFWORD                   (MXC_V_DMA_CFG_SRCWD_HALFWORD &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS) </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabbaaea47d5c7476b05b82fee78270f8e">  391</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_SRCWD_WORD                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaabc2ee25b7dc18689372e5d339e2613b">  392</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_SRCWD_WORD                       (MXC_V_DMA_CFG_SRCWD_WORD &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS) </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2ca77d2c32cf4cbeb2c7af131e2c1b96">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCINC_POS                       18 </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga833bec7c08604767bd213c2806773d8e">  395</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCINC                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_SRCINC_POS)) </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga27f8d1250a4f6a36b3d64b7827434007">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTWD_POS                        20 </span></div><div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6963e9e6aa3b9546fdb6539bb26591ff">  398</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTWD                            ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga317bcdd6d71cc64923332db1f1ea254f">  399</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_DSTWD_BYTE                       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadfc85f260796ac3c9673ede9885f0328">  400</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_DSTWD_BYTE                       (MXC_V_DMA_CFG_DSTWD_BYTE &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS) </span></div><div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1a5027e22465fe7a5fe4ad2d36c99a85">  401</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_DSTWD_HALFWORD                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga9127fddb84cfa1694e143c092a147cdc">  402</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_DSTWD_HALFWORD                   (MXC_V_DMA_CFG_DSTWD_HALFWORD &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS) </span></div><div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac25fe229dea35959b43d47426aa2bfe4">  403</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_DSTWD_WORD                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00404"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga0131dd27829b3bf79c8a560b992482ad">  404</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_DSTWD_WORD                       (MXC_V_DMA_CFG_DSTWD_WORD &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS) </span></div><div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa3d66754a80c75b1cec1191d7fbee094">  406</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTINC_POS                       22 </span></div><div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4b364def0a6d9037ea58bfb80a42bfa1">  407</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTINC                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_DSTINC_POS)) </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaff33a3a5a97caa029365b3098786a005">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_BRST_POS                         24 </span></div><div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga5a04e3893d8635ff9d231782748f9748">  410</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_BRST                             ((uint32_t)(0x1FUL &lt;&lt; MXC_F_DMA_CFG_BRST_POS)) </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga692f74730f8594dca7def7100c4e76dc">  412</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHDIEN_POS                       30 </span></div><div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga505cf35e7cfb27aef90c9deda19e9560">  413</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHDIEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_CHDIEN_POS)) </span></div><div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa1d7ca7d80680d4b559a97fd002da5db">  415</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CTZIEN_POS                       31 </span></div><div class="line"><a name="l00416"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaae295cd36d93fa6328055fb38d967b73">  416</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CTZIEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_CTZIEN_POS)) </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga5645c288f283ce11642dbc64263005d1">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CH_ST_POS                         0 </span></div><div class="line"><a name="l00427"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gaf895eb5b6925ed84f348e9d776b70406">  427</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CH_ST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_CH_ST_POS)) </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gabec7a3b5aa15482766edc29249552e5a">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_IPEND_POS                         1 </span></div><div class="line"><a name="l00430"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gabd2a9320393484740eabc1bac1b2317a">  430</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_IPEND                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_IPEND_POS)) </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gad0a06dfd7ab044a16177723541d54dd2">  432</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CTZ_ST_POS                        2 </span></div><div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga30ddebf6ba447de2d435c11d73adf634">  433</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CTZ_ST                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_CTZ_ST_POS)) </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gabf05b8a722ecde54629ad1b737840ee9">  435</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_RLD_ST_POS                        3 </span></div><div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gaf2c0d526a9335c0ff83853747fba16ef">  436</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_RLD_ST                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_RLD_ST_POS)) </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga83b9ed97423571f29c194ff90ef99e2a">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_BUS_ERR_POS                       4 </span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gafdd0fce12884fac18f3c4656eaa7249d">  439</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_BUS_ERR                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_BUS_ERR_POS)) </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga992544df6f0a968273341705d4ac3ace">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_TO_ST_POS                         6 </span></div><div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga340e62cc8777c228baeb0c7d850aa55a">  442</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_TO_ST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_TO_ST_POS)) </span></div><div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="group__DMA__SRC.html#ga08418c424a6a371af6a83c003df2ec63">  456</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_ADDR_POS                         0 </span></div><div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group__DMA__SRC.html#ga06cd0f3c2335474d0dd7fe80ca87bf18">  457</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_DMA_SRC_ADDR_POS)) </span></div><div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="group__DMA__DST.html#ga41867234ec8188ae2c4cc3ce4e5cc765">  471</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_ADDR_POS                         0 </span></div><div class="line"><a name="l00472"></a><span class="lineno"><a class="line" href="group__DMA__DST.html#ga724d286463d1b6249509f89cf72fba08">  472</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_DMA_DST_ADDR_POS)) </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__DMA__CNT.html#ga3eee46c3f015d14631d1f054dfab074c">  485</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_CNT_POS                          0 </span></div><div class="line"><a name="l00486"></a><span class="lineno"><a class="line" href="group__DMA__CNT.html#ga164f175a19499778c7f8400a1da02332">  486</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_DMA_CNT_CNT_POS)) </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__DMA__SRC__RLD.html#ga940f51543f2b861c8280182d98a58078">  497</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS                  0 </span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group__DMA__SRC__RLD.html#ga05c23fee088a6e5e1a4e4e68c6463f7a">  498</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_RLD_SRC_RLD                      ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) </span></div><div class="line"><a name="l00509"></a><span class="lineno"><a class="line" href="group__DMA__DST__RLD.html#ga100dd74eec7b0c2d5a40238338ea0ee3">  509</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_RLD_DST_RLD_POS                  0 </span></div><div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group__DMA__DST__RLD.html#gaedc9fd3c9d4287f7015d976cb26d6a01">  510</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_RLD_DST_RLD                      ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_DMA_DST_RLD_DST_RLD_POS)) </span></div><div class="line"><a name="l00520"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#ga52d6009b54bcf3ddee695f5d645e58ea">  520</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS                  0 </span></div><div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#gab72baed67e0f50d12c18162894963e1b">  521</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_CNT_RLD                      ((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) </span></div><div class="line"><a name="l00523"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#ga06f8c3679bafd7e0d7d7c8ba4d7de153">  523</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_RLDEN_POS                    31 </span></div><div class="line"><a name="l00524"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#ga2b2627df47054c575889174515d15ed8">  524</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_RLDEN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CNT_RLD_RLDEN_POS)) </span></div><div class="line"><a name="l00528"></a><span class="lineno">  528</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00529"></a><span class="lineno">  529</span>&#160;}</div><div class="line"><a name="l00530"></a><span class="lineno">  530</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00531"></a><span class="lineno">  531</span>&#160;</div><div class="line"><a name="l00532"></a><span class="lineno">  532</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _DMA_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__dma__ch__regs__t_html_adf30fd26a788d6185c69c4e1ad2eac3b"><div class="ttname"><a href="structmxc__dma__ch__regs__t.html#adf30fd26a788d6185c69c4e1ad2eac3b">mxc_dma_ch_regs_t::cnt_rld</a></div><div class="ttdeci">__IO uint32_t cnt_rld</div><div class="ttdoc">0x11C: DMA CNT_RLD Register </div><div class="ttdef"><b>Definition:</b> dma_regs.h:96</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _DMA_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _DMA_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; 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MXC_F_DMA_CN_CH0_IEN_POS)) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gacbc8d96f1b88c791f8cb77afc75dfa98">  135</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH1_IEN_POS                       1 </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga917d01cea603dda759124c9c6c9851a2">  136</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH1_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH1_IEN_POS)) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gadbd5dd353f49dbe7fcc9ea95f2871769">  138</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH2_IEN_POS                       2 </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga293c515505c1657e6fda4c8652427128">  139</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH2_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH2_IEN_POS)) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga457b73cb88fbd075a8af3731feb8014d">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH3_IEN_POS                       3 </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga6246140775b36041cb3dd8e94c04580c">  142</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH3_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH3_IEN_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaff45133c027b287b1f64e8c570b6be73">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH4_IEN_POS                       4 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga8c14181a489bb391330caba5da58f135">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH4_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH4_IEN_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gafd2e33adf2d00c0717d288f4cc41e0d2">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH5_IEN_POS                       5 </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gad71c0eeb98ba75df7071189accca3e95">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH5_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH5_IEN_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gabb41f0db418d78d13d58b708781e8151">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH6_IEN_POS                       6 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gadaee65afe92d1a253e4301a3ae4e6c78">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH6_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH6_IEN_POS)) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga4a4678eeb3ce1f591d07e42b501a0cfe">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH7_IEN_POS                       7 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaa04622eeb0d62b3149bc3ffcf24ed171">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH7_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH7_IEN_POS)) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga0f3947db3bbe7818a359d4f2841da5bf">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH8_IEN_POS                       8 </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaa0793a949fcfe137311c38c8e1e452fc">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH8_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH8_IEN_POS)) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gadc3f00825c640bf298d00962c7874381">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH9_IEN_POS                       9 </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga0a2f82a3f811b2d42b6aa8cb2a268990">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH9_IEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH9_IEN_POS)) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga2c03660a4c36656b70d783ba56a99828">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH10_IEN_POS                      10 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga293dd9af543756d19ecc7123bc6e28d4">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH10_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH10_IEN_POS)) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga94dc253feb04cc1194f18a8b52d1539d">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH11_IEN_POS                      11 </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga1efc732ea74cc0673c1a7380ef36414c">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH11_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH11_IEN_POS)) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaea3dd5c62a1213b7ae660e63d2c2b006">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH12_IEN_POS                      12 </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga38776061a14cf64251fe16e4dfad6c49">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH12_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH12_IEN_POS)) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gace0fd55cd838afe0a52a4fefe8b339b6">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH13_IEN_POS                      13 </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga396b5e16d9c58e4e87b0cdad1125c365">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH13_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH13_IEN_POS)) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga19adf9265edc475caa9d3f1a963884fe">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH14_IEN_POS                      14 </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaaff0a2d7b6ceb70a648f3aca3b8abb9e">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH14_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH14_IEN_POS)) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#ga6c5874bee4e18238c9f4f9bde46ee860">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH15_IEN_POS                      15 </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__DMA__CN.html#gaa72823e410849805c86175a6daa45e3c">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CN_CH15_IEN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CN_CH15_IEN_POS)) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga57b288d992d1d92f75c4cccac1c3cbaf">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH0_IPEND_POS                   0 </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga89f23258e3d69615ae8c343bc6fa5ce7">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH0_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH0_IPEND_POS)) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga7c79ef9b04caa86bb4fff9d5ac1ee889">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH1_IPEND_POS                   1 </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga09c03353d3f53840b968e8a725eb9b54">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH1_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH1_IPEND_POS)) </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gae4d2a765f372651876ea0852d6ca5be1">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH2_IPEND_POS                   2 </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga0022fa66237e4e625ece19f8a6b9d795">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH2_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH2_IPEND_POS)) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gac58ff1fe84266baba9d4d6ab18d5690d">  197</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH3_IPEND_POS                   3 </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga6ca2a671d5915cb5dc297f9b810ad704">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH3_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH3_IPEND_POS)) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga92a274d388492d89a8dbac1c92777d38">  200</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH4_IPEND_POS                   4 </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gaf6584c1d63d0761e790ab5649aeaa58f">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH4_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH4_IPEND_POS)) </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gab41f19a54b983e142c64546f07eff94e">  203</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH5_IPEND_POS                   5 </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga6cb03ad810963e17a39260f111821677">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH5_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH5_IPEND_POS)) </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga26cd70a7d36c39fd8450011c171b5be8">  206</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH6_IPEND_POS                   6 </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga5d7a2e3e28821d3bcb40b4678a4caece">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH6_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH6_IPEND_POS)) </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga438e25eccbc6bc58a704672376074297">  209</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH7_IPEND_POS                   7 </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gaa8fcfea2d98e3cc5989e7ba08efc66af">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH7_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH7_IPEND_POS)) </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga15b217f6bf29a8f31c1553bf42b306cd">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH8_IPEND_POS                   8 </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga189ccfd95375ff10b36a9045f5e6aac5">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH8_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH8_IPEND_POS)) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga68fcb6d800e48feb464e8e7c46c84b5b">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH9_IPEND_POS                   9 </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga4f372d4dea6652da4341e2b4673da9a2">  216</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH9_IPEND                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH9_IPEND_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gab59de7f3592c2ac8b3bcf4068a4ab891">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH10_IPEND_POS                  10 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga7c907db9dc7111989dd01d8f2d6ba3b2">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH10_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH10_IPEND_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga31d236eb1226390cb3517e12189a6a7a">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH11_IPEND_POS                  11 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga61b10f79c2c80d1af6d701b413224850">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH11_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH11_IPEND_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gac2d8a83e68b16fba9cd89ca589360a8e">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH12_IPEND_POS                  12 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga3c41a714c951e2c3301b1f19ea7ff57c">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH12_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH12_IPEND_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga396ddec1bfa54bbdbddabeae7b3c1010">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH13_IPEND_POS                  13 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gafc4e738aad3bef7e85d2d416b5469046">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH13_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH13_IPEND_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga0960a66936967afaab6ba663f7f31c6c">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH14_IPEND_POS                  14 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga03187088c5b74dd5e43039bc4eb021a0">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH14_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH14_IPEND_POS)) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#gabadc997a9d6c1a530a834933c3f705c2">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH15_IPEND_POS                  15 </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__DMA__INTR.html#ga63868190062f637557c23e2de0218cae">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_INTR_CH15_IPEND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_INTR_CH15_IPEND_POS)) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gad8788d2be626779c965bd8edae4c2057">  244</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHEN_POS                         0 </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabb9215341b86b5bd08d00c83a5f17cbf">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHEN                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_CHEN_POS)) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4aef700763abb52f9b5ce089c6e118e4">  247</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_RLDEN_POS                        1 </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadf5c7b670153984d28e858b6375c6135">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_RLDEN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_RLDEN_POS)) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga8d3eae53922e0c21fb29e4ef8ee2c90c">  250</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PRI_POS                          2 </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab1c2846d4535cd0319ef23599cb16f6f">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PRI                              ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_PRI_POS)) </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaec995470f08943883e5f60f83163ca8d">  252</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_HIGH                         ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2c6b67059a94cb9e63438faa10e18908">  253</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_HIGH                         (MXC_V_DMA_CFG_PRI_HIGH &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacd9a18766517306801ff34d4ebf819f7">  254</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_MEDHIGH                      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2bd08149d46a3d823b60468fd2250293">  255</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_MEDHIGH                      (MXC_V_DMA_CFG_PRI_MEDHIGH &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga55cbadab3b8fd40edf267c1b39fd0bd1">  256</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_MEDLOW                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaacadb81a6a1ef7fb7aabcc92f6df1a2f">  257</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_MEDLOW                       (MXC_V_DMA_CFG_PRI_MEDLOW &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1b5f0a12fb6b444edfae225dfb6e7bdf">  258</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PRI_LOW                          ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga52b9e89b113d30ee7fee1aceecd4619f">  259</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PRI_LOW                          (MXC_V_DMA_CFG_PRI_LOW &lt;&lt; MXC_F_DMA_CFG_PRI_POS) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga03b16149181424405cc14cc5aacc6a6b">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQSEL_POS                       4 </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaddaf5defb97d4587fafb78575d40e037">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQSEL                           ((uint32_t)(0x3FUL &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS)) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga008c60c169b71e7075e95e7f1aa422c3">  263</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_MEMTOMEM                  ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaab33bbc5b4fcb13a55cdb8e716b2df95">  264</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_MEMTOMEM                  (MXC_V_DMA_CFG_REQSEL_MEMTOMEM &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga090233ebbf1ab67f94bf3427b81087e8">  265</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI1RX                    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2ca72c3d3e653d28c8862e1e1e73ae16">  266</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI1RX                    (MXC_V_DMA_CFG_REQSEL_SPI1RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga48dc9d5a7aba7592f779ed9667201a28">  267</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI2RX                    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacfbe66e9428a311fde3b6879c60da6b0">  268</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI2RX                    (MXC_V_DMA_CFG_REQSEL_SPI2RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4449ecef8d439c68653316c9dbb92456">  269</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI3RX                    ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf131253bf03e1bb7e63198431f0ff639">  270</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI3RX                    (MXC_V_DMA_CFG_REQSEL_SPI3RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3a3b5f284123dcfbd2e6752db69b93bd">  271</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART0RX                   ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga83b6321725f03daa527979b86d2d7fea">  272</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART0RX                   (MXC_V_DMA_CFG_REQSEL_UART0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaac9f95327aec4a7e10609f4e06e3e408">  273</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART1RX                   ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga9dc214dee46338800b770bd8d436c09e">  274</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART1RX                   (MXC_V_DMA_CFG_REQSEL_UART1RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf67b9c1b93435eeb839fbb713bbc28ef">  275</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C0RX                    ((uint32_t)0x7UL) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac9cb6e4074715c6ae1900ec0dc133464">  276</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C0RX                    (MXC_V_DMA_CFG_REQSEL_I2C0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab33e5862e5a84f60181576793cee3543">  277</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C1RX                    ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa871e9c25f06854c77f4a13ef72c4868">  278</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C1RX                    (MXC_V_DMA_CFG_REQSEL_I2C1RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaada7a5a00bab0a0d540b4690d5789ea3">  279</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_ADC                       ((uint32_t)0x9UL) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gace9660a09dc239db5fbcc19a2eff1a5d">  280</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_ADC                       (MXC_V_DMA_CFG_REQSEL_ADC &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga32fa58a44707ec0dc04c2475ede271b3">  281</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART2RX                   ((uint32_t)0xEUL) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga558829f658022cdc489bd0906227752a">  282</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART2RX                   (MXC_V_DMA_CFG_REQSEL_UART2RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaec6de3f265bcfedfbd8c650c4c43ecd0">  283</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI0RX                    ((uint32_t)0xFUL) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga94a9fbd8bb720eb2b6e289a80eca1a9a">  284</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI0RX                    (MXC_V_DMA_CFG_REQSEL_SPI0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4890f1dff25f80855704fe86b8d173ac">  285</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX                ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga625831734be28d96e7bcc8090acbe3b8">  286</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX                (MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga5e7f98d000749aaf98ff3e2ed272978c">  287</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP1                  ((uint32_t)0x11UL) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc5b39f84758ac7b43c7e8c127eeab46">  288</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP1                  (MXC_V_DMA_CFG_REQSEL_USBRXEP1 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga50c86e65c8303114b72558ec25623448">  289</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP2                  ((uint32_t)0x12UL) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa94c4c24fc99b4d5bee38f5726950333">  290</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP2                  (MXC_V_DMA_CFG_REQSEL_USBRXEP2 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga7cda6e10d7f60961f46dc0d387e293f4">  291</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP3                  ((uint32_t)0x13UL) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac80c461e8265c7576b3bf8ba7eeffee4">  292</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP3                  (MXC_V_DMA_CFG_REQSEL_USBRXEP3 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3a74c1bf70decd47173fc13bb7317a47">  293</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP4                  ((uint32_t)0x14UL) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga655204beb229c26ccc3809e1edaa7361">  294</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP4                  (MXC_V_DMA_CFG_REQSEL_USBRXEP4 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa5e45fafd8e34b7bedf68276e94dc022">  295</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP5                  ((uint32_t)0x15UL) </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga419ba3c18269073c520cd8ff317c7fc2">  296</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP5                  (MXC_V_DMA_CFG_REQSEL_USBRXEP5 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa40064aedd82461156cafea9f28b5637">  297</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP6                  ((uint32_t)0x16UL) </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6330761be59ddfd7836bfd815ac81573">  298</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP6                  (MXC_V_DMA_CFG_REQSEL_USBRXEP6 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga85a962ed68cc2038972e562ad704fe52">  299</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP7                  ((uint32_t)0x17UL) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga856ddf760786a7a1d85340989b85d90b">  300</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP7                  (MXC_V_DMA_CFG_REQSEL_USBRXEP7 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc358244c44c42e8a390eca2e39420a0">  301</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP8                  ((uint32_t)0x18UL) </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1487a02e09dbbb6df355a74776596f72">  302</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP8                  (MXC_V_DMA_CFG_REQSEL_USBRXEP8 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga76611849a0724ef4c0a61c53c10a58b9">  303</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP9                  ((uint32_t)0x19UL) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac404cca1dac17794e20bfd25655b2443">  304</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP9                  (MXC_V_DMA_CFG_REQSEL_USBRXEP9 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga80e5a07e525c8358ec6800a604b4f3cd">  305</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP10                 ((uint32_t)0x1AUL) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga17fca0704d673883615813c0e436a486">  306</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP10                 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga63855563f74194b2702f36722169c667">  307</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBRXEP11                 ((uint32_t)0x1BUL) </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga73e07ad27c6e0f6859b3765c81a9a59f">  308</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBRXEP11                 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2063a26c093bfe3699134a9a3defa403">  309</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI1TX                    ((uint32_t)0x21UL) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga59a0cdb0d780752093a04132d3aa80d3">  310</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI1TX                    (MXC_V_DMA_CFG_REQSEL_SPI1TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabe3ae057abab200af7f84e92cc0d55c4">  311</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI2TX                    ((uint32_t)0x22UL) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gad3a1d6b9f0161f5cd633fd04a3817226">  312</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI2TX                    (MXC_V_DMA_CFG_REQSEL_SPI2TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga69cb063b48ef0fd41b6bd7db7aae9def">  313</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI3TX                    ((uint32_t)0x23UL) </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b">  314</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI3TX                    (MXC_V_DMA_CFG_REQSEL_SPI3TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6f7d5538511de9c21714d8a8f4b84a4b">  315</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART0TX                   ((uint32_t)0x24UL) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6b454bf5654872a6b0954865dfdedc4d">  316</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART0TX                   (MXC_V_DMA_CFG_REQSEL_UART0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2dbc01d93a93b32b8f3befbad23b3917">  317</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART1TX                   ((uint32_t)0x25UL) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga24cae5e873707512474e80daa1a83d0f">  318</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART1TX                   (MXC_V_DMA_CFG_REQSEL_UART1TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc396c3a0fcec0fdca843d1babac1f94">  319</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C0TX                    ((uint32_t)0x27UL) </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga19ccddaaec7f5d15362c3331c1901411">  320</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C0TX                    (MXC_V_DMA_CFG_REQSEL_I2C0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadd56f4442caac4bd7bb09552519c882b">  321</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_I2C1TX                    ((uint32_t)0x28UL) </span></div><div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadf1da5f6f88cc60476e345ad0f4cb984">  322</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_I2C1TX                    (MXC_V_DMA_CFG_REQSEL_I2C1TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf66d145949474eba9cf18275aa12fa40">  323</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_UART2TX                   ((uint32_t)0x2EUL) </span></div><div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gafbd3c8451764f125184213be8adedc95">  324</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_UART2TX                   (MXC_V_DMA_CFG_REQSEL_UART2TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab57be50928424427440ae1550e458610">  325</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI0TX                    ((uint32_t)0x2FUL) </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000">  326</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI0TX                    (MXC_V_DMA_CFG_REQSEL_SPI0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga387dae08cef4a75de7a2fcd15642d54d">  327</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX                ((uint32_t)0x30UL) </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac4b209297fe9fee806e1ea1286cf5001">  328</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX                (MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga54e9b247505edf08571690565b72b647">  329</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP1                  ((uint32_t)0x31UL) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gad954469358987e3d3dc0c78356cee783">  330</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP1                  (MXC_V_DMA_CFG_REQSEL_USBTXEP1 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaae3c21f2a013c9c427c1fa637b743a9f">  331</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP2                  ((uint32_t)0x32UL) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga22cd21918e4ce20fc8690c334c63b0c8">  332</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP2                  (MXC_V_DMA_CFG_REQSEL_USBTXEP2 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga66523c77b67a8b01e3c00aa0622b2850">  333</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP3                  ((uint32_t)0x33UL) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3255788a83195bb2d0f1a4e37f47cdb0">  334</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP3                  (MXC_V_DMA_CFG_REQSEL_USBTXEP3 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacdf5ab8392e256af13bc4049194b4152">  335</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP4                  ((uint32_t)0x34UL) </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga515ceb7d26504984b1ca229cec786b22">  336</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP4                  (MXC_V_DMA_CFG_REQSEL_USBTXEP4 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf556c7996dd6f76c06ebdcb429ebd04d">  337</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP5                  ((uint32_t)0x35UL) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa1c6cad4dfb0766726238cf29cda1509">  338</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP5                  (MXC_V_DMA_CFG_REQSEL_USBTXEP5 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga59c9157cdefab9916214f981d7058f09">  339</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP6                  ((uint32_t)0x36UL) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga854bd263d54bee8622305ea0cd65ed44">  340</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP6                  (MXC_V_DMA_CFG_REQSEL_USBTXEP6 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga7d8a74e28a64c4e6377ea6ecc7423790">  341</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP7                  ((uint32_t)0x37UL) </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga51288c54b6422d7775d84780efbe757a">  342</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP7                  (MXC_V_DMA_CFG_REQSEL_USBTXEP7 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf9fe56970c382913244f4d39eb8c012f">  343</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP8                  ((uint32_t)0x38UL) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6c3f75da4dceae47af0ff9bea6dd9a10">  344</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP8                  (MXC_V_DMA_CFG_REQSEL_USBTXEP8 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga0721eb0d6e0c54ae9a31d59f07f04b32">  345</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP9                  ((uint32_t)0x39UL) </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga691bc44c837e4c3f0bee6d6d1fc9b13d">  346</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP9                  (MXC_V_DMA_CFG_REQSEL_USBTXEP9 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00347"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac4633e78570f85d2afbe5f30ae0f0c15">  347</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP10                 ((uint32_t)0x3AUL) </span></div><div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaf5feeb1d958b25d1aca32e333f8ecb2b">  348</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP10                 (MXC_V_DMA_CFG_REQSEL_USBTXEP10 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga526b7edb52a69d3d920f2a018fc01a1f">  349</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_REQSEL_USBTXEP11                 ((uint32_t)0x3BUL) </span></div><div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga30d56f29d9829264795b6086ed591973">  350</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_REQSEL_USBTXEP11                 (MXC_V_DMA_CFG_REQSEL_USBTXEP11 &lt;&lt; MXC_F_DMA_CFG_REQSEL_POS) </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga89fc4a96f38da5ecd1023ec972eb3baf">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQWAIT_POS                      10 </span></div><div class="line"><a name="l00353"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga91987cb8e9ba16fb16e1736e0d00463b">  353</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_REQWAIT                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_REQWAIT_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga68560874214b251d0705821d105d40e8">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_TOSEL_POS                        11 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga82b8a26be3bdd6a424e72693df35e07a">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_TOSEL                            ((uint32_t)(0x7UL &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS)) </span></div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga15b35265b7f5af2945e502d69f840c93">  357</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO4                        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa65a8e6e9a47f8baaf48bfbe30e857e5">  358</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO4                        (MXC_V_DMA_CFG_TOSEL_TO4 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga32ca288d8df91355807a352234f8fe6b">  359</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO8                        ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab37cd6e6aab4352f55c6bf2b7c8ebf8c">  360</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO8                        (MXC_V_DMA_CFG_TOSEL_TO8 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3bfc3ba550e5ad6096e518aa2eb49b17">  361</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO16                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3adb094f786f489adb93e9d182163a89">  362</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO16                       (MXC_V_DMA_CFG_TOSEL_TO16 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab278c7ae0475ca7ee04891fdde01bc89">  363</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO32                       ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga945246e090f5da1fb54792f3378b8084">  364</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO32                       (MXC_V_DMA_CFG_TOSEL_TO32 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac4ee36e08c1cf6669c0c86babaaf3236">  365</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO64                       ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gacb9ce2dab8569c1614027d388634ddbe">  366</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO64                       (MXC_V_DMA_CFG_TOSEL_TO64 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaaa64e15a23c5f9428a335cdaaa3276fd">  367</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO128                      ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1b0df84d9dd17d90b7aae0e5d9fc17cb">  368</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO128                      (MXC_V_DMA_CFG_TOSEL_TO128 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga8b0b811ed8e654f9b5c01649fd5f7222">  369</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO256                      ((uint32_t)0x6UL) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa8881ab56ad4bb8c7fa593a75aef23a8">  370</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO256                      (MXC_V_DMA_CFG_TOSEL_TO256 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabc276290f72d8f30f56798ed096b5eb8">  371</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_TOSEL_TO512                      ((uint32_t)0x7UL) </span></div><div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga7a52b4d7b63f05aa7f40d473e402909a">  372</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_TOSEL_TO512                      (MXC_V_DMA_CFG_TOSEL_TO512 &lt;&lt; MXC_F_DMA_CFG_TOSEL_POS) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga36f6611f1b51448654cbfc34fa09625e">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PSSEL_POS                        14 </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac6a613169c808ae7e321df9766f73774">  375</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_PSSEL                            ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga9e2e528c615634cd3cbe4a42aaab8d99">  376</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIS                        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae8500e02648065503cb8d0724f64439f">  377</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIS                        (MXC_V_DMA_CFG_PSSEL_DIS &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga73bfd76f65f1253eb5932e546e12917d">  378</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIV256                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab33e7b4da545b54e51bdd8e37bf31a1f">  379</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIV256                     (MXC_V_DMA_CFG_PSSEL_DIV256 &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabcee969c3d08fd3fb01ad2aff3ea3ac0">  380</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIV64K                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga81c828d319077f1a3e4740ea14bd29c5">  381</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIV64K                     (MXC_V_DMA_CFG_PSSEL_DIV64K &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2a8e4ce350752be63a899c7fd950e759">  382</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_PSSEL_DIV16M                     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2c51b0b043738b1f2b1c1df0feceaf93">  383</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_PSSEL_DIV16M                     (MXC_V_DMA_CFG_PSSEL_DIV16M &lt;&lt; MXC_F_DMA_CFG_PSSEL_POS) </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae72cce35caa6cf5c5b64f42ce2d33d9c">  385</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCWD_POS                        16 </span></div><div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga8542857f944797e85d8b808e1d77ed80">  386</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCWD                            ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS)) </span></div><div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga3495e30108a57dcf2d6b7c3e60f516f1">  387</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_SRCWD_BYTE                       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gab89ad10788611110f80df88e2555b464">  388</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_SRCWD_BYTE                       (MXC_V_DMA_CFG_SRCWD_BYTE &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS) </span></div><div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gae3dac96e9661c9dd79398ecd317a326b">  389</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_SRCWD_HALFWORD                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac8ec688df9a7d8cda25bea18bc7d6e8c">  390</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_SRCWD_HALFWORD                   (MXC_V_DMA_CFG_SRCWD_HALFWORD &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS) </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gabbaaea47d5c7476b05b82fee78270f8e">  391</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_SRCWD_WORD                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaabc2ee25b7dc18689372e5d339e2613b">  392</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_SRCWD_WORD                       (MXC_V_DMA_CFG_SRCWD_WORD &lt;&lt; MXC_F_DMA_CFG_SRCWD_POS) </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga2ca77d2c32cf4cbeb2c7af131e2c1b96">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCINC_POS                       18 </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga833bec7c08604767bd213c2806773d8e">  395</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_SRCINC                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_SRCINC_POS)) </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga27f8d1250a4f6a36b3d64b7827434007">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTWD_POS                        20 </span></div><div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga6963e9e6aa3b9546fdb6539bb26591ff">  398</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTWD                            ((uint32_t)(0x3UL &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga317bcdd6d71cc64923332db1f1ea254f">  399</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_DSTWD_BYTE                       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gadfc85f260796ac3c9673ede9885f0328">  400</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_DSTWD_BYTE                       (MXC_V_DMA_CFG_DSTWD_BYTE &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS) </span></div><div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga1a5027e22465fe7a5fe4ad2d36c99a85">  401</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_DSTWD_HALFWORD                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga9127fddb84cfa1694e143c092a147cdc">  402</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_DSTWD_HALFWORD                   (MXC_V_DMA_CFG_DSTWD_HALFWORD &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS) </span></div><div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gac25fe229dea35959b43d47426aa2bfe4">  403</a></span>&#160;<span class="preprocessor"> #define MXC_V_DMA_CFG_DSTWD_WORD                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00404"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga0131dd27829b3bf79c8a560b992482ad">  404</a></span>&#160;<span class="preprocessor"> #define MXC_S_DMA_CFG_DSTWD_WORD                       (MXC_V_DMA_CFG_DSTWD_WORD &lt;&lt; MXC_F_DMA_CFG_DSTWD_POS) </span></div><div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa3d66754a80c75b1cec1191d7fbee094">  406</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTINC_POS                       22 </span></div><div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga4b364def0a6d9037ea58bfb80a42bfa1">  407</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_DSTINC                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_DSTINC_POS)) </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaff33a3a5a97caa029365b3098786a005">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_BRST_POS                         24 </span></div><div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga5a04e3893d8635ff9d231782748f9748">  410</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_BRST                             ((uint32_t)(0x1FUL &lt;&lt; MXC_F_DMA_CFG_BRST_POS)) </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga692f74730f8594dca7def7100c4e76dc">  412</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHDIEN_POS                       30 </span></div><div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#ga505cf35e7cfb27aef90c9deda19e9560">  413</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CHDIEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_CHDIEN_POS)) </span></div><div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaa1d7ca7d80680d4b559a97fd002da5db">  415</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CTZIEN_POS                       31 </span></div><div class="line"><a name="l00416"></a><span class="lineno"><a class="line" href="group__DMA__CFG.html#gaae295cd36d93fa6328055fb38d967b73">  416</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CFG_CTZIEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CFG_CTZIEN_POS)) </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga5645c288f283ce11642dbc64263005d1">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CH_ST_POS                         0 </span></div><div class="line"><a name="l00427"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gaf895eb5b6925ed84f348e9d776b70406">  427</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CH_ST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_CH_ST_POS)) </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gabec7a3b5aa15482766edc29249552e5a">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_IPEND_POS                         1 </span></div><div class="line"><a name="l00430"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gabd2a9320393484740eabc1bac1b2317a">  430</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_IPEND                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_IPEND_POS)) </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gad0a06dfd7ab044a16177723541d54dd2">  432</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CTZ_ST_POS                        2 </span></div><div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga30ddebf6ba447de2d435c11d73adf634">  433</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_CTZ_ST                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_CTZ_ST_POS)) </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gabf05b8a722ecde54629ad1b737840ee9">  435</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_RLD_ST_POS                        3 </span></div><div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gaf2c0d526a9335c0ff83853747fba16ef">  436</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_RLD_ST                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_RLD_ST_POS)) </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga83b9ed97423571f29c194ff90ef99e2a">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_BUS_ERR_POS                       4 </span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#gafdd0fce12884fac18f3c4656eaa7249d">  439</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_BUS_ERR                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_BUS_ERR_POS)) </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga992544df6f0a968273341705d4ac3ace">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_TO_ST_POS                         6 </span></div><div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group__DMA__ST.html#ga340e62cc8777c228baeb0c7d850aa55a">  442</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_ST_TO_ST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_ST_TO_ST_POS)) </span></div><div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="group__DMA__SRC.html#ga08418c424a6a371af6a83c003df2ec63">  456</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_ADDR_POS                         0 </span></div><div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group__DMA__SRC.html#ga06cd0f3c2335474d0dd7fe80ca87bf18">  457</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_DMA_SRC_ADDR_POS)) </span></div><div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="group__DMA__DST.html#ga41867234ec8188ae2c4cc3ce4e5cc765">  471</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_ADDR_POS                         0 </span></div><div class="line"><a name="l00472"></a><span class="lineno"><a class="line" href="group__DMA__DST.html#ga724d286463d1b6249509f89cf72fba08">  472</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_DMA_DST_ADDR_POS)) </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__DMA__CNT.html#ga3eee46c3f015d14631d1f054dfab074c">  485</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_CNT_POS                          0 </span></div><div class="line"><a name="l00486"></a><span class="lineno"><a class="line" href="group__DMA__CNT.html#ga164f175a19499778c7f8400a1da02332">  486</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_DMA_CNT_CNT_POS)) </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__DMA__SRC__RLD.html#ga940f51543f2b861c8280182d98a58078">  497</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_RLD_SRC_RLD_POS                  0 </span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group__DMA__SRC__RLD.html#ga05c23fee088a6e5e1a4e4e68c6463f7a">  498</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_SRC_RLD_SRC_RLD                      ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_DMA_SRC_RLD_SRC_RLD_POS)) </span></div><div class="line"><a name="l00509"></a><span class="lineno"><a class="line" href="group__DMA__DST__RLD.html#ga100dd74eec7b0c2d5a40238338ea0ee3">  509</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_RLD_DST_RLD_POS                  0 </span></div><div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group__DMA__DST__RLD.html#gaedc9fd3c9d4287f7015d976cb26d6a01">  510</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_DST_RLD_DST_RLD                      ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_DMA_DST_RLD_DST_RLD_POS)) </span></div><div class="line"><a name="l00520"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#ga52d6009b54bcf3ddee695f5d645e58ea">  520</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_CNT_RLD_POS                  0 </span></div><div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#gab72baed67e0f50d12c18162894963e1b">  521</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_CNT_RLD                      ((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_DMA_CNT_RLD_CNT_RLD_POS)) </span></div><div class="line"><a name="l00523"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#ga06f8c3679bafd7e0d7d7c8ba4d7de153">  523</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_RLDEN_POS                    31 </span></div><div class="line"><a name="l00524"></a><span class="lineno"><a class="line" href="group__DMA__CNT__RLD.html#ga2b2627df47054c575889174515d15ed8">  524</a></span>&#160;<span class="preprocessor"> #define MXC_F_DMA_CNT_RLD_RLDEN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_DMA_CNT_RLD_RLDEN_POS)) </span></div><div class="line"><a name="l00528"></a><span class="lineno">  528</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00529"></a><span class="lineno">  529</span>&#160;}</div><div class="line"><a name="l00530"></a><span class="lineno">  530</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00531"></a><span class="lineno">  531</span>&#160;</div><div class="line"><a name="l00532"></a><span class="lineno">  532</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _DMA_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__dma__ch__regs__t_html_adf30fd26a788d6185c69c4e1ad2eac3b"><div class="ttname"><a href="structmxc__dma__ch__regs__t.html#adf30fd26a788d6185c69c4e1ad2eac3b">mxc_dma_ch_regs_t::cnt_rld</a></div><div class="ttdeci">__IO uint32_t cnt_rld</div><div class="ttdoc">0x11C: DMA CNT_RLD Register </div><div class="ttdef"><b>Definition:</b> dma_regs.h:96</div></div>
 <div class="ttc" id="structmxc__dma__ch__regs__t_html_a1a7e35c8c34af54704b10fc27dc0266d"><div class="ttname"><a href="structmxc__dma__ch__regs__t.html#a1a7e35c8c34af54704b10fc27dc0266d">mxc_dma_ch_regs_t::dst</a></div><div class="ttdeci">__IO uint32_t dst</div><div class="ttdoc">0x10C: DMA DST Register </div><div class="ttdef"><b>Definition:</b> dma_regs.h:92</div></div>
 <div class="ttc" id="structmxc__dma__ch__regs__t_html"><div class="ttname"><a href="structmxc__dma__ch__regs__t.html">mxc_dma_ch_regs_t</a></div><div class="ttdoc">Structure type to access the DMA Registers. </div><div class="ttdef"><b>Definition:</b> dma_regs.h:88</div></div>
 <div class="ttc" id="structmxc__dma__regs__t_html_a21e1cfb0af372e336277034eccefcb1a"><div class="ttname"><a href="structmxc__dma__regs__t.html#a21e1cfb0af372e336277034eccefcb1a">mxc_dma_regs_t::cn</a></div><div class="ttdeci">__IO uint32_t cn</div><div class="ttdoc">0x000: DMA CN Register </div><div class="ttdef"><b>Definition:</b> dma_regs.h:100</div></div>
diff --git a/lib/sdk/Documentation/html/flc_8h_source.html b/lib/sdk/Documentation/html/flc_8h_source.html
index 6a22f10dbcb90c9324c2b1d4513186a02b29623b..f979ed5cb4581a514a439647571eb450000b34a5 100644
--- a/lib/sdk/Documentation/html/flc_8h_source.html
+++ b/lib/sdk/Documentation/html/flc_8h_source.html
@@ -71,13 +71,14 @@ $(document).ready(function(){initNavTree('flc_8h_source.html','');});
 <div class="title">flc.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Date: 2018-11-08 09:36:51 -0600 (Thu, 08 Nov 2018) $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> * $Revision: 39038 $</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _FLC_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _FLC_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;flc_regs.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;mxc_sys.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">/***** Definitions *****/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;</div><div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="group__flc.html#gad726ec4ae8a020fffe03fafaf0ff08a9">   63</a></span>&#160;<span class="preprocessor">#define MXC_FLASH_PAGE_MASK         ~(MXC_FLASH_PAGE_SIZE - 1)</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="group__flc.html#gafd2d64053cfb7718540dabced58857f4">   66</a></span>&#160;<span class="preprocessor">#define MXC_FLASH_PAGE_ADDR(page)   (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="comment">/***** Function Prototypes *****/</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;</div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gad4e017bec766e2425ecb89ab2d8d55d7">FLC_Init</a>(<span class="keyword">const</span> sys_cfg_t *sys_cfg);</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;  </div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga0cbf3341a611eb6d6cb216337a1666f0">FLC_Busy</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;  </div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga6ffdba912987544c1b9f20bfb502cafa">FLC_MassErase</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gae17acd43a6a605787a9e4aa6bfb2f7f1">FLC_PageErase</a>(uint32_t address);</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga6dd7cadd48dd6794326c9513dbb28b3f">FLC_MultiPageErase</a>(uint32_t start, uint32_t end);</div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;</div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga611826546917e9934f0156262043c95a">FLC_Erase</a>(uint32_t start, uint32_t end, uint32_t *buffer, <span class="keywordtype">unsigned</span> length);</div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;</div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gab2c7ff8827d00225e7529ad27317d4df">FLC_Write32</a>(uint32_t address, uint32_t data);</div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;</div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga27ef33b7f611fee4a17d402d4de367f0">FLC_Write128</a>(uint32_t address, uint32_t *data);</div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;</div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gaaa2f14afa9ffc0ef11e9e5b61c815b6e">FLC_Write</a>(uint32_t address, uint32_t length, uint32_t *buffer);</div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;</div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga60c6b368bd0b32348d37c239dec870a2">FLC_EnableInt</a>(uint32_t mask);</div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;</div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga78f8d1567ce795fcc348d15433a62e13">FLC_DisableInt</a>(uint32_t mask);</div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;</div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gac20cb51e1abada52834314564046bdaa">FLC_GetFlags</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00175"></a><span class="lineno">  175</span>&#160;</div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gad66c50abe1036551df8fe389b48634d3">FLC_ClearFlags</a>(uint32_t mask);</div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga7d13b8204f1163e40d6f3369091ec562">FLC_UnlockInfoBlock</a>(uint32_t address);</div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;</div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga0cb38b992f55df3a8f2b7fe191237baa">FLC_LockInfoBlock</a>(uint32_t address);</div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;}</div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _FLC_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__flc_html_gae17acd43a6a605787a9e4aa6bfb2f7f1"><div class="ttname"><a href="group__flc.html#gae17acd43a6a605787a9e4aa6bfb2f7f1">FLC_PageErase</a></div><div class="ttdeci">int FLC_PageErase(uint32_t address)</div><div class="ttdoc">Erases the page of flash at the specified address. </div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Date: 2019-12-18 09:31:02 -0600 (Wed, 18 Dec 2019) $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> * $Revision: 50100 $</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _FLC_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _FLC_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;flc_regs.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;mxc_sys.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">/***** Definitions *****/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;</div><div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="group__flc.html#gad726ec4ae8a020fffe03fafaf0ff08a9">   63</a></span>&#160;<span class="preprocessor">#define MXC_FLASH_PAGE_MASK         ~(MXC_FLASH_PAGE_SIZE - 1)</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="group__flc.html#gafd2d64053cfb7718540dabced58857f4">   66</a></span>&#160;<span class="preprocessor">#define MXC_FLASH_PAGE_ADDR(page)   (MXC_FLASH_MEM_BASE + ((unsigned long)page * MXC_FLASH_PAGE_SIZE))</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="comment">/***** Function Prototypes *****/</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;</div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gad4e017bec766e2425ecb89ab2d8d55d7">FLC_Init</a>(<span class="keyword">const</span> sys_cfg_t *sys_cfg);</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;  </div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga0cbf3341a611eb6d6cb216337a1666f0">FLC_Busy</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;  </div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga6ffdba912987544c1b9f20bfb502cafa">FLC_MassErase</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga91e5033e4b2b68ff1d0a4d352e1ac837">FLC_MassEraseInst</a>(<span class="keywordtype">int</span> inst);</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gae17acd43a6a605787a9e4aa6bfb2f7f1">FLC_PageErase</a>(uint32_t address);</div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;</div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga6dd7cadd48dd6794326c9513dbb28b3f">FLC_MultiPageErase</a>(uint32_t start, uint32_t end);</div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga611826546917e9934f0156262043c95a">FLC_Erase</a>(uint32_t start, uint32_t end, uint32_t *buffer, <span class="keywordtype">unsigned</span> length);</div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;</div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gab2c7ff8827d00225e7529ad27317d4df">FLC_Write32</a>(uint32_t address, uint32_t data);</div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;</div><div class="line"><a name="l00151"></a><span class="lineno">  151</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga27ef33b7f611fee4a17d402d4de367f0">FLC_Write128</a>(uint32_t address, uint32_t *data);</div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;</div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gaaa2f14afa9ffc0ef11e9e5b61c815b6e">FLC_Write</a>(uint32_t address, uint32_t length, uint32_t *buffer);</div><div class="line"><a name="l00163"></a><span class="lineno">  163</span>&#160;</div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga60c6b368bd0b32348d37c239dec870a2">FLC_EnableInt</a>(uint32_t mask);</div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;</div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga78f8d1567ce795fcc348d15433a62e13">FLC_DisableInt</a>(uint32_t mask);</div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;</div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gac20cb51e1abada52834314564046bdaa">FLC_GetFlags</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;</div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#gad66c50abe1036551df8fe389b48634d3">FLC_ClearFlags</a>(uint32_t mask);</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;</div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga9f27160d352d96821a7336fa7277f0d9">FLC_InfoBlockUnlocked</a>(uint32_t address);</div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;</div><div class="line"><a name="l00208"></a><span class="lineno">  208</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga7d13b8204f1163e40d6f3369091ec562">FLC_UnlockInfoBlock</a>(uint32_t address);</div><div class="line"><a name="l00209"></a><span class="lineno">  209</span>&#160;</div><div class="line"><a name="l00216"></a><span class="lineno">  216</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__flc.html#ga0cb38b992f55df3a8f2b7fe191237baa">FLC_LockInfoBlock</a>(uint32_t address);</div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00220"></a><span class="lineno">  220</span>&#160;}</div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;</div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _FLC_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__flc_html_gae17acd43a6a605787a9e4aa6bfb2f7f1"><div class="ttname"><a href="group__flc.html#gae17acd43a6a605787a9e4aa6bfb2f7f1">FLC_PageErase</a></div><div class="ttdeci">int FLC_PageErase(uint32_t address)</div><div class="ttdoc">Erases the page of flash at the specified address. </div></div>
 <div class="ttc" id="group__flc_html_ga6ffdba912987544c1b9f20bfb502cafa"><div class="ttname"><a href="group__flc.html#ga6ffdba912987544c1b9f20bfb502cafa">FLC_MassErase</a></div><div class="ttdeci">int FLC_MassErase(void)</div><div class="ttdoc">Erases the entire flash array. </div></div>
 <div class="ttc" id="group__flc_html_gaaa2f14afa9ffc0ef11e9e5b61c815b6e"><div class="ttname"><a href="group__flc.html#gaaa2f14afa9ffc0ef11e9e5b61c815b6e">FLC_Write</a></div><div class="ttdeci">int FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer)</div><div class="ttdoc">Writes data to flash. </div></div>
 <div class="ttc" id="group__flc_html_gac20cb51e1abada52834314564046bdaa"><div class="ttname"><a href="group__flc.html#gac20cb51e1abada52834314564046bdaa">FLC_GetFlags</a></div><div class="ttdeci">int FLC_GetFlags(void)</div><div class="ttdoc">Retrieve flash interrupt flags. </div></div>
 <div class="ttc" id="group__flc_html_ga78f8d1567ce795fcc348d15433a62e13"><div class="ttname"><a href="group__flc.html#ga78f8d1567ce795fcc348d15433a62e13">FLC_DisableInt</a></div><div class="ttdeci">int FLC_DisableInt(uint32_t mask)</div><div class="ttdoc">Disable flash interrupts. </div></div>
 <div class="ttc" id="group__flc_html_gab2c7ff8827d00225e7529ad27317d4df"><div class="ttname"><a href="group__flc.html#gab2c7ff8827d00225e7529ad27317d4df">FLC_Write32</a></div><div class="ttdeci">int FLC_Write32(uint32_t address, uint32_t data)</div><div class="ttdoc">Writes the specified 32-bit value to flash. </div></div>
 <div class="ttc" id="group__flc_html_gad4e017bec766e2425ecb89ab2d8d55d7"><div class="ttname"><a href="group__flc.html#gad4e017bec766e2425ecb89ab2d8d55d7">FLC_Init</a></div><div class="ttdeci">int FLC_Init(const sys_cfg_t *sys_cfg)</div><div class="ttdoc">Initializes the Flash Controller for erase/write operations. </div></div>
+<div class="ttc" id="group__flc_html_ga91e5033e4b2b68ff1d0a4d352e1ac837"><div class="ttname"><a href="group__flc.html#ga91e5033e4b2b68ff1d0a4d352e1ac837">FLC_MassEraseInst</a></div><div class="ttdeci">int FLC_MassEraseInst(int inst)</div><div class="ttdoc">Erases the selected flash array. </div></div>
 <div class="ttc" id="group__flc_html_ga27ef33b7f611fee4a17d402d4de367f0"><div class="ttname"><a href="group__flc.html#ga27ef33b7f611fee4a17d402d4de367f0">FLC_Write128</a></div><div class="ttdeci">int FLC_Write128(uint32_t address, uint32_t *data)</div><div class="ttdoc">Writes the specified 128-bits of data to flash. </div></div>
 <div class="ttc" id="group__flc_html_ga60c6b368bd0b32348d37c239dec870a2"><div class="ttname"><a href="group__flc.html#ga60c6b368bd0b32348d37c239dec870a2">FLC_EnableInt</a></div><div class="ttdeci">int FLC_EnableInt(uint32_t mask)</div><div class="ttdoc">Enable flash interrupts. </div></div>
 <div class="ttc" id="group__flc_html_ga7d13b8204f1163e40d6f3369091ec562"><div class="ttname"><a href="group__flc.html#ga7d13b8204f1163e40d6f3369091ec562">FLC_UnlockInfoBlock</a></div><div class="ttdeci">int FLC_UnlockInfoBlock(uint32_t address)</div><div class="ttdoc">Unlock info block. </div></div>
@@ -85,6 +86,7 @@ $(document).ready(function(){initNavTree('flc_8h_source.html','');});
 <div class="ttc" id="group__flc_html_ga0cb38b992f55df3a8f2b7fe191237baa"><div class="ttname"><a href="group__flc.html#ga0cb38b992f55df3a8f2b7fe191237baa">FLC_LockInfoBlock</a></div><div class="ttdeci">int FLC_LockInfoBlock(uint32_t address)</div><div class="ttdoc">Lock info block. </div></div>
 <div class="ttc" id="group__flc_html_gad66c50abe1036551df8fe389b48634d3"><div class="ttname"><a href="group__flc.html#gad66c50abe1036551df8fe389b48634d3">FLC_ClearFlags</a></div><div class="ttdeci">int FLC_ClearFlags(uint32_t mask)</div><div class="ttdoc">Clear flash interrupt flags. </div></div>
 <div class="ttc" id="group__flc_html_ga6dd7cadd48dd6794326c9513dbb28b3f"><div class="ttname"><a href="group__flc.html#ga6dd7cadd48dd6794326c9513dbb28b3f">FLC_MultiPageErase</a></div><div class="ttdeci">int FLC_MultiPageErase(uint32_t start, uint32_t end)</div><div class="ttdoc">Erases flash pages from start to end address inclusive. </div></div>
+<div class="ttc" id="group__flc_html_ga9f27160d352d96821a7336fa7277f0d9"><div class="ttname"><a href="group__flc.html#ga9f27160d352d96821a7336fa7277f0d9">FLC_InfoBlockUnlocked</a></div><div class="ttdeci">int FLC_InfoBlockUnlocked(uint32_t address)</div><div class="ttdoc">Test to see if info block is already unlocked. </div></div>
 <div class="ttc" id="group__flc_html_ga611826546917e9934f0156262043c95a"><div class="ttname"><a href="group__flc.html#ga611826546917e9934f0156262043c95a">FLC_Erase</a></div><div class="ttdeci">int FLC_Erase(uint32_t start, uint32_t end, uint32_t *buffer, unsigned length)</div><div class="ttdoc">Erase a range from start to end address. </div></div>
 </div><!-- fragment --></div><!-- contents -->
 </div><!-- doc-content -->
diff --git a/lib/sdk/Documentation/html/flc__regs_8h_source.html b/lib/sdk/Documentation/html/flc__regs_8h_source.html
index b9e1f30b31b4ccbed37a5853f75838fa39472438..ed1208c74b29b2d8e95bc572950e6497989ff525 100644
--- a/lib/sdk/Documentation/html/flc__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/flc__regs_8h_source.html
@@ -71,9 +71,10 @@ $(document).ready(function(){initNavTree('flc__regs_8h_source.html','');});
 <div class="title">flc_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _FLC_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _FLC_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#a5fc5cc259eebdefa74dfcb05baf66b76">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#a5fc5cc259eebdefa74dfcb05baf66b76">addr</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#aed9f8453e61f6d9a9aa7d61810029607">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#aed9f8453e61f6d9a9aa7d61810029607">clkdiv</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#acdc56fe6a92b6082cde1672b01864248">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#acdc56fe6a92b6082cde1672b01864248">cn</a>;                   </div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    __R  uint32_t rsv_0xc_0x23[6];</div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#ae9c80a4b74e3ad442406f52c094a8a7d">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#ae9c80a4b74e3ad442406f52c094a8a7d">intr</a>;                 </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    __R  uint32_t rsv_0x28_0x2f[2];</div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#ad997fa5bd51b834b8859c1164768098c">   95</a></span>&#160;    __IO uint32_t data[4];              </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#a5521cfb585e4b2747422327407c264d2">   96</a></span>&#160;    __O  uint32_t <a class="code" href="structmxc__flc__regs__t.html#a5521cfb585e4b2747422327407c264d2">acntl</a>;                </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;} <a class="code" href="structmxc__flc__regs__t.html">mxc_flc_regs_t</a>;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;<span class="comment">/* Register offsets for module FLC */</span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga4c0a38df14a439a01772116edf6be7b9">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_ADDR                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga61cc2f4d654ee0f63b03a374286500e6">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_CLKDIV                   ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#gab8604a203f4e2d204421adda37634fe7">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_CN                       ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga80fb9816b684c67a72399b6740e5f4d1">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_INTR                     ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga83d4d92b698fca4c920c7d18a09ce0f8">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_DATA                     ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga7f6c4b7ba0cb7402ced056ef016b838c">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_ACNTL                    ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__FLC__ADDR.html#ga8d8eab503d3a269970b82badab743445">  120</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ADDR_ADDR_POS                        0 </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__FLC__ADDR.html#gaa9117911c51bfe563dcdb8f263b00b6e">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ADDR_ADDR                            ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_FLC_ADDR_ADDR_POS)) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__FLC__CLKDIV.html#ga979ea3d709faf2bb6c19b10d433873c7">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CLKDIV_CLKDIV_POS                    0 </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__FLC__CLKDIV.html#ga63fb24529deab5a97a3fd26046bd6be1">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CLKDIV_CLKDIV                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_FLC_CLKDIV_CLKDIV_POS)) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga68e8e05a50655e93ee263b38c37cd0b9">  143</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WR_POS                            0 </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaa4a127bb1a1ced0bb4666df428c7b333">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WR                                ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_WR_POS)) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga4dc3edd9a2f56aa40caafe199c201e06">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ME_POS                            1 </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga14362e7211b30affe8faa56a67b984d1">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ME                                ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_ME_POS)) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga83d16857d9a5e184e2d95b4d5b296113">  149</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PGE_POS                           2 </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf3e68a8baf19c6301e202d106ca8c37c">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PGE                               ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_PGE_POS)) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaa25da90773c2aca0693b27cc6b9a221e">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WDTH_POS                          4 </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gab2ea186492fcaf16440bcad9ce073385">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WDTH                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_WDTH_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaaa19779d6c7f049358b12fcacbe81433">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ERASE_CODE_POS                    8 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga77cbb98afa8c4b84dbbf8679ef936497">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ERASE_CODE                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf67a9f9b3d7ec9d9475dd6ae43a827a7">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_ERASE_CODE_NOP                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gafbed0de29b325de1fedd4a0809da2cea">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_ERASE_CODE_NOP                    (MXC_V_FLC_CN_ERASE_CODE_NOP &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf1e1e7a3e2834cd04e99de7b58daa5b9">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE              ((uint32_t)0x55UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga116c05aa1251454733ff917a611854ed">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE              (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf63e9967db4a5c7907195fe4c4839c40">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL               ((uint32_t)0xAAUL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gada4413cbd6d4834ac42896121b3400fd">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL               (MXC_V_FLC_CN_ERASE_CODE_ERASEALL &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gad553a62f9574c6a6665315ce60c13c32">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PEND_POS                          24 </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga62f26c5210689f575253fe15ed31c0f8">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PEND                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_PEND_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga9d513bc192ab33ecd175093ed9b48b2a">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_LVE_POS                           25 </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gad6fd30e0b10bbe77250834bb141235d3">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_LVE                               ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_LVE_POS)) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gae36e44d74c1415e835e4644a20e34d7c">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_BRST_POS                          27 </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga06be6b9392c8dd6dbad0434f5e70fe08">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_BRST                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_BRST_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga6861f22ee99248bf588705c65c02c791">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_UNLOCK_POS                        28 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga42925a7ef20f185a2f94c672c06b0cd7">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_UNLOCK                            ((uint32_t)(0xFUL &lt;&lt; MXC_F_FLC_CN_UNLOCK_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga399effb1be40f1b3b144f808a084be0e">  175</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_UNLOCK_UNLOCKED                   ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga6193c11666c081d176f194cde5bdc433">  176</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_UNLOCK_UNLOCKED                   (MXC_V_FLC_CN_UNLOCK_UNLOCKED &lt;&lt; MXC_F_FLC_CN_UNLOCK_POS) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga9617696496caaf94788d631619239837">  177</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_UNLOCK_LOCKED                     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gafdce423f45e171148e79ceff4bebb846">  178</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_UNLOCK_LOCKED                     (MXC_V_FLC_CN_UNLOCK_LOCKED &lt;&lt; MXC_F_FLC_CN_UNLOCK_POS) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#gae2d4df085f186ec36bae60612ba4ae7c">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONE_POS                        0 </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga1b94008edb4500355934b76d2fb99717">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_DONE_POS)) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga17cb37260d2d9551f910634841795d4c">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AF_POS                          1 </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga318b14a48f29b849d4b120b03e1140fe">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AF                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_AF_POS)) </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#gad1e098c53d6e2704f4e84b34fc9841ba">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONEIE_POS                      8 </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga6282ba32ae6e44d3cde63cbf9bd2e7b3">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONEIE                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_DONEIE_POS)) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga0e527008fe3fa23227835acce089fc3d">  197</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AFIE_POS                        9 </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#gaca151c44b60a4fac9528bcf79f69fc67">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AFIE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_AFIE_POS)) </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__FLC__DATA.html#ga1b11310f09a3bdc3002a1ceb433b9beb">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_DATA_DATA_POS                        0 </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__FLC__DATA.html#gaf0876180d517178b78cace2f82513831">  209</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_DATA_DATA                            ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_FLC_DATA_DATA_POS)) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__FLC__ACNTL.html#ga2d3e8c3548b27d9beac2dbc28a1d7f16">  223</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ACNTL_ACNTL_POS                      0 </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__FLC__ACNTL.html#gabd916dfa6330118f6afe23d41a87c876">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ACNTL_ACNTL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_FLC_ACNTL_ACNTL_POS)) </span></div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00229"></a><span class="lineno">  229</span>&#160;}</div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00231"></a><span class="lineno">  231</span>&#160;</div><div class="line"><a name="l00232"></a><span class="lineno">  232</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _FLC_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__flc__regs__t_html_a5521cfb585e4b2747422327407c264d2"><div class="ttname"><a href="structmxc__flc__regs__t.html#a5521cfb585e4b2747422327407c264d2">mxc_flc_regs_t::acntl</a></div><div class="ttdeci">__O uint32_t acntl</div><div class="ttdoc">0x40: FLC ACNTL Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:96</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _FLC_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _FLC_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#a5fc5cc259eebdefa74dfcb05baf66b76">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#a5fc5cc259eebdefa74dfcb05baf66b76">addr</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#aed9f8453e61f6d9a9aa7d61810029607">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#aed9f8453e61f6d9a9aa7d61810029607">clkdiv</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#acdc56fe6a92b6082cde1672b01864248">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#acdc56fe6a92b6082cde1672b01864248">cn</a>;                   </div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    __R  uint32_t rsv_0xc_0x23[6];</div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#ae9c80a4b74e3ad442406f52c094a8a7d">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__flc__regs__t.html#ae9c80a4b74e3ad442406f52c094a8a7d">intr</a>;                 </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#a8dae1b3b860055653a1eceb54f453da7">   94</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__flc__regs__t.html#a8dae1b3b860055653a1eceb54f453da7">ecc_data</a>;             </div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;    __R  uint32_t rsv_0x2c;</div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#ad997fa5bd51b834b8859c1164768098c">   96</a></span>&#160;    __IO uint32_t data[4];              </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__flc__regs__t.html#a5521cfb585e4b2747422327407c264d2">   97</a></span>&#160;    __O  uint32_t <a class="code" href="structmxc__flc__regs__t.html#a5521cfb585e4b2747422327407c264d2">acntl</a>;                </div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;} <a class="code" href="structmxc__flc__regs__t.html">mxc_flc_regs_t</a>;</div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;</div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;<span class="comment">/* Register offsets for module FLC */</span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga4c0a38df14a439a01772116edf6be7b9">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_ADDR                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga61cc2f4d654ee0f63b03a374286500e6">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_CLKDIV                   ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#gab8604a203f4e2d204421adda37634fe7">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_CN                       ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga80fb9816b684c67a72399b6740e5f4d1">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_INTR                     ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#gaf0d8ac458f415559cc015c9219465c4b">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_ECC_DATA                 ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga83d4d92b698fca4c920c7d18a09ce0f8">  112</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_DATA                     ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="group__FLC__Register__Offsets.html#ga7f6c4b7ba0cb7402ced056ef016b838c">  113</a></span>&#160;<span class="preprocessor"> #define MXC_R_FLC_ACNTL                    ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__FLC__ADDR.html#ga8d8eab503d3a269970b82badab743445">  122</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ADDR_ADDR_POS                        0 </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__FLC__ADDR.html#gaa9117911c51bfe563dcdb8f263b00b6e">  123</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ADDR_ADDR                            ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_FLC_ADDR_ADDR_POS)) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__FLC__CLKDIV.html#ga979ea3d709faf2bb6c19b10d433873c7">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CLKDIV_CLKDIV_POS                    0 </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__FLC__CLKDIV.html#ga63fb24529deab5a97a3fd26046bd6be1">  135</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CLKDIV_CLKDIV                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_FLC_CLKDIV_CLKDIV_POS)) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga68e8e05a50655e93ee263b38c37cd0b9">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WR_POS                            0 </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaa4a127bb1a1ced0bb4666df428c7b333">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WR                                ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_WR_POS)) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga4dc3edd9a2f56aa40caafe199c201e06">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ME_POS                            1 </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga14362e7211b30affe8faa56a67b984d1">  149</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ME                                ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_ME_POS)) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga83d16857d9a5e184e2d95b4d5b296113">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PGE_POS                           2 </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf3e68a8baf19c6301e202d106ca8c37c">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PGE                               ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_PGE_POS)) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaa25da90773c2aca0693b27cc6b9a221e">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WDTH_POS                          4 </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gab2ea186492fcaf16440bcad9ce073385">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_WDTH                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_WDTH_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaaa19779d6c7f049358b12fcacbe81433">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ERASE_CODE_POS                    8 </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga77cbb98afa8c4b84dbbf8679ef936497">  158</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_ERASE_CODE                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS)) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf67a9f9b3d7ec9d9475dd6ae43a827a7">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_ERASE_CODE_NOP                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gafbed0de29b325de1fedd4a0809da2cea">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_ERASE_CODE_NOP                    (MXC_V_FLC_CN_ERASE_CODE_NOP &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf1e1e7a3e2834cd04e99de7b58daa5b9">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE              ((uint32_t)0x55UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga116c05aa1251454733ff917a611854ed">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE              (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gaf63e9967db4a5c7907195fe4c4839c40">  163</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL               ((uint32_t)0xAAUL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gada4413cbd6d4834ac42896121b3400fd">  164</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL               (MXC_V_FLC_CN_ERASE_CODE_ERASEALL &lt;&lt; MXC_F_FLC_CN_ERASE_CODE_POS) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gad553a62f9574c6a6665315ce60c13c32">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PEND_POS                          24 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga62f26c5210689f575253fe15ed31c0f8">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_PEND                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_PEND_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga9d513bc192ab33ecd175093ed9b48b2a">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_LVE_POS                           25 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gad6fd30e0b10bbe77250834bb141235d3">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_LVE                               ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_LVE_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga6861f22ee99248bf588705c65c02c791">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_UNLOCK_POS                        28 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga42925a7ef20f185a2f94c672c06b0cd7">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_CN_UNLOCK                            ((uint32_t)(0xFUL &lt;&lt; MXC_F_FLC_CN_UNLOCK_POS)) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga399effb1be40f1b3b144f808a084be0e">  174</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_UNLOCK_UNLOCKED                   ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga6193c11666c081d176f194cde5bdc433">  175</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_UNLOCK_UNLOCKED                   (MXC_V_FLC_CN_UNLOCK_UNLOCKED &lt;&lt; MXC_F_FLC_CN_UNLOCK_POS) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#ga9617696496caaf94788d631619239837">  176</a></span>&#160;<span class="preprocessor"> #define MXC_V_FLC_CN_UNLOCK_LOCKED                     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__FLC__CN.html#gafdce423f45e171148e79ceff4bebb846">  177</a></span>&#160;<span class="preprocessor"> #define MXC_S_FLC_CN_UNLOCK_LOCKED                     (MXC_V_FLC_CN_UNLOCK_LOCKED &lt;&lt; MXC_F_FLC_CN_UNLOCK_POS) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#gae2d4df085f186ec36bae60612ba4ae7c">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONE_POS                        0 </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga1b94008edb4500355934b76d2fb99717">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_DONE_POS)) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga17cb37260d2d9551f910634841795d4c">  190</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AF_POS                          1 </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga318b14a48f29b849d4b120b03e1140fe">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AF                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_AF_POS)) </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#gad1e098c53d6e2704f4e84b34fc9841ba">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONEIE_POS                      8 </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga6282ba32ae6e44d3cde63cbf9bd2e7b3">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_DONEIE                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_DONEIE_POS)) </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#ga0e527008fe3fa23227835acce089fc3d">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AFIE_POS                        9 </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__FLC__INTR.html#gaca151c44b60a4fac9528bcf79f69fc67">  197</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_INTR_AFIE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_INTR_AFIE_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__FLC__ECC__DATA.html#gafd59564e84419f8bc4bdb1df264006cd">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ECC_DATA_ECC_EVEN_POS                0 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__FLC__ECC__DATA.html#gadf7d942683803abaafaab48009ff1e61">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ECC_DATA_ECC_EVEN                    ((uint32_t)(0xFFUL &lt;&lt; MXC_F_FLC_ECC_DATA_ECC_EVEN_POS)) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__FLC__ECC__DATA.html#ga5cd5b48e5435d9ee8395036ff18715de">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ECC_DATA_ECC_ODD_POS                 16 </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__FLC__ECC__DATA.html#gaa9e1d4590b2eb39266a07db77739cc30">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ECC_DATA_ECC_ODD                     ((uint32_t)(0xFFUL &lt;&lt; MXC_F_FLC_ECC_DATA_ECC_ODD_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__FLC__DATA.html#ga1b11310f09a3bdc3002a1ceb433b9beb">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_DATA_DATA_POS                        0 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__FLC__DATA.html#gaf0876180d517178b78cace2f82513831">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_DATA_DATA                            ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_FLC_DATA_DATA_POS)) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__FLC__ACNTL.html#ga2d3e8c3548b27d9beac2dbc28a1d7f16">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ACNTL_ACNTL_POS                      0 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__FLC__ACNTL.html#gabd916dfa6330118f6afe23d41a87c876">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_FLC_ACNTL_ACNTL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_FLC_ACNTL_ACNTL_POS)) </span></div><div class="line"><a name="l00241"></a><span class="lineno">  241</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;}</div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00244"></a><span class="lineno">  244</span>&#160;</div><div class="line"><a name="l00245"></a><span class="lineno">  245</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _FLC_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__flc__regs__t_html_a5521cfb585e4b2747422327407c264d2"><div class="ttname"><a href="structmxc__flc__regs__t.html#a5521cfb585e4b2747422327407c264d2">mxc_flc_regs_t::acntl</a></div><div class="ttdeci">__O uint32_t acntl</div><div class="ttdoc">0x40: FLC ACNTL Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:97</div></div>
 <div class="ttc" id="structmxc__flc__regs__t_html_aed9f8453e61f6d9a9aa7d61810029607"><div class="ttname"><a href="structmxc__flc__regs__t.html#aed9f8453e61f6d9a9aa7d61810029607">mxc_flc_regs_t::clkdiv</a></div><div class="ttdeci">__IO uint32_t clkdiv</div><div class="ttdoc">0x04: FLC CLKDIV Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:90</div></div>
 <div class="ttc" id="structmxc__flc__regs__t_html_a5fc5cc259eebdefa74dfcb05baf66b76"><div class="ttname"><a href="structmxc__flc__regs__t.html#a5fc5cc259eebdefa74dfcb05baf66b76">mxc_flc_regs_t::addr</a></div><div class="ttdeci">__IO uint32_t addr</div><div class="ttdoc">0x00: FLC ADDR Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:89</div></div>
+<div class="ttc" id="structmxc__flc__regs__t_html_a8dae1b3b860055653a1eceb54f453da7"><div class="ttname"><a href="structmxc__flc__regs__t.html#a8dae1b3b860055653a1eceb54f453da7">mxc_flc_regs_t::ecc_data</a></div><div class="ttdeci">__I uint32_t ecc_data</div><div class="ttdoc">0x28: FLC ECC_DATA Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:94</div></div>
 <div class="ttc" id="structmxc__flc__regs__t_html_ae9c80a4b74e3ad442406f52c094a8a7d"><div class="ttname"><a href="structmxc__flc__regs__t.html#ae9c80a4b74e3ad442406f52c094a8a7d">mxc_flc_regs_t::intr</a></div><div class="ttdeci">__IO uint32_t intr</div><div class="ttdoc">0x024: FLC INTR Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:93</div></div>
 <div class="ttc" id="structmxc__flc__regs__t_html"><div class="ttname"><a href="structmxc__flc__regs__t.html">mxc_flc_regs_t</a></div><div class="ttdoc">Structure type to access the FLC Registers. </div><div class="ttdef"><b>Definition:</b> flc_regs.h:88</div></div>
 <div class="ttc" id="structmxc__flc__regs__t_html_acdc56fe6a92b6082cde1672b01864248"><div class="ttname"><a href="structmxc__flc__regs__t.html#acdc56fe6a92b6082cde1672b01864248">mxc_flc_regs_t::cn</a></div><div class="ttdeci">__IO uint32_t cn</div><div class="ttdoc">0x08: FLC CN Register </div><div class="ttdef"><b>Definition:</b> flc_regs.h:91</div></div>
diff --git a/lib/sdk/Documentation/html/functions_b.html b/lib/sdk/Documentation/html/functions_b.html
index d8553243acc61148afcee202e6027c6bf4aca390..81ac15849f474a22c00aa3d578c595515155f0e7 100644
--- a/lib/sdk/Documentation/html/functions_b.html
+++ b/lib/sdk/Documentation/html/functions_b.html
@@ -86,9 +86,6 @@ $(document).ready(function(){initNavTree('functions_b.html','');});
 <li>baud_scale
 : <a class="el" href="structspixr__cfg__t.html#a66c378f5c62d5ad13a8e644e4b01bb5b">spixr_cfg_t</a>
 </li>
-<li>bbcr
-: <a class="el" href="structmxc__rpu__regs__t.html#a578dd37f6abddf3a8daea235ce614185">mxc_rpu_regs_t</a>
-</li>
 <li>bbsir
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 </li>
@@ -123,9 +120,18 @@ $(document).ready(function(){initNavTree('functions_b.html','');});
 <li>btle
 : <a class="el" href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">mxc_rpu_regs_t</a>
 </li>
+<li>buaod
+: <a class="el" href="structmxc__pwrseq__regs__t.html#a2afa0f0e932e56ca6e98bd3dda5e7eaf">mxc_pwrseq_regs_t</a>
+</li>
 <li>buffer
 : <a class="el" href="structmxc__sdhc__regs__t.html#a8cad04843752527360c737ed6d7dac30">mxc_sdhc_regs_t</a>
 </li>
+<li>buretvec
+: <a class="el" href="structmxc__pwrseq__regs__t.html#a275e49a4b3f5f23ec82436ac339972fe">mxc_pwrseq_regs_t</a>
+</li>
+<li>bus_idle
+: <a class="el" href="structmxc__spixf__regs__t.html#adb6d248035b8e5ce0de141816df4d6dc">mxc_spixf_regs_t</a>
+</li>
 <li>bus_voltage
 : <a class="el" href="structsdhc__cfg__t.html#ab7d48a68e020038373a84944bddfb72c">sdhc_cfg_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_d.html b/lib/sdk/Documentation/html/functions_d.html
index b8a4f4d446e8e09362f9f831afc1d0838c4851f8..20338f97bc0db7c5b6d07610e8e8d72d4724064e 100644
--- a/lib/sdk/Documentation/html/functions_d.html
+++ b/lib/sdk/Documentation/html/functions_d.html
@@ -91,9 +91,6 @@ $(document).ready(function(){initNavTree('functions_d.html','');});
 <li>data_width
 : <a class="el" href="structspixr__cfg__t.html#aedbf77a5da7ac1cec9b9655faa9e0c00">spixr_cfg_t</a>
 </li>
-<li>dcache
-: <a class="el" href="structmxc__rpu__regs__t.html#a5fc2a3b485206573e4054868b11ca9eb">mxc_rpu_regs_t</a>
-</li>
 <li>deass
 : <a class="el" href="structspi17y__req.html#a112ade8d677dd8ab8752dd45a5ccb2fb">spi17y_req_t</a>
 , <a class="el" href="structspi__req.html#a6b2b9c354900fe0d49436a151f592998">spi_req_t</a>
diff --git a/lib/sdk/Documentation/html/functions_dup.js b/lib/sdk/Documentation/html/functions_dup.js
index 714cf419ed56a122825811ade07389ebaddf62b5..d24eec0323cf0ab46c79bf2fb0a21fe1cd75c04b 100644
--- a/lib/sdk/Documentation/html/functions_dup.js
+++ b/lib/sdk/Documentation/html/functions_dup.js
@@ -14,7 +14,6 @@ var functions_dup =
     [ "n", "functions_n.html", null ],
     [ "o", "functions_o.html", null ],
     [ "p", "functions_p.html", null ],
-    [ "q", "functions_q.html", null ],
     [ "r", "functions_r.html", null ],
     [ "s", "functions_s.html", null ],
     [ "t", "functions_t.html", null ],
diff --git a/lib/sdk/Documentation/html/functions_e.html b/lib/sdk/Documentation/html/functions_e.html
index ff84ca46152a184d28a000829d1e4ede95fb086b..31c6835783f0c798f271ecc641a22de3e4269f05 100644
--- a/lib/sdk/Documentation/html/functions_e.html
+++ b/lib/sdk/Documentation/html/functions_e.html
@@ -70,6 +70,9 @@ $(document).ready(function(){initNavTree('functions_e.html','');});
 <div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
 
 <h3><a id="index_e"></a>- e -</h3><ul>
+<li>ecc_data
+: <a class="el" href="structmxc__flc__regs__t.html#a8dae1b3b860055653a1eceb54f453da7">mxc_flc_regs_t</a>
+</li>
 <li>en
 : <a class="el" href="structmxc__gpio__regs__t.html#a12ebf0d620fc9bcd0e7a04bb0eb87095">mxc_gpio_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_g.html b/lib/sdk/Documentation/html/functions_g.html
index 70039ac7823ed81435a6516aae15e3ec58a287b7..f5cb2ed928132e325d54fbcf6f0fe7307cd17ed7 100644
--- a/lib/sdk/Documentation/html/functions_g.html
+++ b/lib/sdk/Documentation/html/functions_g.html
@@ -76,12 +76,6 @@ $(document).ready(function(){initNavTree('functions_g.html','');});
 <li>gen_ctrl
 : <a class="el" href="structmxc__spixfc__regs__t.html#a8e0da2cd9d0235b9b068e3ed43b89662">mxc_spixfc_regs_t</a>
 </li>
-<li>gp0
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a5489a99b3c2604deceaa24eb3041955a">mxc_pwrseq_regs_t</a>
-</li>
-<li>gp1
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a22b51eadb62898ff2252e91f3f1d2e02">mxc_pwrseq_regs_t</a>
-</li>
 <li>gpio0
 : <a class="el" href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">mxc_rpu_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_i.html b/lib/sdk/Documentation/html/functions_i.html
index 76b6910e7450f2e64cecd13cc43a1b2322744866..466dea6917784b56b882e2550f4456c354a48501 100644
--- a/lib/sdk/Documentation/html/functions_i.html
+++ b/lib/sdk/Documentation/html/functions_i.html
@@ -70,30 +70,27 @@ $(document).ready(function(){initNavTree('functions_i.html','');});
 <div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
 
 <h3><a id="index_i"></a>- i -</h3><ul>
-<li>i2c0
-: <a class="el" href="structmxc__rpu__regs__t.html#a67f843cf68d636443ee57ce3133fbd12">mxc_rpu_regs_t</a>
+<li>i2c0_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#aee54ba2b716b8ec8eb511d6d7dee57a1">mxc_rpu_regs_t</a>
 </li>
-<li>i2c1
-: <a class="el" href="structmxc__rpu__regs__t.html#a05e9a4140c71fdab6518205e023c6313">mxc_rpu_regs_t</a>
+<li>i2c1_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#ae1f643fe22f713dc8f1345ac2582a628">mxc_rpu_regs_t</a>
 </li>
-<li>i2c2
-: <a class="el" href="structmxc__rpu__regs__t.html#ab2184b645146cece7001515e57b190ad">mxc_rpu_regs_t</a>
+<li>i2c2_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#a46f94aa32bf20f1306dd0b30bad69ec6">mxc_rpu_regs_t</a>
 </li>
-<li>i2s_ctrl
-: <a class="el" href="structmxc__spixr__regs__t.html#a90608b29b3f3212205facf083fc3864e">mxc_spixr_regs_t</a>
+<li>icc0
+: <a class="el" href="structmxc__rpu__regs__t.html#a4f719bdddec9869dc1226debe906860d">mxc_rpu_regs_t</a>
 </li>
-<li>icache0
-: <a class="el" href="structmxc__rpu__regs__t.html#a3f3c752957bc9e467f5c9d2e831f555f">mxc_rpu_regs_t</a>
-</li>
-<li>icache1
-: <a class="el" href="structmxc__rpu__regs__t.html#a58cadc3c2770b44b7ebfa6c5f55635bd">mxc_rpu_regs_t</a>
-</li>
-<li>icachexip
-: <a class="el" href="structmxc__rpu__regs__t.html#a0214735f8b048f0386a35b3db6832bb1">mxc_rpu_regs_t</a>
+<li>icc1
+: <a class="el" href="structmxc__rpu__regs__t.html#aafa4124620f7faaef5a033b4309be329">mxc_rpu_regs_t</a>
 </li>
 <li>in
 : <a class="el" href="structmxc__gpio__regs__t.html#a0e9363bc6e34884e294f55287d764399">mxc_gpio_regs_t</a>
 </li>
+<li>in_en
+: <a class="el" href="structmxc__gpio__regs__t.html#aa6c384a08f486469b6aa1868f8ef4720">mxc_gpio_regs_t</a>
+</li>
 <li>int_clr
 : <a class="el" href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">mxc_gpio_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_l.html b/lib/sdk/Documentation/html/functions_l.html
index a946bc2561b19393f0d76034ae29695a1e258353..eea28f8cbc769facc0bfb2be903d53b05d2393fd 100644
--- a/lib/sdk/Documentation/html/functions_l.html
+++ b/lib/sdk/Documentation/html/functions_l.html
@@ -92,12 +92,6 @@ $(document).ready(function(){initNavTree('functions_l.html','');});
 <li>lpcn
 : <a class="el" href="structmxc__pwrseq__regs__t.html#acda7cefaab59b1351d543490c7de08fd">mxc_pwrseq_regs_t</a>
 </li>
-<li>lpmcreq
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a28f6161d913462e38ed382f10c8f38e6">mxc_pwrseq_regs_t</a>
-</li>
-<li>lpmcstat
-: <a class="el" href="structmxc__pwrseq__regs__t.html#ad3f173b5c522262557112a4a871643ce">mxc_pwrseq_regs_t</a>
-</li>
 <li>lpmemsd
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 </li>
@@ -116,24 +110,12 @@ $(document).ready(function(){initNavTree('functions_l.html','');});
 <li>lpwken1
 : <a class="el" href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">mxc_pwrseq_regs_t</a>
 </li>
-<li>lpwken2
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a94c29a74efad6c3cebe1f55110b52e61">mxc_pwrseq_regs_t</a>
-</li>
-<li>lpwken3
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a0c14230a8bd930a7d6fb6a20f9453711">mxc_pwrseq_regs_t</a>
-</li>
 <li>lpwkst0
 : <a class="el" href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">mxc_pwrseq_regs_t</a>
 </li>
 <li>lpwkst1
 : <a class="el" href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">mxc_pwrseq_regs_t</a>
 </li>
-<li>lpwkst2
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a6e78094b2c983a37535445dd946d9e59">mxc_pwrseq_regs_t</a>
-</li>
-<li>lpwkst3
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a846955a96142e1e7564aa77214f25a04">mxc_pwrseq_regs_t</a>
-</li>
 </ul>
 </div><!-- contents -->
 </div><!-- doc-content -->
diff --git a/lib/sdk/Documentation/html/functions_m.html b/lib/sdk/Documentation/html/functions_m.html
index f60a701c9707006d5cefa653e31108f556a1d1b1..b38ce01b82d9ef70477853b70238357f5ecaae2f 100644
--- a/lib/sdk/Documentation/html/functions_m.html
+++ b/lib/sdk/Documentation/html/functions_m.html
@@ -85,6 +85,9 @@ $(document).ready(function(){initNavTree('functions_m.html','');});
 <li>max_curr_cfg
 : <a class="el" href="structmxc__sdhc__regs__t.html#a3ca2d1f1a83ae4f8ef6c0e02c9a9eae3">mxc_sdhc_regs_t</a>
 </li>
+<li>mcr
+: <a class="el" href="structmxc__rpu__regs__t.html#a171cf0c62b66f6b04ee8ff99ee230ba1">mxc_rpu_regs_t</a>
+</li>
 <li>memcfg
 : <a class="el" href="structmxc__emcc__regs__t.html#a1919b3c0d53f9485fe762b201c4c6bf1">mxc_emcc_regs_t</a>
 , <a class="el" href="structmxc__icc__regs__t.html#a5893df1d78d78b98e1f8e80bf9a499a1">mxc_icc_regs_t</a>
diff --git a/lib/sdk/Documentation/html/functions_p.html b/lib/sdk/Documentation/html/functions_p.html
index fa72353950f5c2aa84d3f2205b9cea733b5446a4..77b77ee587460da7adc4cadbcb0ad8374949f9ac 100644
--- a/lib/sdk/Documentation/html/functions_p.html
+++ b/lib/sdk/Documentation/html/functions_p.html
@@ -122,8 +122,8 @@ $(document).ready(function(){initNavTree('functions_p.html','');});
 <li>ps
 : <a class="el" href="structmxc__gpio__regs__t.html#a2ebe119356fa75bd745984ae2bf71494">mxc_gpio_regs_t</a>
 </li>
-<li>pt
-: <a class="el" href="structmxc__rpu__regs__t.html#a8c9edc39d61f24c7df1c403a4a1b9e78">mxc_rpu_regs_t</a>
+<li>ptg_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#a7cf24cf377876560e35ce321484cf3a4">mxc_rpu_regs_t</a>
 </li>
 <li>ptLength
 : <a class="el" href="structpt__pt__cfg__t.html#ae559465ca17078f68e10d8aa12db493a">pt_pt_cfg_t</a>
diff --git a/lib/sdk/Documentation/html/functions_r.html b/lib/sdk/Documentation/html/functions_r.html
index 4b2fcecabd2bd2c0f0b9c28f3e7ff31d2c1eacff..d98107f992c622e82e7afc450453d92bb0c7e6b2 100644
--- a/lib/sdk/Documentation/html/functions_r.html
+++ b/lib/sdk/Documentation/html/functions_r.html
@@ -72,7 +72,6 @@ $(document).ready(function(){initNavTree('functions_r.html','');});
 <h3><a id="index_r"></a>- r -</h3><ul>
 <li>ras
 : <a class="el" href="structmxc__htmr__regs__t.html#aee1617647a48af22d7f0b9eca3b04200">mxc_htmr_regs_t</a>
-, <a class="el" href="structmxc__rtc__regs__t.html#a312f52a6335fbc5d1bfab003689e725f">mxc_rtc_regs_t</a>
 </li>
 <li>rate_length
 : <a class="el" href="structmxc__pt__regs__t.html#a1c1d3f13299e64ab71e2a25dc8e1f967">mxc_pt_regs_t</a>
@@ -89,7 +88,6 @@ $(document).ready(function(){initNavTree('functions_r.html','');});
 </li>
 <li>rssa
 : <a class="el" href="structmxc__htmr__regs__t.html#a47538fa66454bc9621f7478438919ca3">mxc_htmr_regs_t</a>
-, <a class="el" href="structmxc__rtc__regs__t.html#a0227333293ec30e21fa6663eb80d6ac7">mxc_rtc_regs_t</a>
 </li>
 <li>rst
 : <a class="el" href="structmxc__wdt__regs__t.html#a6f54c7641e7e68bafaf287c4954f386b">mxc_wdt_regs_t</a>
diff --git a/lib/sdk/Documentation/html/functions_s.html b/lib/sdk/Documentation/html/functions_s.html
index 46921e867833757fcf8469ecf8ca1117395f4095..ce42881b08772ef3c771ed78424e784188bbaa0f 100644
--- a/lib/sdk/Documentation/html/functions_s.html
+++ b/lib/sdk/Documentation/html/functions_s.html
@@ -94,6 +94,9 @@ $(document).ready(function(){initNavTree('functions_s.html','');});
 <li>semaphores
 : <a class="el" href="structmxc__sema__regs__t.html#a7707db84b6a52bf6a2141a321e90bb17">mxc_sema_regs_t</a>
 </li>
+<li>sfcc
+: <a class="el" href="structmxc__rpu__regs__t.html#a8080c2b6a8f3a34c04a83d4255e96b61">mxc_rpu_regs_t</a>
+</li>
 <li>shared_bus
 : <a class="el" href="structmxc__sdhc__regs__t.html#a358719de16d4f7765bd5f96192c9176e">mxc_sdhc_regs_t</a>
 </li>
@@ -118,41 +121,29 @@ $(document).ready(function(){initNavTree('functions_s.html','');});
 <li>spctrl
 : <a class="el" href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">mxc_spixfc_regs_t</a>
 </li>
-<li>spid
-: <a class="el" href="structmxc__rpu__regs__t.html#a107ce59e766452ddd16ba0c679c756c7">mxc_rpu_regs_t</a>
-</li>
-<li>spixipm
-: <a class="el" href="structmxc__rpu__regs__t.html#acd8b09dccd4281e8fa47a3f690e0c287">mxc_rpu_regs_t</a>
-</li>
-<li>spixipmc
-: <a class="el" href="structmxc__rpu__regs__t.html#a835774853a29501e6a1f750d5a57956c">mxc_rpu_regs_t</a>
+<li>spi0
+: <a class="el" href="structmxc__rpu__regs__t.html#ab3363e181a7630bc3d3201eb3b879dfa">mxc_rpu_regs_t</a>
 </li>
-<li>spixipmfifo
-: <a class="el" href="structmxc__rpu__regs__t.html#ab79390483fc759b36c1492da84c39142">mxc_rpu_regs_t</a>
+<li>spi1
+: <a class="el" href="structmxc__rpu__regs__t.html#a6a8f3593c33e8e2a2c07ed8389670108">mxc_rpu_regs_t</a>
 </li>
-<li>sr
-: <a class="el" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">mxc_gpio_regs_t</a>
+<li>spi2
+: <a class="el" href="structmxc__rpu__regs__t.html#aa617d084516acc758d283a33deed9a38">mxc_rpu_regs_t</a>
 </li>
-<li>sram0
-: <a class="el" href="structmxc__rpu__regs__t.html#a73401214b554adea90654ae4ee9e441a">mxc_rpu_regs_t</a>
+<li>spixfc
+: <a class="el" href="structmxc__rpu__regs__t.html#a938e8c511fe710606bb950a76477b9a2">mxc_rpu_regs_t</a>
 </li>
-<li>sram1
-: <a class="el" href="structmxc__rpu__regs__t.html#af36206f67702f1598a065ceacb42ed76">mxc_rpu_regs_t</a>
+<li>spixfm
+: <a class="el" href="structmxc__rpu__regs__t.html#a0fa6182dc552923bce9dcbf52de361a3">mxc_rpu_regs_t</a>
 </li>
-<li>sram2
-: <a class="el" href="structmxc__rpu__regs__t.html#ae1d1de4f98df3b2171e9635b742376d1">mxc_rpu_regs_t</a>
+<li>spixm_fifo
+: <a class="el" href="structmxc__rpu__regs__t.html#aa66553c7c4c2ff2a65e176af948e6399">mxc_rpu_regs_t</a>
 </li>
-<li>sram3
-: <a class="el" href="structmxc__rpu__regs__t.html#ac31f8fe960e70e7f63a3e9b355204150">mxc_rpu_regs_t</a>
+<li>spixr
+: <a class="el" href="structmxc__rpu__regs__t.html#a493a625cf6437fc4ea51aeb6433d377b">mxc_rpu_regs_t</a>
 </li>
-<li>sram4
-: <a class="el" href="structmxc__rpu__regs__t.html#afce0eed072aa6ea690e311ea03098e96">mxc_rpu_regs_t</a>
-</li>
-<li>sram5
-: <a class="el" href="structmxc__rpu__regs__t.html#a7f226e3d43e02fcba1bbe3c75b8818dd">mxc_rpu_regs_t</a>
-</li>
-<li>sram6
-: <a class="el" href="structmxc__rpu__regs__t.html#a66156e610712dd5d497ea9cc69c82b7d">mxc_rpu_regs_t</a>
+<li>sr
+: <a class="el" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">mxc_gpio_regs_t</a>
 </li>
 <li>src
 : <a class="el" href="structmxc__dma__ch__regs__t.html#a892f57a64656deca7c61e76fc5806423">mxc_dma_ch_regs_t</a>
@@ -160,6 +151,9 @@ $(document).ready(function(){initNavTree('functions_s.html','');});
 <li>src_rld
 : <a class="el" href="structmxc__dma__ch__regs__t.html#a90a232c419b3b32ae4849761d31fe9df">mxc_dma_ch_regs_t</a>
 </li>
+<li>srcc
+: <a class="el" href="structmxc__rpu__regs__t.html#ace3ea78cbad80bfeca273e59f9f7b9c1">mxc_rpu_regs_t</a>
+</li>
 <li>ss_pol
 : <a class="el" href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">mxc_spixfc_regs_t</a>
 </li>
@@ -170,6 +164,9 @@ $(document).ready(function(){initNavTree('functions_s.html','');});
 : <a class="el" href="structmxc__htmr__regs__t.html#ab7d391aa538691e380b9162726395d4a">mxc_htmr_regs_t</a>
 , <a class="el" href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">mxc_rtc_regs_t</a>
 </li>
+<li>sseca
+: <a class="el" href="structmxc__rtc__regs__t.html#a5b608ffa87981e34088b40bada72144e">mxc_rtc_regs_t</a>
+</li>
 <li>ssel
 : <a class="el" href="structspi17y__req.html#a72a31cb80122e910c9ea82da1fc41b1f">spi17y_req_t</a>
 , <a class="el" href="structspi__req.html#af8cbfde9101e93efd08e104a478febce">spi_req_t</a>
@@ -216,6 +213,27 @@ $(document).ready(function(){initNavTree('functions_s.html','');});
 <li>sw_reset
 : <a class="el" href="structmxc__sdhc__regs__t.html#a4f574c19965cc110393f87fd1a22f5fc">mxc_sdhc_regs_t</a>
 </li>
+<li>sysram0
+: <a class="el" href="structmxc__rpu__regs__t.html#a326ba0b5ed008b242db40e9ab75500bc">mxc_rpu_regs_t</a>
+</li>
+<li>sysram1
+: <a class="el" href="structmxc__rpu__regs__t.html#acf032f7d78b6532dd6ad36ba8443a121">mxc_rpu_regs_t</a>
+</li>
+<li>sysram2
+: <a class="el" href="structmxc__rpu__regs__t.html#a3d15538d060546e2f115288d3a9ab709">mxc_rpu_regs_t</a>
+</li>
+<li>sysram3
+: <a class="el" href="structmxc__rpu__regs__t.html#a33efdc41a5dab826941aff9e4ee47d0d">mxc_rpu_regs_t</a>
+</li>
+<li>sysram4
+: <a class="el" href="structmxc__rpu__regs__t.html#a70722dd45c3732d6e3d827e46e722c39">mxc_rpu_regs_t</a>
+</li>
+<li>sysram5
+: <a class="el" href="structmxc__rpu__regs__t.html#a26e3639950f8bd188d066afec39d2bfe">mxc_rpu_regs_t</a>
+</li>
+<li>sysram6
+: <a class="el" href="structmxc__rpu__regs__t.html#a086921af8001fdf0d9af8935b068f865">mxc_rpu_regs_t</a>
+</li>
 </ul>
 </div><!-- contents -->
 </div><!-- doc-content -->
diff --git a/lib/sdk/Documentation/html/functions_t.html b/lib/sdk/Documentation/html/functions_t.html
index 296be1ad884d2bc0917c07ddc5c6f6342cf0d1eb..3020c71c4969ebf2cb0c20f803b389b0802bfce3 100644
--- a/lib/sdk/Documentation/html/functions_t.html
+++ b/lib/sdk/Documentation/html/functions_t.html
@@ -97,6 +97,9 @@ $(document).ready(function(){initNavTree('functions_t.html','');});
 <li>to
 : <a class="el" href="structmxc__sdhc__regs__t.html#a02e7f138ca6346b494b40c7c6901f615">mxc_sdhc_regs_t</a>
 </li>
+<li>toda
+: <a class="el" href="structmxc__rtc__regs__t.html#ad4a4f5073aea7dcc1a623e0b7e3ca3a5">mxc_rtc_regs_t</a>
+</li>
 <li>train
 : <a class="el" href="structmxc__pt__regs__t.html#a0eb87145bab2b61825026fb5d955d264">mxc_pt_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_vars.js b/lib/sdk/Documentation/html/functions_vars.js
index 26e8d7a7e23a4fdca1a1ea17798a69c8a7e0822d..8ea334a3b5a8be1c6271d3b2b6f39222b7dc18bb 100644
--- a/lib/sdk/Documentation/html/functions_vars.js
+++ b/lib/sdk/Documentation/html/functions_vars.js
@@ -14,7 +14,6 @@ var functions_vars =
     [ "n", "functions_vars_n.html", null ],
     [ "o", "functions_vars_o.html", null ],
     [ "p", "functions_vars_p.html", null ],
-    [ "q", "functions_vars_q.html", null ],
     [ "r", "functions_vars_r.html", null ],
     [ "s", "functions_vars_s.html", null ],
     [ "t", "functions_vars_t.html", null ],
diff --git a/lib/sdk/Documentation/html/functions_vars_b.html b/lib/sdk/Documentation/html/functions_vars_b.html
index 5a78db179664c8a03a2da5f1cbf0c0c38e7cf907..ec01ecbf290dc8975811280eb3774ac082a98dfd 100644
--- a/lib/sdk/Documentation/html/functions_vars_b.html
+++ b/lib/sdk/Documentation/html/functions_vars_b.html
@@ -86,9 +86,6 @@ $(document).ready(function(){initNavTree('functions_vars_b.html','');});
 <li>baud_scale
 : <a class="el" href="structspixr__cfg__t.html#a66c378f5c62d5ad13a8e644e4b01bb5b">spixr_cfg_t</a>
 </li>
-<li>bbcr
-: <a class="el" href="structmxc__rpu__regs__t.html#a578dd37f6abddf3a8daea235ce614185">mxc_rpu_regs_t</a>
-</li>
 <li>bbsir
 : <a class="el" href="structmxc__rpu__regs__t.html#a509d073c9df3c06db1dc8a5fe779f377">mxc_rpu_regs_t</a>
 </li>
@@ -123,9 +120,18 @@ $(document).ready(function(){initNavTree('functions_vars_b.html','');});
 <li>btle
 : <a class="el" href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">mxc_rpu_regs_t</a>
 </li>
+<li>buaod
+: <a class="el" href="structmxc__pwrseq__regs__t.html#a2afa0f0e932e56ca6e98bd3dda5e7eaf">mxc_pwrseq_regs_t</a>
+</li>
 <li>buffer
 : <a class="el" href="structmxc__sdhc__regs__t.html#a8cad04843752527360c737ed6d7dac30">mxc_sdhc_regs_t</a>
 </li>
+<li>buretvec
+: <a class="el" href="structmxc__pwrseq__regs__t.html#a275e49a4b3f5f23ec82436ac339972fe">mxc_pwrseq_regs_t</a>
+</li>
+<li>bus_idle
+: <a class="el" href="structmxc__spixf__regs__t.html#adb6d248035b8e5ce0de141816df4d6dc">mxc_spixf_regs_t</a>
+</li>
 <li>bus_voltage
 : <a class="el" href="structsdhc__cfg__t.html#ab7d48a68e020038373a84944bddfb72c">sdhc_cfg_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_vars_d.html b/lib/sdk/Documentation/html/functions_vars_d.html
index 08bdcd479662c85b3712b6775786ff77d590d40f..e33776fad1454df201ca4206177821c10cbc1e32 100644
--- a/lib/sdk/Documentation/html/functions_vars_d.html
+++ b/lib/sdk/Documentation/html/functions_vars_d.html
@@ -91,9 +91,6 @@ $(document).ready(function(){initNavTree('functions_vars_d.html','');});
 <li>data_width
 : <a class="el" href="structspixr__cfg__t.html#aedbf77a5da7ac1cec9b9655faa9e0c00">spixr_cfg_t</a>
 </li>
-<li>dcache
-: <a class="el" href="structmxc__rpu__regs__t.html#a5fc2a3b485206573e4054868b11ca9eb">mxc_rpu_regs_t</a>
-</li>
 <li>deass
 : <a class="el" href="structspi17y__req.html#a112ade8d677dd8ab8752dd45a5ccb2fb">spi17y_req_t</a>
 , <a class="el" href="structspi__req.html#a6b2b9c354900fe0d49436a151f592998">spi_req_t</a>
diff --git a/lib/sdk/Documentation/html/functions_vars_e.html b/lib/sdk/Documentation/html/functions_vars_e.html
index 3f09a3b6e90e3b1cf2b94c20bc6cdb78f4a752e9..669b12c6d6290b5c0fcc4e0d0b5fe45952c90274 100644
--- a/lib/sdk/Documentation/html/functions_vars_e.html
+++ b/lib/sdk/Documentation/html/functions_vars_e.html
@@ -70,6 +70,9 @@ $(document).ready(function(){initNavTree('functions_vars_e.html','');});
 &#160;
 
 <h3><a id="index_e"></a>- e -</h3><ul>
+<li>ecc_data
+: <a class="el" href="structmxc__flc__regs__t.html#a8dae1b3b860055653a1eceb54f453da7">mxc_flc_regs_t</a>
+</li>
 <li>en
 : <a class="el" href="structmxc__gpio__regs__t.html#a12ebf0d620fc9bcd0e7a04bb0eb87095">mxc_gpio_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_vars_g.html b/lib/sdk/Documentation/html/functions_vars_g.html
index 5a2181b248c54185a5f3bf5c1529e2169904d346..05d958cb9e29fca31d29b8ad889cb4b882392bed 100644
--- a/lib/sdk/Documentation/html/functions_vars_g.html
+++ b/lib/sdk/Documentation/html/functions_vars_g.html
@@ -76,12 +76,6 @@ $(document).ready(function(){initNavTree('functions_vars_g.html','');});
 <li>gen_ctrl
 : <a class="el" href="structmxc__spixfc__regs__t.html#a8e0da2cd9d0235b9b068e3ed43b89662">mxc_spixfc_regs_t</a>
 </li>
-<li>gp0
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a5489a99b3c2604deceaa24eb3041955a">mxc_pwrseq_regs_t</a>
-</li>
-<li>gp1
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a22b51eadb62898ff2252e91f3f1d2e02">mxc_pwrseq_regs_t</a>
-</li>
 <li>gpio0
 : <a class="el" href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">mxc_rpu_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_vars_i.html b/lib/sdk/Documentation/html/functions_vars_i.html
index 246ba6bb8d35e8b48649ac21befbf92575576457..2de9816e3d1e32a384c3b467e0664b86a10330a6 100644
--- a/lib/sdk/Documentation/html/functions_vars_i.html
+++ b/lib/sdk/Documentation/html/functions_vars_i.html
@@ -70,30 +70,27 @@ $(document).ready(function(){initNavTree('functions_vars_i.html','');});
 &#160;
 
 <h3><a id="index_i"></a>- i -</h3><ul>
-<li>i2c0
-: <a class="el" href="structmxc__rpu__regs__t.html#a67f843cf68d636443ee57ce3133fbd12">mxc_rpu_regs_t</a>
+<li>i2c0_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#aee54ba2b716b8ec8eb511d6d7dee57a1">mxc_rpu_regs_t</a>
 </li>
-<li>i2c1
-: <a class="el" href="structmxc__rpu__regs__t.html#a05e9a4140c71fdab6518205e023c6313">mxc_rpu_regs_t</a>
+<li>i2c1_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#ae1f643fe22f713dc8f1345ac2582a628">mxc_rpu_regs_t</a>
 </li>
-<li>i2c2
-: <a class="el" href="structmxc__rpu__regs__t.html#ab2184b645146cece7001515e57b190ad">mxc_rpu_regs_t</a>
+<li>i2c2_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#a46f94aa32bf20f1306dd0b30bad69ec6">mxc_rpu_regs_t</a>
 </li>
-<li>i2s_ctrl
-: <a class="el" href="structmxc__spixr__regs__t.html#a90608b29b3f3212205facf083fc3864e">mxc_spixr_regs_t</a>
+<li>icc0
+: <a class="el" href="structmxc__rpu__regs__t.html#a4f719bdddec9869dc1226debe906860d">mxc_rpu_regs_t</a>
 </li>
-<li>icache0
-: <a class="el" href="structmxc__rpu__regs__t.html#a3f3c752957bc9e467f5c9d2e831f555f">mxc_rpu_regs_t</a>
-</li>
-<li>icache1
-: <a class="el" href="structmxc__rpu__regs__t.html#a58cadc3c2770b44b7ebfa6c5f55635bd">mxc_rpu_regs_t</a>
-</li>
-<li>icachexip
-: <a class="el" href="structmxc__rpu__regs__t.html#a0214735f8b048f0386a35b3db6832bb1">mxc_rpu_regs_t</a>
+<li>icc1
+: <a class="el" href="structmxc__rpu__regs__t.html#aafa4124620f7faaef5a033b4309be329">mxc_rpu_regs_t</a>
 </li>
 <li>in
 : <a class="el" href="structmxc__gpio__regs__t.html#a0e9363bc6e34884e294f55287d764399">mxc_gpio_regs_t</a>
 </li>
+<li>in_en
+: <a class="el" href="structmxc__gpio__regs__t.html#aa6c384a08f486469b6aa1868f8ef4720">mxc_gpio_regs_t</a>
+</li>
 <li>int_clr
 : <a class="el" href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">mxc_gpio_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/functions_vars_l.html b/lib/sdk/Documentation/html/functions_vars_l.html
index 8d84db545baf6d98752869d36191e8b1b2f624a4..2da3b3c7f3998a96744a5709215c4052d4c16bb2 100644
--- a/lib/sdk/Documentation/html/functions_vars_l.html
+++ b/lib/sdk/Documentation/html/functions_vars_l.html
@@ -92,12 +92,6 @@ $(document).ready(function(){initNavTree('functions_vars_l.html','');});
 <li>lpcn
 : <a class="el" href="structmxc__pwrseq__regs__t.html#acda7cefaab59b1351d543490c7de08fd">mxc_pwrseq_regs_t</a>
 </li>
-<li>lpmcreq
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a28f6161d913462e38ed382f10c8f38e6">mxc_pwrseq_regs_t</a>
-</li>
-<li>lpmcstat
-: <a class="el" href="structmxc__pwrseq__regs__t.html#ad3f173b5c522262557112a4a871643ce">mxc_pwrseq_regs_t</a>
-</li>
 <li>lpmemsd
 : <a class="el" href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">mxc_pwrseq_regs_t</a>
 </li>
@@ -116,24 +110,12 @@ $(document).ready(function(){initNavTree('functions_vars_l.html','');});
 <li>lpwken1
 : <a class="el" href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">mxc_pwrseq_regs_t</a>
 </li>
-<li>lpwken2
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a94c29a74efad6c3cebe1f55110b52e61">mxc_pwrseq_regs_t</a>
-</li>
-<li>lpwken3
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a0c14230a8bd930a7d6fb6a20f9453711">mxc_pwrseq_regs_t</a>
-</li>
 <li>lpwkst0
 : <a class="el" href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">mxc_pwrseq_regs_t</a>
 </li>
 <li>lpwkst1
 : <a class="el" href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">mxc_pwrseq_regs_t</a>
 </li>
-<li>lpwkst2
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a6e78094b2c983a37535445dd946d9e59">mxc_pwrseq_regs_t</a>
-</li>
-<li>lpwkst3
-: <a class="el" href="structmxc__pwrseq__regs__t.html#a846955a96142e1e7564aa77214f25a04">mxc_pwrseq_regs_t</a>
-</li>
 </ul>
 </div><!-- contents -->
 </div><!-- doc-content -->
diff --git a/lib/sdk/Documentation/html/functions_vars_m.html b/lib/sdk/Documentation/html/functions_vars_m.html
index 552befd958ce5567c67038e4152d3e6fcc21d90f..81cd29a7e3c5fe7763894a91aca331ea18075f7a 100644
--- a/lib/sdk/Documentation/html/functions_vars_m.html
+++ b/lib/sdk/Documentation/html/functions_vars_m.html
@@ -85,6 +85,9 @@ $(document).ready(function(){initNavTree('functions_vars_m.html','');});
 <li>max_curr_cfg
 : <a class="el" href="structmxc__sdhc__regs__t.html#a3ca2d1f1a83ae4f8ef6c0e02c9a9eae3">mxc_sdhc_regs_t</a>
 </li>
+<li>mcr
+: <a class="el" href="structmxc__rpu__regs__t.html#a171cf0c62b66f6b04ee8ff99ee230ba1">mxc_rpu_regs_t</a>
+</li>
 <li>memcfg
 : <a class="el" href="structmxc__emcc__regs__t.html#a1919b3c0d53f9485fe762b201c4c6bf1">mxc_emcc_regs_t</a>
 , <a class="el" href="structmxc__icc__regs__t.html#a5893df1d78d78b98e1f8e80bf9a499a1">mxc_icc_regs_t</a>
diff --git a/lib/sdk/Documentation/html/functions_vars_p.html b/lib/sdk/Documentation/html/functions_vars_p.html
index c9b0378548036e2392a4f5d5681a833b04829ec3..d84f725ec69906c5f7d3dabba1b770cbe6f6cbd3 100644
--- a/lib/sdk/Documentation/html/functions_vars_p.html
+++ b/lib/sdk/Documentation/html/functions_vars_p.html
@@ -122,8 +122,8 @@ $(document).ready(function(){initNavTree('functions_vars_p.html','');});
 <li>ps
 : <a class="el" href="structmxc__gpio__regs__t.html#a2ebe119356fa75bd745984ae2bf71494">mxc_gpio_regs_t</a>
 </li>
-<li>pt
-: <a class="el" href="structmxc__rpu__regs__t.html#a8c9edc39d61f24c7df1c403a4a1b9e78">mxc_rpu_regs_t</a>
+<li>ptg_bus0
+: <a class="el" href="structmxc__rpu__regs__t.html#a7cf24cf377876560e35ce321484cf3a4">mxc_rpu_regs_t</a>
 </li>
 <li>ptLength
 : <a class="el" href="structpt__pt__cfg__t.html#ae559465ca17078f68e10d8aa12db493a">pt_pt_cfg_t</a>
diff --git a/lib/sdk/Documentation/html/functions_vars_r.html b/lib/sdk/Documentation/html/functions_vars_r.html
index 3326da706d4741d02ebdde4582bf561a11ef3a36..bab7fea9146e2ce2db628debeae83f75b5033c9b 100644
--- a/lib/sdk/Documentation/html/functions_vars_r.html
+++ b/lib/sdk/Documentation/html/functions_vars_r.html
@@ -72,7 +72,6 @@ $(document).ready(function(){initNavTree('functions_vars_r.html','');});
 <h3><a id="index_r"></a>- r -</h3><ul>
 <li>ras
 : <a class="el" href="structmxc__htmr__regs__t.html#aee1617647a48af22d7f0b9eca3b04200">mxc_htmr_regs_t</a>
-, <a class="el" href="structmxc__rtc__regs__t.html#a312f52a6335fbc5d1bfab003689e725f">mxc_rtc_regs_t</a>
 </li>
 <li>rate_length
 : <a class="el" href="structmxc__pt__regs__t.html#a1c1d3f13299e64ab71e2a25dc8e1f967">mxc_pt_regs_t</a>
@@ -89,7 +88,6 @@ $(document).ready(function(){initNavTree('functions_vars_r.html','');});
 </li>
 <li>rssa
 : <a class="el" href="structmxc__htmr__regs__t.html#a47538fa66454bc9621f7478438919ca3">mxc_htmr_regs_t</a>
-, <a class="el" href="structmxc__rtc__regs__t.html#a0227333293ec30e21fa6663eb80d6ac7">mxc_rtc_regs_t</a>
 </li>
 <li>rst
 : <a class="el" href="structmxc__wdt__regs__t.html#a6f54c7641e7e68bafaf287c4954f386b">mxc_wdt_regs_t</a>
diff --git a/lib/sdk/Documentation/html/functions_vars_s.html b/lib/sdk/Documentation/html/functions_vars_s.html
index 0ca77e61915f251ee6f5def7c52f277cb7b20380..4e882fe3c73437af48976beff40ae71254f714bd 100644
--- a/lib/sdk/Documentation/html/functions_vars_s.html
+++ b/lib/sdk/Documentation/html/functions_vars_s.html
@@ -94,6 +94,9 @@ $(document).ready(function(){initNavTree('functions_vars_s.html','');});
 <li>semaphores
 : <a class="el" href="structmxc__sema__regs__t.html#a7707db84b6a52bf6a2141a321e90bb17">mxc_sema_regs_t</a>
 </li>
+<li>sfcc
+: <a class="el" href="structmxc__rpu__regs__t.html#a8080c2b6a8f3a34c04a83d4255e96b61">mxc_rpu_regs_t</a>
+</li>
 <li>shared_bus
 : <a class="el" href="structmxc__sdhc__regs__t.html#a358719de16d4f7765bd5f96192c9176e">mxc_sdhc_regs_t</a>
 </li>
@@ -118,41 +121,29 @@ $(document).ready(function(){initNavTree('functions_vars_s.html','');});
 <li>spctrl
 : <a class="el" href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">mxc_spixfc_regs_t</a>
 </li>
-<li>spid
-: <a class="el" href="structmxc__rpu__regs__t.html#a107ce59e766452ddd16ba0c679c756c7">mxc_rpu_regs_t</a>
-</li>
-<li>spixipm
-: <a class="el" href="structmxc__rpu__regs__t.html#acd8b09dccd4281e8fa47a3f690e0c287">mxc_rpu_regs_t</a>
-</li>
-<li>spixipmc
-: <a class="el" href="structmxc__rpu__regs__t.html#a835774853a29501e6a1f750d5a57956c">mxc_rpu_regs_t</a>
+<li>spi0
+: <a class="el" href="structmxc__rpu__regs__t.html#ab3363e181a7630bc3d3201eb3b879dfa">mxc_rpu_regs_t</a>
 </li>
-<li>spixipmfifo
-: <a class="el" href="structmxc__rpu__regs__t.html#ab79390483fc759b36c1492da84c39142">mxc_rpu_regs_t</a>
+<li>spi1
+: <a class="el" href="structmxc__rpu__regs__t.html#a6a8f3593c33e8e2a2c07ed8389670108">mxc_rpu_regs_t</a>
 </li>
-<li>sr
-: <a class="el" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">mxc_gpio_regs_t</a>
+<li>spi2
+: <a class="el" href="structmxc__rpu__regs__t.html#aa617d084516acc758d283a33deed9a38">mxc_rpu_regs_t</a>
 </li>
-<li>sram0
-: <a class="el" href="structmxc__rpu__regs__t.html#a73401214b554adea90654ae4ee9e441a">mxc_rpu_regs_t</a>
+<li>spixfc
+: <a class="el" href="structmxc__rpu__regs__t.html#a938e8c511fe710606bb950a76477b9a2">mxc_rpu_regs_t</a>
 </li>
-<li>sram1
-: <a class="el" href="structmxc__rpu__regs__t.html#af36206f67702f1598a065ceacb42ed76">mxc_rpu_regs_t</a>
+<li>spixfm
+: <a class="el" href="structmxc__rpu__regs__t.html#a0fa6182dc552923bce9dcbf52de361a3">mxc_rpu_regs_t</a>
 </li>
-<li>sram2
-: <a class="el" href="structmxc__rpu__regs__t.html#ae1d1de4f98df3b2171e9635b742376d1">mxc_rpu_regs_t</a>
+<li>spixm_fifo
+: <a class="el" href="structmxc__rpu__regs__t.html#aa66553c7c4c2ff2a65e176af948e6399">mxc_rpu_regs_t</a>
 </li>
-<li>sram3
-: <a class="el" href="structmxc__rpu__regs__t.html#ac31f8fe960e70e7f63a3e9b355204150">mxc_rpu_regs_t</a>
+<li>spixr
+: <a class="el" href="structmxc__rpu__regs__t.html#a493a625cf6437fc4ea51aeb6433d377b">mxc_rpu_regs_t</a>
 </li>
-<li>sram4
-: <a class="el" href="structmxc__rpu__regs__t.html#afce0eed072aa6ea690e311ea03098e96">mxc_rpu_regs_t</a>
-</li>
-<li>sram5
-: <a class="el" href="structmxc__rpu__regs__t.html#a7f226e3d43e02fcba1bbe3c75b8818dd">mxc_rpu_regs_t</a>
-</li>
-<li>sram6
-: <a class="el" href="structmxc__rpu__regs__t.html#a66156e610712dd5d497ea9cc69c82b7d">mxc_rpu_regs_t</a>
+<li>sr
+: <a class="el" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">mxc_gpio_regs_t</a>
 </li>
 <li>src
 : <a class="el" href="structmxc__dma__ch__regs__t.html#a892f57a64656deca7c61e76fc5806423">mxc_dma_ch_regs_t</a>
@@ -160,6 +151,9 @@ $(document).ready(function(){initNavTree('functions_vars_s.html','');});
 <li>src_rld
 : <a class="el" href="structmxc__dma__ch__regs__t.html#a90a232c419b3b32ae4849761d31fe9df">mxc_dma_ch_regs_t</a>
 </li>
+<li>srcc
+: <a class="el" href="structmxc__rpu__regs__t.html#ace3ea78cbad80bfeca273e59f9f7b9c1">mxc_rpu_regs_t</a>
+</li>
 <li>ss_pol
 : <a class="el" href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">mxc_spixfc_regs_t</a>
 </li>
@@ -170,6 +164,9 @@ $(document).ready(function(){initNavTree('functions_vars_s.html','');});
 : <a class="el" href="structmxc__htmr__regs__t.html#ab7d391aa538691e380b9162726395d4a">mxc_htmr_regs_t</a>
 , <a class="el" href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">mxc_rtc_regs_t</a>
 </li>
+<li>sseca
+: <a class="el" href="structmxc__rtc__regs__t.html#a5b608ffa87981e34088b40bada72144e">mxc_rtc_regs_t</a>
+</li>
 <li>ssel
 : <a class="el" href="structspi17y__req.html#a72a31cb80122e910c9ea82da1fc41b1f">spi17y_req_t</a>
 , <a class="el" href="structspi__req.html#af8cbfde9101e93efd08e104a478febce">spi_req_t</a>
@@ -216,6 +213,27 @@ $(document).ready(function(){initNavTree('functions_vars_s.html','');});
 <li>sw_reset
 : <a class="el" href="structmxc__sdhc__regs__t.html#a4f574c19965cc110393f87fd1a22f5fc">mxc_sdhc_regs_t</a>
 </li>
+<li>sysram0
+: <a class="el" href="structmxc__rpu__regs__t.html#a326ba0b5ed008b242db40e9ab75500bc">mxc_rpu_regs_t</a>
+</li>
+<li>sysram1
+: <a class="el" href="structmxc__rpu__regs__t.html#acf032f7d78b6532dd6ad36ba8443a121">mxc_rpu_regs_t</a>
+</li>
+<li>sysram2
+: <a class="el" href="structmxc__rpu__regs__t.html#a3d15538d060546e2f115288d3a9ab709">mxc_rpu_regs_t</a>
+</li>
+<li>sysram3
+: <a class="el" href="structmxc__rpu__regs__t.html#a33efdc41a5dab826941aff9e4ee47d0d">mxc_rpu_regs_t</a>
+</li>
+<li>sysram4
+: <a class="el" href="structmxc__rpu__regs__t.html#a70722dd45c3732d6e3d827e46e722c39">mxc_rpu_regs_t</a>
+</li>
+<li>sysram5
+: <a class="el" href="structmxc__rpu__regs__t.html#a26e3639950f8bd188d066afec39d2bfe">mxc_rpu_regs_t</a>
+</li>
+<li>sysram6
+: <a class="el" href="structmxc__rpu__regs__t.html#a086921af8001fdf0d9af8935b068f865">mxc_rpu_regs_t</a>
+</li>
 </ul>
 </div><!-- contents -->
 </div><!-- doc-content -->
diff --git a/lib/sdk/Documentation/html/functions_vars_t.html b/lib/sdk/Documentation/html/functions_vars_t.html
index 33a9156bd010b62baa38311582afbb42e6052794..c3bc423b63f6c64f1234559e6e25807e5b160c92 100644
--- a/lib/sdk/Documentation/html/functions_vars_t.html
+++ b/lib/sdk/Documentation/html/functions_vars_t.html
@@ -97,6 +97,9 @@ $(document).ready(function(){initNavTree('functions_vars_t.html','');});
 <li>to
 : <a class="el" href="structmxc__sdhc__regs__t.html#a02e7f138ca6346b494b40c7c6901f615">mxc_sdhc_regs_t</a>
 </li>
+<li>toda
+: <a class="el" href="structmxc__rtc__regs__t.html#ad4a4f5073aea7dcc1a623e0b7e3ca3a5">mxc_rtc_regs_t</a>
+</li>
 <li>train
 : <a class="el" href="structmxc__pt__regs__t.html#a0eb87145bab2b61825026fb5d955d264">mxc_pt_regs_t</a>
 </li>
diff --git a/lib/sdk/Documentation/html/gpio__regs_8h_source.html b/lib/sdk/Documentation/html/gpio__regs_8h_source.html
index dd0237cbfdd5e06362b47566674e7b5dc4ca2099..c4cacf6e9abf5148e00cf5dd1d8ab7e85915499b 100644
--- a/lib/sdk/Documentation/html/gpio__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/gpio__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('gpio__regs_8h_source.html','');});
 <div class="title">gpio_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _GPIO_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _GPIO_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a12ebf0d620fc9bcd0e7a04bb0eb87095">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a12ebf0d620fc9bcd0e7a04bb0eb87095">en</a>;                   </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a19920be0077d7e457fd8f78e592e8ee7">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a19920be0077d7e457fd8f78e592e8ee7">en_set</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a09c244fbc1eb2b68000e3446c9da7092">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a09c244fbc1eb2b68000e3446c9da7092">en_clr</a>;               </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a59397d720eb460fad58c573a8f863e07">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a59397d720eb460fad58c573a8f863e07">out_en</a>;               </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aee2936a5c5dedb62edcb74445f45dad5">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aee2936a5c5dedb62edcb74445f45dad5">out_en_set</a>;           </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae602770bef6e294d047a2ee7975e25d0">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae602770bef6e294d047a2ee7975e25d0">out_en_clr</a>;           </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a569d1b15db75f25b605a0e31b4af24f1">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a569d1b15db75f25b605a0e31b4af24f1">out</a>;                  </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae8eb843fcc4aa762cdd6daf467ca1ab5">   96</a></span>&#160;    __O  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae8eb843fcc4aa762cdd6daf467ca1ab5">out_set</a>;              </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a28fac16f51d6c2bdba3a56f058bc1a09">   97</a></span>&#160;    __O  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a28fac16f51d6c2bdba3a56f058bc1a09">out_clr</a>;              </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a0e9363bc6e34884e294f55287d764399">   98</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a0e9363bc6e34884e294f55287d764399">in</a>;                   </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#af79908b309ce0db975d2fc86f715df03">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#af79908b309ce0db975d2fc86f715df03">int_mod</a>;              </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a4f913ed090f662fe8b65860c2937faff">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a4f913ed090f662fe8b65860c2937faff">int_pol</a>;              </div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    __R  uint32_t rsv_0x30;</div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ab7bb644b9ff7da05df3addd6884b90c1">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ab7bb644b9ff7da05df3addd6884b90c1">int_en</a>;               </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a9612ed1d0d8919844ace750f947844f2">  103</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a9612ed1d0d8919844ace750f947844f2">int_en_set</a>;           </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a40c3185a68d40c6f23acba1f722b98c2">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a40c3185a68d40c6f23acba1f722b98c2">int_en_clr</a>;           </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aafca04b07b05f384110bad47f03a11c5">  105</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aafca04b07b05f384110bad47f03a11c5">int_stat</a>;             </div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;    __R  uint32_t rsv_0x44;</div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">int_clr</a>;              </div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a3628e36093e2b9e7653a9d6dc9e0a767">  108</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a3628e36093e2b9e7653a9d6dc9e0a767">wake_en</a>;              </div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aabdf76d86254e27c51d49674ec34a97d">  109</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aabdf76d86254e27c51d49674ec34a97d">wake_en_set</a>;          </div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a59981dba0d003b2d1869a2e9583fb5ea">  110</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a59981dba0d003b2d1869a2e9583fb5ea">wake_en_clr</a>;          </div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    __R  uint32_t rsv_0x58;</div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae38ef1bb1b50e0c44a0b179d004e401c">  112</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae38ef1bb1b50e0c44a0b179d004e401c">int_dual_edge</a>;        </div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#af170c398f4cdc87c8b2c4cd6f0c135da">  113</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#af170c398f4cdc87c8b2c4cd6f0c135da">pad_cfg1</a>;             </div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae9a085f22f1e2aa41ce4fcb606a55327">  114</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae9a085f22f1e2aa41ce4fcb606a55327">pad_cfg2</a>;             </div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a1be455cc78ca47c12031e924be841be3">  115</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a1be455cc78ca47c12031e924be841be3">en1</a>;                  </div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ab4dc84cfaccce1a45dddf48ae55541b9">  116</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ab4dc84cfaccce1a45dddf48ae55541b9">en1_set</a>;              </div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a5530f6655cb11931921d527b2d97ce82">  117</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a5530f6655cb11931921d527b2d97ce82">en1_clr</a>;              </div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a1bf54ff6d19358935cae207fb30f78b9">  118</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a1bf54ff6d19358935cae207fb30f78b9">en2</a>;                  </div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#abf8c5a5c842a4c07c023d218a3e3c16d">  119</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#abf8c5a5c842a4c07c023d218a3e3c16d">en2_set</a>;              </div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae3fee91062860fb154b6056ea2d184d4">  120</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae3fee91062860fb154b6056ea2d184d4">en2_clr</a>;              </div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    __R  uint32_t rsv_0x80_0xa7[10];</div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#af63c0f10e0d2dd9723a7a6de899c33ec">  122</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#af63c0f10e0d2dd9723a7a6de899c33ec">is</a>;                   </div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">  123</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">sr</a>;                   </div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aa1416bcf0a3a68c007b167e0ac79ae9d">  124</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aa1416bcf0a3a68c007b167e0ac79ae9d">ds</a>;                   </div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a91168a379332b56f62afa1c690beb379">  125</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a91168a379332b56f62afa1c690beb379">ds1</a>;                  </div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a2ebe119356fa75bd745984ae2bf71494">  126</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a2ebe119356fa75bd745984ae2bf71494">ps</a>;                   </div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    __R  uint32_t rsv_0xbc;</div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a98fbb84df6f74baff23d056a526c1ec4">  128</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a98fbb84df6f74baff23d056a526c1ec4">vssel</a>;                </div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;} <a class="code" href="structmxc__gpio__regs__t.html">mxc_gpio_regs_t</a>;</div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;<span class="comment">/* Register offsets for module GPIO */</span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga2dd795d5dc058c4442a19bd7cf1c7a9d">  138</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gadb9cc9cd4c0a8a962581db3d8a324e22">  139</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN_SET                  ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaac082442a39bb364e9b2facef607e87d">  140</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN_CLR                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga39abe8ea9c9cca4c36569e24c1c1a955">  141</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_EN                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaca62cc1d87cd41857e1c64cc0af54a2f">  142</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_EN_SET              ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga69be75eb84cc5e5c86534aa6c69c27ce">  143</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_EN_CLR              ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gacedd52f61c661de1cfdb2ec550ce0f2b">  144</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT                     ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gab4c80b1e1d756c951150c4c3d92fc10c">  145</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_SET                 ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gab8d0414874e7a723126cb452a0e0eec4">  146</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_CLR                 ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gadd058220f09d4fa558eae6aa2577d210">  147</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_IN                      ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga461cba15ab8c92c8d3733baca4805220">  148</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_MOD                 ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf45e24dff8f4c63869c98683ffe3f7f1">  149</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_POL                 ((uint32_t)0x0000002CUL) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga8e43896a7dae653d606fc1b6ceae8d1e">  150</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_EN                  ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gae49adb067d0f0cbcfa1e617f849d2839">  151</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_EN_SET              ((uint32_t)0x00000038UL) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga2085b59188ee0fc2b18aea73712b1f4a">  152</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_EN_CLR              ((uint32_t)0x0000003CUL) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga568051a18cfeb923dd66174577d7e484">  153</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_STAT                ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga4e1bb5efe2d55931ad066985c5a5ff69">  154</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_CLR                 ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaed5b341948ea5cb2e0a15890c698ede4">  155</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_WAKE_EN                 ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga872c82d804151dff57ae7b282471af68">  156</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_WAKE_EN_SET             ((uint32_t)0x00000050UL) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf93f122a8219b17479517bed53af0bdc">  157</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_WAKE_EN_CLR             ((uint32_t)0x00000054UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga8622f35f7d89141d2dbc4f18ef4e14b9">  158</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_DUAL_EDGE           ((uint32_t)0x0000005CUL) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga78f781b3f1f6b801340682e4755405a5">  159</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_PAD_CFG1                ((uint32_t)0x00000060UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga2ff3ae3085625507996679a05995b33f">  160</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_PAD_CFG2                ((uint32_t)0x00000064UL) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga1cabc6e94d9c034f093e99e2b52e4ad8">  161</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN1                     ((uint32_t)0x00000068UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga3cec9b7df9db083d4ca600a559357f24">  162</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN1_SET                 ((uint32_t)0x0000006CUL) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf73912b8ff595ba2b536a8ccac988d01">  163</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN1_CLR                 ((uint32_t)0x00000070UL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf35a746852595cd4ea1cfd05fae65928">  164</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN2                     ((uint32_t)0x00000074UL) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga282b023aa645fde7e8d3d0ae9ba14987">  165</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN2_SET                 ((uint32_t)0x00000078UL) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gab238e38f894983e5bdad185644a12c07">  166</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN2_CLR                 ((uint32_t)0x0000007CUL) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga4fdeb971ffcaaa861b1c5fab91f0deb0">  167</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_IS                      ((uint32_t)0x000000A8UL) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga5bfd98d3e6944feca7d78f2960b4fdd2">  168</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_SR                      ((uint32_t)0x000000ACUL) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga184787ed50ed8cfa3486b70993128a83">  169</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_DS                      ((uint32_t)0x000000B0UL) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gad5ad180e0488ac0597b2416ae0f6801e">  170</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_DS1                     ((uint32_t)0x000000B4UL) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga3f5e991f9954a9be74d40e3d41707266">  171</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_PS                      ((uint32_t)0x000000B8UL) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga263d5b2fe4fa353b8ca726894799497d">  172</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_VSSEL                   ((uint32_t)0x000000C0UL) </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga6d74c8fc1b9a28951219d8fab67d678b">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_GPIO_EN_POS                      0 </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga07c4593df5b48749f882b942164fb3b5">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_GPIO_EN                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN_GPIO_EN_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga10df8f1950aa07d835162dbaa2f543b4">  184</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#gab6a71028094ab09633528827f4a206c7">  185</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE &lt;&lt; MXC_F_GPIO_EN_GPIO_EN_POS) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga70ce7650a26b935cae6b4f5dbeb27b14">  186</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN_GPIO_EN_GPIO                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga2168d84c4b49c7ec0656b34f43d6ac6b">  187</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN_GPIO_EN_GPIO                     (MXC_V_GPIO_EN_GPIO_EN_GPIO &lt;&lt; MXC_F_GPIO_EN_GPIO_EN_POS) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__GPIO__EN__SET.html#ga16b03ea3c606ef96936359a9952bc7e2">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_SET_ALL_POS                      0 </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__GPIO__EN__SET.html#ga6e56867c905a3fb419ac159fc808c226">  200</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_SET_ALL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN_SET_ALL_POS)) </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__GPIO__EN__CLR.html#ga0a04a27dd2f9316d31eecae25ab1bdf7">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_CLR_ALL_POS                      0 </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__GPIO__EN__CLR.html#gaa7485e96a347bbad9afece88d32d5756">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_CLR_ALL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN_CLR_ALL_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga2fdeff86005b15b94ac6a18c356cb771">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS              0 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga128fd3b7e7444ae5cf4eced2dee7e718">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                  ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga1ac90f34f16339f706636d6e5d3e9a27">  226</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga33a93366522841a6a88c08b8a14fd977">  227</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS              (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS &lt;&lt; MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga2c1a12174106b1b519fb63846126b4a1">  228</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#gaf5b5c65a8d501bdd16dbf1a131ebe9d5">  229</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN               (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN &lt;&lt; MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__SET.html#ga2a7c400a761a556004a55effc2837194">  241</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_SET_ALL_POS                  0 </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__SET.html#gafa2051418d43e8e4c41163ca47037fa7">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_SET_ALL                      ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_EN_SET_ALL_POS)) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__CLR.html#ga9c7529dd79ed64a1918e29cc9fa79e28">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS                  0 </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__CLR.html#ga03a375e71717b9f4fb8fd990bcee2b0b">  255</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_CLR_ALL                      ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#gac4fab39a1a698b572f8d168ce195a7b0">  267</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_GPIO_OUT_POS                    0 </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga6c818e902ab9cc94006b0d8e854ac83c">  268</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_GPIO_OUT                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_GPIO_OUT_POS)) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga49c5cb2a9bea00ef5c93f8e0d1181341">  269</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_GPIO_OUT_LOW                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga942cbf531303a8a158225a34ea6a31a2">  270</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_GPIO_OUT_LOW                    (MXC_V_GPIO_OUT_GPIO_OUT_LOW &lt;&lt; MXC_F_GPIO_OUT_GPIO_OUT_POS) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#gac39c2062974b8158195592699626e109">  271</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga9d390b39684e0cafbaf219c0f1a97261">  272</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                   (MXC_V_GPIO_OUT_GPIO_OUT_HIGH &lt;&lt; MXC_F_GPIO_OUT_GPIO_OUT_POS) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#gaa82f721e63b00f2f41f4934c86484297">  284</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS            0 </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga5a9cc6a352f23b5977dc0c231424742c">  285</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga2cf923a86445b99706c58de44a71221b">  286</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO             ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga0f9bbb99248d10768ce95b527f5e2f47">  287</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO             (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO &lt;&lt; MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga8374c6d6ca12d6ccec1084a45b66372a">  288</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga350556688902ab8d7e91f0f8bdb39701">  289</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET            (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET &lt;&lt; MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__CLR.html#gaea49754bc59ac193ee602547333d0733">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS            0 </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__CLR.html#ga34be6b2874b6a6c8bfc01185e3583a12">  302</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__GPIO__IN.html#ga0e6c50f7f11dde5324b45d67f113c0cb">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_IN_GPIO_IN_POS                      0 </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__GPIO__IN.html#ga7a8581225a93489013e9f7b8461659e3">  314</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_IN_GPIO_IN                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_IN_GPIO_IN_POS)) </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga0a2221eeab673daaabcd7b63866aab7e">  325</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS            0 </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga6f418867dcc872f03b7d73decfdad1dd">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga4d1d091bcd110dad604c62a909485695">  327</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL          ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga40c1f7e6be9b8f30018d98c69ec831ad">  328</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL          (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL &lt;&lt; MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#gae8c514db9902542799fd5ecda19c997a">  329</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga645c827ad58cf81a6679c12319e7aaf0">  330</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE           (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE &lt;&lt; MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gaf7642a4e46009fb784b10a5b5ed9323f">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS            0 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gaed925beb749458f2b39448721525758c">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_POL_GPIO_INT_POL                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#ga5573663abbd9dcab76d3bcd30cfbb10a">  343</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gab365d25bafd5f200e171292be98acb82">  344</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING        (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING &lt;&lt; MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gab2cf1b7bbc7c088eaa3bba0b00297d46">  345</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING         ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#ga339580e5912389cbbe0de2818a3781b5">  346</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING         (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING &lt;&lt; MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) </span></div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#gab9600d31b81f25d1097809c22bb0a754">  357</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS              0 </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#gabc277cf79371a75eaaecbc41a7793355">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_GPIO_INT_EN                  ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#ga7cf45430acd0def6b5bacfaf7694c04e">  359</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#ga47d53db9b65138db6de6eae593d63f06">  360</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS              (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS &lt;&lt; MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#ga2e4fd708b7eb3f52797d0cc194794663">  361</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#gab37a3fef5ee5cb3a378cf9957c94d6c0">  362</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN               (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN &lt;&lt; MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#gacecfa7f7ded9473ee9d4c2b21ac66836">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS      0 </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#gaf292bd963c3b83708f565a835a121962">  375</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga3315651bea00d1fb49355b2a12a1abd4">  376</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga9bfca6180d6bd4fb672fb887cdf938a6">  377</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO       (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO &lt;&lt; MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga030fc5712481ba967818df90c32382e4">  378</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga04b91301fae7574614fb105fef7806c7">  379</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET      (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET &lt;&lt; MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#gaef43aa0436a24603edd3d8cb00a31dbf">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS      0 </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga11fff0baf6506d123f56c7e896145a87">  392</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga34eb73b689d0fa3d8c61b89b99aeb9de">  393</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga4ea55c1e91914e348e26e7fceb38877e">  394</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO       (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO &lt;&lt; MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga51f34696244b971a31ea29bb2b223b44">  395</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga822f66f49a20ea6c09dad7111ef75967">  396</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR    (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR &lt;&lt; MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) </span></div><div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#ga4a8896dc4ff31fcb30da5f5786f9ac1c">  407</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS          0 </span></div><div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#ga4d187137bc92866c6f44d40c0461585e">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gaf4d8ab951557571cb797b709ce85a2be">  409</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO           ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gaa39d8238bcdb20670a9b4366f5ed2c70">  410</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO           (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO &lt;&lt; MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gab8b0dbf75669f89c7608d89a39e61076">  411</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gac09f0f3897bbaa498d35c5f2f9b4a711">  412</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING      (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING &lt;&lt; MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group__GPIO__INT__CLR.html#gad3cc3472d76c5858672b7ebbe1dfc1c2">  424</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_CLR_ALL_POS                     0 </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__GPIO__INT__CLR.html#ga634a5b77fbb0d3f9e07193cb88f05a4a">  425</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_CLR_ALL_POS)) </span></div><div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga5f1e01a7c85aac4c7bcf47fe73035a5d">  436</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS            0 </span></div><div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga11c66804493d7552a082b6649e2d8d24">  437</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga4c4b3f87ac89adc1be55663ebda38b6c">  438</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga6d0186952c5df60dc25f3efc6734b4e0">  439</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS            (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS &lt;&lt; MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga72b884817720a5cc27a01561b37d9712">  440</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN             ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#gafc48f2b7bb177640b2781324d548e2f5">  441</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN             (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN &lt;&lt; MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) </span></div><div class="line"><a name="l00453"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__SET.html#ga9a13f6b748e559fd3d668cb5c09aecc2">  453</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS                 0 </span></div><div class="line"><a name="l00454"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__SET.html#ga6898b0b326604fe29415ce288d75c523">  454</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_SET_ALL                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) </span></div><div class="line"><a name="l00466"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__CLR.html#gae9159c8dcd944cde538b4f1e4e113652">  466</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS                 0 </span></div><div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__CLR.html#gafbb2fa7c72ff5f1abcfc97654951822a">  467</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_CLR_ALL                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) </span></div><div class="line"><a name="l00478"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gad858c9975958376ca05f4fa61799f616">  478</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 </span></div><div class="line"><a name="l00479"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#ga2da4065b2dda907deb9d2667e6a563d5">  479</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE    ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) </span></div><div class="line"><a name="l00480"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#ga5cb1e1b246cf12d4968482dee154c410">  480</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00481"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gabda1d70e4894aa5f1b9fbf92feeb5ee3">  481</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO &lt;&lt; MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) </span></div><div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gaed5912f5f7bfe2c2f5e339fdf43a58bc">  482</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00483"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gaed4cde596d35ae9786dbe415d012ffdd">  483</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN &lt;&lt; MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) </span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gad4671a3f371a3db59678c6f16f3aa8c5">  494</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS          0 </span></div><div class="line"><a name="l00495"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaf9e5a6dde9cbd513f83aefba8cf53233">  495</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaaa020b93dd5e46076681100e038fd911">  496</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaee891e0f74869b758125258a55cd302f">  497</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE    (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) </span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaddd398bb6aa717551c399f842a72a8d5">  498</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#ga9190ed585baa7004268155e47c28c905">  499</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU           (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) </span></div><div class="line"><a name="l00500"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#ga9016649c2d5b21dc37dc95e6b710743e">  500</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00501"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gac2a8618b03ff8a0afe93d2792d3601c3">  501</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD           (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) </span></div><div class="line"><a name="l00512"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#gab4347447d3eadf3f7d0bee8cb0bb1788">  512</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS          0 </span></div><div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga19088390b32000b948fb91417ffdb64e">  513</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) </span></div><div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga33c73392b6ee368ab525d91a563a0793">  514</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00515"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga17593381b2dd30d9f08c1abcc58217e2">  515</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE    (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) </span></div><div class="line"><a name="l00516"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga4c4b433a72c072489cd7fc0a7007e879">  516</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga740b6a4a77b5db8b17fffa69d9499d47">  517</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU           (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) </span></div><div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga6cf9a09a68785d37b9b16c9a9267a0d2">  518</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00519"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#gacd073c4f4f7cc39455e4cf29230a7d8a">  519</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD           (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#gae2c3e728533d5dcff875dd3b3a8eeac7">  530</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_GPIO_EN1_POS                    0 </span></div><div class="line"><a name="l00531"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga3724a944f84a049facb97bf25593e6c2">  531</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_GPIO_EN1                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN1_GPIO_EN1_POS)) </span></div><div class="line"><a name="l00532"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga41d28569d92c7a59cd54f2c7e4155fb6">  532</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#gac7a8f2fbf52f510db22b99c77184cd47">  533</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY &lt;&lt; MXC_F_GPIO_EN1_GPIO_EN1_POS) </span></div><div class="line"><a name="l00534"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga5c8a103328700fcf1d0c0fd9b4a9acad">  534</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga489775d0dea2907ac3e4d0dcdf7b2eca">  535</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY              (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY &lt;&lt; MXC_F_GPIO_EN1_GPIO_EN1_POS) </span></div><div class="line"><a name="l00547"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__SET.html#ga582e5b6339fd338628b4c8a8e653fb26">  547</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_SET_ALL_POS                     0 </span></div><div class="line"><a name="l00548"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__SET.html#gac09654b4817049e68773ee4543495fea">  548</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN1_SET_ALL_POS)) </span></div><div class="line"><a name="l00560"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__CLR.html#gaf418bee2299bdc9d72c1eede1e92e36c">  560</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_CLR_ALL_POS                     0 </span></div><div class="line"><a name="l00561"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__CLR.html#gad06bf21c50d2000d60f610f1547bfa96">  561</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN1_CLR_ALL_POS)) </span></div><div class="line"><a name="l00572"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#ga58999c0118aecddf982168b772de8bad">  572</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_GPIO_EN2_POS                    0 </span></div><div class="line"><a name="l00573"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#ga944a65449a004122b73762c85f9fba86">  573</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_GPIO_EN2                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN2_GPIO_EN2_POS)) </span></div><div class="line"><a name="l00574"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#gae2fd276695fb33b3afd222bbaf975906">  574</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00575"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#gaa28d84b44f47df032f4a9160b03e8b8d">  575</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY &lt;&lt; MXC_F_GPIO_EN2_GPIO_EN2_POS) </span></div><div class="line"><a name="l00576"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#ga7c85916db6cdba6779c6b856c572228d">  576</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00577"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#gaca446f72783206ce36021eb34b7bc41b">  577</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY              (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY &lt;&lt; MXC_F_GPIO_EN2_GPIO_EN2_POS) </span></div><div class="line"><a name="l00589"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__SET.html#gace9256e9bdf151c1fc7846dd958e7011">  589</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_SET_ALL_POS                     0 </span></div><div class="line"><a name="l00590"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__SET.html#ga4dc28b7fe82c5c11f3f76a2df9e35d98">  590</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN2_SET_ALL_POS)) </span></div><div class="line"><a name="l00602"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__CLR.html#gaaeaa2a6414a5e205c277cdbcee0e0cd0">  602</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_CLR_ALL_POS                     0 </span></div><div class="line"><a name="l00603"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__CLR.html#ga09378b8178626663cef26c51e4a82e72">  603</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN2_CLR_ALL_POS)) </span></div><div class="line"><a name="l00615"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga125e85906fc3da0c1aa3197701735719">  615</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS_DS_POS                           0 </span></div><div class="line"><a name="l00616"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga6c8ed9dac830fabed7698e569299e27c">  616</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS_DS                               ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_DS_DS_POS)) </span></div><div class="line"><a name="l00617"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#gad739fa75372dd6bdd2b5e0841fc9effa">  617</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_DS_DS_LD                            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00618"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga67b0392d52d02fed334c79687470b3e6">  618</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_DS_DS_LD                            (MXC_V_GPIO_DS_DS_LD &lt;&lt; MXC_F_GPIO_DS_DS_POS) </span></div><div class="line"><a name="l00619"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga713c84ffbbd7fc410b2dd952a4539652">  619</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_DS_DS_HD                            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00620"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga73778b081741348d83b0d7beab1003ef">  620</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_DS_DS_HD                            (MXC_V_GPIO_DS_DS_HD &lt;&lt; MXC_F_GPIO_DS_DS_POS) </span></div><div class="line"><a name="l00632"></a><span class="lineno"><a class="line" href="group__GPIO__DS1.html#gad7d27ae232274b660b090ef4ce6317ae">  632</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS1_ALL_POS                         0 </span></div><div class="line"><a name="l00633"></a><span class="lineno"><a class="line" href="group__GPIO__DS1.html#gaeef652494907cca2bd64ad0aabc67072">  633</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS1_ALL                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_DS1_ALL_POS)) </span></div><div class="line"><a name="l00643"></a><span class="lineno"><a class="line" href="group__GPIO__PS.html#gada026aa655bc7bbe45b1dee3a3f3cd19">  643</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PS_ALL_POS                          0 </span></div><div class="line"><a name="l00644"></a><span class="lineno"><a class="line" href="group__GPIO__PS.html#ga1c4941df25cf05cea19969b5a2c26c66">  644</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PS_ALL                              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_PS_ALL_POS)) </span></div><div class="line"><a name="l00654"></a><span class="lineno"><a class="line" href="group__GPIO__VSSEL.html#ga4cd24bdac8b92fb2f1e3d3a05669e850">  654</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_VSSEL_ALL_POS                       0 </span></div><div class="line"><a name="l00655"></a><span class="lineno"><a class="line" href="group__GPIO__VSSEL.html#ga30f60e7506c199b69d1e69b200fe1b6b">  655</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_VSSEL_ALL                           ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_VSSEL_ALL_POS)) </span></div><div class="line"><a name="l00659"></a><span class="lineno">  659</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00660"></a><span class="lineno">  660</span>&#160;}</div><div class="line"><a name="l00661"></a><span class="lineno">  661</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00662"></a><span class="lineno">  662</span>&#160;</div><div class="line"><a name="l00663"></a><span class="lineno">  663</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _GPIO_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__gpio__regs__t_html_a87f96b8f0b9f74dde9665327e64f59c6"><div class="ttname"><a href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">mxc_gpio_regs_t::int_clr</a></div><div class="ttdeci">__IO uint32_t int_clr</div><div class="ttdoc">0x48: GPIO INT_CLR Register </div><div class="ttdef"><b>Definition:</b> gpio_regs.h:107</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _GPIO_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _GPIO_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a12ebf0d620fc9bcd0e7a04bb0eb87095">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a12ebf0d620fc9bcd0e7a04bb0eb87095">en</a>;                   </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a19920be0077d7e457fd8f78e592e8ee7">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a19920be0077d7e457fd8f78e592e8ee7">en_set</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a09c244fbc1eb2b68000e3446c9da7092">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a09c244fbc1eb2b68000e3446c9da7092">en_clr</a>;               </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a59397d720eb460fad58c573a8f863e07">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a59397d720eb460fad58c573a8f863e07">out_en</a>;               </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aee2936a5c5dedb62edcb74445f45dad5">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aee2936a5c5dedb62edcb74445f45dad5">out_en_set</a>;           </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae602770bef6e294d047a2ee7975e25d0">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae602770bef6e294d047a2ee7975e25d0">out_en_clr</a>;           </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a569d1b15db75f25b605a0e31b4af24f1">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a569d1b15db75f25b605a0e31b4af24f1">out</a>;                  </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae8eb843fcc4aa762cdd6daf467ca1ab5">   96</a></span>&#160;    __O  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae8eb843fcc4aa762cdd6daf467ca1ab5">out_set</a>;              </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a28fac16f51d6c2bdba3a56f058bc1a09">   97</a></span>&#160;    __O  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a28fac16f51d6c2bdba3a56f058bc1a09">out_clr</a>;              </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a0e9363bc6e34884e294f55287d764399">   98</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a0e9363bc6e34884e294f55287d764399">in</a>;                   </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#af79908b309ce0db975d2fc86f715df03">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#af79908b309ce0db975d2fc86f715df03">int_mod</a>;              </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a4f913ed090f662fe8b65860c2937faff">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a4f913ed090f662fe8b65860c2937faff">int_pol</a>;              </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aa6c384a08f486469b6aa1868f8ef4720">  101</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aa6c384a08f486469b6aa1868f8ef4720">in_en</a>;                </div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ab7bb644b9ff7da05df3addd6884b90c1">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ab7bb644b9ff7da05df3addd6884b90c1">int_en</a>;               </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a9612ed1d0d8919844ace750f947844f2">  103</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a9612ed1d0d8919844ace750f947844f2">int_en_set</a>;           </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a40c3185a68d40c6f23acba1f722b98c2">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a40c3185a68d40c6f23acba1f722b98c2">int_en_clr</a>;           </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aafca04b07b05f384110bad47f03a11c5">  105</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aafca04b07b05f384110bad47f03a11c5">int_stat</a>;             </div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;    __R  uint32_t rsv_0x44;</div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">int_clr</a>;              </div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a3628e36093e2b9e7653a9d6dc9e0a767">  108</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a3628e36093e2b9e7653a9d6dc9e0a767">wake_en</a>;              </div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aabdf76d86254e27c51d49674ec34a97d">  109</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aabdf76d86254e27c51d49674ec34a97d">wake_en_set</a>;          </div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a59981dba0d003b2d1869a2e9583fb5ea">  110</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a59981dba0d003b2d1869a2e9583fb5ea">wake_en_clr</a>;          </div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    __R  uint32_t rsv_0x58;</div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae38ef1bb1b50e0c44a0b179d004e401c">  112</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae38ef1bb1b50e0c44a0b179d004e401c">int_dual_edge</a>;        </div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#af170c398f4cdc87c8b2c4cd6f0c135da">  113</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#af170c398f4cdc87c8b2c4cd6f0c135da">pad_cfg1</a>;             </div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae9a085f22f1e2aa41ce4fcb606a55327">  114</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae9a085f22f1e2aa41ce4fcb606a55327">pad_cfg2</a>;             </div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a1be455cc78ca47c12031e924be841be3">  115</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a1be455cc78ca47c12031e924be841be3">en1</a>;                  </div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ab4dc84cfaccce1a45dddf48ae55541b9">  116</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ab4dc84cfaccce1a45dddf48ae55541b9">en1_set</a>;              </div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a5530f6655cb11931921d527b2d97ce82">  117</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a5530f6655cb11931921d527b2d97ce82">en1_clr</a>;              </div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a1bf54ff6d19358935cae207fb30f78b9">  118</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a1bf54ff6d19358935cae207fb30f78b9">en2</a>;                  </div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#abf8c5a5c842a4c07c023d218a3e3c16d">  119</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#abf8c5a5c842a4c07c023d218a3e3c16d">en2_set</a>;              </div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#ae3fee91062860fb154b6056ea2d184d4">  120</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#ae3fee91062860fb154b6056ea2d184d4">en2_clr</a>;              </div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    __R  uint32_t rsv_0x80_0xa7[10];</div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#af63c0f10e0d2dd9723a7a6de899c33ec">  122</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#af63c0f10e0d2dd9723a7a6de899c33ec">is</a>;                   </div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">  123</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aa15134bd59dc86c6735a8126ccd86bc1">sr</a>;                   </div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#aa1416bcf0a3a68c007b167e0ac79ae9d">  124</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#aa1416bcf0a3a68c007b167e0ac79ae9d">ds</a>;                   </div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a91168a379332b56f62afa1c690beb379">  125</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a91168a379332b56f62afa1c690beb379">ds1</a>;                  </div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a2ebe119356fa75bd745984ae2bf71494">  126</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a2ebe119356fa75bd745984ae2bf71494">ps</a>;                   </div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    __R  uint32_t rsv_0xbc;</div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="structmxc__gpio__regs__t.html#a98fbb84df6f74baff23d056a526c1ec4">  128</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__gpio__regs__t.html#a98fbb84df6f74baff23d056a526c1ec4">vssel</a>;                </div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;} <a class="code" href="structmxc__gpio__regs__t.html">mxc_gpio_regs_t</a>;</div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;<span class="comment">/* Register offsets for module GPIO */</span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga2dd795d5dc058c4442a19bd7cf1c7a9d">  138</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gadb9cc9cd4c0a8a962581db3d8a324e22">  139</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN_SET                  ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaac082442a39bb364e9b2facef607e87d">  140</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN_CLR                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga39abe8ea9c9cca4c36569e24c1c1a955">  141</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_EN                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaca62cc1d87cd41857e1c64cc0af54a2f">  142</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_EN_SET              ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga69be75eb84cc5e5c86534aa6c69c27ce">  143</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_EN_CLR              ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gacedd52f61c661de1cfdb2ec550ce0f2b">  144</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT                     ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gab4c80b1e1d756c951150c4c3d92fc10c">  145</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_SET                 ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gab8d0414874e7a723126cb452a0e0eec4">  146</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_OUT_CLR                 ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gadd058220f09d4fa558eae6aa2577d210">  147</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_IN                      ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga461cba15ab8c92c8d3733baca4805220">  148</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_MOD                 ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf45e24dff8f4c63869c98683ffe3f7f1">  149</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_POL                 ((uint32_t)0x0000002CUL) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga9fefcf1855f78ea1d86bae79d8bd31d1">  150</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_IN_EN                   ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga8e43896a7dae653d606fc1b6ceae8d1e">  151</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_EN                  ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gae49adb067d0f0cbcfa1e617f849d2839">  152</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_EN_SET              ((uint32_t)0x00000038UL) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga2085b59188ee0fc2b18aea73712b1f4a">  153</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_EN_CLR              ((uint32_t)0x0000003CUL) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga568051a18cfeb923dd66174577d7e484">  154</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_STAT                ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga4e1bb5efe2d55931ad066985c5a5ff69">  155</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_CLR                 ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaed5b341948ea5cb2e0a15890c698ede4">  156</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_WAKE_EN                 ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga872c82d804151dff57ae7b282471af68">  157</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_WAKE_EN_SET             ((uint32_t)0x00000050UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf93f122a8219b17479517bed53af0bdc">  158</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_WAKE_EN_CLR             ((uint32_t)0x00000054UL) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga8622f35f7d89141d2dbc4f18ef4e14b9">  159</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_INT_DUAL_EDGE           ((uint32_t)0x0000005CUL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga78f781b3f1f6b801340682e4755405a5">  160</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_PAD_CFG1                ((uint32_t)0x00000060UL) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga2ff3ae3085625507996679a05995b33f">  161</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_PAD_CFG2                ((uint32_t)0x00000064UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga1cabc6e94d9c034f093e99e2b52e4ad8">  162</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN1                     ((uint32_t)0x00000068UL) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga3cec9b7df9db083d4ca600a559357f24">  163</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN1_SET                 ((uint32_t)0x0000006CUL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf73912b8ff595ba2b536a8ccac988d01">  164</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN1_CLR                 ((uint32_t)0x00000070UL) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gaf35a746852595cd4ea1cfd05fae65928">  165</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN2                     ((uint32_t)0x00000074UL) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga282b023aa645fde7e8d3d0ae9ba14987">  166</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN2_SET                 ((uint32_t)0x00000078UL) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gab238e38f894983e5bdad185644a12c07">  167</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_EN2_CLR                 ((uint32_t)0x0000007CUL) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga4fdeb971ffcaaa861b1c5fab91f0deb0">  168</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_IS                      ((uint32_t)0x000000A8UL) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga5bfd98d3e6944feca7d78f2960b4fdd2">  169</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_SR                      ((uint32_t)0x000000ACUL) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga184787ed50ed8cfa3486b70993128a83">  170</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_DS                      ((uint32_t)0x000000B0UL) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#gad5ad180e0488ac0597b2416ae0f6801e">  171</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_DS1                     ((uint32_t)0x000000B4UL) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga3f5e991f9954a9be74d40e3d41707266">  172</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_PS                      ((uint32_t)0x000000B8UL) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__GPIO__Register__Offsets.html#ga263d5b2fe4fa353b8ca726894799497d">  173</a></span>&#160;<span class="preprocessor"> #define MXC_R_GPIO_VSSEL                   ((uint32_t)0x000000C0UL) </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga6d74c8fc1b9a28951219d8fab67d678b">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_GPIO_EN_POS                      0 </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga07c4593df5b48749f882b942164fb3b5">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_GPIO_EN                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN_GPIO_EN_POS)) </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga10df8f1950aa07d835162dbaa2f543b4">  185</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN_GPIO_EN_ALTERNATE                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#gab6a71028094ab09633528827f4a206c7">  186</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN_GPIO_EN_ALTERNATE                (MXC_V_GPIO_EN_GPIO_EN_ALTERNATE &lt;&lt; MXC_F_GPIO_EN_GPIO_EN_POS) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga70ce7650a26b935cae6b4f5dbeb27b14">  187</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN_GPIO_EN_GPIO                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__GPIO__EN.html#ga2168d84c4b49c7ec0656b34f43d6ac6b">  188</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN_GPIO_EN_GPIO                     (MXC_V_GPIO_EN_GPIO_EN_GPIO &lt;&lt; MXC_F_GPIO_EN_GPIO_EN_POS) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__GPIO__EN__SET.html#ga16b03ea3c606ef96936359a9952bc7e2">  200</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_SET_ALL_POS                      0 </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__GPIO__EN__SET.html#ga6e56867c905a3fb419ac159fc808c226">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_SET_ALL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN_SET_ALL_POS)) </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__GPIO__EN__CLR.html#ga0a04a27dd2f9316d31eecae25ab1bdf7">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_CLR_ALL_POS                      0 </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__GPIO__EN__CLR.html#gaa7485e96a347bbad9afece88d32d5756">  214</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN_CLR_ALL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN_CLR_ALL_POS)) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga2fdeff86005b15b94ac6a18c356cb771">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS              0 </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga128fd3b7e7444ae5cf4eced2dee7e718">  226</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_GPIO_OUT_EN                  ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga1ac90f34f16339f706636d6e5d3e9a27">  227</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga33a93366522841a6a88c08b8a14fd977">  228</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_DIS              (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_DIS &lt;&lt; MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#ga2c1a12174106b1b519fb63846126b4a1">  229</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN.html#gaf5b5c65a8d501bdd16dbf1a131ebe9d5">  230</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_EN_GPIO_OUT_EN_EN               (MXC_V_GPIO_OUT_EN_GPIO_OUT_EN_EN &lt;&lt; MXC_F_GPIO_OUT_EN_GPIO_OUT_EN_POS) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__SET.html#ga2a7c400a761a556004a55effc2837194">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_SET_ALL_POS                  0 </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__SET.html#gafa2051418d43e8e4c41163ca47037fa7">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_SET_ALL                      ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_EN_SET_ALL_POS)) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__CLR.html#ga9c7529dd79ed64a1918e29cc9fa79e28">  255</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_CLR_ALL_POS                  0 </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__EN__CLR.html#ga03a375e71717b9f4fb8fd990bcee2b0b">  256</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_EN_CLR_ALL                      ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_EN_CLR_ALL_POS)) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#gac4fab39a1a698b572f8d168ce195a7b0">  268</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_GPIO_OUT_POS                    0 </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga6c818e902ab9cc94006b0d8e854ac83c">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_GPIO_OUT                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_GPIO_OUT_POS)) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga49c5cb2a9bea00ef5c93f8e0d1181341">  270</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_GPIO_OUT_LOW                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga942cbf531303a8a158225a34ea6a31a2">  271</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_GPIO_OUT_LOW                    (MXC_V_GPIO_OUT_GPIO_OUT_LOW &lt;&lt; MXC_F_GPIO_OUT_GPIO_OUT_POS) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#gac39c2062974b8158195592699626e109">  272</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_GPIO_OUT_HIGH                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__GPIO__OUT.html#ga9d390b39684e0cafbaf219c0f1a97261">  273</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_GPIO_OUT_HIGH                   (MXC_V_GPIO_OUT_GPIO_OUT_HIGH &lt;&lt; MXC_F_GPIO_OUT_GPIO_OUT_POS) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#gaa82f721e63b00f2f41f4934c86484297">  285</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS            0 </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga5a9cc6a352f23b5977dc0c231424742c">  286</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_SET_GPIO_OUT_SET                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS)) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga2cf923a86445b99706c58de44a71221b">  287</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO             ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga0f9bbb99248d10768ce95b527f5e2f47">  288</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_NO             (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_NO &lt;&lt; MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga8374c6d6ca12d6ccec1084a45b66372a">  289</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__SET.html#ga350556688902ab8d7e91f0f8bdb39701">  290</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_OUT_SET_GPIO_OUT_SET_SET            (MXC_V_GPIO_OUT_SET_GPIO_OUT_SET_SET &lt;&lt; MXC_F_GPIO_OUT_SET_GPIO_OUT_SET_POS) </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__CLR.html#gaea49754bc59ac193ee602547333d0733">  302</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS            0 </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__GPIO__OUT__CLR.html#ga34be6b2874b6a6c8bfc01185e3583a12">  303</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_OUT_CLR_GPIO_OUT_CLR_POS)) </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__GPIO__IN.html#ga0e6c50f7f11dde5324b45d67f113c0cb">  314</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_IN_GPIO_IN_POS                      0 </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__GPIO__IN.html#ga7a8581225a93489013e9f7b8461659e3">  315</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_IN_GPIO_IN                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_IN_GPIO_IN_POS)) </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga0a2221eeab673daaabcd7b63866aab7e">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS            0 </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga6f418867dcc872f03b7d73decfdad1dd">  327</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_MOD_GPIO_INT_MOD                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS)) </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga4d1d091bcd110dad604c62a909485695">  328</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL          ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga40c1f7e6be9b8f30018d98c69ec831ad">  329</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL          (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_LEVEL &lt;&lt; MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#gae8c514db9902542799fd5ecda19c997a">  330</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__GPIO__INT__MOD.html#ga645c827ad58cf81a6679c12319e7aaf0">  331</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_MOD_GPIO_INT_MOD_EDGE           (MXC_V_GPIO_INT_MOD_GPIO_INT_MOD_EDGE &lt;&lt; MXC_F_GPIO_INT_MOD_GPIO_INT_MOD_POS) </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gaf7642a4e46009fb784b10a5b5ed9323f">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS            0 </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gaed925beb749458f2b39448721525758c">  343</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_POL_GPIO_INT_POL                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS)) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#ga5573663abbd9dcab76d3bcd30cfbb10a">  344</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gab365d25bafd5f200e171292be98acb82">  345</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_FALLING        (MXC_V_GPIO_INT_POL_GPIO_INT_POL_FALLING &lt;&lt; MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#gab2cf1b7bbc7c088eaa3bba0b00297d46">  346</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING         ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00347"></a><span class="lineno"><a class="line" href="group__GPIO__INT__POL.html#ga339580e5912389cbbe0de2818a3781b5">  347</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_POL_GPIO_INT_POL_RISING         (MXC_V_GPIO_INT_POL_GPIO_INT_POL_RISING &lt;&lt; MXC_F_GPIO_INT_POL_GPIO_INT_POL_POS) </span></div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="group__GPIO__IN__EN.html#gaf9258e3f1a0f2c06f873d9fd44cb97a1">  357</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS                0 </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__GPIO__IN__EN.html#ga59f6dc00fcb471e0bf836ae2b05044dc">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_IN_EN_GPIO_IN_EN                    ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__GPIO__IN__EN.html#ga63d87bbf00e13f398d9cca41c32be962">  359</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="group__GPIO__IN__EN.html#ga095fbbc2a2535efa7c87584cc4398172">  360</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS                (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS &lt;&lt; MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__GPIO__IN__EN.html#ga2499d6208c11970537974121c56747fa">  361</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN                 ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__GPIO__IN__EN.html#ga0ec72103964ad08ada80899cd2f89da5">  362</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN                 (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN &lt;&lt; MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#gab9600d31b81f25d1097809c22bb0a754">  373</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS              0 </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#gabc277cf79371a75eaaecbc41a7793355">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_GPIO_INT_EN                  ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS)) </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#ga7cf45430acd0def6b5bacfaf7694c04e">  375</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#ga47d53db9b65138db6de6eae593d63f06">  376</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_DIS              (MXC_V_GPIO_INT_EN_GPIO_INT_EN_DIS &lt;&lt; MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#ga2e4fd708b7eb3f52797d0cc194794663">  377</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN.html#gab37a3fef5ee5cb3a378cf9957c94d6c0">  378</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_GPIO_INT_EN_EN               (MXC_V_GPIO_INT_EN_GPIO_INT_EN_EN &lt;&lt; MXC_F_GPIO_INT_EN_GPIO_INT_EN_POS) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#gacecfa7f7ded9473ee9d4c2b21ac66836">  390</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS      0 </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#gaf292bd963c3b83708f565a835a121962">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS)) </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga3315651bea00d1fb49355b2a12a1abd4">  392</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga9bfca6180d6bd4fb672fb887cdf938a6">  393</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO       (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_NO &lt;&lt; MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga030fc5712481ba967818df90c32382e4">  394</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__SET.html#ga04b91301fae7574614fb105fef7806c7">  395</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET      (MXC_V_GPIO_INT_EN_SET_GPIO_INT_EN_SET_SET &lt;&lt; MXC_F_GPIO_INT_EN_SET_GPIO_INT_EN_SET_POS) </span></div><div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#gaef43aa0436a24603edd3d8cb00a31dbf">  407</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS      0 </span></div><div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga11fff0baf6506d123f56c7e896145a87">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS)) </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga34eb73b689d0fa3d8c61b89b99aeb9de">  409</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga4ea55c1e91914e348e26e7fceb38877e">  410</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO       (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_NO &lt;&lt; MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga51f34696244b971a31ea29bb2b223b44">  411</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__GPIO__INT__EN__CLR.html#ga822f66f49a20ea6c09dad7111ef75967">  412</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR    (MXC_V_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_CLEAR &lt;&lt; MXC_F_GPIO_INT_EN_CLR_GPIO_INT_EN_CLR_POS) </span></div><div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#ga4a8896dc4ff31fcb30da5f5786f9ac1c">  423</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS          0 </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#ga4d187137bc92866c6f44d40c0461585e">  424</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_STAT_GPIO_INT_STAT              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS)) </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gaf4d8ab951557571cb797b709ce85a2be">  425</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO           ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gaa39d8238bcdb20670a9b4366f5ed2c70">  426</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_NO           (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_NO &lt;&lt; MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) </span></div><div class="line"><a name="l00427"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gab8b0dbf75669f89c7608d89a39e61076">  427</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__GPIO__INT__STAT.html#gac09f0f3897bbaa498d35c5f2f9b4a711">  428</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_STAT_GPIO_INT_STAT_PENDING      (MXC_V_GPIO_INT_STAT_GPIO_INT_STAT_PENDING &lt;&lt; MXC_F_GPIO_INT_STAT_GPIO_INT_STAT_POS) </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__GPIO__INT__CLR.html#gad3cc3472d76c5858672b7ebbe1dfc1c2">  440</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_CLR_ALL_POS                     0 </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__GPIO__INT__CLR.html#ga634a5b77fbb0d3f9e07193cb88f05a4a">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_CLR_ALL_POS)) </span></div><div class="line"><a name="l00452"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga5f1e01a7c85aac4c7bcf47fe73035a5d">  452</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS            0 </span></div><div class="line"><a name="l00453"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga11c66804493d7552a082b6649e2d8d24">  453</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN                ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS)) </span></div><div class="line"><a name="l00454"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga4c4b3f87ac89adc1be55663ebda38b6c">  454</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00455"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga6d0186952c5df60dc25f3efc6734b4e0">  455</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS            (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_DIS &lt;&lt; MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) </span></div><div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#ga72b884817720a5cc27a01561b37d9712">  456</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN             ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN.html#gafc48f2b7bb177640b2781324d548e2f5">  457</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_WAKE_EN_GPIO_WAKE_EN_EN             (MXC_V_GPIO_WAKE_EN_GPIO_WAKE_EN_EN &lt;&lt; MXC_F_GPIO_WAKE_EN_GPIO_WAKE_EN_POS) </span></div><div class="line"><a name="l00469"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__SET.html#ga9a13f6b748e559fd3d668cb5c09aecc2">  469</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_SET_ALL_POS                 0 </span></div><div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__SET.html#ga6898b0b326604fe29415ce288d75c523">  470</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_SET_ALL                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_WAKE_EN_SET_ALL_POS)) </span></div><div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__CLR.html#gae9159c8dcd944cde538b4f1e4e113652">  482</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_CLR_ALL_POS                 0 </span></div><div class="line"><a name="l00483"></a><span class="lineno"><a class="line" href="group__GPIO__WAKE__EN__CLR.html#gafbb2fa7c72ff5f1abcfc97654951822a">  483</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_WAKE_EN_CLR_ALL                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_WAKE_EN_CLR_ALL_POS)) </span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gad858c9975958376ca05f4fa61799f616">  494</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS 0 </span></div><div class="line"><a name="l00495"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#ga2da4065b2dda907deb9d2667e6a563d5">  495</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE    ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS)) </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#ga5cb1e1b246cf12d4968482dee154c410">  496</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gabda1d70e4894aa5f1b9fbf92feeb5ee3">  497</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_NO &lt;&lt; MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) </span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gaed5912f5f7bfe2c2f5e339fdf43a58bc">  498</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__GPIO__INT__DUAL__EDGE.html#gaed4cde596d35ae9786dbe415d012ffdd">  499</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN (MXC_V_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_EN &lt;&lt; MXC_F_GPIO_INT_DUAL_EDGE_GPIO_INT_DUAL_EDGE_POS) </span></div><div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gad4671a3f371a3db59678c6f16f3aa8c5">  510</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS          0 </span></div><div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaf9e5a6dde9cbd513f83aefba8cf53233">  511</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS)) </span></div><div class="line"><a name="l00512"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaaa020b93dd5e46076681100e038fd911">  512</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaee891e0f74869b758125258a55cd302f">  513</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE    (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_IMPEDANCE &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) </span></div><div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gaddd398bb6aa717551c399f842a72a8d5">  514</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00515"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#ga9190ed585baa7004268155e47c28c905">  515</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU           (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PU &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) </span></div><div class="line"><a name="l00516"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#ga9016649c2d5b21dc37dc95e6b710743e">  516</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG1.html#gac2a8618b03ff8a0afe93d2792d3601c3">  517</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD           (MXC_V_GPIO_PAD_CFG1_GPIO_PAD_CFG1_PD &lt;&lt; MXC_F_GPIO_PAD_CFG1_GPIO_PAD_CFG1_POS) </span></div><div class="line"><a name="l00528"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#gab4347447d3eadf3f7d0bee8cb0bb1788">  528</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS          0 </span></div><div class="line"><a name="l00529"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga19088390b32000b948fb91417ffdb64e">  529</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS)) </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga33c73392b6ee368ab525d91a563a0793">  530</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00531"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga17593381b2dd30d9f08c1abcc58217e2">  531</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE    (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_IMPEDANCE &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) </span></div><div class="line"><a name="l00532"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga4c4b433a72c072489cd7fc0a7007e879">  532</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga740b6a4a77b5db8b17fffa69d9499d47">  533</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU           (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PU &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) </span></div><div class="line"><a name="l00534"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#ga6cf9a09a68785d37b9b16c9a9267a0d2">  534</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group__GPIO__PAD__CFG2.html#gacd073c4f4f7cc39455e4cf29230a7d8a">  535</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD           (MXC_V_GPIO_PAD_CFG2_GPIO_PAD_CFG2_PD &lt;&lt; MXC_F_GPIO_PAD_CFG2_GPIO_PAD_CFG2_POS) </span></div><div class="line"><a name="l00546"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#gae2c3e728533d5dcff875dd3b3a8eeac7">  546</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_GPIO_EN1_POS                    0 </span></div><div class="line"><a name="l00547"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga3724a944f84a049facb97bf25593e6c2">  547</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_GPIO_EN1                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN1_GPIO_EN1_POS)) </span></div><div class="line"><a name="l00548"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga41d28569d92c7a59cd54f2c7e4155fb6">  548</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00549"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#gac7a8f2fbf52f510db22b99c77184cd47">  549</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN1_GPIO_EN1_PRIMARY                (MXC_V_GPIO_EN1_GPIO_EN1_PRIMARY &lt;&lt; MXC_F_GPIO_EN1_GPIO_EN1_POS) </span></div><div class="line"><a name="l00550"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga5c8a103328700fcf1d0c0fd9b4a9acad">  550</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00551"></a><span class="lineno"><a class="line" href="group__GPIO__EN1.html#ga489775d0dea2907ac3e4d0dcdf7b2eca">  551</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN1_GPIO_EN1_SECONDARY              (MXC_V_GPIO_EN1_GPIO_EN1_SECONDARY &lt;&lt; MXC_F_GPIO_EN1_GPIO_EN1_POS) </span></div><div class="line"><a name="l00563"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__SET.html#ga582e5b6339fd338628b4c8a8e653fb26">  563</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_SET_ALL_POS                     0 </span></div><div class="line"><a name="l00564"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__SET.html#gac09654b4817049e68773ee4543495fea">  564</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN1_SET_ALL_POS)) </span></div><div class="line"><a name="l00576"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__CLR.html#gaf418bee2299bdc9d72c1eede1e92e36c">  576</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_CLR_ALL_POS                     0 </span></div><div class="line"><a name="l00577"></a><span class="lineno"><a class="line" href="group__GPIO__EN1__CLR.html#gad06bf21c50d2000d60f610f1547bfa96">  577</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN1_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN1_CLR_ALL_POS)) </span></div><div class="line"><a name="l00588"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#ga58999c0118aecddf982168b772de8bad">  588</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_GPIO_EN2_POS                    0 </span></div><div class="line"><a name="l00589"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#ga944a65449a004122b73762c85f9fba86">  589</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_GPIO_EN2                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN2_GPIO_EN2_POS)) </span></div><div class="line"><a name="l00590"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#gae2fd276695fb33b3afd222bbaf975906">  590</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY                ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00591"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#gaa28d84b44f47df032f4a9160b03e8b8d">  591</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN2_GPIO_EN2_PRIMARY                (MXC_V_GPIO_EN2_GPIO_EN2_PRIMARY &lt;&lt; MXC_F_GPIO_EN2_GPIO_EN2_POS) </span></div><div class="line"><a name="l00592"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#ga7c85916db6cdba6779c6b856c572228d">  592</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00593"></a><span class="lineno"><a class="line" href="group__GPIO__EN2.html#gaca446f72783206ce36021eb34b7bc41b">  593</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_EN2_GPIO_EN2_SECONDARY              (MXC_V_GPIO_EN2_GPIO_EN2_SECONDARY &lt;&lt; MXC_F_GPIO_EN2_GPIO_EN2_POS) </span></div><div class="line"><a name="l00605"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__SET.html#gace9256e9bdf151c1fc7846dd958e7011">  605</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_SET_ALL_POS                     0 </span></div><div class="line"><a name="l00606"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__SET.html#ga4dc28b7fe82c5c11f3f76a2df9e35d98">  606</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_SET_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN2_SET_ALL_POS)) </span></div><div class="line"><a name="l00618"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__CLR.html#gaaeaa2a6414a5e205c277cdbcee0e0cd0">  618</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_CLR_ALL_POS                     0 </span></div><div class="line"><a name="l00619"></a><span class="lineno"><a class="line" href="group__GPIO__EN2__CLR.html#ga09378b8178626663cef26c51e4a82e72">  619</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_EN2_CLR_ALL                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_EN2_CLR_ALL_POS)) </span></div><div class="line"><a name="l00631"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga125e85906fc3da0c1aa3197701735719">  631</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS_DS_POS                           0 </span></div><div class="line"><a name="l00632"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga6c8ed9dac830fabed7698e569299e27c">  632</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS_DS                               ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_DS_DS_POS)) </span></div><div class="line"><a name="l00633"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#gad739fa75372dd6bdd2b5e0841fc9effa">  633</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_DS_DS_LD                            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00634"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga67b0392d52d02fed334c79687470b3e6">  634</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_DS_DS_LD                            (MXC_V_GPIO_DS_DS_LD &lt;&lt; MXC_F_GPIO_DS_DS_POS) </span></div><div class="line"><a name="l00635"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga713c84ffbbd7fc410b2dd952a4539652">  635</a></span>&#160;<span class="preprocessor"> #define MXC_V_GPIO_DS_DS_HD                            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00636"></a><span class="lineno"><a class="line" href="group__GPIO__DS.html#ga73778b081741348d83b0d7beab1003ef">  636</a></span>&#160;<span class="preprocessor"> #define MXC_S_GPIO_DS_DS_HD                            (MXC_V_GPIO_DS_DS_HD &lt;&lt; MXC_F_GPIO_DS_DS_POS) </span></div><div class="line"><a name="l00648"></a><span class="lineno"><a class="line" href="group__GPIO__DS1.html#gad7d27ae232274b660b090ef4ce6317ae">  648</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS1_ALL_POS                         0 </span></div><div class="line"><a name="l00649"></a><span class="lineno"><a class="line" href="group__GPIO__DS1.html#gaeef652494907cca2bd64ad0aabc67072">  649</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_DS1_ALL                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_DS1_ALL_POS)) </span></div><div class="line"><a name="l00659"></a><span class="lineno"><a class="line" href="group__GPIO__PS.html#gada026aa655bc7bbe45b1dee3a3f3cd19">  659</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PS_ALL_POS                          0 </span></div><div class="line"><a name="l00660"></a><span class="lineno"><a class="line" href="group__GPIO__PS.html#ga1c4941df25cf05cea19969b5a2c26c66">  660</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_PS_ALL                              ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_PS_ALL_POS)) </span></div><div class="line"><a name="l00670"></a><span class="lineno"><a class="line" href="group__GPIO__VSSEL.html#ga4cd24bdac8b92fb2f1e3d3a05669e850">  670</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_VSSEL_ALL_POS                       0 </span></div><div class="line"><a name="l00671"></a><span class="lineno"><a class="line" href="group__GPIO__VSSEL.html#ga30f60e7506c199b69d1e69b200fe1b6b">  671</a></span>&#160;<span class="preprocessor"> #define MXC_F_GPIO_VSSEL_ALL                           ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_GPIO_VSSEL_ALL_POS)) </span></div><div class="line"><a name="l00675"></a><span class="lineno">  675</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00676"></a><span class="lineno">  676</span>&#160;}</div><div class="line"><a name="l00677"></a><span class="lineno">  677</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00678"></a><span class="lineno">  678</span>&#160;</div><div class="line"><a name="l00679"></a><span class="lineno">  679</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _GPIO_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__gpio__regs__t_html_a87f96b8f0b9f74dde9665327e64f59c6"><div class="ttname"><a href="structmxc__gpio__regs__t.html#a87f96b8f0b9f74dde9665327e64f59c6">mxc_gpio_regs_t::int_clr</a></div><div class="ttdeci">__IO uint32_t int_clr</div><div class="ttdoc">0x48: GPIO INT_CLR Register </div><div class="ttdef"><b>Definition:</b> gpio_regs.h:107</div></div>
 <div class="ttc" id="structmxc__gpio__regs__t_html_ae8eb843fcc4aa762cdd6daf467ca1ab5"><div class="ttname"><a href="structmxc__gpio__regs__t.html#ae8eb843fcc4aa762cdd6daf467ca1ab5">mxc_gpio_regs_t::out_set</a></div><div class="ttdeci">__O uint32_t out_set</div><div class="ttdoc">0x1C: GPIO OUT_SET Register </div><div class="ttdef"><b>Definition:</b> gpio_regs.h:96</div></div>
 <div class="ttc" id="structmxc__gpio__regs__t_html_a1bf54ff6d19358935cae207fb30f78b9"><div class="ttname"><a href="structmxc__gpio__regs__t.html#a1bf54ff6d19358935cae207fb30f78b9">mxc_gpio_regs_t::en2</a></div><div class="ttdeci">__IO uint32_t en2</div><div class="ttdoc">0x74: GPIO EN2 Register </div><div class="ttdef"><b>Definition:</b> gpio_regs.h:118</div></div>
 <div class="ttc" id="structmxc__gpio__regs__t_html_ab7bb644b9ff7da05df3addd6884b90c1"><div class="ttname"><a href="structmxc__gpio__regs__t.html#ab7bb644b9ff7da05df3addd6884b90c1">mxc_gpio_regs_t::int_en</a></div><div class="ttdeci">__IO uint32_t int_en</div><div class="ttdoc">0x34: GPIO INT_EN Register </div><div class="ttdef"><b>Definition:</b> gpio_regs.h:102</div></div>
@@ -84,6 +84,7 @@ $(document).ready(function(){initNavTree('gpio__regs_8h_source.html','');});
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+<div class="ttc" id="structmxc__gpio__regs__t_html_aa6c384a08f486469b6aa1868f8ef4720"><div class="ttname"><a href="structmxc__gpio__regs__t.html#aa6c384a08f486469b6aa1868f8ef4720">mxc_gpio_regs_t::in_en</a></div><div class="ttdeci">__IO uint32_t in_en</div><div class="ttdoc">0x30: GPIO IN_EN Register </div><div class="ttdef"><b>Definition:</b> gpio_regs.h:101</div></div>
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diff --git a/lib/sdk/Documentation/html/group__DMA__CFG.html b/lib/sdk/Documentation/html/group__DMA__CFG.html
index c87ec9d7fd2e8facff0d9995cc8a604cf1337eaa..bcc0bdc0594da5e9db745decf4f898a3d8da2106 100644
--- a/lib/sdk/Documentation/html/group__DMA__CFG.html
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b">MXC_S_DMA_CFG_REQSEL_SPI3TX</a>&#160;&#160;&#160;(<a class="el" href="group__DMA__CFG.html#ga69cb063b48ef0fd41b6bd7db7aae9def">MXC_V_DMA_CFG_REQSEL_SPI3TX</a> &lt;&lt; <a class="el" href="group__DMA__CFG.html#ga03b16149181424405cc14cc5aacc6a6b">MXC_F_DMA_CFG_REQSEL_POS</a>)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__DMA__CFG.html#gab57be50928424427440ae1550e458610">MXC_V_DMA_CFG_REQSEL_SPI0TX</a>&#160;&#160;&#160;((uint32_t)0x2FUL)</td></tr>
+<tr class="memdesc:gab57be50928424427440ae1550e458610"><td class="mdescLeft">&#160;</td><td class="mdescRight">CFG_REQSEL_SPI0TX Value. <br /></td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000">MXC_S_DMA_CFG_REQSEL_SPI0TX</a>&#160;&#160;&#160;(<a class="el" href="group__DMA__CFG.html#gab57be50928424427440ae1550e458610">MXC_V_DMA_CFG_REQSEL_SPI0TX</a> &lt;&lt; <a class="el" href="group__DMA__CFG.html#ga03b16149181424405cc14cc5aacc6a6b">MXC_F_DMA_CFG_REQSEL_POS</a>)</td></tr>
+<tr class="memdesc:gae14d1d9ad0b5bc476ae30fb75eedb000"><td class="mdescLeft">&#160;</td><td class="mdescRight">CFG_REQSEL_SPI0TX Setting. <br /></td></tr>
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diff --git a/lib/sdk/Documentation/html/group__DMA__CFG.js b/lib/sdk/Documentation/html/group__DMA__CFG.js
index af029c04f8ea9db0b5f76497e7bed96b438efe89..54e25081fa09bb4c4d7e46a204622b9af19b18b6 100644
--- a/lib/sdk/Documentation/html/group__DMA__CFG.js
+++ b/lib/sdk/Documentation/html/group__DMA__CFG.js
@@ -18,12 +18,12 @@ var group__DMA__CFG =
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     [ "MXC_V_DMA_CFG_REQSEL_MEMTOMEM", "group__DMA__CFG.html#ga008c60c169b71e7075e95e7f1aa422c3", null ],
     [ "MXC_S_DMA_CFG_REQSEL_MEMTOMEM", "group__DMA__CFG.html#gaab33bbc5b4fcb13a55cdb8e716b2df95", null ],
-    [ "MXC_V_DMA_CFG_REQSEL_SPI0RX", "group__DMA__CFG.html#gaec6de3f265bcfedfbd8c650c4c43ecd0", null ],
-    [ "MXC_S_DMA_CFG_REQSEL_SPI0RX", "group__DMA__CFG.html#ga94a9fbd8bb720eb2b6e289a80eca1a9a", null ],
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     [ "MXC_S_DMA_CFG_REQSEL_SPI1RX", "group__DMA__CFG.html#ga2ca72c3d3e653d28c8862e1e1e73ae16", null ],
     [ "MXC_V_DMA_CFG_REQSEL_SPI2RX", "group__DMA__CFG.html#ga48dc9d5a7aba7592f779ed9667201a28", null ],
     [ "MXC_S_DMA_CFG_REQSEL_SPI2RX", "group__DMA__CFG.html#gacfbe66e9428a311fde3b6879c60da6b0", null ],
+    [ "MXC_V_DMA_CFG_REQSEL_SPI3RX", "group__DMA__CFG.html#ga4449ecef8d439c68653316c9dbb92456", null ],
+    [ "MXC_S_DMA_CFG_REQSEL_SPI3RX", "group__DMA__CFG.html#gaf131253bf03e1bb7e63198431f0ff639", null ],
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@@ -36,8 +36,8 @@ var group__DMA__CFG =
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     [ "MXC_V_DMA_CFG_REQSEL_UART2RX", "group__DMA__CFG.html#ga32fa58a44707ec0dc04c2475ede271b3", null ],
     [ "MXC_S_DMA_CFG_REQSEL_UART2RX", "group__DMA__CFG.html#ga558829f658022cdc489bd0906227752a", null ],
-    [ "MXC_V_DMA_CFG_REQSEL_SPI3RX", "group__DMA__CFG.html#ga4449ecef8d439c68653316c9dbb92456", null ],
-    [ "MXC_S_DMA_CFG_REQSEL_SPI3RX", "group__DMA__CFG.html#gaf131253bf03e1bb7e63198431f0ff639", null ],
+    [ "MXC_V_DMA_CFG_REQSEL_SPI0RX", "group__DMA__CFG.html#gaec6de3f265bcfedfbd8c650c4c43ecd0", null ],
+    [ "MXC_S_DMA_CFG_REQSEL_SPI0RX", "group__DMA__CFG.html#ga94a9fbd8bb720eb2b6e289a80eca1a9a", null ],
     [ "MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX", "group__DMA__CFG.html#ga4890f1dff25f80855704fe86b8d173ac", null ],
     [ "MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX", "group__DMA__CFG.html#ga625831734be28d96e7bcc8090acbe3b8", null ],
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@@ -62,12 +62,12 @@ var group__DMA__CFG =
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-    [ "MXC_V_DMA_CFG_REQSEL_SPI0TX", "group__DMA__CFG.html#gab57be50928424427440ae1550e458610", null ],
-    [ "MXC_S_DMA_CFG_REQSEL_SPI0TX", "group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000", null ],
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     [ "MXC_V_DMA_CFG_REQSEL_SPI2TX", "group__DMA__CFG.html#gabe3ae057abab200af7f84e92cc0d55c4", null ],
     [ "MXC_S_DMA_CFG_REQSEL_SPI2TX", "group__DMA__CFG.html#gad3a1d6b9f0161f5cd633fd04a3817226", null ],
+    [ "MXC_V_DMA_CFG_REQSEL_SPI3TX", "group__DMA__CFG.html#ga69cb063b48ef0fd41b6bd7db7aae9def", null ],
+    [ "MXC_S_DMA_CFG_REQSEL_SPI3TX", "group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b", null ],
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     [ "MXC_S_DMA_CFG_REQSEL_UART0TX", "group__DMA__CFG.html#ga6b454bf5654872a6b0954865dfdedc4d", null ],
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@@ -78,8 +78,8 @@ var group__DMA__CFG =
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-    [ "MXC_V_DMA_CFG_REQSEL_SPI3TX", "group__DMA__CFG.html#ga69cb063b48ef0fd41b6bd7db7aae9def", null ],
-    [ "MXC_S_DMA_CFG_REQSEL_SPI3TX", "group__DMA__CFG.html#ga41434e3a003ef48bae78988373094f8b", null ],
+    [ "MXC_V_DMA_CFG_REQSEL_SPI0TX", "group__DMA__CFG.html#gab57be50928424427440ae1550e458610", null ],
+    [ "MXC_S_DMA_CFG_REQSEL_SPI0TX", "group__DMA__CFG.html#gae14d1d9ad0b5bc476ae30fb75eedb000", null ],
     [ "MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX", "group__DMA__CFG.html#ga387dae08cef4a75de7a2fcd15642d54d", null ],
     [ "MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX", "group__DMA__CFG.html#gac4b209297fe9fee806e1ea1286cf5001", null ],
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diff --git a/lib/sdk/Documentation/html/group__FLC__CN.html b/lib/sdk/Documentation/html/group__FLC__CN.html
index 2d76cb1facd3855860596a5b4a69c75bc4b7fd64..1c3bcf978c0309a342bc2471f76635bfdb823816 100644
--- a/lib/sdk/Documentation/html/group__FLC__CN.html
+++ b/lib/sdk/Documentation/html/group__FLC__CN.html
@@ -159,14 +159,6 @@ Macros</h2></td></tr>
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-<tr class="memitem:ga06be6b9392c8dd6dbad0434f5e70fe08"><td class="memItemLeft" align="right" valign="top"><a id="ga06be6b9392c8dd6dbad0434f5e70fe08"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__FLC__CN.html#ga06be6b9392c8dd6dbad0434f5e70fe08">MXC_F_FLC_CN_BRST</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_FLC_CN_BRST_POS))</td></tr>
-<tr class="memdesc:ga06be6b9392c8dd6dbad0434f5e70fe08"><td class="mdescLeft">&#160;</td><td class="mdescRight">CN_BRST Mask. <br /></td></tr>
-<tr class="separator:ga06be6b9392c8dd6dbad0434f5e70fe08"><td class="memSeparator" colspan="2">&#160;</td></tr>
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 <tr class="memdesc:ga6861f22ee99248bf588705c65c02c791"><td class="mdescLeft">&#160;</td><td class="mdescRight">CN_UNLOCK Position. <br /></td></tr>
diff --git a/lib/sdk/Documentation/html/group__FLC__CN.js b/lib/sdk/Documentation/html/group__FLC__CN.js
index cb3961abcf005a8a0f0f3e91bff2b6854016e54f..1ab2656d1654fab0b79c77772c39df1c73ba9215 100644
--- a/lib/sdk/Documentation/html/group__FLC__CN.js
+++ b/lib/sdk/Documentation/html/group__FLC__CN.js
@@ -20,8 +20,6 @@ var group__FLC__CN =
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-    [ "MXC_F_FLC_CN_BRST_POS", "group__FLC__CN.html#gae36e44d74c1415e835e4644a20e34d7c", null ],
-    [ "MXC_F_FLC_CN_BRST", "group__FLC__CN.html#ga06be6b9392c8dd6dbad0434f5e70fe08", null ],
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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">
+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/lib/sdk/Documentation/html/group__GPIO__IN__EN.js b/lib/sdk/Documentation/html/group__GPIO__IN__EN.js
new file mode 100644
index 0000000000000000000000000000000000000000..9e8a45824da97e2478b7426edee8e7ee956e4eba
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__GPIO__IN__EN.js
@@ -0,0 +1,9 @@
+var group__GPIO__IN__EN =
+[
+    [ "MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS", "group__GPIO__IN__EN.html#gaf9258e3f1a0f2c06f873d9fd44cb97a1", null ],
+    [ "MXC_F_GPIO_IN_EN_GPIO_IN_EN", "group__GPIO__IN__EN.html#ga59f6dc00fcb471e0bf836ae2b05044dc", null ],
+    [ "MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS", "group__GPIO__IN__EN.html#ga63d87bbf00e13f398d9cca41c32be962", null ],
+    [ "MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS", "group__GPIO__IN__EN.html#ga095fbbc2a2535efa7c87584cc4398172", null ],
+    [ "MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN", "group__GPIO__IN__EN.html#ga2499d6208c11970537974121c56747fa", null ],
+    [ "MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN", "group__GPIO__IN__EN.html#ga0ec72103964ad08ada80899cd2f89da5", null ]
+];
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 <tr class="separator:gaf45e24dff8f4c63869c98683ffe3f7f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GPIO__Register__Offsets.html#ga9fefcf1855f78ea1d86bae79d8bd31d1">MXC_R_GPIO_IN_EN</a>&#160;&#160;&#160;((uint32_t)0x00000030UL)</td></tr>
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--- a/lib/sdk/Documentation/html/group__GPIO__Register__Offsets.js
+++ b/lib/sdk/Documentation/html/group__GPIO__Register__Offsets.js
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     [ "MXC_R_GPIO_INT_POL", "group__GPIO__Register__Offsets.html#gaf45e24dff8f4c63869c98683ffe3f7f1", null ],
+    [ "MXC_R_GPIO_IN_EN", "group__GPIO__Register__Offsets.html#ga9fefcf1855f78ea1d86bae79d8bd31d1", null ],
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 <script type="text/javascript" src="jquery.js"></script>
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+<div class="title">HTMR_SEC<div class="ingroups"><a class="el" href="group__htmr.html">HTMR</a> &raquo; <a class="el" href="group__htmr__registers.html">HTMR_Registers</a></div></div>  </div>
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 <div class="contents">
 
-<p>Time-of-day Alarm.  
+<p>HTimer Long-Interval Counter.  
 <a href="#details">More...</a></p>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__HTMR__SEC.html#gaf760018a3933ba55f6f948cb3a3a8027">MXC_F_HTMR_SEC_RTS_POS</a>&#160;&#160;&#160;0</td></tr>
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+<tr class="memitem:gaf0ac1a7a89a7ddc31f13020f1509b16e"><td class="memItemLeft" align="right" valign="top"><a id="gaf0ac1a7a89a7ddc31f13020f1509b16e"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__HTMR__SEC.html#gaf0ac1a7a89a7ddc31f13020f1509b16e">MXC_F_HTMR_SEC_RTS</a>&#160;&#160;&#160;((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_HTMR_SEC_RTS_POS))</td></tr>
+<tr class="memdesc:gaf0ac1a7a89a7ddc31f13020f1509b16e"><td class="mdescLeft">&#160;</td><td class="mdescRight">SEC_RTS Mask. <br /></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<p>This register contains the 32 most significant bits of the counter. </p>
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
diff --git a/lib/sdk/Documentation/html/group__HTMR__SEC.js b/lib/sdk/Documentation/html/group__HTMR__SEC.js
new file mode 100644
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@@ -0,0 +1,5 @@
+var group__HTMR__SEC =
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+];
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-    [ "MXC_F_I2C_INT_EN1_TX_UNDERFLOW", "group__I2C__INT__EN1.html#gae7d0d8d7aa75c415be274b0320fee224", null ]
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+    [ "MXC_F_I2C_INT_EN1_START_POS", "group__I2C__INT__EN1.html#ga75acf6309e89235c523774c9a4024cc8", null ],
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--- a/lib/sdk/Documentation/html/group__I2C__SLAVE__ADDR.js
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 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__I2C__STATUS.js b/lib/sdk/Documentation/html/group__I2C__STATUS.js
index aab72eee8dbd312b79eb8f7a07a2130146063506..edf2ff745840faa200fc3633119de92e23375c79 100644
--- a/lib/sdk/Documentation/html/group__I2C__STATUS.js
+++ b/lib/sdk/Documentation/html/group__I2C__STATUS.js
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diff --git a/lib/sdk/Documentation/html/group__I2C__TX__CTRL0.html b/lib/sdk/Documentation/html/group__I2C__TX__CTRL0.html
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--- a/lib/sdk/Documentation/html/group__I2C__TX__CTRL0.html
+++ b/lib/sdk/Documentation/html/group__I2C__TX__CTRL0.html
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index f500da1bd0484e443c860932d90cb8e534e34f9c..e10ef702730b3eef8ce5956450126be07beddea0 100644
--- a/lib/sdk/Documentation/html/group__I2C__TX__CTRL0.js
+++ b/lib/sdk/Documentation/html/group__I2C__TX__CTRL0.js
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     [ "MXC_F_I2C_TX_CTRL0_TX_READY_MODE", "group__I2C__TX__CTRL0.html#ga26af00f81b0cd84aba67440058a022b8", null ],
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+    [ "MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD", "group__I2C__TX__CTRL0.html#ga189de16f7f78a1d65e9aece0bd5d4116", null ],
+    [ "MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS", "group__I2C__TX__CTRL0.html#ga3e9fae8b136784898c9d6daf2f331cf4", null ],
+    [ "MXC_F_I2C_TX_CTRL0_TX_AMW_AFD", "group__I2C__TX__CTRL0.html#ga4543f5eb5c086a1133d624b6162981f0", null ],
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+    [ "MXC_F_I2C_TX_CTRL0_TX_AMR_AFD", "group__I2C__TX__CTRL0.html#ga9746703e5e01e63d5496f33b1b200b92", null ],
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index 621be022707df53be91718f0c4576e8cce7e7156..fa1bf04c0602d81cbaab96e44060c05685e8679f 100644
--- a/lib/sdk/Documentation/html/group__OWM__CTRL__STAT.html
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__OWM__CTRL__STAT.html#gabe65c782f5b84f611654ee1bb62c9a64">MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS</a>&#160;&#160;&#160;4</td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__PWRSEQ__LPCN.html#gaca87c53fefb8cf5d93dc114639486405">MXC_S_PWRSEQ_LPCN_OVR_0_9V</a>&#160;&#160;&#160;(<a class="el" href="group__PWRSEQ__LPCN.html#gaf0661a8a4ab2d239da09fdef4bd53f2d">MXC_V_PWRSEQ_LPCN_OVR_0_9V</a> &lt;&lt; <a class="el" href="group__PWRSEQ__LPCN.html#ga411c4daefb36a07ba8161c5665a6596b">MXC_F_PWRSEQ_LPCN_OVR_POS</a>)</td></tr>
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 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__PWRSEQ__LPCN.js b/lib/sdk/Documentation/html/group__PWRSEQ__LPCN.js
index 881e86292a92a2df1516d5f811c42b9dc845536e..595f361689c773ae8a8dff5015cca7a064349b82 100644
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 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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+   <div id="projectname">MAX32665 SDK Documentation
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+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
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+</div><!--header-->
+<div class="contents">
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+<p>Low Power I/O Wakeup Enable Register 1.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__PWRSEQ__LPWKEN1.html#gab1631819e3a4f2e2e82f36c90ea1dd49">MXC_F_PWRSEQ_LPWKEN1_WAKEEN</a>&#160;&#160;&#160;((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS))</td></tr>
+<tr class="memdesc:gab1631819e3a4f2e2e82f36c90ea1dd49"><td class="mdescLeft">&#160;</td><td class="mdescRight">LPWKEN1_WAKEEN Mask. <br /></td></tr>
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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<p>This register enables low power wakeup functionality for GPIO1. </p>
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+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
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+<title>MAX32665 SDK Documentation: PWRSEQ_LPWKST1</title>
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">MAX32665 SDK Documentation
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+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
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+<!-- Generated by Doxygen 1.8.13 -->
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+</div><!--header-->
+<div class="contents">
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+<p>Low Power I/O Wakeup Status Register 1.  
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+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+<tr class="memdesc:ga892e5b881f116b1dc635bc6cfec92f0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">LPWKST1_WAKEST Mask. <br /></td></tr>
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+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<p>This register indicates the low power wakeup status for GPIO1. </p>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
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+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
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+   <div id="projectname">MAX32665 SDK Documentation
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+<a href="#define-members">Macros</a>  </div>
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+<div class="title">RPU_ICC1<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<a href="#define-members">Macros</a>  </div>
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+</div><!--header-->
+<div class="contents">
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-<p>QSPI0 Protection Register.  
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-Macros</h2></td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__QSPI0.html#ga88425e260324c897d27e322cd2c936ac">MXC_F_RPU_QSPI0_USBACNR</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_USBACNR_POS))</td></tr>
-<tr class="memdesc:ga88425e260324c897d27e322cd2c936ac"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI0_USBACNR Mask. <br /></td></tr>
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diff --git a/lib/sdk/Documentation/html/group__RPU__Register__Offsets.html b/lib/sdk/Documentation/html/group__RPU__Register__Offsets.html
index ecf968fefedb8e221a9b7ccfad4691ce982b2b1f..127595ce5a3e29fb2909cbfc3bd8ace2760a8b24 100644
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga3782ba8b5448573834be52c54d7b36a6">MXC_R_RPU_I2C2</a>&#160;&#160;&#160;((uint32_t)0x000001F0UL)</td></tr>
-<tr class="memdesc:ga3782ba8b5448573834be52c54d7b36a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x01F0</code> <br /></td></tr>
-<tr class="separator:ga3782ba8b5448573834be52c54d7b36a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:ga6be2aeefa0e54c4269d488de15b342dc"><td class="memItemLeft" align="right" valign="top"><a id="ga6be2aeefa0e54c4269d488de15b342dc"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga6be2aeefa0e54c4269d488de15b342dc">MXC_R_RPU_SPIXIPM</a>&#160;&#160;&#160;((uint32_t)0x00000260UL)</td></tr>
-<tr class="memdesc:ga6be2aeefa0e54c4269d488de15b342dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0260</code> <br /></td></tr>
-<tr class="separator:ga6be2aeefa0e54c4269d488de15b342dc"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:ga27265f4239201e692c712210d163545a"><td class="memItemLeft" align="right" valign="top"><a id="ga27265f4239201e692c712210d163545a"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga27265f4239201e692c712210d163545a">MXC_R_RPU_SPIXIPMC</a>&#160;&#160;&#160;((uint32_t)0x00000270UL)</td></tr>
-<tr class="memdesc:ga27265f4239201e692c712210d163545a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0270</code> <br /></td></tr>
-<tr class="separator:ga27265f4239201e692c712210d163545a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaefb51f683d5b95a5eb7f8b96baa916e0"><td class="memItemLeft" align="right" valign="top"><a id="gaefb51f683d5b95a5eb7f8b96baa916e0"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaefb51f683d5b95a5eb7f8b96baa916e0">MXC_R_RPU_I2C0_BUS0</a>&#160;&#160;&#160;((uint32_t)0x000001D0UL)</td></tr>
+<tr class="memdesc:gaefb51f683d5b95a5eb7f8b96baa916e0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x01D0</code> <br /></td></tr>
+<tr class="separator:gaefb51f683d5b95a5eb7f8b96baa916e0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga35491a688595e6a95011d50b045fa087"><td class="memItemLeft" align="right" valign="top"><a id="ga35491a688595e6a95011d50b045fa087"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga35491a688595e6a95011d50b045fa087">MXC_R_RPU_I2C1_BUS0</a>&#160;&#160;&#160;((uint32_t)0x000001E0UL)</td></tr>
+<tr class="memdesc:ga35491a688595e6a95011d50b045fa087"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x01E0</code> <br /></td></tr>
+<tr class="separator:ga35491a688595e6a95011d50b045fa087"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga3c770e9f2dac8ddb3d8811ab78ed4ec5"><td class="memItemLeft" align="right" valign="top"><a id="ga3c770e9f2dac8ddb3d8811ab78ed4ec5"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga3c770e9f2dac8ddb3d8811ab78ed4ec5">MXC_R_RPU_I2C2_BUS0</a>&#160;&#160;&#160;((uint32_t)0x000001F0UL)</td></tr>
+<tr class="memdesc:ga3c770e9f2dac8ddb3d8811ab78ed4ec5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x01F0</code> <br /></td></tr>
+<tr class="separator:ga3c770e9f2dac8ddb3d8811ab78ed4ec5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae1db0eeb2bf918bcd61de3eb74150a9d"><td class="memItemLeft" align="right" valign="top"><a id="gae1db0eeb2bf918bcd61de3eb74150a9d"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gae1db0eeb2bf918bcd61de3eb74150a9d">MXC_R_RPU_SPIXFM</a>&#160;&#160;&#160;((uint32_t)0x00000260UL)</td></tr>
+<tr class="memdesc:gae1db0eeb2bf918bcd61de3eb74150a9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0260</code> <br /></td></tr>
+<tr class="separator:gae1db0eeb2bf918bcd61de3eb74150a9d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga36ab22a27b914e37e8ac89738b311409"><td class="memItemLeft" align="right" valign="top"><a id="ga36ab22a27b914e37e8ac89738b311409"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga36ab22a27b914e37e8ac89738b311409">MXC_R_RPU_SPIXFC</a>&#160;&#160;&#160;((uint32_t)0x00000270UL)</td></tr>
+<tr class="memdesc:ga36ab22a27b914e37e8ac89738b311409"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0270</code> <br /></td></tr>
+<tr class="separator:ga36ab22a27b914e37e8ac89738b311409"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:ga057a038e76a4e64b85b8ae1a1efea609"><td class="memItemLeft" align="right" valign="top"><a id="ga057a038e76a4e64b85b8ae1a1efea609"></a>
 #define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga057a038e76a4e64b85b8ae1a1efea609">MXC_R_RPU_DMA0</a>&#160;&#160;&#160;((uint32_t)0x00000280UL)</td></tr>
 <tr class="memdesc:ga057a038e76a4e64b85b8ae1a1efea609"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0280</code> <br /></td></tr>
@@ -211,22 +211,22 @@ Macros</h2></td></tr>
 #define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga0bc3cc9ea9796806169c81de21f64850">MXC_R_RPU_FLC1</a>&#160;&#160;&#160;((uint32_t)0x00000294UL)</td></tr>
 <tr class="memdesc:ga0bc3cc9ea9796806169c81de21f64850"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0294</code> <br /></td></tr>
 <tr class="separator:ga0bc3cc9ea9796806169c81de21f64850"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gac36de9b35c4c19ac0261ea7dbedf87fe"><td class="memItemLeft" align="right" valign="top"><a id="gac36de9b35c4c19ac0261ea7dbedf87fe"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gac36de9b35c4c19ac0261ea7dbedf87fe">MXC_R_RPU_ICACHE0</a>&#160;&#160;&#160;((uint32_t)0x000002A0UL)</td></tr>
-<tr class="memdesc:gac36de9b35c4c19ac0261ea7dbedf87fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x02A0</code> <br /></td></tr>
-<tr class="separator:gac36de9b35c4c19ac0261ea7dbedf87fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gab2811596dad4ed289cf61ba37758efd3"><td class="memItemLeft" align="right" valign="top"><a id="gab2811596dad4ed289cf61ba37758efd3"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gab2811596dad4ed289cf61ba37758efd3">MXC_R_RPU_ICACHE1</a>&#160;&#160;&#160;((uint32_t)0x000002A4UL)</td></tr>
-<tr class="memdesc:gab2811596dad4ed289cf61ba37758efd3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x02A4</code> <br /></td></tr>
-<tr class="separator:gab2811596dad4ed289cf61ba37758efd3"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:ga5d8f7ae5b0005a179405fc2b3eb803c3"><td class="memItemLeft" align="right" valign="top"><a id="ga5d8f7ae5b0005a179405fc2b3eb803c3"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga5d8f7ae5b0005a179405fc2b3eb803c3">MXC_R_RPU_ICACHEXIP</a>&#160;&#160;&#160;((uint32_t)0x000002F0UL)</td></tr>
-<tr class="memdesc:ga5d8f7ae5b0005a179405fc2b3eb803c3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x02F0</code> <br /></td></tr>
-<tr class="separator:ga5d8f7ae5b0005a179405fc2b3eb803c3"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gaed262a7e25af135fc96803ebf4857d2a"><td class="memItemLeft" align="right" valign="top"><a id="gaed262a7e25af135fc96803ebf4857d2a"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaed262a7e25af135fc96803ebf4857d2a">MXC_R_RPU_DCACHE</a>&#160;&#160;&#160;((uint32_t)0x00000330UL)</td></tr>
-<tr class="memdesc:gaed262a7e25af135fc96803ebf4857d2a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0330</code> <br /></td></tr>
-<tr class="separator:gaed262a7e25af135fc96803ebf4857d2a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga25089af9382221427f076a0a744dcbc0"><td class="memItemLeft" align="right" valign="top"><a id="ga25089af9382221427f076a0a744dcbc0"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga25089af9382221427f076a0a744dcbc0">MXC_R_RPU_ICC0</a>&#160;&#160;&#160;((uint32_t)0x000002A0UL)</td></tr>
+<tr class="memdesc:ga25089af9382221427f076a0a744dcbc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x02A0</code> <br /></td></tr>
+<tr class="separator:ga25089af9382221427f076a0a744dcbc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga4b79d6a28a97c7e4672d87343f6e000a"><td class="memItemLeft" align="right" valign="top"><a id="ga4b79d6a28a97c7e4672d87343f6e000a"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga4b79d6a28a97c7e4672d87343f6e000a">MXC_R_RPU_ICC1</a>&#160;&#160;&#160;((uint32_t)0x000002A4UL)</td></tr>
+<tr class="memdesc:ga4b79d6a28a97c7e4672d87343f6e000a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x02A4</code> <br /></td></tr>
+<tr class="separator:ga4b79d6a28a97c7e4672d87343f6e000a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa5c2e1662d3e38eeb649437d5ea7b732"><td class="memItemLeft" align="right" valign="top"><a id="gaa5c2e1662d3e38eeb649437d5ea7b732"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaa5c2e1662d3e38eeb649437d5ea7b732">MXC_R_RPU_SFCC</a>&#160;&#160;&#160;((uint32_t)0x000002F0UL)</td></tr>
+<tr class="memdesc:gaa5c2e1662d3e38eeb649437d5ea7b732"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x02F0</code> <br /></td></tr>
+<tr class="separator:gaa5c2e1662d3e38eeb649437d5ea7b732"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga5f1e62fc14fe4e1804029026aef6a31c"><td class="memItemLeft" align="right" valign="top"><a id="ga5f1e62fc14fe4e1804029026aef6a31c"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga5f1e62fc14fe4e1804029026aef6a31c">MXC_R_RPU_SRCC</a>&#160;&#160;&#160;((uint32_t)0x00000330UL)</td></tr>
+<tr class="memdesc:ga5f1e62fc14fe4e1804029026aef6a31c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0330</code> <br /></td></tr>
+<tr class="separator:ga5f1e62fc14fe4e1804029026aef6a31c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:ga5ddb3702ca58e824b39080fd943ad0e8"><td class="memItemLeft" align="right" valign="top"><a id="ga5ddb3702ca58e824b39080fd943ad0e8"></a>
 #define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga5ddb3702ca58e824b39080fd943ad0e8">MXC_R_RPU_ADC</a>&#160;&#160;&#160;((uint32_t)0x00000340UL)</td></tr>
 <tr class="memdesc:ga5ddb3702ca58e824b39080fd943ad0e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0340</code> <br /></td></tr>
@@ -243,14 +243,14 @@ Macros</h2></td></tr>
 #define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gac35bab8d18cc60bf5a2c26e6ac570fc8">MXC_R_RPU_SDHCCTRL</a>&#160;&#160;&#160;((uint32_t)0x00000370UL)</td></tr>
 <tr class="memdesc:gac35bab8d18cc60bf5a2c26e6ac570fc8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0370</code> <br /></td></tr>
 <tr class="separator:gac35bab8d18cc60bf5a2c26e6ac570fc8"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gae16a302687610cb6cfaf2f06b92f3945"><td class="memItemLeft" align="right" valign="top"><a id="gae16a302687610cb6cfaf2f06b92f3945"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gae16a302687610cb6cfaf2f06b92f3945">MXC_R_RPU_SPID</a>&#160;&#160;&#160;((uint32_t)0x000003A0UL)</td></tr>
-<tr class="memdesc:gae16a302687610cb6cfaf2f06b92f3945"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x03A0</code> <br /></td></tr>
-<tr class="separator:gae16a302687610cb6cfaf2f06b92f3945"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gac45db9f28336917b0ad4ec34e10fedb8"><td class="memItemLeft" align="right" valign="top"><a id="gac45db9f28336917b0ad4ec34e10fedb8"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gac45db9f28336917b0ad4ec34e10fedb8">MXC_R_RPU_PT</a>&#160;&#160;&#160;((uint32_t)0x000003C0UL)</td></tr>
-<tr class="memdesc:gac45db9f28336917b0ad4ec34e10fedb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x03C0</code> <br /></td></tr>
-<tr class="separator:gac45db9f28336917b0ad4ec34e10fedb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga81a72a43bdfa013b0483f14367077d90"><td class="memItemLeft" align="right" valign="top"><a id="ga81a72a43bdfa013b0483f14367077d90"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga81a72a43bdfa013b0483f14367077d90">MXC_R_RPU_SPIXR</a>&#160;&#160;&#160;((uint32_t)0x000003A0UL)</td></tr>
+<tr class="memdesc:ga81a72a43bdfa013b0483f14367077d90"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x03A0</code> <br /></td></tr>
+<tr class="separator:ga81a72a43bdfa013b0483f14367077d90"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga3d11b03929af18e7a7a25937b1c9b63c"><td class="memItemLeft" align="right" valign="top"><a id="ga3d11b03929af18e7a7a25937b1c9b63c"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga3d11b03929af18e7a7a25937b1c9b63c">MXC_R_RPU_PTG_BUS0</a>&#160;&#160;&#160;((uint32_t)0x000003C0UL)</td></tr>
+<tr class="memdesc:ga3d11b03929af18e7a7a25937b1c9b63c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x03C0</code> <br /></td></tr>
+<tr class="separator:ga3d11b03929af18e7a7a25937b1c9b63c"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:ga2f9642cfb30ad9b3022f70b6866a7b66"><td class="memItemLeft" align="right" valign="top"><a id="ga2f9642cfb30ad9b3022f70b6866a7b66"></a>
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 <tr class="memdesc:ga2f9642cfb30ad9b3022f70b6866a7b66"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x03D0</code> <br /></td></tr>
@@ -271,14 +271,14 @@ Macros</h2></td></tr>
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 <tr class="separator:gac516a6afad33b1224b22756bf1eb996c"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gae15f816006a79932498b5ecb7ca815be"><td class="memItemLeft" align="right" valign="top"><a id="gae15f816006a79932498b5ecb7ca815be"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gae15f816006a79932498b5ecb7ca815be">MXC_R_RPU_QSPI1</a>&#160;&#160;&#160;((uint32_t)0x00000460UL)</td></tr>
-<tr class="memdesc:gae15f816006a79932498b5ecb7ca815be"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0460</code> <br /></td></tr>
-<tr class="separator:gae15f816006a79932498b5ecb7ca815be"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:gabeb20fbe45ae0c66dd64e810e63981ca"><td class="memItemLeft" align="right" valign="top"><a id="gabeb20fbe45ae0c66dd64e810e63981ca"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gabeb20fbe45ae0c66dd64e810e63981ca">MXC_R_RPU_QSPI2</a>&#160;&#160;&#160;((uint32_t)0x00000480UL)</td></tr>
-<tr class="memdesc:gabeb20fbe45ae0c66dd64e810e63981ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0480</code> <br /></td></tr>
-<tr class="separator:gabeb20fbe45ae0c66dd64e810e63981ca"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga6e25854a9510774e7aa70a1cd10f79c9"><td class="memItemLeft" align="right" valign="top"><a id="ga6e25854a9510774e7aa70a1cd10f79c9"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga6e25854a9510774e7aa70a1cd10f79c9">MXC_R_RPU_SPI1</a>&#160;&#160;&#160;((uint32_t)0x00000460UL)</td></tr>
+<tr class="memdesc:ga6e25854a9510774e7aa70a1cd10f79c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from RPU Base Address: <code> 0x0460</code> <br /></td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga50ac3cdb93d1c48ace45667fec075bfe">MXC_R_RPU_SPI2</a>&#160;&#160;&#160;((uint32_t)0x00000480UL)</td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga8fc796061e0da47243c5094a440b24af">MXC_R_RPU_SPIXIPMFIFO</a>&#160;&#160;&#160;((uint32_t)0x00000BC0UL)</td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaf0edccb0dc771f958b394f1d43f1c724">MXC_R_RPU_QSPI0</a>&#160;&#160;&#160;((uint32_t)0x00000BE0UL)</td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaa89e41fc29f41d205182c2b5c1562fb4">MXC_R_RPU_SRAM0</a>&#160;&#160;&#160;((uint32_t)0x00000F00UL)</td></tr>
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-<tr class="separator:ga17c7ebc31497a1b176b5a43aeec56120"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga01858d55ade4d3d95e4b816b205a614c">MXC_R_RPU_SPIXM_FIFO</a>&#160;&#160;&#160;((uint32_t)0x00000BC0UL)</td></tr>
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+<tr class="memitem:gaaead5559747a6cf80244155c9a3fb00d"><td class="memItemLeft" align="right" valign="top"><a id="gaaead5559747a6cf80244155c9a3fb00d"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaaead5559747a6cf80244155c9a3fb00d">MXC_R_RPU_SPI0</a>&#160;&#160;&#160;((uint32_t)0x00000BE0UL)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga9adb439090f1e123ea26b27419b78e0d">MXC_R_RPU_SYSRAM0</a>&#160;&#160;&#160;((uint32_t)0x00000F00UL)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga3b02a3527d90fe72a9370275c10e0a7f">MXC_R_RPU_SYSRAM1</a>&#160;&#160;&#160;((uint32_t)0x00000F10UL)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaad0aea08157e57d140a785373293a87c">MXC_R_RPU_SYSRAM2</a>&#160;&#160;&#160;((uint32_t)0x00000F20UL)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gaf535375ba256f6704127e211319dcd1b">MXC_R_RPU_SYSRAM3</a>&#160;&#160;&#160;((uint32_t)0x00000F30UL)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga646bc7e0120b60ddb0f1685e73a730e2">MXC_R_RPU_SYSRAM4</a>&#160;&#160;&#160;((uint32_t)0x00000F40UL)</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#gab62de04717839368cc2d2f4069ce5b00">MXC_R_RPU_SYSRAM5</a>&#160;&#160;&#160;((uint32_t)0x00000F50UL)</td></tr>
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+<tr class="separator:gab62de04717839368cc2d2f4069ce5b00"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__Register__Offsets.html#ga3d076f2b8bc705e27a68c4aab0d79113">MXC_R_RPU_SYSRAM6</a>&#160;&#160;&#160;((uint32_t)0x00000F60UL)</td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
 </div><!-- contents -->
diff --git a/lib/sdk/Documentation/html/group__RPU__Register__Offsets.js b/lib/sdk/Documentation/html/group__RPU__Register__Offsets.js
index cd175aeb77cceeac01ef36783301424a06f779e7..be1264d58f70e333db3932cac01d4b5747b5f7a2 100644
--- a/lib/sdk/Documentation/html/group__RPU__Register__Offsets.js
+++ b/lib/sdk/Documentation/html/group__RPU__Register__Offsets.js
@@ -14,7 +14,7 @@ var group__RPU__Register__Offsets =
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     [ "MXC_R_RPU_WUT", "group__RPU__Register__Offsets.html#ga195ab65b469105cd3b9f94f39a9f2211", null ],
     [ "MXC_R_RPU_PWRSEQ", "group__RPU__Register__Offsets.html#ga3aa16487adf823d6da62ef102304513a", null ],
-    [ "MXC_R_RPU_BBCR", "group__RPU__Register__Offsets.html#ga7b36e48cb85c710ed58a1f5dc762d6f5", null ],
+    [ "MXC_R_RPU_MCR", "group__RPU__Register__Offsets.html#ga21b6c3af682ef64e5178e15e509588da", null ],
     [ "MXC_R_RPU_GPIO0", "group__RPU__Register__Offsets.html#ga75ed135f829f917e0a5df435779b6cb9", null ],
     [ "MXC_R_RPU_GPIO1", "group__RPU__Register__Offsets.html#ga6485a93c06828e0a150fed7a9f606416", null ],
     [ "MXC_R_RPU_TMR0", "group__RPU__Register__Offsets.html#gab2d78a4ac627079ab600e4d70f37f9d6", null ],
@@ -25,43 +25,43 @@ var group__RPU__Register__Offsets =
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     [ "MXC_R_RPU_HTIMER1", "group__RPU__Register__Offsets.html#gaa58379e2534bb94356a25513fcd63fb9", null ],
-    [ "MXC_R_RPU_I2C0", "group__RPU__Register__Offsets.html#ga43082d71a4f3f0d11685dc4d887776fc", null ],
-    [ "MXC_R_RPU_I2C1", "group__RPU__Register__Offsets.html#ga0f1eb3de53098d80fc5fac38a33694df", null ],
-    [ "MXC_R_RPU_I2C2", "group__RPU__Register__Offsets.html#ga3782ba8b5448573834be52c54d7b36a6", null ],
-    [ "MXC_R_RPU_SPIXIPM", "group__RPU__Register__Offsets.html#ga6be2aeefa0e54c4269d488de15b342dc", null ],
-    [ "MXC_R_RPU_SPIXIPMC", "group__RPU__Register__Offsets.html#ga27265f4239201e692c712210d163545a", null ],
+    [ "MXC_R_RPU_I2C0_BUS0", "group__RPU__Register__Offsets.html#gaefb51f683d5b95a5eb7f8b96baa916e0", null ],
+    [ "MXC_R_RPU_I2C1_BUS0", "group__RPU__Register__Offsets.html#ga35491a688595e6a95011d50b045fa087", null ],
+    [ "MXC_R_RPU_I2C2_BUS0", "group__RPU__Register__Offsets.html#ga3c770e9f2dac8ddb3d8811ab78ed4ec5", null ],
+    [ "MXC_R_RPU_SPIXFM", "group__RPU__Register__Offsets.html#gae1db0eeb2bf918bcd61de3eb74150a9d", null ],
+    [ "MXC_R_RPU_SPIXFC", "group__RPU__Register__Offsets.html#ga36ab22a27b914e37e8ac89738b311409", null ],
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     [ "MXC_R_RPU_FLC1", "group__RPU__Register__Offsets.html#ga0bc3cc9ea9796806169c81de21f64850", null ],
-    [ "MXC_R_RPU_ICACHE0", "group__RPU__Register__Offsets.html#gac36de9b35c4c19ac0261ea7dbedf87fe", null ],
-    [ "MXC_R_RPU_ICACHE1", "group__RPU__Register__Offsets.html#gab2811596dad4ed289cf61ba37758efd3", null ],
-    [ "MXC_R_RPU_ICACHEXIP", "group__RPU__Register__Offsets.html#ga5d8f7ae5b0005a179405fc2b3eb803c3", null ],
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+  <td id="projectlogo" style="vertical-align:middle"><img alt="Logo" style="width:144px;height:63px;" src="MI_Logo_Small_Pos_RGB_150dpi.png"/></td>
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+   <div id="projectname">MAX32665 SDK Documentation
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+   <div id="projectbrief">Software Development Kit Overview and API Documentation</div>
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+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SPI0<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<p>QSPI0 Protection Register.  
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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">
+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/lib/sdk/Documentation/html/group__RPU__SPI0.js b/lib/sdk/Documentation/html/group__RPU__SPI0.js
new file mode 100644
index 0000000000000000000000000000000000000000..8055bfe7a72af39e0521d33349cb0a72445567b8
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__RPU__SPI0.js
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+   <div id="projectname">MAX32665 SDK Documentation
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+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SPI1<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<p>QSPI1 Protection Register.  
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+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
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+   <div id="projectname">MAX32665 SDK Documentation
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+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SPI2<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<p>QSPI2 Protection Register.  
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+  </ul>
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+   <div id="projectname">MAX32665 SDK Documentation
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+<a href="#define-members">Macros</a>  </div>
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+<div class="title">RPU_SPIXM_FIFO<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<p>SPI XIP Master FIFO Protection Register.  
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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">
+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/lib/sdk/Documentation/html/group__RPU__SPIXM__FIFO.js b/lib/sdk/Documentation/html/group__RPU__SPIXM__FIFO.js
new file mode 100644
index 0000000000000000000000000000000000000000..a40053319d414f2d8512a2cc9cb3d1e4a539a113
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__RPU__SPIXM__FIFO.js
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+  <td id="projectalign" style="padding-left: 0.5em;">
+   <div id="projectname">MAX32665 SDK Documentation
+   &#160;<span id="projectnumber">0.2</span>
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+   <div id="projectbrief">Software Development Kit Overview and API Documentation</div>
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+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SPIXR<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<p>SPI Data Controller Protection Register.  
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-<a href="#define-members">Macros</a>  </div>
-  <div class="headertitle">
-<div class="title">RPU_SRAM1<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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-<div class="contents">
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-<p>SRAM1 Protection Register.  
-<a href="#details">More...</a></p>
-<table class="memberdecls">
-<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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-<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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+   <div id="projectname">MAX32665 SDK Documentation
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+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SYSRAM0<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<p>SYSRAM0 Protection Register.  
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+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
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+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SYSRAM2<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">
+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
+</div>
+</body>
+</html>
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new file mode 100644
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+<a href="#define-members">Macros</a>  </div>
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+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">
+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
+</div>
+</body>
+</html>
diff --git a/lib/sdk/Documentation/html/group__RPU__SYSRAM3.js b/lib/sdk/Documentation/html/group__RPU__SYSRAM3.js
new file mode 100644
index 0000000000000000000000000000000000000000..659acfc81d296b9e18e5c38ef4974064e74cca61
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__RPU__SYSRAM3.js
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+   <div id="projectname">MAX32665 SDK Documentation
+   &#160;<span id="projectnumber">0.2</span>
+   </div>
+   <div id="projectbrief">Software Development Kit Overview and API Documentation</div>
+  </td>
+ </tr>
+ </tbody>
+</table>
+</div>
+<!-- end header part -->
+<!-- Generated by Doxygen 1.8.13 -->
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+       class="ui-resizable-handle">
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+$(document).ready(function(){initNavTree('group__RPU__SYSRAM5.html','');});
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+<div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RPU_SYSRAM5<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> &raquo; <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div>  </div>
+</div><!--header-->
+<div class="contents">
+
+<p>SYSRAM5 Protection Register.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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+</div><!-- contents -->
+</div><!-- doc-content -->
+<!-- HTML footer for doxygen 1.8.12-->
+<!-- start footer part -->
+<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->
+  <ul>
+    <li class="footer">
+    <a href="http://www.maximintegrated.com/index.html">
+    <img class="footer" align="middle" src="MI_Logo_Small_Footer_RGB_150dpi.png" alt="Maxim Integrated"/></a> 0.2 </li>
+  </ul>
+</div>
+</body>
+</html>
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diff --git a/lib/sdk/Documentation/html/group__RTC__CTRL.html b/lib/sdk/Documentation/html/group__RTC__CTRL.html
index b7132c90c4000db0de77320dd940481aa4479ac6..06fa01fd1dd5dbfb306a404f6782a2a15cfa593b 100644
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index 5f0f1d7b55ee49fb3eac709f1f962bc0886ff2a4..4d9e3a6afd53f3d2fc0aef7bd5bd645625ea0f93 100644
--- a/lib/sdk/Documentation/html/group__RTC__SSEC.html
+++ b/lib/sdk/Documentation/html/group__RTC__SSEC.html
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__SSEC.html#gab16841aee1aba935eb428d9ed58a471d">MXC_F_RTC_SSEC_RTSS_POS</a>&#160;&#160;&#160;0</td></tr>
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+<tr class="memitem:gafdaa58b891651572600f9431f43fe3a9"><td class="memItemLeft" align="right" valign="top"><a id="gafdaa58b891651572600f9431f43fe3a9"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__SSEC.html#gafdaa58b891651572600f9431f43fe3a9">MXC_F_RTC_SSEC_SSEC_POS</a>&#160;&#160;&#160;0</td></tr>
+<tr class="memdesc:gafdaa58b891651572600f9431f43fe3a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSEC_SSEC Position. <br /></td></tr>
+<tr class="separator:gafdaa58b891651572600f9431f43fe3a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa638cc42213fa96b0a402679cdcb588a"><td class="memItemLeft" align="right" valign="top"><a id="gaa638cc42213fa96b0a402679cdcb588a"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__SSEC.html#gaa638cc42213fa96b0a402679cdcb588a">MXC_F_RTC_SSEC_SSEC</a>&#160;&#160;&#160;((uint32_t)(0xFFUL &lt;&lt; MXC_F_RTC_SSEC_SSEC_POS))</td></tr>
+<tr class="memdesc:gaa638cc42213fa96b0a402679cdcb588a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSEC_SSEC Mask. <br /></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__RTC__SSEC.js b/lib/sdk/Documentation/html/group__RTC__SSEC.js
index 8734a8cf8863b7ad45a5420599443adfdbf7abe0..cc4c9fc33a4bd923bc81a70a18baed0faff4b9a8 100644
--- a/lib/sdk/Documentation/html/group__RTC__SSEC.js
+++ b/lib/sdk/Documentation/html/group__RTC__SSEC.js
@@ -1,5 +1,5 @@
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-    [ "MXC_F_RTC_SSEC_RTSS", "group__RTC__SSEC.html#ga309c0ca5a1b0dd0d7f9dc1999156864a", null ]
+    [ "MXC_F_RTC_SSEC_SSEC_POS", "group__RTC__SSEC.html#gafdaa58b891651572600f9431f43fe3a9", null ],
+    [ "MXC_F_RTC_SSEC_SSEC", "group__RTC__SSEC.html#gaa638cc42213fa96b0a402679cdcb588a", null ]
 ];
\ No newline at end of file
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similarity index 58%
rename from lib/sdk/Documentation/html/functions_vars_q.html
rename to lib/sdk/Documentation/html/group__RTC__SSECA.html
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+<title>MAX32665 SDK Documentation: RTC_SSECA</title>
 <link href="tabs.css" rel="stylesheet" type="text/css"/>
 <script type="text/javascript" src="jquery.js"></script>
 <script type="text/javascript" src="dynsections.js"></script>
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 </div>
 <script type="text/javascript">
-$(document).ready(function(){initNavTree('functions_vars_q.html','');});
+$(document).ready(function(){initNavTree('group__RTC__SSECA.html','');});
 </script>
 <div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">RTC_SSECA<div class="ingroups"><a class="el" href="group__rtc.html">RTC</a> &raquo; <a class="el" href="group__rtc__registers.html">RTC_Registers</a></div></div>  </div>
+</div><!--header-->
 <div class="contents">
-&#160;
 
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-: <a class="el" href="structmxc__rpu__regs__t.html#aa9bf22e9a1dc0d8436bace1228c1cfd1">mxc_rpu_regs_t</a>
-</li>
-</ul>
+<p>RTC sub-second alarm.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga931a51b7b73776149b20f9bcd0e4ef95"><td class="memItemLeft" align="right" valign="top"><a id="ga931a51b7b73776149b20f9bcd0e4ef95"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__SSECA.html#ga931a51b7b73776149b20f9bcd0e4ef95">MXC_F_RTC_SSECA_SSEC_ALARM_POS</a>&#160;&#160;&#160;0</td></tr>
+<tr class="memdesc:ga931a51b7b73776149b20f9bcd0e4ef95"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSECA_SSEC_ALARM Position. <br /></td></tr>
+<tr class="separator:ga931a51b7b73776149b20f9bcd0e4ef95"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga851dcc91e76b84e2633161f5b34c01d3"><td class="memItemLeft" align="right" valign="top"><a id="ga851dcc91e76b84e2633161f5b34c01d3"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__SSECA.html#ga851dcc91e76b84e2633161f5b34c01d3">MXC_F_RTC_SSECA_SSEC_ALARM</a>&#160;&#160;&#160;((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_RTC_SSECA_SSEC_ALARM_POS))</td></tr>
+<tr class="memdesc:ga851dcc91e76b84e2633161f5b34c01d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSECA_SSEC_ALARM Mask. <br /></td></tr>
+<tr class="separator:ga851dcc91e76b84e2633161f5b34c01d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
+<p>This register contains the reload value for the sub- second alarm. </p>
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
diff --git a/lib/sdk/Documentation/html/group__RTC__SSECA.js b/lib/sdk/Documentation/html/group__RTC__SSECA.js
new file mode 100644
index 0000000000000000000000000000000000000000..979c8321cba12321ef04597639e8e367583c2fd7
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__RTC__SSECA.js
@@ -0,0 +1,5 @@
+var group__RTC__SSECA =
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+    [ "MXC_F_RTC_SSECA_SSEC_ALARM_POS", "group__RTC__SSECA.html#ga931a51b7b73776149b20f9bcd0e4ef95", null ],
+    [ "MXC_F_RTC_SSECA_SSEC_ALARM", "group__RTC__SSECA.html#ga851dcc91e76b84e2633161f5b34c01d3", null ]
+];
\ No newline at end of file
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-<title>MAX32665 SDK Documentation: RTC_RSSA</title>
+<title>MAX32665 SDK Documentation: RTC_TODA</title>
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 <script type="text/javascript" src="jquery.js"></script>
 <script type="text/javascript" src="dynsections.js"></script>
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 </div>
 <script type="text/javascript">
-$(document).ready(function(){initNavTree('group__RTC__RSSA.html','');});
+$(document).ready(function(){initNavTree('group__RTC__TODA.html','');});
 </script>
 <div id="doc-content">
 <div class="header">
   <div class="summary">
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+<div class="title">RTC_TODA<div class="ingroups"><a class="el" href="group__rtc.html">RTC</a> &raquo; <a class="el" href="group__rtc__registers.html">RTC_Registers</a></div></div>  </div>
 </div><!--header-->
 <div class="contents">
 
-<p>RTC sub-second alarm.  
+<p>Time-of-day Alarm.  
 <a href="#details">More...</a></p>
 <table class="memberdecls">
 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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-<tr class="separator:gadf24b1af1a1603f0b56b36ca29d737a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga073d96ca04ace269124b9fb109db20fb"><td class="memItemLeft" align="right" valign="top"><a id="ga073d96ca04ace269124b9fb109db20fb"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__TODA.html#ga073d96ca04ace269124b9fb109db20fb">MXC_F_RTC_TODA_TOD_ALARM_POS</a>&#160;&#160;&#160;0</td></tr>
+<tr class="memdesc:ga073d96ca04ace269124b9fb109db20fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">TODA_TOD_ALARM Position. <br /></td></tr>
+<tr class="separator:ga073d96ca04ace269124b9fb109db20fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab21e9d34fdffcb561650af11304783ec"><td class="memItemLeft" align="right" valign="top"><a id="gab21e9d34fdffcb561650af11304783ec"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__TODA.html#gab21e9d34fdffcb561650af11304783ec">MXC_F_RTC_TODA_TOD_ALARM</a>&#160;&#160;&#160;((uint32_t)(0xFFFFFUL &lt;&lt; MXC_F_RTC_TODA_TOD_ALARM_POS))</td></tr>
+<tr class="memdesc:gab21e9d34fdffcb561650af11304783ec"><td class="mdescLeft">&#160;</td><td class="mdescRight">TODA_TOD_ALARM Mask. <br /></td></tr>
+<tr class="separator:gab21e9d34fdffcb561650af11304783ec"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
-<p>This register contains the reload value for the sub- second alarm. </p>
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
diff --git a/lib/sdk/Documentation/html/group__RTC__TODA.js b/lib/sdk/Documentation/html/group__RTC__TODA.js
new file mode 100644
index 0000000000000000000000000000000000000000..ccbde9a2c871c6c2844f99bf4a8606f3ae86e4b3
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__RTC__TODA.js
@@ -0,0 +1,5 @@
+var group__RTC__TODA =
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+    [ "MXC_F_RTC_TODA_TOD_ALARM_POS", "group__RTC__TODA.html#ga073d96ca04ace269124b9fb109db20fb", null ],
+    [ "MXC_F_RTC_TODA_TOD_ALARM", "group__RTC__TODA.html#gab21e9d34fdffcb561650af11304783ec", null ]
+];
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index d42b2fca09203e36e9e434628adee8c29eee0f5e..643209e843b68050953b26634e7caf3439770fce 100644
--- a/lib/sdk/Documentation/html/group__RTC__TRIM.html
+++ b/lib/sdk/Documentation/html/group__RTC__TRIM.html
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 <tr class="memdesc:ga86e740da97d1b31153ee646c8a6ce2bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIM_TRIM Mask. <br /></td></tr>
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-<tr class="memitem:gafea4cd0c0b3ac475a1d4d02cb2c40ca5"><td class="memItemLeft" align="right" valign="top"><a id="gafea4cd0c0b3ac475a1d4d02cb2c40ca5"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__TRIM.html#gafea4cd0c0b3ac475a1d4d02cb2c40ca5">MXC_F_RTC_TRIM_VBATTMR_POS</a>&#160;&#160;&#160;8</td></tr>
-<tr class="memdesc:gafea4cd0c0b3ac475a1d4d02cb2c40ca5"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIM_VBATTMR Position. <br /></td></tr>
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-<tr class="memdesc:gae8a3888487e827eb64f789d9ef4e1ad7"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIM_VBATTMR Mask. <br /></td></tr>
-<tr class="separator:gae8a3888487e827eb64f789d9ef4e1ad7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gad50bc4a4caeccb1acbf1459f7ef5477c"><td class="memItemLeft" align="right" valign="top"><a id="gad50bc4a4caeccb1acbf1459f7ef5477c"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__TRIM.html#gad50bc4a4caeccb1acbf1459f7ef5477c">MXC_F_RTC_TRIM_VRTC_TMR_POS</a>&#160;&#160;&#160;8</td></tr>
+<tr class="memdesc:gad50bc4a4caeccb1acbf1459f7ef5477c"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIM_VRTC_TMR Position. <br /></td></tr>
+<tr class="separator:gad50bc4a4caeccb1acbf1459f7ef5477c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga2983c625e5b413f542e3503d2f8d5cb6"><td class="memItemLeft" align="right" valign="top"><a id="ga2983c625e5b413f542e3503d2f8d5cb6"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__TRIM.html#ga2983c625e5b413f542e3503d2f8d5cb6">MXC_F_RTC_TRIM_VRTC_TMR</a>&#160;&#160;&#160;((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_RTC_TRIM_VRTC_TMR_POS))</td></tr>
+<tr class="memdesc:ga2983c625e5b413f542e3503d2f8d5cb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">TRIM_VRTC_TMR Mask. <br /></td></tr>
+<tr class="separator:ga2983c625e5b413f542e3503d2f8d5cb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__RTC__TRIM.js b/lib/sdk/Documentation/html/group__RTC__TRIM.js
index 96d66af93783fd0f1db5d35624c96bfd9cc74758..de4e7d44eb8b6863ff80cd7f4c0e1a64fdeee6b0 100644
--- a/lib/sdk/Documentation/html/group__RTC__TRIM.js
+++ b/lib/sdk/Documentation/html/group__RTC__TRIM.js
@@ -2,6 +2,6 @@ var group__RTC__TRIM =
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-    [ "MXC_F_RTC_TRIM_VBATTMR_POS", "group__RTC__TRIM.html#gafea4cd0c0b3ac475a1d4d02cb2c40ca5", null ],
-    [ "MXC_F_RTC_TRIM_VBATTMR", "group__RTC__TRIM.html#gae8a3888487e827eb64f789d9ef4e1ad7", null ]
+    [ "MXC_F_RTC_TRIM_VRTC_TMR_POS", "group__RTC__TRIM.html#gad50bc4a4caeccb1acbf1459f7ef5477c", null ],
+    [ "MXC_F_RTC_TRIM_VRTC_TMR", "group__RTC__TRIM.html#ga2983c625e5b413f542e3503d2f8d5cb6", null ]
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__CONFIG.html#gac74d504d9231746bc49cefa243d250dd">MXC_F_SPIXFC_CONFIG_IOSMPL_POS</a>&#160;&#160;&#160;20</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__CONFIG.html#ga7c64c73b1857df74c0cc12d0e6f8f135">MXC_F_SPIXFC_CONFIG_IOSMPL</a>&#160;&#160;&#160;((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_CONFIG_IOSMPL_POS))</td></tr>
+<tr class="memdesc:ga7c64c73b1857df74c0cc12d0e6f8f135"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG_IOSMPL Mask. <br /></td></tr>
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diff --git a/lib/sdk/Documentation/html/group__SPIXFC__CONFIG.js b/lib/sdk/Documentation/html/group__SPIXFC__CONFIG.js
index ce6727bb26d65ea867f3e10539b3b01daf7513f8..6277e7f6aef23c640c29cd018009b99ed29f8dbd 100644
--- a/lib/sdk/Documentation/html/group__SPIXFC__CONFIG.js
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-    [ "MXC_S_SPIXFC_CONFIG_SS_INACT_12_CLKS", "group__SPIXFC__CONFIG.html#gabd2725b013c9eab22fc0ee1302590166", null ]
+    [ "MXC_S_SPIXFC_CONFIG_SS_INACT_12_CLKS", "group__SPIXFC__CONFIG.html#gabd2725b013c9eab22fc0ee1302590166", null ],
+    [ "MXC_F_SPIXFC_CONFIG_IOSMPL_POS", "group__SPIXFC__CONFIG.html#gac74d504d9231746bc49cefa243d250dd", null ],
+    [ "MXC_F_SPIXFC_CONFIG_IOSMPL", "group__SPIXFC__CONFIG.html#ga7c64c73b1857df74c0cc12d0e6f8f135", null ]
 ];
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index 1fcce4897a38a951975f48396e2847f63dce56f7..d476ad2bc127c726d6d151e1e03f19b04ad58b85 100644
--- a/lib/sdk/Documentation/html/group__SPIXFC__GEN__CTRL.html
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#gaef7f0691612c6d823049eb01d72af1a4">MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS</a>&#160;&#160;&#160;20</td></tr>
+<tr class="memdesc:gaef7f0691612c6d823049eb01d72af1a4"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SIMPLE Position. <br /></td></tr>
+<tr class="separator:gaef7f0691612c6d823049eb01d72af1a4"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga5d3c4aa7140c781c2ce2a64c48cfc97e"><td class="memItemLeft" align="right" valign="top"><a id="ga5d3c4aa7140c781c2ce2a64c48cfc97e"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#ga5d3c4aa7140c781c2ce2a64c48cfc97e">MXC_F_SPIXFC_GEN_CTRL_SIMPLE</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS))</td></tr>
+<tr class="memdesc:ga5d3c4aa7140c781c2ce2a64c48cfc97e"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SIMPLE Mask. <br /></td></tr>
+<tr class="separator:ga5d3c4aa7140c781c2ce2a64c48cfc97e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa82399326332c0820222c79258133c4e"><td class="memItemLeft" align="right" valign="top"><a id="gaa82399326332c0820222c79258133c4e"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#gaa82399326332c0820222c79258133c4e">MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS</a>&#160;&#160;&#160;21</td></tr>
+<tr class="memdesc:gaa82399326332c0820222c79258133c4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SIMPLERX Position. <br /></td></tr>
+<tr class="separator:gaa82399326332c0820222c79258133c4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga8e7477fb8933b11eb5e9164f6f5ce7fb"><td class="memItemLeft" align="right" valign="top"><a id="ga8e7477fb8933b11eb5e9164f6f5ce7fb"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#ga8e7477fb8933b11eb5e9164f6f5ce7fb">MXC_F_SPIXFC_GEN_CTRL_SIMPLERX</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS))</td></tr>
+<tr class="memdesc:ga8e7477fb8933b11eb5e9164f6f5ce7fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SIMPLERX Mask. <br /></td></tr>
+<tr class="separator:ga8e7477fb8933b11eb5e9164f6f5ce7fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac1be82614a59928257c3bc3dce18aed0"><td class="memItemLeft" align="right" valign="top"><a id="gac1be82614a59928257c3bc3dce18aed0"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#gac1be82614a59928257c3bc3dce18aed0">MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS</a>&#160;&#160;&#160;22</td></tr>
+<tr class="memdesc:gac1be82614a59928257c3bc3dce18aed0"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SMPLSS Position. <br /></td></tr>
+<tr class="separator:gac1be82614a59928257c3bc3dce18aed0"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#ga400feac06e267fa73d25e650ab0c26ed">MXC_F_SPIXFC_GEN_CTRL_SMPLSS</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS))</td></tr>
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+<tr class="memitem:gaad4c03803ea42c014dfd8f1d24e376f5"><td class="memItemLeft" align="right" valign="top"><a id="gaad4c03803ea42c014dfd8f1d24e376f5"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#gaad4c03803ea42c014dfd8f1d24e376f5">MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS</a>&#160;&#160;&#160;25</td></tr>
+<tr class="memdesc:gaad4c03803ea42c014dfd8f1d24e376f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SCKFBINV Position. <br /></td></tr>
+<tr class="separator:gaad4c03803ea42c014dfd8f1d24e376f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga677bbeac63a8de9508434d3efd6047f2"><td class="memItemLeft" align="right" valign="top"><a id="ga677bbeac63a8de9508434d3efd6047f2"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__GEN__CTRL.html#ga677bbeac63a8de9508434d3efd6047f2">MXC_F_SPIXFC_GEN_CTRL_SCKFBINV</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS))</td></tr>
+<tr class="memdesc:ga677bbeac63a8de9508434d3efd6047f2"><td class="mdescLeft">&#160;</td><td class="mdescRight">GEN_CTRL_SCKFBINV Mask. <br /></td></tr>
+<tr class="separator:ga677bbeac63a8de9508434d3efd6047f2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__SPIXFC__GEN__CTRL.js b/lib/sdk/Documentation/html/group__SPIXFC__GEN__CTRL.js
index a15cded5b57f43dcc2c6a77212b6970453e47b9a..e47a3bfb736c4eae4736492169593fd39faf665d 100644
--- a/lib/sdk/Documentation/html/group__SPIXFC__GEN__CTRL.js
+++ b/lib/sdk/Documentation/html/group__SPIXFC__GEN__CTRL.js
@@ -42,6 +42,14 @@ var group__SPIXFC__GEN__CTRL =
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+    [ "MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS", "group__SPIXFC__GEN__CTRL.html#gaef7f0691612c6d823049eb01d72af1a4", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SIMPLE", "group__SPIXFC__GEN__CTRL.html#ga5d3c4aa7140c781c2ce2a64c48cfc97e", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS", "group__SPIXFC__GEN__CTRL.html#gaa82399326332c0820222c79258133c4e", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SIMPLERX", "group__SPIXFC__GEN__CTRL.html#ga8e7477fb8933b11eb5e9164f6f5ce7fb", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS", "group__SPIXFC__GEN__CTRL.html#gac1be82614a59928257c3bc3dce18aed0", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SMPLSS", "group__SPIXFC__GEN__CTRL.html#ga400feac06e267fa73d25e650ab0c26ed", null ],
     [ "MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS", "group__SPIXFC__GEN__CTRL.html#ga5bc076c350b3f52e0ecd85b1c83c2e71", null ],
-    [ "MXC_F_SPIXFC_GEN_CTRL_SCLK_FB", "group__SPIXFC__GEN__CTRL.html#ga767eed2b4cca468c6940dbff2374b2d0", null ]
+    [ "MXC_F_SPIXFC_GEN_CTRL_SCLK_FB", "group__SPIXFC__GEN__CTRL.html#ga767eed2b4cca468c6940dbff2374b2d0", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS", "group__SPIXFC__GEN__CTRL.html#gaad4c03803ea42c014dfd8f1d24e376f5", null ],
+    [ "MXC_F_SPIXFC_GEN_CTRL_SCKFBINV", "group__SPIXFC__GEN__CTRL.html#ga677bbeac63a8de9508434d3efd6047f2", null ]
 ];
\ No newline at end of file
diff --git a/lib/sdk/Documentation/html/group__SPIXFC__SPCTRL.html b/lib/sdk/Documentation/html/group__SPIXFC__SPCTRL.html
index 91c7bb82227617095fee83c3b86019ba40979a6a..cd53d5e4cb10c58cd352f22af527e30135bbcb6e 100644
--- a/lib/sdk/Documentation/html/group__SPIXFC__SPCTRL.html
+++ b/lib/sdk/Documentation/html/group__SPIXFC__SPCTRL.html
@@ -79,6 +79,94 @@ $(document).ready(function(){initNavTree('group__SPIXFC__SPCTRL.html','');});
 <table class="memberdecls">
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__SPCTRL.html#ga7d0d6d355ddaebe32c52cd70349b89db">MXC_F_SPIXFC_SPCTRL_SAMPL_POS</a>&#160;&#160;&#160;0</td></tr>
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+<tr class="memdesc:gacd895c1752c7ff306b65cbce7dc89481"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPCTRL_SAMPL Mask. <br /></td></tr>
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+<tr class="memdesc:ga5904d6a5d33ce55586bce59bc600702c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPCTRL_SDIOOUT Position. <br /></td></tr>
+<tr class="separator:ga5904d6a5d33ce55586bce59bc600702c"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gaa78289098181770f0b76b55f905aa78c"><td class="memItemLeft" align="right" valign="top"><a id="gaa78289098181770f0b76b55f905aa78c"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXFC__SPCTRL.html#gaa78289098181770f0b76b55f905aa78c">MXC_F_SPIXFC_SPCTRL_SDIOOUT</a>&#160;&#160;&#160;((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS))</td></tr>
+<tr class="memdesc:gaa78289098181770f0b76b55f905aa78c"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPCTRL_SDIOOUT Mask. <br /></td></tr>
+<tr class="separator:gaa78289098181770f0b76b55f905aa78c"><td class="memSeparator" colspan="2">&#160;</td></tr>
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diff --git a/lib/sdk/Documentation/html/functions_q.html b/lib/sdk/Documentation/html/group__SPIXF__BUS__IDLE.html
similarity index 58%
rename from lib/sdk/Documentation/html/functions_q.html
rename to lib/sdk/Documentation/html/group__SPIXF__BUS__IDLE.html
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 <meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
 <meta http-equiv="X-UA-Compatible" content="IE=9"/>
 <meta name="generator" content="Doxygen 1.8.13"/>
-<title>MAX32665 SDK Documentation: Data Fields</title>
+<title>MAX32665 SDK Documentation: SPIXF_BUS_IDLE</title>
 <link href="tabs.css" rel="stylesheet" type="text/css"/>
 <script type="text/javascript" src="jquery.js"></script>
 <script type="text/javascript" src="dynsections.js"></script>
@@ -63,23 +63,32 @@ $(function() {
   </div>
 </div>
 <script type="text/javascript">
-$(document).ready(function(){initNavTree('functions_q.html','');});
+$(document).ready(function(){initNavTree('group__SPIXF__BUS__IDLE.html','');});
 </script>
 <div id="doc-content">
+<div class="header">
+  <div class="summary">
+<a href="#define-members">Macros</a>  </div>
+  <div class="headertitle">
+<div class="title">SPIXF_BUS_IDLE<div class="ingroups"><a class="el" href="group__spixf.html">SPI External Flash (SPIXF)</a> &raquo; <a class="el" href="group__spixf__registers.html">SPIXF_Registers</a></div></div>  </div>
+</div><!--header-->
 <div class="contents">
-<div class="textblock">Here is a list of all documented struct and union fields with links to the struct/union documentation for each field:</div>
 
-<h3><a id="index_q"></a>- q -</h3><ul>
-<li>qspi0
-: <a class="el" href="structmxc__rpu__regs__t.html#aa2846a575112b79bd39dc16bf16b260d">mxc_rpu_regs_t</a>
-</li>
-<li>qspi1
-: <a class="el" href="structmxc__rpu__regs__t.html#a5877aea894835edc9344e9a0c9fab0d0">mxc_rpu_regs_t</a>
-</li>
-<li>qspi2
-: <a class="el" href="structmxc__rpu__regs__t.html#aa9bf22e9a1dc0d8436bace1228c1cfd1">mxc_rpu_regs_t</a>
-</li>
-</ul>
+<p>SPIXF Bus Idle Detection.  
+<a href="#details">More...</a></p>
+<table class="memberdecls">
+<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
+Macros</h2></td></tr>
+<tr class="memitem:ga383dd31610501ff21fa820e4424b8ed4"><td class="memItemLeft" align="right" valign="top"><a id="ga383dd31610501ff21fa820e4424b8ed4"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__BUS__IDLE.html#ga383dd31610501ff21fa820e4424b8ed4">MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS</a>&#160;&#160;&#160;0</td></tr>
+<tr class="memdesc:ga383dd31610501ff21fa820e4424b8ed4"><td class="mdescLeft">&#160;</td><td class="mdescRight">BUS_IDLE_BUSIDLE Position. <br /></td></tr>
+<tr class="separator:ga383dd31610501ff21fa820e4424b8ed4"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga7e7635989dd7965a7985bb887c96578d"><td class="memItemLeft" align="right" valign="top"><a id="ga7e7635989dd7965a7985bb887c96578d"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__BUS__IDLE.html#ga7e7635989dd7965a7985bb887c96578d">MXC_F_SPIXF_BUS_IDLE_BUSIDLE</a>&#160;&#160;&#160;((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS))</td></tr>
+<tr class="memdesc:ga7e7635989dd7965a7985bb887c96578d"><td class="mdescLeft">&#160;</td><td class="mdescRight">BUS_IDLE_BUSIDLE Mask. <br /></td></tr>
+<tr class="separator:ga7e7635989dd7965a7985bb887c96578d"><td class="memSeparator" colspan="2">&#160;</td></tr>
+</table>
+<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
 </div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
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new file mode 100644
index 0000000000000000000000000000000000000000..35a1bee7e4de52e0d8e79ace9ca7b7032d67cac9
--- /dev/null
+++ b/lib/sdk/Documentation/html/group__SPIXF__BUS__IDLE.js
@@ -0,0 +1,5 @@
+var group__SPIXF__BUS__IDLE =
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+    [ "MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS", "group__SPIXF__BUS__IDLE.html#ga383dd31610501ff21fa820e4424b8ed4", null ],
+    [ "MXC_F_SPIXF_BUS_IDLE_BUSIDLE", "group__SPIXF__BUS__IDLE.html#ga7e7635989dd7965a7985bb887c96578d", null ]
+];
\ No newline at end of file
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index 3037590aac537796066e4276994b18a8c269188c..1f2a7a4cd868d7940c90ca882790c07a340d5d7f 100644
--- a/lib/sdk/Documentation/html/group__SPIXF__MEMSECCN.html
+++ b/lib/sdk/Documentation/html/group__SPIXF__MEMSECCN.html
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+<tr class="memitem:ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9"><td class="memItemLeft" align="right" valign="top"><a id="ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__MEMSECCN.html#ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9">MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS</a>&#160;&#160;&#160;1</td></tr>
+<tr class="memdesc:ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9"><td class="mdescLeft">&#160;</td><td class="mdescRight">MEMSECCN_AUTH_DISABLE Position. <br /></td></tr>
+<tr class="separator:ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga32b82a2d7de4a644b46febd47b647113"><td class="memItemLeft" align="right" valign="top"><a id="ga32b82a2d7de4a644b46febd47b647113"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__MEMSECCN.html#ga32b82a2d7de4a644b46febd47b647113">MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS))</td></tr>
+<tr class="memdesc:ga32b82a2d7de4a644b46febd47b647113"><td class="mdescLeft">&#160;</td><td class="mdescRight">MEMSECCN_AUTH_DISABLE Mask. <br /></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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index 3d8b696a13bb28fa054956ad25fad5b68b329e56..ef8c9370ec0448d622d3e2b78ca05c39b025c72e 100644
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-    [ "MXC_F_SPIXF_MEMSECCN_DECEN", "group__SPIXF__MEMSECCN.html#ga76b351beb675241b60add0c8e284602a", null ]
+    [ "MXC_F_SPIXF_MEMSECCN_DECEN", "group__SPIXF__MEMSECCN.html#ga76b351beb675241b60add0c8e284602a", null ],
+    [ "MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS", "group__SPIXF__MEMSECCN.html#ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9", null ],
+    [ "MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE", "group__SPIXF__MEMSECCN.html#ga32b82a2d7de4a644b46febd47b647113", null ]
 ];
\ No newline at end of file
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index 13d0d92f27aa90ebe1352fe08ab21168946cec2e..92eeecc86b0e4ef3085117ff77aa45d83c1d830b 100644
--- a/lib/sdk/Documentation/html/group__SPIXF__MODE__CTRL.html
+++ b/lib/sdk/Documentation/html/group__SPIXF__MODE__CTRL.html
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 <tr class="separator:ga1dcec540b782ed05c494052c2e5b590d"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__MODE__CTRL.html#ga31cf36c4851b11c4ea53d04768a0d1dd">MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS</a>&#160;&#160;&#160;9</td></tr>
+<tr class="memdesc:ga31cf36c4851b11c4ea53d04768a0d1dd"><td class="mdescLeft">&#160;</td><td class="mdescRight">MODE_CTRL_MODE_SEND Position. <br /></td></tr>
+<tr class="separator:ga31cf36c4851b11c4ea53d04768a0d1dd"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gac39dd7ba7ce6bdd2a0a969bee52729aa"><td class="memItemLeft" align="right" valign="top"><a id="gac39dd7ba7ce6bdd2a0a969bee52729aa"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__MODE__CTRL.html#gac39dd7ba7ce6bdd2a0a969bee52729aa">MXC_F_SPIXF_MODE_CTRL_MODE_SEND</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS))</td></tr>
+<tr class="memdesc:gac39dd7ba7ce6bdd2a0a969bee52729aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">MODE_CTRL_MODE_SEND Mask. <br /></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__SPIXF__MODE__CTRL.js b/lib/sdk/Documentation/html/group__SPIXF__MODE__CTRL.js
index b21ca94eded12af3de221196f8970e18a71c6a6d..c2914e249a056e5ed05a53bb94febb43d3938e9d 100644
--- a/lib/sdk/Documentation/html/group__SPIXF__MODE__CTRL.js
+++ b/lib/sdk/Documentation/html/group__SPIXF__MODE__CTRL.js
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     [ "MXC_F_SPIXF_MODE_CTRL_MDCLK", "group__SPIXF__MODE__CTRL.html#ga291a7580b88617cda178be4a7b9340e5", null ],
     [ "MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS", "group__SPIXF__MODE__CTRL.html#gab2c5f199491f54905e886b6cd73532bd", null ],
-    [ "MXC_F_SPIXF_MODE_CTRL_NO_CMD", "group__SPIXF__MODE__CTRL.html#ga1dcec540b782ed05c494052c2e5b590d", null ]
+    [ "MXC_F_SPIXF_MODE_CTRL_NO_CMD", "group__SPIXF__MODE__CTRL.html#ga1dcec540b782ed05c494052c2e5b590d", null ],
+    [ "MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS", "group__SPIXF__MODE__CTRL.html#ga31cf36c4851b11c4ea53d04768a0d1dd", null ],
+    [ "MXC_F_SPIXF_MODE_CTRL_MODE_SEND", "group__SPIXF__MODE__CTRL.html#gac39dd7ba7ce6bdd2a0a969bee52729aa", null ]
 ];
\ No newline at end of file
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index c4c77eac46aa18abc03f3a3e527d45763e910958..b169941837a2a1efc4c3263e08c0ba35e3b4b1c7 100644
--- a/lib/sdk/Documentation/html/group__SPIXF__Register__Offsets.html
+++ b/lib/sdk/Documentation/html/group__SPIXF__Register__Offsets.html
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 <tr class="separator:ga70b69216b6afbeb6a25d6544a9971524"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXF__Register__Offsets.html#ga4810c9ad8281456cb75a401834622df6">MXC_R_SPIXF_BUS_IDLE</a>&#160;&#160;&#160;((uint32_t)0x00000024UL)</td></tr>
+<tr class="memdesc:ga4810c9ad8281456cb75a401834622df6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset from SPIXF Base Address: <code> 0x0024</code> <br /></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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diff --git a/lib/sdk/Documentation/html/group__SPIXF__Register__Offsets.js b/lib/sdk/Documentation/html/group__SPIXF__Register__Offsets.js
index affb9fd1dd8ab25d7249b757abbd8b6569c85a18..d0f70d47a386fafc93155fee06964ab3da055bde 100644
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+++ b/lib/sdk/Documentation/html/group__SPIXF__Register__Offsets.js
@@ -6,5 +6,6 @@ var group__SPIXF__Register__Offsets =
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     [ "MXC_R_SPIXF_IO_CTRL", "group__SPIXF__Register__Offsets.html#ga40eade3daa7d0aa833b9ec5482964369", null ],
-    [ "MXC_R_SPIXF_MEMSECCN", "group__SPIXF__Register__Offsets.html#ga70b69216b6afbeb6a25d6544a9971524", null ]
+    [ "MXC_R_SPIXF_MEMSECCN", "group__SPIXF__Register__Offsets.html#ga70b69216b6afbeb6a25d6544a9971524", null ],
+    [ "MXC_R_SPIXF_BUS_IDLE", "group__SPIXF__Register__Offsets.html#ga4810c9ad8281456cb75a401834622df6", null ]
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diff --git a/lib/sdk/Documentation/html/group__SPIXR__CTRL3.html b/lib/sdk/Documentation/html/group__SPIXR__CTRL3.html
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-  <div class="headertitle">
-<div class="title">SPIXR_I2S_CTRL<div class="ingroups"><a class="el" href="group__spixr.html">SPI External Ram (SPIXR)</a> &raquo; <a class="el" href="group__spixr__registers.html">SPIXR_Registers</a></div></div>  </div>
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-<p>Register for controlling I2C mode.  
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-<table class="memberdecls">
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__I2S__CTRL.html#gaf490ec69370cb7ee3710474cbeca54ab">MXC_F_SPIXR_I2S_CTRL_I2S_LJ</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_I2S_CTRL_I2S_LJ_POS))</td></tr>
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 <tr class="memdesc:ga77c41cc89f87b6292bd6e83ae1b46823"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ_ABORT Mask. <br /></td></tr>
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-<tr class="memdesc:gacdea4e812d205eee1fda8e556a0ebb43"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ_SR3A Mask. <br /></td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga9253a959f55632249d8b47328056ddeb">MXC_F_SPIXR_IRQ_SR4A_POS</a>&#160;&#160;&#160;20</td></tr>
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-<tr class="memitem:ga4d8ca4fa01626dffbf5e32a2ff721a8e"><td class="memItemLeft" align="right" valign="top"><a id="ga4d8ca4fa01626dffbf5e32a2ff721a8e"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga4d8ca4fa01626dffbf5e32a2ff721a8e">MXC_F_SPIXR_IRQ_SR4A</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR4A_POS))</td></tr>
-<tr class="memdesc:ga4d8ca4fa01626dffbf5e32a2ff721a8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ_SR4A Mask. <br /></td></tr>
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-<tr class="memitem:ga769e5db855f1d1f4d12e79ee489d59a9"><td class="memItemLeft" align="right" valign="top"><a id="ga769e5db855f1d1f4d12e79ee489d59a9"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga769e5db855f1d1f4d12e79ee489d59a9">MXC_F_SPIXR_IRQ_SR5A_POS</a>&#160;&#160;&#160;21</td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga15c0ba7818efc3499cb9bb0654260e77">MXC_F_SPIXR_IRQ_SR5A</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR5A_POS))</td></tr>
-<tr class="memdesc:ga15c0ba7818efc3499cb9bb0654260e77"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ_SR5A Mask. <br /></td></tr>
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-<tr class="memitem:ga290dea21b7055be386fc1099c7252d4c"><td class="memItemLeft" align="right" valign="top"><a id="ga290dea21b7055be386fc1099c7252d4c"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga290dea21b7055be386fc1099c7252d4c">MXC_F_SPIXR_IRQ_SR6A_POS</a>&#160;&#160;&#160;22</td></tr>
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-<tr class="memitem:gad379401c97e7066d133214dc86547390"><td class="memItemLeft" align="right" valign="top"><a id="gad379401c97e7066d133214dc86547390"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#gad379401c97e7066d133214dc86547390">MXC_F_SPIXR_IRQ_SR6A</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR6A_POS))</td></tr>
-<tr class="memdesc:gad379401c97e7066d133214dc86547390"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ_SR6A Mask. <br /></td></tr>
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-<tr class="memitem:ga12336062ab9df83457ef7c7e8a4479b8"><td class="memItemLeft" align="right" valign="top"><a id="ga12336062ab9df83457ef7c7e8a4479b8"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga12336062ab9df83457ef7c7e8a4479b8">MXC_F_SPIXR_IRQ_SR7A_POS</a>&#160;&#160;&#160;23</td></tr>
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-<tr class="memitem:ga626c631a04a927fd03b34d4e78332b2d"><td class="memItemLeft" align="right" valign="top"><a id="ga626c631a04a927fd03b34d4e78332b2d"></a>
-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQ.html#ga626c631a04a927fd03b34d4e78332b2d">MXC_F_SPIXR_IRQ_SR7A</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR7A_POS))</td></tr>
-<tr class="memdesc:ga626c631a04a927fd03b34d4e78332b2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQ_SR7A Mask. <br /></td></tr>
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 </table>
 <a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
 <p>All bits are write 1 to clear. </p>
diff --git a/lib/sdk/Documentation/html/group__SPIXR__IRQ.js b/lib/sdk/Documentation/html/group__SPIXR__IRQ.js
index 68777776213aba1041f5d280e9824f4993d30040..e893242df3e1ce35d10c574709af15ace0e65ee5 100644
--- a/lib/sdk/Documentation/html/group__SPIXR__IRQ.js
+++ b/lib/sdk/Documentation/html/group__SPIXR__IRQ.js
@@ -16,8 +16,6 @@ var group__SPIXR__IRQ =
     [ "MXC_F_SPIXR_IRQ_FAULT", "group__SPIXR__IRQ.html#ga8be8c63f2de0227449a8c51c4415b3b2", null ],
     [ "MXC_F_SPIXR_IRQ_ABORT_POS", "group__SPIXR__IRQ.html#ga1a9c3d1ea7748f31ad562136b31bc147", null ],
     [ "MXC_F_SPIXR_IRQ_ABORT", "group__SPIXR__IRQ.html#ga77c41cc89f87b6292bd6e83ae1b46823", null ],
-    [ "MXC_F_SPIXR_IRQ_TIMEOUT_POS", "group__SPIXR__IRQ.html#ga5eab5abf06cf004258d4666e4120a4c1", null ],
-    [ "MXC_F_SPIXR_IRQ_TIMEOUT", "group__SPIXR__IRQ.html#gafcd1bb73e33d035de58d21f5dcc9d388", null ],
     [ "MXC_F_SPIXR_IRQ_M_DONE_POS", "group__SPIXR__IRQ.html#ga02062dca9c5c3ffbbdb1b447e21e4201", null ],
     [ "MXC_F_SPIXR_IRQ_M_DONE", "group__SPIXR__IRQ.html#gac8637d8c77e37b13a4005490d8410516", null ],
     [ "MXC_F_SPIXR_IRQ_TX_OVR_POS", "group__SPIXR__IRQ.html#ga3fb2e1a5f7c568af297e1c9c299a8d51", null ],
@@ -27,21 +25,5 @@ var group__SPIXR__IRQ =
     [ "MXC_F_SPIXR_IRQ_RX_OVR_POS", "group__SPIXR__IRQ.html#ga382577a6fb53c52ae23b8750cba59cfb", null ],
     [ "MXC_F_SPIXR_IRQ_RX_OVR", "group__SPIXR__IRQ.html#ga553faaa3e9820c393f4e6a7e61a0b48d", null ],
     [ "MXC_F_SPIXR_IRQ_RX_UND_POS", "group__SPIXR__IRQ.html#ga5f784abbbdffc2a19b1721ff3a735319", null ],
-    [ "MXC_F_SPIXR_IRQ_RX_UND", "group__SPIXR__IRQ.html#ga177fac38055f74bf130d630f09a090e5", null ],
-    [ "MXC_F_SPIXR_IRQ_SR0A_POS", "group__SPIXR__IRQ.html#ga60a2bbe9ff7f39f6c69820ac876477fd", null ],
-    [ "MXC_F_SPIXR_IRQ_SR0A", "group__SPIXR__IRQ.html#ga6a07a387320bc362964a4dedafcac838", null ],
-    [ "MXC_F_SPIXR_IRQ_SR1A_POS", "group__SPIXR__IRQ.html#ga400722ab96c78e3983e0ba3b2bc12df2", null ],
-    [ "MXC_F_SPIXR_IRQ_SR1A", "group__SPIXR__IRQ.html#ga36bcc5b3587e0a326dde86c90be1974c", null ],
-    [ "MXC_F_SPIXR_IRQ_SR2A_POS", "group__SPIXR__IRQ.html#ga4a20140c119d3db946978bf3e9622c07", null ],
-    [ "MXC_F_SPIXR_IRQ_SR2A", "group__SPIXR__IRQ.html#ga13005f45c8e5b60850aee82aead81bf8", null ],
-    [ "MXC_F_SPIXR_IRQ_SR3A_POS", "group__SPIXR__IRQ.html#gae2d30196cb9bbb28a2af3093ba728e82", null ],
-    [ "MXC_F_SPIXR_IRQ_SR3A", "group__SPIXR__IRQ.html#gacdea4e812d205eee1fda8e556a0ebb43", null ],
-    [ "MXC_F_SPIXR_IRQ_SR4A_POS", "group__SPIXR__IRQ.html#ga9253a959f55632249d8b47328056ddeb", null ],
-    [ "MXC_F_SPIXR_IRQ_SR4A", "group__SPIXR__IRQ.html#ga4d8ca4fa01626dffbf5e32a2ff721a8e", null ],
-    [ "MXC_F_SPIXR_IRQ_SR5A_POS", "group__SPIXR__IRQ.html#ga769e5db855f1d1f4d12e79ee489d59a9", null ],
-    [ "MXC_F_SPIXR_IRQ_SR5A", "group__SPIXR__IRQ.html#ga15c0ba7818efc3499cb9bb0654260e77", null ],
-    [ "MXC_F_SPIXR_IRQ_SR6A_POS", "group__SPIXR__IRQ.html#ga290dea21b7055be386fc1099c7252d4c", null ],
-    [ "MXC_F_SPIXR_IRQ_SR6A", "group__SPIXR__IRQ.html#gad379401c97e7066d133214dc86547390", null ],
-    [ "MXC_F_SPIXR_IRQ_SR7A_POS", "group__SPIXR__IRQ.html#ga12336062ab9df83457ef7c7e8a4479b8", null ],
-    [ "MXC_F_SPIXR_IRQ_SR7A", "group__SPIXR__IRQ.html#ga626c631a04a927fd03b34d4e78332b2d", null ]
+    [ "MXC_F_SPIXR_IRQ_RX_UND", "group__SPIXR__IRQ.html#ga177fac38055f74bf130d630f09a090e5", null ]
 ];
\ No newline at end of file
diff --git a/lib/sdk/Documentation/html/group__SPIXR__IRQE.html b/lib/sdk/Documentation/html/group__SPIXR__IRQE.html
index 7f629df7342498107eedaf6c6f1b60355c11e150..81d68395cfbf40b6ba241a8d0245ed12220cb31f 100644
--- a/lib/sdk/Documentation/html/group__SPIXR__IRQE.html
+++ b/lib/sdk/Documentation/html/group__SPIXR__IRQE.html
@@ -143,14 +143,6 @@ Macros</h2></td></tr>
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 <tr class="memdesc:gabd01395c01eb1760cf1522df3ff40f9d"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQE_ABORT Mask. <br /></td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQE.html#gaef73c1aa5a18cc39c1e2fd3c81d76848">MXC_F_SPIXR_IRQE_TIMEOUT_POS</a>&#160;&#160;&#160;10</td></tr>
-<tr class="memdesc:gaef73c1aa5a18cc39c1e2fd3c81d76848"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQE_TIMEOUT Position. <br /></td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQE.html#gaf8eedfd93bae073a546b28c36360c07c">MXC_F_SPIXR_IRQE_TIMEOUT</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TIMEOUT_POS))</td></tr>
-<tr class="memdesc:gaf8eedfd93bae073a546b28c36360c07c"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQE_TIMEOUT Mask. <br /></td></tr>
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 <tr class="memdesc:gac338f3acd8af2328efc334bcabfed971"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQE_RX_UND Mask. <br /></td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__IRQE.html#ga554d8b890644528b218eb3575275a5e7">MXC_F_SPIXR_IRQE_SR0A_POS</a>&#160;&#160;&#160;16</td></tr>
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-<tr class="memitem:ga3769c955c257126ebb9783940c08e032"><td class="memItemLeft" align="right" valign="top"><a id="ga3769c955c257126ebb9783940c08e032"></a>
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-<tr class="memdesc:ga3769c955c257126ebb9783940c08e032"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQE_SR0A Mask. <br /></td></tr>
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-<tr class="memitem:ga0aa554db81b6f9ce209664a73d72b7ac"><td class="memItemLeft" align="right" valign="top"><a id="ga0aa554db81b6f9ce209664a73d72b7ac"></a>
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-<tr class="memitem:ga7815051fe517230bfbce4a1675bead1f"><td class="memItemLeft" align="right" valign="top"><a id="ga7815051fe517230bfbce4a1675bead1f"></a>
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-<tr class="memdesc:ga7815051fe517230bfbce4a1675bead1f"><td class="mdescLeft">&#160;</td><td class="mdescRight">IRQE_SR2A Mask. <br /></td></tr>
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-<tr class="memitem:gaf6cb1817f209d521966c154e8015c05e"><td class="memItemLeft" align="right" valign="top"><a id="gaf6cb1817f209d521966c154e8015c05e"></a>
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diff --git a/lib/sdk/Documentation/html/group__SPIXR__IRQE.js b/lib/sdk/Documentation/html/group__SPIXR__IRQE.js
index 801c5202e64699147c782f32a648498c8cf54b4f..d1b6b18c662f85539db381fdabff417c2d8b37b9 100644
--- a/lib/sdk/Documentation/html/group__SPIXR__IRQE.js
+++ b/lib/sdk/Documentation/html/group__SPIXR__IRQE.js
@@ -16,8 +16,6 @@ var group__SPIXR__IRQE =
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-    [ "MXC_F_SPIXR_IRQE_TIMEOUT_POS", "group__SPIXR__IRQE.html#gaef73c1aa5a18cc39c1e2fd3c81d76848", null ],
-    [ "MXC_F_SPIXR_IRQE_TIMEOUT", "group__SPIXR__IRQE.html#gaf8eedfd93bae073a546b28c36360c07c", null ],
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     [ "MXC_F_SPIXR_IRQE_M_DONE", "group__SPIXR__IRQE.html#gab3237d1c64c3ead640f2b74581ca3590", null ],
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-    [ "MXC_F_SPIXR_IRQE_RX_UND", "group__SPIXR__IRQE.html#gac338f3acd8af2328efc334bcabfed971", null ],
-    [ "MXC_F_SPIXR_IRQE_SR0A_POS", "group__SPIXR__IRQE.html#ga554d8b890644528b218eb3575275a5e7", null ],
-    [ "MXC_F_SPIXR_IRQE_SR0A", "group__SPIXR__IRQE.html#ga3769c955c257126ebb9783940c08e032", null ],
-    [ "MXC_F_SPIXR_IRQE_SR1A_POS", "group__SPIXR__IRQE.html#ga0aa554db81b6f9ce209664a73d72b7ac", null ],
-    [ "MXC_F_SPIXR_IRQE_SR1A", "group__SPIXR__IRQE.html#ga0adb168d964a951187f66cfa6ccc9574", null ],
-    [ "MXC_F_SPIXR_IRQE_SR2A_POS", "group__SPIXR__IRQE.html#ga2df0cd8db593b81aa43d9daf745906d1", null ],
-    [ "MXC_F_SPIXR_IRQE_SR2A", "group__SPIXR__IRQE.html#ga7815051fe517230bfbce4a1675bead1f", null ],
-    [ "MXC_F_SPIXR_IRQE_SR3A_POS", "group__SPIXR__IRQE.html#gaf6cb1817f209d521966c154e8015c05e", null ],
-    [ "MXC_F_SPIXR_IRQE_SR3A", "group__SPIXR__IRQE.html#ga77a6e73b154f7c70df113b573fa627f4", null ],
-    [ "MXC_F_SPIXR_IRQE_SR4A_POS", "group__SPIXR__IRQE.html#gae1b897cf0ffa57405f5262e4403b25c2", null ],
-    [ "MXC_F_SPIXR_IRQE_SR4A", "group__SPIXR__IRQE.html#ga10b702a26f8a608d112c86f2b922d4fd", null ],
-    [ "MXC_F_SPIXR_IRQE_SR5A_POS", "group__SPIXR__IRQE.html#ga74ca53e7f795882a0e4c71cb90d7f416", null ],
-    [ "MXC_F_SPIXR_IRQE_SR5A", "group__SPIXR__IRQE.html#ga9f22d32d49df47d9e86fd3b02cd541c4", null ],
-    [ "MXC_F_SPIXR_IRQE_SR6A_POS", "group__SPIXR__IRQE.html#ga2abc323fb53390b2963f4a747c9bba49", null ],
-    [ "MXC_F_SPIXR_IRQE_SR6A", "group__SPIXR__IRQE.html#gae2c1d5475f06cdda44613298100f50ac", null ],
-    [ "MXC_F_SPIXR_IRQE_SR7A_POS", "group__SPIXR__IRQE.html#gafb399bd9198fa72a6b3cdd98778f8805", null ],
-    [ "MXC_F_SPIXR_IRQE_SR7A", "group__SPIXR__IRQE.html#ga8c56485c6e6dd59206dd99f1f82ff749", null ]
+    [ "MXC_F_SPIXR_IRQE_RX_UND", "group__SPIXR__IRQE.html#gac338f3acd8af2328efc334bcabfed971", null ]
 ];
\ No newline at end of file
diff --git a/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.html b/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.html
index 02c4b6ec27755796d432cc856e3372c46e0c2589..aa467b27d3d2315969f5255cecc9712a64868d18 100644
--- a/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.html
+++ b/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.html
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diff --git a/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.js b/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.js
index e5aa69900d8201eb74546f18c93e52ab7d2b4b9b..7d058a042c8948737d57b5eee435050858a566b3 100644
--- a/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.js
+++ b/lib/sdk/Documentation/html/group__SPIXR__Register__Offsets.js
@@ -8,7 +8,6 @@ var group__SPIXR__Register__Offsets =
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     [ "MXC_R_SPIXR_CTRL4", "group__SPIXR__Register__Offsets.html#gab6e44d192d452963b8d9fa153534bf3e", null ],
     [ "MXC_R_SPIXR_BRG_CTRL", "group__SPIXR__Register__Offsets.html#ga34dc7a0b8cfe6da9c8e21acd06195289", null ],
-    [ "MXC_R_SPIXR_I2S_CTRL", "group__SPIXR__Register__Offsets.html#ga225fa8aeed7a6a2c4cc96a723fe989ff", null ],
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index c14a33fd11cde97e8b33fd1c96f2eba3bd1b94d7..b63607a2c1ec98cf76c6dd6f9373a9ecdfb37654 100644
--- a/lib/sdk/Documentation/html/group__TPU__DMA__CNT.html
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__TPU__DMA__CNT.html#ga55939cfcf13b3f5e95b699c4552b8545">MXC_F_TPU_DMA_CNT_ADDR_POS</a>&#160;&#160;&#160;0</td></tr>
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+<tr class="memitem:ga0729ed3035dd2a7a4ac6675c9994fca4"><td class="memItemLeft" align="right" valign="top"><a id="ga0729ed3035dd2a7a4ac6675c9994fca4"></a>
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diff --git a/lib/sdk/Documentation/html/group__TPU__DMA__CNT.js b/lib/sdk/Documentation/html/group__TPU__DMA__CNT.js
index 6db20982bbff109958c96b7e911b7c5052713adf..1f92a97c02a5a79803217879df54082afb91bec3 100644
--- a/lib/sdk/Documentation/html/group__TPU__DMA__CNT.js
+++ b/lib/sdk/Documentation/html/group__TPU__DMA__CNT.js
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-    [ "MXC_F_TPU_DMA_CNT_ADDR", "group__TPU__DMA__CNT.html#gad80a471a7e3aba41a0040634aa3ec577", null ]
+    [ "MXC_F_TPU_DMA_CNT_COUNT_POS", "group__TPU__DMA__CNT.html#ga0729ed3035dd2a7a4ac6675c9994fca4", null ],
+    [ "MXC_F_TPU_DMA_CNT_COUNT", "group__TPU__DMA__CNT.html#gaa68cdae5364d4218a7527f919ac90f33", null ]
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\ No newline at end of file
diff --git a/lib/sdk/Documentation/html/group__UART__DMA.html b/lib/sdk/Documentation/html/group__UART__DMA.html
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 <table class="memberdecls">
 <tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="define-members"></a>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gabf796cd48d76f982569d92e74e22f93c">MXC_F_UART_DMA_TDMA_EN_POS</a>&#160;&#160;&#160;0</td></tr>
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-#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gadf4bfcec181fbb27009155519f0685c0">MXC_F_UART_DMA_TDMA_EN</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_TDMA_EN_POS))</td></tr>
-<tr class="memdesc:gadf4bfcec181fbb27009155519f0685c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_TDMA_EN Mask. <br /></td></tr>
-<tr class="separator:gadf4bfcec181fbb27009155519f0685c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae641dd039384fe57e34c4bd47a72895a"><td class="memItemLeft" align="right" valign="top"><a id="gae641dd039384fe57e34c4bd47a72895a"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gae641dd039384fe57e34c4bd47a72895a">MXC_F_UART_DMA_TXDMA_EN_POS</a>&#160;&#160;&#160;0</td></tr>
+<tr class="memdesc:gae641dd039384fe57e34c4bd47a72895a"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_TXDMA_EN Position. <br /></td></tr>
+<tr class="separator:gae641dd039384fe57e34c4bd47a72895a"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae80f906d46e20cf77586834fda24b5a8"><td class="memItemLeft" align="right" valign="top"><a id="gae80f906d46e20cf77586834fda24b5a8"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gae80f906d46e20cf77586834fda24b5a8">MXC_F_UART_DMA_TXDMA_EN</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_TXDMA_EN_POS))</td></tr>
+<tr class="memdesc:gae80f906d46e20cf77586834fda24b5a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_TXDMA_EN Mask. <br /></td></tr>
+<tr class="separator:gae80f906d46e20cf77586834fda24b5a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:gaa04a7beef7f509b5fab449818e62e5dc"><td class="memItemLeft" align="right" valign="top"><a id="gaa04a7beef7f509b5fab449818e62e5dc"></a>
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 <tr class="memdesc:gaa04a7beef7f509b5fab449818e62e5dc"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_RXDMA_EN Position. <br /></td></tr>
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 <tr class="memdesc:gac96cf5a87e82fc202dd6e0007150ff4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_RXDMA_EN Mask. <br /></td></tr>
 <tr class="separator:gac96cf5a87e82fc202dd6e0007150ff4e"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gab7f87e3f7bed3b1cbe8ddf237fc45fe6"><td class="memItemLeft" align="right" valign="top"><a id="gab7f87e3f7bed3b1cbe8ddf237fc45fe6"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gab7f87e3f7bed3b1cbe8ddf237fc45fe6">MXC_F_UART_DMA_RXDMA_START_POS</a>&#160;&#160;&#160;3</td></tr>
+<tr class="memdesc:gab7f87e3f7bed3b1cbe8ddf237fc45fe6"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_RXDMA_START Position. <br /></td></tr>
+<tr class="separator:gab7f87e3f7bed3b1cbe8ddf237fc45fe6"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga26fd201c29b8ab6aabed050ad4e6c4ea"><td class="memItemLeft" align="right" valign="top"><a id="ga26fd201c29b8ab6aabed050ad4e6c4ea"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#ga26fd201c29b8ab6aabed050ad4e6c4ea">MXC_F_UART_DMA_RXDMA_START</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_RXDMA_START_POS))</td></tr>
+<tr class="memdesc:ga26fd201c29b8ab6aabed050ad4e6c4ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_RXDMA_START Mask. <br /></td></tr>
+<tr class="separator:ga26fd201c29b8ab6aabed050ad4e6c4ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga16f66d46a24c45c8f69f4de32aedf27b"><td class="memItemLeft" align="right" valign="top"><a id="ga16f66d46a24c45c8f69f4de32aedf27b"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#ga16f66d46a24c45c8f69f4de32aedf27b">MXC_F_UART_DMA_RXDMA_AUTO_TO_POS</a>&#160;&#160;&#160;5</td></tr>
+<tr class="memdesc:ga16f66d46a24c45c8f69f4de32aedf27b"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_RXDMA_AUTO_TO Position. <br /></td></tr>
+<tr class="separator:ga16f66d46a24c45c8f69f4de32aedf27b"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:gae2eac669d530adaaff606c0e5b7b1c52"><td class="memItemLeft" align="right" valign="top"><a id="gae2eac669d530adaaff606c0e5b7b1c52"></a>
+#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gae2eac669d530adaaff606c0e5b7b1c52">MXC_F_UART_DMA_RXDMA_AUTO_TO</a>&#160;&#160;&#160;((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_RXDMA_AUTO_TO_POS))</td></tr>
+<tr class="memdesc:gae2eac669d530adaaff606c0e5b7b1c52"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_RXDMA_AUTO_TO Mask. <br /></td></tr>
+<tr class="separator:gae2eac669d530adaaff606c0e5b7b1c52"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:gae752540ed4cfe99f7ea8ab1c9b3d6f05"><td class="memItemLeft" align="right" valign="top"><a id="gae752540ed4cfe99f7ea8ab1c9b3d6f05"></a>
 #define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__UART__DMA.html#gae752540ed4cfe99f7ea8ab1c9b3d6f05">MXC_F_UART_DMA_TXDMA_LEVEL_POS</a>&#160;&#160;&#160;8</td></tr>
 <tr class="memdesc:gae752540ed4cfe99f7ea8ab1c9b3d6f05"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA_TXDMA_LEVEL Position. <br /></td></tr>
diff --git a/lib/sdk/Documentation/html/group__UART__DMA.js b/lib/sdk/Documentation/html/group__UART__DMA.js
index ac20f84a8daa8409ce18aae52b630894901912e7..d3ee404796dd423e89c80dab03f2919dcc87374b 100644
--- a/lib/sdk/Documentation/html/group__UART__DMA.js
+++ b/lib/sdk/Documentation/html/group__UART__DMA.js
@@ -1,9 +1,13 @@
 var group__UART__DMA =
 [
-    [ "MXC_F_UART_DMA_TDMA_EN_POS", "group__UART__DMA.html#gabf796cd48d76f982569d92e74e22f93c", null ],
-    [ "MXC_F_UART_DMA_TDMA_EN", "group__UART__DMA.html#gadf4bfcec181fbb27009155519f0685c0", null ],
+    [ "MXC_F_UART_DMA_TXDMA_EN_POS", "group__UART__DMA.html#gae641dd039384fe57e34c4bd47a72895a", null ],
+    [ "MXC_F_UART_DMA_TXDMA_EN", "group__UART__DMA.html#gae80f906d46e20cf77586834fda24b5a8", null ],
     [ "MXC_F_UART_DMA_RXDMA_EN_POS", "group__UART__DMA.html#gaa04a7beef7f509b5fab449818e62e5dc", null ],
     [ "MXC_F_UART_DMA_RXDMA_EN", "group__UART__DMA.html#gac96cf5a87e82fc202dd6e0007150ff4e", null ],
+    [ "MXC_F_UART_DMA_RXDMA_START_POS", "group__UART__DMA.html#gab7f87e3f7bed3b1cbe8ddf237fc45fe6", null ],
+    [ "MXC_F_UART_DMA_RXDMA_START", "group__UART__DMA.html#ga26fd201c29b8ab6aabed050ad4e6c4ea", null ],
+    [ "MXC_F_UART_DMA_RXDMA_AUTO_TO_POS", "group__UART__DMA.html#ga16f66d46a24c45c8f69f4de32aedf27b", null ],
+    [ "MXC_F_UART_DMA_RXDMA_AUTO_TO", "group__UART__DMA.html#gae2eac669d530adaaff606c0e5b7b1c52", null ],
     [ "MXC_F_UART_DMA_TXDMA_LEVEL_POS", "group__UART__DMA.html#gae752540ed4cfe99f7ea8ab1c9b3d6f05", null ],
     [ "MXC_F_UART_DMA_TXDMA_LEVEL", "group__UART__DMA.html#ga1fa761deacc326a55af7438669b01b21", null ],
     [ "MXC_F_UART_DMA_RXDMA_LEVEL_POS", "group__UART__DMA.html#ga324fd0547f84fa0bc10517d662f0837a", null ],
diff --git a/lib/sdk/Documentation/html/group__flc.html b/lib/sdk/Documentation/html/group__flc.html
index 40167e56ec094988ae5e785e1189d623388d0c0b..a75ba7687a59bfbc9541e71aab26b068211be73e 100644
--- a/lib/sdk/Documentation/html/group__flc.html
+++ b/lib/sdk/Documentation/html/group__flc.html
@@ -104,6 +104,9 @@ Functions</h2></td></tr>
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 <tr class="memdesc:ga6ffdba912987544c1b9f20bfb502cafa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Erases the entire flash array.  <a href="#ga6ffdba912987544c1b9f20bfb502cafa">More...</a><br /></td></tr>
 <tr class="separator:ga6ffdba912987544c1b9f20bfb502cafa"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga91e5033e4b2b68ff1d0a4d352e1ac837"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__flc.html#ga91e5033e4b2b68ff1d0a4d352e1ac837">FLC_MassEraseInst</a> (int inst)</td></tr>
+<tr class="memdesc:ga91e5033e4b2b68ff1d0a4d352e1ac837"><td class="mdescLeft">&#160;</td><td class="mdescRight">Erases the selected flash array.  <a href="#ga91e5033e4b2b68ff1d0a4d352e1ac837">More...</a><br /></td></tr>
+<tr class="separator:ga91e5033e4b2b68ff1d0a4d352e1ac837"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:gae17acd43a6a605787a9e4aa6bfb2f7f1"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__flc.html#gae17acd43a6a605787a9e4aa6bfb2f7f1">FLC_PageErase</a> (uint32_t address)</td></tr>
 <tr class="memdesc:gae17acd43a6a605787a9e4aa6bfb2f7f1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Erases the page of flash at the specified address.  <a href="#gae17acd43a6a605787a9e4aa6bfb2f7f1">More...</a><br /></td></tr>
 <tr class="separator:gae17acd43a6a605787a9e4aa6bfb2f7f1"><td class="memSeparator" colspan="2">&#160;</td></tr>
@@ -134,6 +137,9 @@ Functions</h2></td></tr>
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 <tr class="memdesc:gad66c50abe1036551df8fe389b48634d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clear flash interrupt flags.  <a href="#gad66c50abe1036551df8fe389b48634d3">More...</a><br /></td></tr>
 <tr class="separator:gad66c50abe1036551df8fe389b48634d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga9f27160d352d96821a7336fa7277f0d9"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__flc.html#ga9f27160d352d96821a7336fa7277f0d9">FLC_InfoBlockUnlocked</a> (uint32_t address)</td></tr>
+<tr class="memdesc:ga9f27160d352d96821a7336fa7277f0d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Test to see if info block is already unlocked.  <a href="#ga9f27160d352d96821a7336fa7277f0d9">More...</a><br /></td></tr>
+<tr class="separator:ga9f27160d352d96821a7336fa7277f0d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:ga7d13b8204f1163e40d6f3369091ec562"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__flc.html#ga7d13b8204f1163e40d6f3369091ec562">FLC_UnlockInfoBlock</a> (uint32_t address)</td></tr>
 <tr class="memdesc:ga7d13b8204f1163e40d6f3369091ec562"><td class="mdescLeft">&#160;</td><td class="mdescRight">Unlock info block.  <a href="#ga7d13b8204f1163e40d6f3369091ec562">More...</a><br /></td></tr>
 <tr class="separator:ga7d13b8204f1163e40d6f3369091ec562"><td class="memSeparator" colspan="2">&#160;</td></tr>
@@ -199,6 +205,32 @@ Functions</h2></td></tr>
 <dl class="section note"><dt>Note</dt><dd>This function must be executed from RAM. </dd></dl>
 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="group__MXC__Error__Codes.html#gaa1f0dfda864fa9d2630645f233e1fdb4" title="No Error. ">E_NO_ERROR</a> If function is successful. </dd></dl>
 
+</div>
+</div>
+<a id="ga91e5033e4b2b68ff1d0a4d352e1ac837"></a>
+<h2 class="memtitle"><span class="permalink"><a href="#ga91e5033e4b2b68ff1d0a4d352e1ac837">&#9670;&nbsp;</a></span>FLC_MassEraseInst()</h2>
+
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int FLC_MassEraseInst </td>
+          <td>(</td>
+          <td class="paramtype">int&#160;</td>
+          <td class="paramname"><em>inst</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramname">inst</td><td>Index of the desired flash array to erase. </td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section note"><dt>Note</dt><dd>This function must be executed from RAM. </dd></dl>
+<dl class="section return"><dt>Returns</dt><dd><a class="el" href="group__MXC__Error__Codes.html#gaa1f0dfda864fa9d2630645f233e1fdb4" title="No Error. ">E_NO_ERROR</a> If function is successful. </dd></dl>
+
 </div>
 </div>
 <a id="gae17acd43a6a605787a9e4aa6bfb2f7f1"></a>
@@ -530,6 +562,31 @@ Functions</h2></td></tr>
 </dl>
 <dl class="section return"><dt>Returns</dt><dd><a class="el" href="group__MXC__Error__Codes.html#gaa1f0dfda864fa9d2630645f233e1fdb4" title="No Error. ">E_NO_ERROR</a> If function is successful. </dd></dl>
 
+</div>
+</div>
+<a id="ga9f27160d352d96821a7336fa7277f0d9"></a>
+<h2 class="memtitle"><span class="permalink"><a href="#ga9f27160d352d96821a7336fa7277f0d9">&#9670;&nbsp;</a></span>FLC_InfoBlockUnlocked()</h2>
+
+<div class="memitem">
+<div class="memproto">
+      <table class="memname">
+        <tr>
+          <td class="memname">int FLC_InfoBlockUnlocked </td>
+          <td>(</td>
+          <td class="paramtype">uint32_t&#160;</td>
+          <td class="paramname"><em>address</em></td><td>)</td>
+          <td></td>
+        </tr>
+      </table>
+</div><div class="memdoc">
+<dl class="params"><dt>Parameters</dt><dd>
+  <table class="params">
+    <tr><td class="paramdir">[in]</td><td class="paramname">address</td><td>The address in the info block</td></tr>
+  </table>
+  </dd>
+</dl>
+<dl class="section return"><dt>Returns</dt><dd><a class="el" href="group__MXC__Error__Codes.html#gaa1f0dfda864fa9d2630645f233e1fdb4" title="No Error. ">E_NO_ERROR</a> If unlocked, E_UNINITIALIZED if locked. </dd></dl>
+
 </div>
 </div>
 <a id="ga7d13b8204f1163e40d6f3369091ec562"></a>
diff --git a/lib/sdk/Documentation/html/group__flc.js b/lib/sdk/Documentation/html/group__flc.js
index a3750eaa967cec9980ea23266173254bef334816..8df09e452a871c6fb811a260412a422009640f72 100644
--- a/lib/sdk/Documentation/html/group__flc.js
+++ b/lib/sdk/Documentation/html/group__flc.js
@@ -6,6 +6,7 @@ var group__flc =
     [ "FLC_Init", "group__flc.html#gad4e017bec766e2425ecb89ab2d8d55d7", null ],
     [ "FLC_Busy", "group__flc.html#ga0cbf3341a611eb6d6cb216337a1666f0", null ],
     [ "FLC_MassErase", "group__flc.html#ga6ffdba912987544c1b9f20bfb502cafa", null ],
+    [ "FLC_MassEraseInst", "group__flc.html#ga91e5033e4b2b68ff1d0a4d352e1ac837", null ],
     [ "FLC_PageErase", "group__flc.html#gae17acd43a6a605787a9e4aa6bfb2f7f1", null ],
     [ "FLC_MultiPageErase", "group__flc.html#ga6dd7cadd48dd6794326c9513dbb28b3f", null ],
     [ "FLC_Erase", "group__flc.html#ga611826546917e9934f0156262043c95a", null ],
@@ -16,6 +17,7 @@ var group__flc =
     [ "FLC_DisableInt", "group__flc.html#ga78f8d1567ce795fcc348d15433a62e13", null ],
     [ "FLC_GetFlags", "group__flc.html#gac20cb51e1abada52834314564046bdaa", null ],
     [ "FLC_ClearFlags", "group__flc.html#gad66c50abe1036551df8fe389b48634d3", null ],
+    [ "FLC_InfoBlockUnlocked", "group__flc.html#ga9f27160d352d96821a7336fa7277f0d9", null ],
     [ "FLC_UnlockInfoBlock", "group__flc.html#ga7d13b8204f1163e40d6f3369091ec562", null ],
     [ "FLC_LockInfoBlock", "group__flc.html#ga0cb38b992f55df3a8f2b7fe191237baa", null ]
 ];
\ No newline at end of file
diff --git a/lib/sdk/Documentation/html/group__flc__registers.html b/lib/sdk/Documentation/html/group__flc__registers.html
index 5ade7b928d281699b647153de8368e146cd1ac87..927a367c778ea3b4f8b2728f7253152e7647ab95 100644
--- a/lib/sdk/Documentation/html/group__flc__registers.html
+++ b/lib/sdk/Documentation/html/group__flc__registers.html
@@ -95,6 +95,9 @@ Modules</h2></td></tr>
 <tr class="memitem:group__FLC__INTR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__FLC__INTR.html">FLC_INTR</a></td></tr>
 <tr class="memdesc:group__FLC__INTR"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash Interrupt Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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+<tr class="memdesc:group__FLC__ECC__DATA"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash Controller ECC Data Register. <br /></td></tr>
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     [ "GPIO_INT_POL", "group__GPIO__INT__POL.html", "group__GPIO__INT__POL" ],
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index 66ad6e208f6534cbb04c76f189220009d18b2945..66cc5473bb1d5d232adc2ed8104380374b376194 100644
--- a/lib/sdk/Documentation/html/group__htmr__registers.js
+++ b/lib/sdk/Documentation/html/group__htmr__registers.js
@@ -1,6 +1,7 @@
 var group__htmr__registers =
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+    [ "HTMR_SEC", "group__HTMR__SEC.html", "group__HTMR__SEC" ],
     [ "HTMR_SSEC", "group__HTMR__SSEC.html", "group__HTMR__SSEC" ],
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index 46fd396499784a24787f44005ca100da7367a901..fb9a61ba4379aa84ea8b25a262e955da6b98e2d4 100644
--- a/lib/sdk/Documentation/html/group__pwrseq.html
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index 704ad2670fa3a0cca6da6a3bd87437f0ecc0cb9e..38dabf1871e07c0c42b2debb9e6a78a7ef749d5c 100644
--- a/lib/sdk/Documentation/html/group__pwrseq.js
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@@ -56,8 +56,6 @@ var group__pwrseq =
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+    [ "PWRSEQ_LPWKST1", "group__PWRSEQ__LPWKST1.html", "group__PWRSEQ__LPWKST1" ],
+    [ "PWRSEQ_LPWKEN1", "group__PWRSEQ__LPWKEN1.html", "group__PWRSEQ__LPWKEN1" ],
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-      [ "gp1", "structmxc__pwrseq__regs__t.html#a22b51eadb62898ff2252e91f3f1d2e02", null ],
-      [ "lpmcstat", "structmxc__pwrseq__regs__t.html#ad3f173b5c522262557112a4a871643ce", null ],
-      [ "lpmcreq", "structmxc__pwrseq__regs__t.html#a28f6161d913462e38ed382f10c8f38e6", null ]
+      [ "buretvec", "structmxc__pwrseq__regs__t.html#a275e49a4b3f5f23ec82436ac339972fe", null ],
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diff --git a/lib/sdk/Documentation/html/group__rpu.html b/lib/sdk/Documentation/html/group__rpu.html
index b67dd081c7d1521ff9a371b3fc49876bfc53dca8..17cfefd135da04dbb2a04fa0dc900d335f08b576 100644
--- a/lib/sdk/Documentation/html/group__rpu.html
+++ b/lib/sdk/Documentation/html/group__rpu.html
@@ -138,7 +138,7 @@ Enumerations</h2></td></tr>
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 <br />
-&#160;&#160;<b>RPU_BBCR</b> = MXC_R_RPU_BBCR, 
+&#160;&#160;<b>RPU_MCR</b> = MXC_R_RPU_MCR, 
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@@ -160,27 +160,27 @@ Enumerations</h2></td></tr>
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-&#160;&#160;<b>RPU_I2C0</b> = MXC_R_RPU_I2C0, 
+&#160;&#160;<b>RPU_I2C0_BUS0</b> = MXC_R_RPU_I2C0_BUS0, 
 <br />
-&#160;&#160;<b>RPU_I2C1</b> = MXC_R_RPU_I2C1, 
+&#160;&#160;<b>RPU_I2C1_BUS0</b> = MXC_R_RPU_I2C1_BUS0, 
 <br />
-&#160;&#160;<b>RPU_I2C2</b> = MXC_R_RPU_I2C2, 
+&#160;&#160;<b>RPU_I2C2_BUS0</b> = MXC_R_RPU_I2C2_BUS0, 
 <br />
-&#160;&#160;<b>RPU_SPIXIPM</b> = MXC_R_RPU_SPIXIPM, 
+&#160;&#160;<b>RPU_SPIXFM</b> = MXC_R_RPU_SPIXFM, 
 <br />
-&#160;&#160;<b>RPU_SPIXIPMC</b> = MXC_R_RPU_SPIXIPMC, 
+&#160;&#160;<b>RPU_SPIXFC</b> = MXC_R_RPU_SPIXFC, 
 <br />
 &#160;&#160;<b>RPU_DMA0</b> = MXC_R_RPU_DMA0, 
 <br />
 &#160;&#160;<b>RPU_FLC1</b> = MXC_R_RPU_FLC1, 
 <br />
-&#160;&#160;<b>RPU_ICACHE0</b> = MXC_R_RPU_ICACHE0, 
+&#160;&#160;<b>RPU_ICC0</b> = MXC_R_RPU_ICC0, 
 <br />
-&#160;&#160;<b>RPU_ICACHE1</b> = MXC_R_RPU_ICACHE1, 
+&#160;&#160;<b>RPU_ICC1</b> = MXC_R_RPU_ICC1, 
 <br />
-&#160;&#160;<b>RPU_ICACHEXIP</b> = MXC_R_RPU_ICACHEXIP, 
+&#160;&#160;<b>RPU_SFCC</b> = MXC_R_RPU_SFCC, 
 <br />
-&#160;&#160;<b>RPU_DCACHE</b> = MXC_R_RPU_DCACHE, 
+&#160;&#160;<b>RPU_SRCC</b> = MXC_R_RPU_SRCC, 
 <br />
 &#160;&#160;<b>RPU_ADC</b> = MXC_R_RPU_ADC, 
 <br />
@@ -188,9 +188,9 @@ Enumerations</h2></td></tr>
 <br />
 &#160;&#160;<b>RPU_SDMA</b> = MXC_R_RPU_SDMA, 
 <br />
-&#160;&#160;<b>RPU_SPID</b> = MXC_R_RPU_SPID, 
+&#160;&#160;<b>RPU_SPIXR</b> = MXC_R_RPU_SPIXR, 
 <br />
-&#160;&#160;<b>RPU_PT</b> = MXC_R_RPU_PT, 
+&#160;&#160;<b>RPU_PTG_BUS0</b> = MXC_R_RPU_PTG_BUS0, 
 <br />
 &#160;&#160;<b>RPU_OWM</b> = MXC_R_RPU_OWM, 
 <br />
@@ -202,9 +202,9 @@ Enumerations</h2></td></tr>
 <br />
 &#160;&#160;<b>RPU_UART2</b> = MXC_R_RPU_UART2, 
 <br />
-&#160;&#160;<b>RPU_QSPI1</b> = MXC_R_RPU_QSPI1, 
+&#160;&#160;<b>RPU_SPI1</b> = MXC_R_RPU_SPI1, 
 <br />
-&#160;&#160;<b>RPU_QSPI2</b> = MXC_R_RPU_QSPI2, 
+&#160;&#160;<b>RPU_SPI2</b> = MXC_R_RPU_SPI2, 
 <br />
 &#160;&#160;<b>RPU_AUDIO</b> = MXC_R_RPU_AUDIO, 
 <br />
@@ -216,9 +216,9 @@ Enumerations</h2></td></tr>
 <br />
 &#160;&#160;<b>RPU_SDIO</b> = MXC_R_RPU_SDIO, 
 <br />
-&#160;&#160;<b>RPU_SPIXIPMFIFO</b> = MXC_R_RPU_SPIXIPMFIFO, 
+&#160;&#160;<b>RPU_SPIXM_FIFO</b> = MXC_R_RPU_SPIXM_FIFO, 
 <br />
-&#160;&#160;<b>RPU_QSPI0</b> = MXC_R_RPU_QSPI0
+&#160;&#160;<b>RPU_SPI0</b> = MXC_R_RPU_SPI0
 <br />
  }</td></tr>
 <tr class="separator:gaf1e3582ed425bd5448f738cf3428581c"><td class="memSeparator" colspan="2">&#160;</td></tr>
diff --git a/lib/sdk/Documentation/html/group__rpu__registers.html b/lib/sdk/Documentation/html/group__rpu__registers.html
index 6013ede948e48d6a96c483908000c50433fe1867..c296e21ff27fb96c49ddeddd0b110fb42d6dee60 100644
--- a/lib/sdk/Documentation/html/group__rpu__registers.html
+++ b/lib/sdk/Documentation/html/group__rpu__registers.html
@@ -125,8 +125,8 @@ Modules</h2></td></tr>
 <tr class="memitem:group__RPU__PWRSEQ"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__PWRSEQ.html">RPU_PWRSEQ</a></td></tr>
 <tr class="memdesc:group__RPU__PWRSEQ"><td class="mdescLeft">&#160;</td><td class="mdescRight">Power Sequencer Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__BBCR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__BBCR.html">RPU_BBCR</a></td></tr>
-<tr class="memdesc:group__RPU__BBCR"><td class="mdescLeft">&#160;</td><td class="mdescRight">BBCR Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__MCR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__MCR.html">RPU_MCR</a></td></tr>
+<tr class="memdesc:group__RPU__MCR"><td class="mdescLeft">&#160;</td><td class="mdescRight">MCR Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__RPU__GPIO0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__GPIO0.html">RPU_GPIO0</a></td></tr>
 <tr class="memdesc:group__RPU__GPIO0"><td class="mdescLeft">&#160;</td><td class="mdescRight">GPIO0 Protection Register. <br /></td></tr>
@@ -158,20 +158,20 @@ Modules</h2></td></tr>
 <tr class="memitem:group__RPU__HTIMER1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__HTIMER1.html">RPU_HTIMER1</a></td></tr>
 <tr class="memdesc:group__RPU__HTIMER1"><td class="mdescLeft">&#160;</td><td class="mdescRight">HTimer1 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__I2C0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__I2C0.html">RPU_I2C0</a></td></tr>
-<tr class="memdesc:group__RPU__I2C0"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C0 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__I2C0__BUS0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__I2C0__BUS0.html">RPU_I2C0_BUS0</a></td></tr>
+<tr class="memdesc:group__RPU__I2C0__BUS0"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C0 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__I2C1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__I2C1.html">RPU_I2C1</a></td></tr>
-<tr class="memdesc:group__RPU__I2C1"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C1 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__I2C1__BUS0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__I2C1__BUS0.html">RPU_I2C1_BUS0</a></td></tr>
+<tr class="memdesc:group__RPU__I2C1__BUS0"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C1 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__I2C2"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__I2C2.html">RPU_I2C2</a></td></tr>
-<tr class="memdesc:group__RPU__I2C2"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C2 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__I2C2__BUS0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__I2C2__BUS0.html">RPU_I2C2_BUS0</a></td></tr>
+<tr class="memdesc:group__RPU__I2C2__BUS0"><td class="mdescLeft">&#160;</td><td class="mdescRight">I2C2 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__SPIXIPM"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPM.html">RPU_SPIXIPM</a></td></tr>
-<tr class="memdesc:group__RPU__SPIXIPM"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI-XIP Master Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPIXFM"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXFM.html">RPU_SPIXFM</a></td></tr>
+<tr class="memdesc:group__RPU__SPIXFM"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI-XIP Master Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__SPIXIPMC"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html">RPU_SPIXIPMC</a></td></tr>
-<tr class="memdesc:group__RPU__SPIXIPMC"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI-XIP Master Controller Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPIXFC"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXFC.html">RPU_SPIXFC</a></td></tr>
+<tr class="memdesc:group__RPU__SPIXFC"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI-XIP Master Controller Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__RPU__DMA0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__DMA0.html">RPU_DMA0</a></td></tr>
 <tr class="memdesc:group__RPU__DMA0"><td class="mdescLeft">&#160;</td><td class="mdescRight">DMA0 Protection Register. <br /></td></tr>
@@ -182,17 +182,17 @@ Modules</h2></td></tr>
 <tr class="memitem:group__RPU__FLC1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__FLC1.html">RPU_FLC1</a></td></tr>
 <tr class="memdesc:group__RPU__FLC1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Flash 1 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__ICACHE0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__ICACHE0.html">RPU_ICACHE0</a></td></tr>
-<tr class="memdesc:group__RPU__ICACHE0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache 0 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__ICC0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__ICC0.html">RPU_ICC0</a></td></tr>
+<tr class="memdesc:group__RPU__ICC0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache 0 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__ICACHE1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__ICACHE1.html">RPU_ICACHE1</a></td></tr>
-<tr class="memdesc:group__RPU__ICACHE1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache 1 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__ICC1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__ICC1.html">RPU_ICC1</a></td></tr>
+<tr class="memdesc:group__RPU__ICC1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache 1 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__ICACHEXIP"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__ICACHEXIP.html">RPU_ICACHEXIP</a></td></tr>
-<tr class="memdesc:group__RPU__ICACHEXIP"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache XIP Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SFCC"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SFCC.html">RPU_SFCC</a></td></tr>
+<tr class="memdesc:group__RPU__SFCC"><td class="mdescLeft">&#160;</td><td class="mdescRight">Instruction Cache XIP Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__DCACHE"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__DCACHE.html">RPU_DCACHE</a></td></tr>
-<tr class="memdesc:group__RPU__DCACHE"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Cache Controller Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SRCC"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SRCC.html">RPU_SRCC</a></td></tr>
+<tr class="memdesc:group__RPU__SRCC"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data Cache Controller Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__RPU__ADC"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__ADC.html">RPU_ADC</a></td></tr>
 <tr class="memdesc:group__RPU__ADC"><td class="mdescLeft">&#160;</td><td class="mdescRight">ADC Protection Register. <br /></td></tr>
@@ -206,11 +206,11 @@ Modules</h2></td></tr>
 <tr class="memitem:group__RPU__SDHCCTRL"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SDHCCTRL.html">RPU_SDHCCTRL</a></td></tr>
 <tr class="memdesc:group__RPU__SDHCCTRL"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDHC Controller Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__SPID"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPID.html">RPU_SPID</a></td></tr>
-<tr class="memdesc:group__RPU__SPID"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Data Controller Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPIXR"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXR.html">RPU_SPIXR</a></td></tr>
+<tr class="memdesc:group__RPU__SPIXR"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI Data Controller Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__PT"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__PT.html">RPU_PT</a></td></tr>
-<tr class="memdesc:group__RPU__PT"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pulse Train Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__PTG__BUS0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__PTG__BUS0.html">RPU_PTG_BUS0</a></td></tr>
+<tr class="memdesc:group__RPU__PTG__BUS0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pulse Train Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__RPU__OWM"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__OWM.html">RPU_OWM</a></td></tr>
 <tr class="memdesc:group__RPU__OWM"><td class="mdescLeft">&#160;</td><td class="mdescRight">One Wire Master Protection Register. <br /></td></tr>
@@ -227,11 +227,11 @@ Modules</h2></td></tr>
 <tr class="memitem:group__RPU__UART2"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART2.html">RPU_UART2</a></td></tr>
 <tr class="memdesc:group__RPU__UART2"><td class="mdescLeft">&#160;</td><td class="mdescRight">UART2 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__QSPI1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__QSPI1.html">RPU_QSPI1</a></td></tr>
-<tr class="memdesc:group__RPU__QSPI1"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI1 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPI1"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPI1.html">RPU_SPI1</a></td></tr>
+<tr class="memdesc:group__RPU__SPI1"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI1 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__QSPI2"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__QSPI2.html">RPU_QSPI2</a></td></tr>
-<tr class="memdesc:group__RPU__QSPI2"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI2 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPI2"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPI2.html">RPU_SPI2</a></td></tr>
+<tr class="memdesc:group__RPU__SPI2"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI2 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__RPU__AUDIO"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__AUDIO.html">RPU_AUDIO</a></td></tr>
 <tr class="memdesc:group__RPU__AUDIO"><td class="mdescLeft">&#160;</td><td class="mdescRight">Audio Subsystem Protection Register. <br /></td></tr>
@@ -248,32 +248,32 @@ Modules</h2></td></tr>
 <tr class="memitem:group__RPU__SDIO"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SDIO.html">RPU_SDIO</a></td></tr>
 <tr class="memdesc:group__RPU__SDIO"><td class="mdescLeft">&#160;</td><td class="mdescRight">SDIO Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__SPIXIPMFIFO"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMFIFO.html">RPU_SPIXIPMFIFO</a></td></tr>
-<tr class="memdesc:group__RPU__SPIXIPMFIFO"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI XIP Master FIFO Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPIXM__FIFO"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXM__FIFO.html">RPU_SPIXM_FIFO</a></td></tr>
+<tr class="memdesc:group__RPU__SPIXM__FIFO"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPI XIP Master FIFO Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__QSPI0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__QSPI0.html">RPU_QSPI0</a></td></tr>
-<tr class="memdesc:group__RPU__QSPI0"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI0 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SPI0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPI0.html">RPU_SPI0</a></td></tr>
+<tr class="memdesc:group__RPU__SPI0"><td class="mdescLeft">&#160;</td><td class="mdescRight">QSPI0 Protection Register. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
-<tr class="memitem:group__RPU__SRAM0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SRAM0.html">RPU_SRAM0</a></td></tr>
-<tr class="memdesc:group__RPU__SRAM0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SRAM0 Protection Register. <br /></td></tr>
+<tr class="memitem:group__RPU__SYSRAM0"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM0.html">RPU_SYSRAM0</a></td></tr>
+<tr class="memdesc:group__RPU__SYSRAM0"><td class="mdescLeft">&#160;</td><td class="mdescRight">SYSRAM0 Protection Register. <br /></td></tr>
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diff --git a/lib/sdk/Documentation/html/group__rtc.html b/lib/sdk/Documentation/html/group__rtc.html
index a7f88296c1abe04cd676b8886954d40436512836..120b59e34c7be4d4b40e3fee9b5cde2909f6305e 100644
--- a/lib/sdk/Documentation/html/group__rtc.html
+++ b/lib/sdk/Documentation/html/group__rtc.html
@@ -102,17 +102,6 @@ Enumerations</h2></td></tr>
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-&#160;&#160;<b>NOISE_IMMUNE_MODE</b> = MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE, 
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-&#160;&#160;<b>QUIET_MODE</b> = MXC_S_RTC_CTRL_X32KMD_QUIETMODE, 
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-&#160;&#160;<b>QUIET_STOP_WARMUP_MODE</b> = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP, 
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-&#160;&#160;<b>QUIET_STOP_NOWARMUP_MODE</b> = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP
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-<tr class="memitem:gaf630f332cfe83aa088aaf8e51f51aeb7"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtc.html#gaf630f332cfe83aa088aaf8e51f51aeb7">RTC_SquareWave</a> (<a class="el" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, <a class="el" href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">rtc_sqwave_en_t</a> sqe, <a class="el" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a> ft, rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t *sys_cfg)</td></tr>
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-<tr class="separator:gaf630f332cfe83aa088aaf8e51f51aeb7"><td class="memSeparator" colspan="2">&#160;</td></tr>
+<tr class="memitem:ga3ec285956d9017f98476b4a672a6c9a2"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtc.html#ga3ec285956d9017f98476b4a672a6c9a2">RTC_SquareWave</a> (<a class="el" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, <a class="el" href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">rtc_sqwave_en_t</a> sqe, <a class="el" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a> ft, const sys_cfg_rtc_t *sys_cfg)</td></tr>
+<tr class="memdesc:ga3ec285956d9017f98476b4a672a6c9a2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Allow generation of Square Wave on the SQW pin.  <a href="#ga3ec285956d9017f98476b4a672a6c9a2">More...</a><br /></td></tr>
+<tr class="separator:ga3ec285956d9017f98476b4a672a6c9a2"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:ga80d06f8c70e8e7c4237ea04c1a306eb5"><td class="memItemLeft" align="right" valign="top">int&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__rtc.html#ga80d06f8c70e8e7c4237ea04c1a306eb5">RTC_Trim</a> (<a class="el" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, int8_t trm)</td></tr>
 <tr class="memdesc:ga80d06f8c70e8e7c4237ea04c1a306eb5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set Trim register value.  <a href="#ga80d06f8c70e8e7c4237ea04c1a306eb5">More...</a><br /></td></tr>
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@@ -519,8 +508,8 @@ Functions</h2></td></tr>
 
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-<h2 class="memtitle"><span class="permalink"><a href="#gaf630f332cfe83aa088aaf8e51f51aeb7">&#9670;&nbsp;</a></span>RTC_SquareWave()</h2>
+<a id="ga3ec285956d9017f98476b4a672a6c9a2"></a>
+<h2 class="memtitle"><span class="permalink"><a href="#ga3ec285956d9017f98476b4a672a6c9a2">&#9670;&nbsp;</a></span>RTC_SquareWave()</h2>
 
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-          <td class="paramname"><em>x32kmd</em>, </td>
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index c2d5687f82c30ff6d289c6cef657b94e249b3a7a..f636ca550966a655040e8d7c96d5a7059bb087ce 100644
--- a/lib/sdk/Documentation/html/group__rtc.js
+++ b/lib/sdk/Documentation/html/group__rtc.js
@@ -20,7 +20,7 @@ var group__rtc =
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+    [ "RTC_SquareWave", "group__rtc.html#ga3ec285956d9017f98476b4a672a6c9a2", null ],
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--- a/lib/sdk/Documentation/html/group__rtc__registers.html
+++ b/lib/sdk/Documentation/html/group__rtc__registers.html
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-<tr class="memitem:group__RTC__RAS"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__RAS.html">RTC_RAS</a></td></tr>
-<tr class="memdesc:group__RTC__RAS"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time-of-day Alarm. <br /></td></tr>
+<tr class="memitem:group__RTC__TODA"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__TODA.html">RTC_TODA</a></td></tr>
+<tr class="memdesc:group__RTC__TODA"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time-of-day Alarm. <br /></td></tr>
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-<tr class="memdesc:group__RTC__RSSA"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC sub-second alarm. <br /></td></tr>
+<tr class="memitem:group__RTC__SSECA"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__RTC__SSECA.html">RTC_SSECA</a></td></tr>
+<tr class="memdesc:group__RTC__SSECA"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTC sub-second alarm. <br /></td></tr>
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--- a/lib/sdk/Documentation/html/group__rtc__registers.js
+++ b/lib/sdk/Documentation/html/group__rtc__registers.js
@@ -2,16 +2,16 @@ var group__rtc__registers =
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-    [ "RTC_RAS", "group__RTC__RAS.html", "group__RTC__RAS" ],
-    [ "RTC_RSSA", "group__RTC__RSSA.html", "group__RTC__RSSA" ],
+    [ "RTC_TODA", "group__RTC__TODA.html", "group__RTC__TODA" ],
+    [ "RTC_SSECA", "group__RTC__SSECA.html", "group__RTC__SSECA" ],
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index 914e9493b0b9184bf81e4f322afdfffdd139bbb8..2166f15140e158febc9cd343fed6c831a49f2813 100644
--- a/lib/sdk/Documentation/html/group__spixf__registers.html
+++ b/lib/sdk/Documentation/html/group__spixf__registers.html
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+<tr class="memdesc:group__SPIXF__BUS__IDLE"><td class="mdescLeft">&#160;</td><td class="mdescRight">SPIXF Bus Idle Detection. <br /></td></tr>
+<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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--- a/lib/sdk/Documentation/html/group__spixf__registers.js
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+      [ "memseccn", "structmxc__spixf__regs__t.html#ac371b60a0d855e78325f945c91912b3f", null ],
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--- a/lib/sdk/Documentation/html/group__spixr__registers.html
+++ b/lib/sdk/Documentation/html/group__spixr__registers.html
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-<tr class="memdesc:group__SPIXR__I2S__CTRL"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register for controlling I2C mode. <br /></td></tr>
-<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
 <tr class="memitem:group__SPIXR__DMA"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__SPIXR__DMA.html">SPIXR_DMA</a></td></tr>
 <tr class="memdesc:group__SPIXR__DMA"><td class="mdescLeft">&#160;</td><td class="mdescRight">Register for controlling DMA. <br /></td></tr>
 <tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
diff --git a/lib/sdk/Documentation/html/group__spixr__registers.js b/lib/sdk/Documentation/html/group__spixr__registers.js
index e8d7304da3cdebbf6d9e113d7e582ca4253b9d78..d1d61f92c4845cf10b9ebbcf33e5ee0a962157b7 100644
--- a/lib/sdk/Documentation/html/group__spixr__registers.js
+++ b/lib/sdk/Documentation/html/group__spixr__registers.js
@@ -9,7 +9,6 @@ var group__spixr__registers =
     [ "SPIXR_CTRL3", "group__SPIXR__CTRL3.html", "group__SPIXR__CTRL3" ],
     [ "SPIXR_CTRL4", "group__SPIXR__CTRL4.html", "group__SPIXR__CTRL4" ],
     [ "SPIXR_BRG_CTRL", "group__SPIXR__BRG__CTRL.html", "group__SPIXR__BRG__CTRL" ],
-    [ "SPIXR_I2S_CTRL", "group__SPIXR__I2S__CTRL.html", "group__SPIXR__I2S__CTRL" ],
     [ "SPIXR_DMA", "group__SPIXR__DMA.html", "group__SPIXR__DMA" ],
     [ "SPIXR_IRQ", "group__SPIXR__IRQ.html", "group__SPIXR__IRQ" ],
     [ "SPIXR_IRQE", "group__SPIXR__IRQE.html", "group__SPIXR__IRQE" ],
@@ -26,7 +25,7 @@ var group__spixr__registers =
       [ "ctrl3", "structmxc__spixr__regs__t.html#a36ae9d4c3d470f49dc519eed1a8ac02a", null ],
       [ "ctrl4", "structmxc__spixr__regs__t.html#a6a681c5f9aa124a8105168e58539c1fa", null ],
       [ "brg_ctrl", "structmxc__spixr__regs__t.html#a959af8bccf851f69ace9c85e4d16f930", null ],
-      [ "i2s_ctrl", "structmxc__spixr__regs__t.html#a90608b29b3f3212205facf083fc3864e", null ],
+      [ "rsv_0x18", "structmxc__spixr__regs__t.html#acf8871d0f8778697e45b600b33691092", null ],
       [ "dma", "structmxc__spixr__regs__t.html#a22c165cb4836264617f9ca7084933cba", null ],
       [ "irq", "structmxc__spixr__regs__t.html#a0e2efcc6a2ea9a09315cd1bf411f1612", null ],
       [ "irqe", "structmxc__spixr__regs__t.html#a694583dda0ca9d64b70e997c6ed41584", null ],
diff --git a/lib/sdk/Documentation/html/htmr__regs_8h_source.html b/lib/sdk/Documentation/html/htmr__regs_8h_source.html
index a21d727b4ed97c18a566864001b09ab253211718..43af03b995760166fc6ae817e652343783d0765e 100644
--- a/lib/sdk/Documentation/html/htmr__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/htmr__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('htmr__regs_8h_source.html','');});
 <div class="title">htmr_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _HTMR_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _HTMR_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; 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MXC_F_HTMR_SSEC_RTSS_POS)) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__HTMR__RAS.html#gae74075c1df0c883876988afec222f0b9">  128</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RAS_RAS_POS                         0 </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__HTMR__RAS.html#ga9cb0d586b37fdf1e0bf6a8d94ef8513c">  129</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RAS_RAS                             ((uint32_t)(0xFFFFFUL &lt;&lt; MXC_F_HTMR_RAS_RAS_POS)) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__HTMR__RSSA.html#gaea282e444e85f719751aa38593539c5a">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RSSA_RSSA_POS                       0 </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__HTMR__RSSA.html#ga86d2f4c5f0c366feab2e86baea4ed40b">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RSSA_RSSA                           ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_HTMR_RSSA_RSSA_POS)) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga803280ad57ee3ba2ebb88528fab35159">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_HTEN_POS                       0 </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga0dd94cea5c80357232645d73580fa9e1">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_HTEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_HTEN_POS)) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga4d55e5c8e0d423aa278a2c6c095bf7bc">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ADE_POS                        1 </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaec7b1c286b0da6b26173db8a95f08fa3">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ADE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ADE_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gac2752c5a2a31365a6f6344fdba405f27">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ASE_POS                        2 </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaa4bf1c0e7ad456b6e094034f26967d2e">  158</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ASE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ASE_POS)) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga88e1a2f737318f438a9bfbd85db18a51">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_BUSY_POS                       3 </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaccf13100bbeac418a604a86e80116c91">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_BUSY                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_BUSY_POS)) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaecc53ec52ee117e5c9c3283ece391795">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDY_POS                        4 </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga5997e343c3eca878f4e0d9b7c6774f00">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDY                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_RDY_POS)) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga7af658bbd0d1dcf47b0d13848666b558">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDYE_POS                       5 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga80abfe42863d82e3bc23df47cf91b01a">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDYE                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_RDYE_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gae7b0fc779eb96ae06ee7a69bb91aa7eb">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALDF_POS                       6 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga27fda48beb32be5be3aee20fa9eb3a07">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALDF                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ALDF_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga4c0278096969a8b45d4a27de5c8c739a">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALSF_POS                       7 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga79a2db375048da274d6e759b213a31b2">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALSF                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ALSF_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga3f9689a3bb0d8338903ddc5a4cd40e22">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ACRE_POS                       14 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga69e0c18ee3555ad148c2d6b3c94f7060">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ACRE                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ACRE_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga9608b1d16956d9f485641ed7630b4992">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_WE_POS                         15 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaaf30df4b192578c6b3f33cf6e3e2050d">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_WE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_WE_POS)) </span></div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;}</div><div class="line"><a name="l00185"></a><span class="lineno">  185</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;</div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _HTMR_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__htmr__regs__t_html_aee1617647a48af22d7f0b9eca3b04200"><div class="ttname"><a href="structmxc__htmr__regs__t.html#aee1617647a48af22d7f0b9eca3b04200">mxc_htmr_regs_t::ras</a></div><div class="ttdeci">__IO uint32_t ras</div><div class="ttdoc">0x08: HTMR RAS Register </div><div class="ttdef"><b>Definition:</b> htmr_regs.h:91</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _HTMR_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _HTMR_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__htmr__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__htmr__regs__t.html#a17ec54ab4709b7f7ebd96b4c561869e8">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__htmr__regs__t.html#a17ec54ab4709b7f7ebd96b4c561869e8">sec</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__htmr__regs__t.html#ab7d391aa538691e380b9162726395d4a">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__htmr__regs__t.html#ab7d391aa538691e380b9162726395d4a">ssec</a>;                 </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__htmr__regs__t.html#aee1617647a48af22d7f0b9eca3b04200">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__htmr__regs__t.html#aee1617647a48af22d7f0b9eca3b04200">ras</a>;                  </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__htmr__regs__t.html#a47538fa66454bc9621f7478438919ca3">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__htmr__regs__t.html#a47538fa66454bc9621f7478438919ca3">rssa</a>;                 </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__htmr__regs__t.html#af15a7e78785d49661d3875fe4a8ba7f8">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__htmr__regs__t.html#af15a7e78785d49661d3875fe4a8ba7f8">ctrl</a>;                 </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;} <a class="code" href="structmxc__htmr__regs__t.html">mxc_htmr_regs_t</a>;</div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;</div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;<span class="comment">/* Register offsets for module HTMR */</span></div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="group__HTMR__Register__Offsets.html#ga4e12fcd056716b771116ab968b35fee5">  103</a></span>&#160;<span class="preprocessor"> #define MXC_R_HTMR_SEC                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="group__HTMR__Register__Offsets.html#ga2c50c81acc3e4f58b9f1f9d639d259b4">  104</a></span>&#160;<span class="preprocessor"> #define MXC_R_HTMR_SSEC                    ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__HTMR__Register__Offsets.html#ga646f0821cf6939754a64d5ac3ff12912">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_HTMR_RAS                     ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__HTMR__Register__Offsets.html#gaa9772ac5edd4d4463658f7095c936770">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_HTMR_RSSA                    ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__HTMR__Register__Offsets.html#ga519f2ced8f4aa7eaad53463982c77516">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_HTMR_CTRL                    ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__HTMR__SEC.html#gaf760018a3933ba55f6f948cb3a3a8027">  117</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_SEC_RTS_POS                         0 </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__HTMR__SEC.html#gaf0ac1a7a89a7ddc31f13020f1509b16e">  118</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_SEC_RTS                             ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_HTMR_SEC_RTS_POS)) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__HTMR__SSEC.html#ga5f8fe441711c6459113c5bfaceaaaaea">  129</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_SSEC_RTSS_POS                       0 </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__HTMR__SSEC.html#gadf070f0bfee39fbc108510d3b62c179b">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_SSEC_RTSS                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_HTMR_SSEC_RTSS_POS)) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__HTMR__RAS.html#gae74075c1df0c883876988afec222f0b9">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RAS_RAS_POS                         0 </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__HTMR__RAS.html#ga9cb0d586b37fdf1e0bf6a8d94ef8513c">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RAS_RAS                             ((uint32_t)(0xFFFFFUL &lt;&lt; MXC_F_HTMR_RAS_RAS_POS)) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__HTMR__RSSA.html#gaea282e444e85f719751aa38593539c5a">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RSSA_RSSA_POS                       0 </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__HTMR__RSSA.html#ga86d2f4c5f0c366feab2e86baea4ed40b">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_RSSA_RSSA                           ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_HTMR_RSSA_RSSA_POS)) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga803280ad57ee3ba2ebb88528fab35159">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_HTEN_POS                       0 </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga0dd94cea5c80357232645d73580fa9e1">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_HTEN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_HTEN_POS)) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga4d55e5c8e0d423aa278a2c6c095bf7bc">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ADE_POS                        1 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaec7b1c286b0da6b26173db8a95f08fa3">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ADE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ADE_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gac2752c5a2a31365a6f6344fdba405f27">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ASE_POS                        2 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaa4bf1c0e7ad456b6e094034f26967d2e">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ASE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ASE_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga88e1a2f737318f438a9bfbd85db18a51">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_BUSY_POS                       3 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaccf13100bbeac418a604a86e80116c91">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_BUSY                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_BUSY_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaecc53ec52ee117e5c9c3283ece391795">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDY_POS                        4 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga5997e343c3eca878f4e0d9b7c6774f00">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDY                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_RDY_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga7af658bbd0d1dcf47b0d13848666b558">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDYE_POS                       5 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga80abfe42863d82e3bc23df47cf91b01a">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_RDYE                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_RDYE_POS)) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gae7b0fc779eb96ae06ee7a69bb91aa7eb">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALDF_POS                       6 </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga27fda48beb32be5be3aee20fa9eb3a07">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALDF                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ALDF_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga4c0278096969a8b45d4a27de5c8c739a">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALSF_POS                       7 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga79a2db375048da274d6e759b213a31b2">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ALSF                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ALSF_POS)) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga3f9689a3bb0d8338903ddc5a4cd40e22">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ACRE_POS                       14 </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga69e0c18ee3555ad148c2d6b3c94f7060">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_ACRE                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_ACRE_POS)) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#ga9608b1d16956d9f485641ed7630b4992">  190</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_WE_POS                         15 </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__HTMR__CTRL.html#gaaf30df4b192578c6b3f33cf6e3e2050d">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_HTMR_CTRL_WE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_HTMR_CTRL_WE_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;}</div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;</div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _HTMR_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__htmr__regs__t_html_aee1617647a48af22d7f0b9eca3b04200"><div class="ttname"><a href="structmxc__htmr__regs__t.html#aee1617647a48af22d7f0b9eca3b04200">mxc_htmr_regs_t::ras</a></div><div class="ttdeci">__IO uint32_t ras</div><div class="ttdoc">0x08: HTMR RAS Register </div><div class="ttdef"><b>Definition:</b> htmr_regs.h:91</div></div>
 <div class="ttc" id="structmxc__htmr__regs__t_html"><div class="ttname"><a href="structmxc__htmr__regs__t.html">mxc_htmr_regs_t</a></div><div class="ttdoc">Structure type to access the HTMR Registers. </div><div class="ttdef"><b>Definition:</b> htmr_regs.h:88</div></div>
 <div class="ttc" id="structmxc__htmr__regs__t_html_ab7d391aa538691e380b9162726395d4a"><div class="ttname"><a href="structmxc__htmr__regs__t.html#ab7d391aa538691e380b9162726395d4a">mxc_htmr_regs_t::ssec</a></div><div class="ttdeci">__IO uint32_t ssec</div><div class="ttdoc">0x04: HTMR SSEC Register </div><div class="ttdef"><b>Definition:</b> htmr_regs.h:90</div></div>
 <div class="ttc" id="structmxc__htmr__regs__t_html_a17ec54ab4709b7f7ebd96b4c561869e8"><div class="ttname"><a href="structmxc__htmr__regs__t.html#a17ec54ab4709b7f7ebd96b4c561869e8">mxc_htmr_regs_t::sec</a></div><div class="ttdeci">__IO uint32_t sec</div><div class="ttdoc">0x00: HTMR SEC Register </div><div class="ttdef"><b>Definition:</b> htmr_regs.h:89</div></div>
diff --git a/lib/sdk/Documentation/html/i2c__regs_8h_source.html b/lib/sdk/Documentation/html/i2c__regs_8h_source.html
index 64c0dbb5fea97f21790fe5a943c4079cc8440fa1..ff1da5ef7c12124665c020f69e98c14d857d6dd4 100644
--- a/lib/sdk/Documentation/html/i2c__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/i2c__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('i2c__regs_8h_source.html','');});
 <div class="title">i2c_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _I2C_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _I2C_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a06f6109ba36c4c2ea4b547fb46330336">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a06f6109ba36c4c2ea4b547fb46330336">ctrl</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a31b564f60aa4f8cb182b03d8ec41219a">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a31b564f60aa4f8cb182b03d8ec41219a">status</a>;               </div><div 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href="structmxc__i2c__regs__t.html#af205f42e7782cd8463dd1119e007cc9d">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#af205f42e7782cd8463dd1119e007cc9d">int_en1</a>;              </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a827118813d9aed638e476cdeeb524f51">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a827118813d9aed638e476cdeeb524f51">fifo_len</a>;             </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a3b650ab9cc6f2e84372ef669bbc6c2c1">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a3b650ab9cc6f2e84372ef669bbc6c2c1">rx_ctrl0</a>;             </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a3d8432b9a97f59a7b419c47ad9fa9cf1">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a3d8432b9a97f59a7b419c47ad9fa9cf1">rx_ctrl1</a>;             </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a4bc3525c663c7a2122d09490fb0e8418">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a4bc3525c663c7a2122d09490fb0e8418">tx_ctrl0</a>;             </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a9ef1babe18d3ca68c0eafc205ae6217d">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a9ef1babe18d3ca68c0eafc205ae6217d">tx_ctrl1</a>;             </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#aa3e1e016bbb6bac0a26fd95b67c4f727">  100</a></span>&#160;    __IO uint32_t <a class="code" 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       </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#aabae162e6b74c4cec4ba5b565737e09d">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#aabae162e6b74c4cec4ba5b565737e09d">hs_clk</a>;               </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a2916a29aa03d9a04749b66d21295e698">  105</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a2916a29aa03d9a04749b66d21295e698">timeout</a>;              </div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;    __R  uint32_t rsv_0x44;</div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#abfadfe9d39e2c853972587ee91fd522e">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#abfadfe9d39e2c853972587ee91fd522e">dma</a>;                  </div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a4f6baf11b0d25f8330bf78fe0fa990d0">  108</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a4f6baf11b0d25f8330bf78fe0fa990d0">slave_addr</a>;           </div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;} <a class="code" href="structmxc__i2c__regs__t.html">mxc_i2c_regs_t</a>;</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;</div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;<span class="comment">/* Register offsets for module I2C */</span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gaf69139bbc89b167ebf91f6b6e151902d">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_CTRL                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga658d93659e64478677800ae3fdb1ba0c">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_STATUS                   ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gaf5cee0441f9f661bad992551d62cc944">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_FL0                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga586d36245b472f6634444df4e7f55046">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_EN0                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gaf1be08524d6a3e8afb021b03fa3388bd">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_FL1                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga801bd82e8c7961191b6f197c6bd62b07">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_EN1                  ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga56b10fe65728ec32ae5d8b11f7b18e53">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_FIFO_LEN                 ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga713c53f72f68be8249b08528543e53d2">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_RX_CTRL0                 ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga334c2b3906c55a2e39d25f985d36b54e">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_RX_CTRL1                 ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga577ec3b1c7b9c3b352e83304de390853">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_TX_CTRL0                 ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga35522c86b4735a06c23210e91f7846e5">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_TX_CTRL1                 ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gad87d1c73f63a4101963758c69ffcf839">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_FIFO                     ((uint32_t)0x0000002CUL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga07f1cfaa7ba682104f59b7605679e8fd">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_MASTER_CTRL              ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gad3a4c6cb6de6644e838d233707da334f">  131</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_CLK_LO                   ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga69e26dbdacb329359b412ab3d25aa7b7">  132</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_CLK_HI                   ((uint32_t)0x00000038UL) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga06105db799fb4dbdddfb7e0934c4ff7c">  133</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_HS_CLK                   ((uint32_t)0x0000003CUL) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga928ae14559e6d0eb5274ab65ae89b7af">  134</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_TIMEOUT                  ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga44d26e6f4adfebfee9d0e2c14a167663">  135</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_DMA                      ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga0324947b335e71195b72eab7c4814257">  136</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_SLAVE_ADDR               ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga8a9117b4fe205f8c8c11830d532aacb9">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_I2C_EN_POS                      0 </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gaddf3efa1bef7c3ab907a5726458c711a">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_I2C_EN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_I2C_EN_POS)) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gadf0e6473366dc5b060f6e244b660e049">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_MST_POS                         1 </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gafee80bc91a784436c8d3c8ce82faeb40">  149</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_MST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_MST_POS)) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac5c4a9e4eb7e12f3a73b51ac1941ce93">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS               2 </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga063a772ef4acf1c233e92075c74013e8">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_GEN_CALL_ADDR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga353cdf49adf093cd64ea348cfbe880c0">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE_POS                     3 </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga5cc191a6513bbefc58149b0419374743">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_RX_MODE_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac91b5f22bdcc9dcc8077f5b1d16474ed">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS                 4 </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gab40232cc4700d304715ebfe6c3b6603e">  158</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE_ACK                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gaa1566dac11f9f06557b0dd3dd8c9e305">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_OUT_POS                     6 </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga1f5b05d63621de2e002b61cb47c75f30">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_OUT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_OUT_POS)) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga147df3674d3b1b232fbe5e298de17fb2">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA_OUT_POS                     7 </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga6045a5f5a839572f3b13c0dce64e8cfa">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA_OUT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SDA_OUT_POS)) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga436f312b1f72dab365a2babae49530e3">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_POS                         8 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gabbafc7da6bbc283f678409299e83f7ee">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga0d41dd26694365a30a8f2d2902aa33d3">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA_POS                         9 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac75b6179bd704dbda93e96739a634046">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SDA_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga8e21a45b4e2d5b2c17e3b431662f1fc7">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SW_OUT_EN_POS                   10 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga39579e0316982d769be0e9b3299f5fd0">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SW_OUT_EN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SW_OUT_EN_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gadb11b95532fc3acf3f2353b8b0d4cbac">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_READ_POS                        11 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gaa54b211dd9f321e8bf3cad30e79ccb2d">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_READ                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_READ_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga964f55369f4cb5f5e956cd37a676f61c">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS          12 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga0bacb33367d1b8eef56788b7098e4b18">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS              ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac8cd8f1724e088d573d37625cdea45cb">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS                 13 </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga88e89f52274d624172e509b94130abe9">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_PP_MODE                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gafac64d1146fca4b73e3f3b040988340a">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_HS_MODE_POS                     15 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga3c1f378b061c172b8a96035d56301a3e">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_HS_MODE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_HS_MODE_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gae40581bfd02fb3ca537add038fe7a9b3">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_BUS_POS                       0 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga9c287135ec7484d6d92e164389f30c27">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_BUS                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_BUS_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaa31a80ed8e805fc110105ee3cab6a6d5">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_EMPTY_POS                  1 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gab9d5393761d4a5a9aebeabfa39dae67e">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_RX_EMPTY_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gafca3db52cf4f08196d4f67fc30fc19a4">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_FULL_POS                   2 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga3344ae128506cc0055ba3995d3597651">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_RX_FULL_POS)) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gacc2527b4b34cce2a1bd59b7692b42275">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_TX_EMPTY_POS                  3 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gae13793309f5f09a6041786c388fe6923">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_TX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gab3f035c261288eb07d87d6fe7be3e680">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_TX_FULL_POS                   4 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaf7bcd0113f0db236bbc82d6304caa8cb">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_TX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_TX_FULL_POS)) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga8959c54af24b8469d538ed3504969882">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_CLK_MODE_POS                  5 </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga7ddfbdb6fdd65bd85b5389119041fe69">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_CLK_MODE                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_CLK_MODE_POS)) </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga72c4d86d63d64a9184a6093692b56882">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_STATUS_POS                    8 </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gace4c1229324fd9f940f7767f4dd5d61c">  214</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_STATUS                        ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS)) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga2313e13e85c8db502b38ec345acca6bf">  215</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_IDLE                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaaa1d2d00ce4b00bfc58089380817f2c6">  216</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_IDLE                   (MXC_V_I2C_STATUS_STATUS_IDLE &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga12fc3aee54acc35e39a14e94d1748eea">  217</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga4756f1a5b3a424f225037bb9c347bf0a">  218</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR               (MXC_V_I2C_STATUS_STATUS_MTX_ADDR &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaac0dc350e1b5517ce32700367e7ad5a3">  219</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gacecd479122d85c4981d497775442d577">  220</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK           (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga8b0c9b8c91cb6faa04c190606c769c4b">  221</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga8027806f304ca30eed56f024ff112e9c">  222</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR            (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga4feb347ad54c47c326e4ee1c6fb82aa5">  223</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR            ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gad4b92fac8298fbe5f4b5d0319b6ffefc">  224</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR            (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga87bd88fb295626a2f9aac2b0a651e364">  225</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR               ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga2c31475a7f2f60c16e89c2c27a0ef244">  226</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR               (MXC_V_I2C_STATUS_STATUS_SRX_ADDR &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaa516256b3d3ddeaef7891871d47782ec">  227</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK           ((uint32_t)0x6UL) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga60b1d93dcf867728bc93a9586f4ac13b">  228</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK           (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga6e24ac08edb3369337fd9081b4981742">  229</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR            ((uint32_t)0x7UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga4ccab7a1284677d139de506190905cf0">  230</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR            (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga35b8daa4ce996f08150c07713ad4cdf0">  231</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK        ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gad846d53d936146573c23cea70f2eb51a">  232</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK        (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaf5ad9edb9c727d669eb9bcb7307111c4">  233</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_TX                     ((uint32_t)0x9UL) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga6b886a9eb62be4072ca8fda70a1bbdf1">  234</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_TX                     (MXC_V_I2C_STATUS_STATUS_TX &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga1fcda2b231fcb0301f9c3c7c78c53502">  235</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_RX_ACK                 ((uint32_t)0xAUL) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga445c857a431b69b3ff81de0776f88f5e">  236</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_RX_ACK                 (MXC_V_I2C_STATUS_STATUS_RX_ACK &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga10954b7e0e9f45cf926d501c995f7d8f">  237</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_RX                     ((uint32_t)0xBUL) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga0c68ac4ce5eac7d21ef4304d821ad460">  238</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_RX                     (MXC_V_I2C_STATUS_STATUS_RX &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gab5cf6e2a3c9a775133dc4fe9ad29c097">  239</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_TX_ACK                 ((uint32_t)0xCUL) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga9e404b41deb3885866dcc3c4fe476ed4">  240</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_TX_ACK                 (MXC_V_I2C_STATUS_STATUS_TX_ACK &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga5006f56957e47b02b4e224292f6b227a">  241</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_NACK                   ((uint32_t)0xDUL) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gab29f636c6a2ca857aae0c8d82794293d">  242</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_NACK                   (MXC_V_I2C_STATUS_STATUS_NACK &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gaedd7c0390a1de85b8b1ffcf552cf6adc">  243</a></span>&#160;<span class="preprocessor"> #define MXC_V_I2C_STATUS_STATUS_BY_ST                  ((uint32_t)0xFUL) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga4934afbab98c3ef66e76b863b1e9e48d">  244</a></span>&#160;<span class="preprocessor"> #define MXC_S_I2C_STATUS_STATUS_BY_ST                  (MXC_V_I2C_STATUS_STATUS_BY_ST &lt;&lt; MXC_F_I2C_STATUS_STATUS_POS) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gae2875a531113e898868cfee2a7dff4c9">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DONE_POS                     0 </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga1b07dc5a14cda3fe65135a49b0832313">  255</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DONE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_DONE_POS)) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga460bc37bc99fe74ad9e179ae404682d8">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_MODE_POS                  1 </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga2f7bbf5a6d4d8ee6f525e36127d20518">  258</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_MODE                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_RX_MODE_POS)) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga0c151db913a2201aa64a971e211817c8">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS            2 </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gae5b457573db720a1b5cf979dca1d5090">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaaa02db6e62fe4f7584811e3e758a906f">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS               3 </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gac43a5f0beb7dcab47de1400c167ae3a5">  264</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_MATCH                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga8c76f3c37fd9026da0ed4cf34a23cace">  266</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_THRESH_POS                4 </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga1bf6532416fa956dd4c3cddfafa858d1">  267</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_RX_THRESH_POS)) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gad3f8d699b2366b43f31312b9f6699175">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_THRESH_POS                5 </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gab7d3742950534541900fd89100f8fa81">  270</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_TX_THRESH_POS)) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga8c52bd19addec1feeb11ca7798c476bb">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP_POS                     6 </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga22a088fa9c286c8f8903bb34373d2cb9">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_STOP_POS)) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga155e1a67a6e212ec8267c7c61c710a43">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS                 7 </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga2d63dfdfd5a98f3b565bb389ded75d0b">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_ACK                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gad079f6deaa2bd753edf34e2dc3c22193">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ARB_ER_POS                   8 </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga9c775de88a357206c009c0941110bff9">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ARB_ER 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class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga5a141e253f96b063bec8e1fc31485235">  285</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaa324df81212a18b9060aa674c6179e62">  287</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DATA_ER_POS                  11 </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga03c3239a1bbc77b4e7ed9b3117b04ca2">  288</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DATA_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_DATA_ER_POS)) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gacc878b1d4a818049f2398dcbe6065db9">  290</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS           12 </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gabb2e392fc70c087049d4e6c8d129f4a9">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga58e09c04c88777133ed95f8e9e71160a">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_START_ER_POS                 13 </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga89c3fa0544e725b278cc8d07999c0ec4">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_START_ER                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_START_ER_POS)) </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga3a1b65b6e7c798094124401e00c1bd97">  296</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP_ER_POS                  14 </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaca1f1827067881ea7e6b7a5d64cd2542">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_STOP_ER_POS)) </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga0727b6e19dc9a95f3b7f7b4c0a744f89">  299</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS              15 </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga5fdead37e2a3629ae1c817246c8cfbfe">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga678df8f1118121e20ff5a63bbe1634fa">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DONE_POS                     0 </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga9eccbf7898a8c9fea30fdcf4c10ba83c">  311</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DONE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_DONE_POS)) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga3f3aaa84cd1383c994dbbb92b522de8c">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_MODE_POS                  1 </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga386c3de6f74b2d17854303b1384a8738">  314</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_MODE                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_RX_MODE_POS)) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga8fe7637ff5c91c01f24e43da8dff5481">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS            2 </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga30f538eba59f055279c00a3ee0c22e46">  317</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gab0ae99ac8cfcd5b541fb214ac5c3936b">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS               3 </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gacc9fba58c14468a6b5eee54340bae4ab">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_MATCH                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gabbc0b2e744f457b413187a888ee7cc07">  322</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_THRESH_POS                4 </span></div><div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gabca7f3de267ef44a329438718f71d023">  323</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_RX_THRESH_POS)) </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gad608233cbef83b3008fa0c1d4eb3a834">  325</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_THRESH_POS                5 </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga8147b8722a48f5be771fa8a7e4147a9d">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_TX_THRESH_POS)) </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gab694a3a9a0305769a2683400fa9ed15b">  328</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP_POS                     6 </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf4021b499cbe0726f219d7dde825253a">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_STOP_POS)) </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf940d4d08ebcc71620fd4b79effb7cd4">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS                 7 </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga76ab5649bcdc0774f9ffd57077dff0a6">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ACK                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga82ecc62b84929de71259c6d1648187f6">  334</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ARB_ER_POS                   8 </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga2d2f6eca9cb372090d02331600b3773b">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ARB_ER                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ARB_ER_POS)) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga591ca9e47303cfb108570073889e0172">  337</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TO_ER_POS                    9 </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf4102d1ae95372a11d29575291eefd40">  338</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TO_ER                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_TO_ER_POS)) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga0f3c07af5bcf9eee564854c16eaa4cb9">  340</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ER_POS                  10 </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gabd93d451cac4053ca657a1b489feec5e">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ADDR_ER_POS)) </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga16ab8ea52281316fe11c5044cce24826">  343</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DATA_ER_POS                  11 </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf994e2a4aec70a5f530e942b0c6a53b8">  344</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DATA_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_DATA_ER_POS)) </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga029bcdf82564e32f49693947d5127aaa">  346</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS           12 </span></div><div class="line"><a name="l00347"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga512f007e7513667ddad911dbfc67a1a1">  347</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) </span></div><div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gad257ebab768fb1860ca2631a607a05d1">  349</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_START_ER_POS                 13 </span></div><div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga2f904e26118b53e12aecc4f49abd3b2c">  350</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_START_ER                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_START_ER_POS)) </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga609700a3f42247a532b3193759507abb">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP_ER_POS                  14 </span></div><div class="line"><a name="l00353"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf517da5ae427334ad38af7cdb09fd271">  353</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_STOP_ER_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga49c5eb1dc116ecdab93d8fbebc1fa7f5">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS              15 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga4759fe60047ffb81879ef1f31d332c33">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) </span></div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga41e085b6fda3eef836cdad9a467c5de2">  366</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS              0 </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga9a5cf0178c8f11229f1bf33e9864158d">  367</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_RX_OVERFLOW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#gad27273c89970675523aafe2c7b2f67fb">  369</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS             1 </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga69b32cfe3c3846de24e296e7f0c6f2e8">  370</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#gafc875c885df3a4d3d95d9b76d663640f">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS              0 </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#ga9bf9eda8efc52023c268dad9ae57339c">  381</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_RX_OVERFLOW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#ga73fb0f04d4a70ed3cc0d8b19158a8100">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS             1 </span></div><div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#gae7d0d8d7aa75c415be274b0320fee224">  384</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#ga8220af1cf67d545751c568a689b8818f">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS                  0 </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#ga8c646d23e5ef61a6f5be09c5f09e5619">  395</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_RX_LEN                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#gae5af1df06317ff9d2eb44f80ef562e69">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS                  8 </span></div><div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#ga423ac93f02361022c642692cb7923cf3">  398</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_TX_LEN                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) </span></div><div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga0eb1fe1f481c693d393a8c67444dc317">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_DNR_POS                     0 </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga1295653d9c2b1dbf8967aa353b7ab433">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_DNR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_RX_CTRL0_DNR_POS)) </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga70d478cb42c5db04fbe44f1498fb207b">  411</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS                7 </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga7e7606672ee72f92e7cae76056730cfa">  412</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_FLUSH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) </span></div><div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga3bc60eb35253f38ab8a67de28fc7d058">  414</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS               8 </span></div><div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#gaccb253439880402feb8c4a2b1637ef97">  415</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_THRESH                   ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#gaba54fbecbfa00d6a1905e728c8b9f1ef">  425</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS                  0 </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#ga1b600c1a92ba679863effae2e58d86ce">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_CNT                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) </span></div><div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#ga501355daeed99f17e71b078e3eec2220">  428</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS                 8 </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#ga193a9126e9fa210cb25afa3e9899cf11">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_FIFO                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) </span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga74630a954110bef5ec0a34c8e450c601">  439</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS              0 </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga90b0482fe14bbeae88f69d1fa8e8cf16">  440</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) </span></div><div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga3042941ff5a0bc134e586ce2fde5d9a9">  442</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS           1 </span></div><div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga26af00f81b0cd84aba67440058a022b8">  443</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) </span></div><div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gad48be875120e447870026e793f4218ac">  445</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS                7 </span></div><div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gaadd0eafb703ccd371b9dc8c03194e84a">  446</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_FLUSH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) </span></div><div class="line"><a name="l00448"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gaad2d44565b2018ccb3f69d3d2fc3aa0b">  448</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS               8 </span></div><div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga7273cbba4414015d12e69105890a73de">  449</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_THRESH                   ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) </span></div><div class="line"><a name="l00459"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga1212d37b1ba2f49ba58655f55886405d">  459</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_READY_POS                0 </span></div><div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga50a3b648fb07188c733c4650831858c9">  460</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_READY                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL1_TX_READY_POS)) </span></div><div class="line"><a name="l00462"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga2b1b92ecc76563de4569f95beb50dde1">  462</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS                 1 </span></div><div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#gae15106166c91a823f1afd28b1fd4b150">  463</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_LAST                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) </span></div><div class="line"><a name="l00465"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga72ddb30fa90dddd97658e6b0c94eb7b2">  465</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS                 8 </span></div><div class="line"><a name="l00466"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga4390142d222c29df100ccf5c9c0670cb">  466</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_FIFO                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) </span></div><div class="line"><a name="l00476"></a><span class="lineno"><a class="line" href="group__I2C__FIFO.html#ga478326c531bd736d4cea31685c6d1a2d">  476</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_DATA_POS                        0 </span></div><div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="group__I2C__FIFO.html#gacbd19f71a81bee962102b5ca98d76de8">  477</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_DATA                            ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_FIFO_DATA_POS)) </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga18dfb884e33752231f87d0efbd5bfe09">  487</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_START_POS                0 </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gafa730baaf1e72bbe672060e5421b2304">  488</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_START                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_START_POS)) </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga16a37d78f018afcbf4c31985c9dba801">  490</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_RESTART_POS              1 </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga0206f1e9b654f910c34699da7b10a2c3">  491</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_RESTART                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_RESTART_POS)) </span></div><div class="line"><a name="l00493"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga5262b9fab4a1b3d61c78b0f52d886629">  493</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_STOP_POS                 2 </span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gadb0bb1a23f2f57615e06c3a2c1a9eed0">  494</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_STOP                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_STOP_POS)) </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga2d43ee3c8189f595859b061e5205799c">  496</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS           7 </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga05d40d5756b4f22f81da2420fec80d71">  497</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga61f14e29c9e2280c419aaf2a8b593bb3">  499</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS          8 </span></div><div class="line"><a name="l00500"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gafcf0bfc40249df241290cbe623ad3f81">  500</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE              ((uint32_t)(0x7UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) </span></div><div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga2a0f153ddac5374cc1a2e2d66dd7903d">  502</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS         11 </span></div><div class="line"><a name="l00503"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gab561d51abd933db62deea048c7a60628">  503</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) </span></div><div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="group__I2C__CLK__LO.html#ga4adcf06b8c73fb66ab2d38331c5435fc">  513</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_LO_CLK_LO_POS                    0 </span></div><div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group__I2C__CLK__LO.html#gaf2cede0f20feaa35fdefb97388c6956b">  514</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_LO_CLK_LO                        ((uint32_t)(0x1FFUL &lt;&lt; MXC_F_I2C_CLK_LO_CLK_LO_POS)) </span></div><div class="line"><a name="l00524"></a><span class="lineno"><a class="line" href="group__I2C__CLK__HI.html#ga5539bfb7b33e486a17d6b5fe54c046ac">  524</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_HI_CKH_POS                       0 </span></div><div class="line"><a name="l00525"></a><span class="lineno"><a class="line" href="group__I2C__CLK__HI.html#ga2ed3220bae741613257865608a7818c5">  525</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_HI_CKH                           ((uint32_t)(0x1FFUL &lt;&lt; MXC_F_I2C_CLK_HI_CKH_POS)) </span></div><div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga1457a762d7e2e903204218a4acb0d7a5">  535</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS                 0 </span></div><div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga0f64333fb7515965765015e9385f3424">  536</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_LO                     ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) </span></div><div class="line"><a name="l00538"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga62466d0f8a60fde594ad9254e314fd96">  538</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS                 8 </span></div><div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga53f1e57e86392dd1498b2e41f6d34326">  539</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_HI                     ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) </span></div><div class="line"><a name="l00549"></a><span class="lineno"><a class="line" href="group__I2C__TIMEOUT.html#gacaec72653bf4c5d0c4c2d2f44e981443">  549</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TIMEOUT_TO_POS                       0 </span></div><div class="line"><a name="l00550"></a><span class="lineno"><a class="line" href="group__I2C__TIMEOUT.html#ga3c69477fcc49ee1388a9b2a78d25dbc0">  550</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TIMEOUT_TO                           ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_I2C_TIMEOUT_TO_POS)) </span></div><div class="line"><a name="l00560"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#ga456c86b3519c4c7f464dcfee939745af">  560</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_TX_EN_POS                        0 </span></div><div class="line"><a name="l00561"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#ga9679d9ae76ce2c083fcba8f5e070e39e">  561</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_TX_EN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_DMA_TX_EN_POS)) </span></div><div class="line"><a name="l00563"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#ga9242f64456c699657f8d7fc849933f9b">  563</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_RX_EN_POS                        1 </span></div><div class="line"><a name="l00564"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#gac99eefebbd24f16f50c871016d487595">  564</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_RX_EN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_DMA_RX_EN_POS)) </span></div><div class="line"><a name="l00574"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#gac46213e0f081bc639aad8428fe92078c">  574</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS            0 </span></div><div class="line"><a name="l00575"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#ga73690311b878c0ac6ed4e6f962966273">  575</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR                ((uint32_t)(0x3FFUL &lt;&lt; MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) </span></div><div class="line"><a name="l00577"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#gabdc42ae8617cfe2fb52df904dc02488d">  577</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS        10 </span></div><div class="line"><a name="l00578"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#gac862c2645a7e9502950ecad9e3c1bf64">  578</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) </span></div><div class="line"><a name="l00580"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#ga7a08433dc406828c8ad4287142c7f347">  580</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS        11 </span></div><div class="line"><a name="l00581"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#ga82953a4b7c13523a88d0fde829e3ceb7">  581</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX            ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) </span></div><div class="line"><a name="l00583"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#ga33df07a4b21768c70fc4aeabcbd036f8">  583</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS               15 </span></div><div class="line"><a name="l00584"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#gabbc2a157709891a5843c594d4353bc86">  584</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) </span></div><div class="line"><a name="l00588"></a><span class="lineno">  588</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00589"></a><span class="lineno">  589</span>&#160;}</div><div class="line"><a name="l00590"></a><span class="lineno">  590</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00591"></a><span class="lineno">  591</span>&#160;</div><div class="line"><a name="l00592"></a><span class="lineno">  592</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _I2C_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__i2c__regs__t_html_a8aae0d638a74fc50445c4f1a53fad3b5"><div class="ttname"><a href="structmxc__i2c__regs__t.html#a8aae0d638a74fc50445c4f1a53fad3b5">mxc_i2c_regs_t::int_en0</a></div><div class="ttdeci">__IO uint32_t int_en0</div><div class="ttdoc">0x0C: I2C INT_EN0 Register </div><div class="ttdef"><b>Definition:</b> i2c_regs.h:92</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _I2C_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _I2C_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a06f6109ba36c4c2ea4b547fb46330336">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a06f6109ba36c4c2ea4b547fb46330336">ctrl</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a31b564f60aa4f8cb182b03d8ec41219a">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a31b564f60aa4f8cb182b03d8ec41219a">status</a>;               </div><div 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href="structmxc__i2c__regs__t.html#af205f42e7782cd8463dd1119e007cc9d">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#af205f42e7782cd8463dd1119e007cc9d">int_en1</a>;              </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a827118813d9aed638e476cdeeb524f51">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a827118813d9aed638e476cdeeb524f51">fifo_len</a>;             </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a3b650ab9cc6f2e84372ef669bbc6c2c1">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a3b650ab9cc6f2e84372ef669bbc6c2c1">rx_ctrl0</a>;             </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a3d8432b9a97f59a7b419c47ad9fa9cf1">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a3d8432b9a97f59a7b419c47ad9fa9cf1">rx_ctrl1</a>;             </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a4bc3525c663c7a2122d09490fb0e8418">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a4bc3525c663c7a2122d09490fb0e8418">tx_ctrl0</a>;             </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#a9ef1babe18d3ca68c0eafc205ae6217d">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__i2c__regs__t.html#a9ef1babe18d3ca68c0eafc205ae6217d">tx_ctrl1</a>;             </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__i2c__regs__t.html#aa3e1e016bbb6bac0a26fd95b67c4f727">  100</a></span>&#160;    __IO uint32_t <a class="code" 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#define MXC_R_I2C_CTRL                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga658d93659e64478677800ae3fdb1ba0c">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_STATUS                   ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gaf5cee0441f9f661bad992551d62cc944">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_FL0                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga586d36245b472f6634444df4e7f55046">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_EN0                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gaf1be08524d6a3e8afb021b03fa3388bd">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_FL1                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga801bd82e8c7961191b6f197c6bd62b07">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_INT_EN1                  ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga56b10fe65728ec32ae5d8b11f7b18e53">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_FIFO_LEN                 ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga713c53f72f68be8249b08528543e53d2">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_RX_CTRL0                 ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga334c2b3906c55a2e39d25f985d36b54e">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_RX_CTRL1                 ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga577ec3b1c7b9c3b352e83304de390853">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_TX_CTRL0                 ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga35522c86b4735a06c23210e91f7846e5">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_TX_CTRL1                 ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gad87d1c73f63a4101963758c69ffcf839">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_FIFO                     ((uint32_t)0x0000002CUL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga07f1cfaa7ba682104f59b7605679e8fd">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_MASTER_CTRL              ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#gad3a4c6cb6de6644e838d233707da334f">  131</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_CLK_LO                   ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga69e26dbdacb329359b412ab3d25aa7b7">  132</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_CLK_HI                   ((uint32_t)0x00000038UL) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga06105db799fb4dbdddfb7e0934c4ff7c">  133</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_HS_CLK                   ((uint32_t)0x0000003CUL) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga928ae14559e6d0eb5274ab65ae89b7af">  134</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_TIMEOUT                  ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga44d26e6f4adfebfee9d0e2c14a167663">  135</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_DMA                      ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__I2C__Register__Offsets.html#ga0324947b335e71195b72eab7c4814257">  136</a></span>&#160;<span class="preprocessor"> #define MXC_R_I2C_SLAVE_ADDR               ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga8a9117b4fe205f8c8c11830d532aacb9">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_I2C_EN_POS                      0 </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gaddf3efa1bef7c3ab907a5726458c711a">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_I2C_EN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_I2C_EN_POS)) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gadf0e6473366dc5b060f6e244b660e049">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_MST_POS                         1 </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gafee80bc91a784436c8d3c8ce82faeb40">  149</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_MST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_MST_POS)) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac5c4a9e4eb7e12f3a73b51ac1941ce93">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS               2 </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga063a772ef4acf1c233e92075c74013e8">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_GEN_CALL_ADDR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga353cdf49adf093cd64ea348cfbe880c0">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE_POS                     3 </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga5cc191a6513bbefc58149b0419374743">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_RX_MODE_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac91b5f22bdcc9dcc8077f5b1d16474ed">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS                 4 </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gab40232cc4700d304715ebfe6c3b6603e">  158</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_RX_MODE_ACK                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gaa1566dac11f9f06557b0dd3dd8c9e305">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_OUT_POS                     6 </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga1f5b05d63621de2e002b61cb47c75f30">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_OUT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_OUT_POS)) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga147df3674d3b1b232fbe5e298de17fb2">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA_OUT_POS                     7 </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga6045a5f5a839572f3b13c0dce64e8cfa">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA_OUT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SDA_OUT_POS)) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga436f312b1f72dab365a2babae49530e3">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_POS                         8 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gabbafc7da6bbc283f678409299e83f7ee">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga0d41dd26694365a30a8f2d2902aa33d3">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA_POS                         9 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac75b6179bd704dbda93e96739a634046">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SDA                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SDA_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga8e21a45b4e2d5b2c17e3b431662f1fc7">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SW_OUT_EN_POS                   10 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga39579e0316982d769be0e9b3299f5fd0">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SW_OUT_EN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SW_OUT_EN_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gadb11b95532fc3acf3f2353b8b0d4cbac">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_READ_POS                        11 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gaa54b211dd9f321e8bf3cad30e79ccb2d">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_READ                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_READ_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga964f55369f4cb5f5e956cd37a676f61c">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS          12 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga0bacb33367d1b8eef56788b7098e4b18">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS              ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gac8cd8f1724e088d573d37625cdea45cb">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS                 13 </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#ga88e89f52274d624172e509b94130abe9">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_SCL_PP_MODE                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__I2C__CTRL.html#gafac64d1146fca4b73e3f3b040988340a">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CTRL_HS_MODE_POS               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href="group__I2C__STATUS.html#gaa31a80ed8e805fc110105ee3cab6a6d5">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_EMPTY_POS                  1 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gab9d5393761d4a5a9aebeabfa39dae67e">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_RX_EMPTY_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#gafca3db52cf4f08196d4f67fc30fc19a4">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_FULL_POS                   2 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga3344ae128506cc0055ba3995d3597651">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_RX_FULL          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class="line" href="group__I2C__STATUS.html#gaf7bcd0113f0db236bbc82d6304caa8cb">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_TX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_TX_FULL_POS)) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga8959c54af24b8469d538ed3504969882">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_CLK_MODE_POS                  5 </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__I2C__STATUS.html#ga7ddfbdb6fdd65bd85b5389119041fe69">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_STATUS_CLK_MODE                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_STATUS_CLK_MODE_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gae2875a531113e898868cfee2a7dff4c9">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DONE_POS                     0 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga1b07dc5a14cda3fe65135a49b0832313">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DONE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_DONE_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga460bc37bc99fe74ad9e179ae404682d8">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_MODE_POS                  1 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga2f7bbf5a6d4d8ee6f525e36127d20518">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_MODE                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_RX_MODE_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga0c151db913a2201aa64a971e211817c8">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS            2 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gae5b457573db720a1b5cf979dca1d5090">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaaa02db6e62fe4f7584811e3e758a906f">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS               3 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gac43a5f0beb7dcab47de1400c167ae3a5">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_MATCH                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga8c76f3c37fd9026da0ed4cf34a23cace">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_THRESH_POS                4 </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga1bf6532416fa956dd4c3cddfafa858d1">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_RX_THRESH_POS)) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gad3f8d699b2366b43f31312b9f6699175">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_THRESH_POS                5 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gab7d3742950534541900fd89100f8fa81">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_TX_THRESH_POS)) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga8c52bd19addec1feeb11ca7798c476bb">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP_POS                     6 </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga22a088fa9c286c8f8903bb34373d2cb9">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_STOP_POS)) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga155e1a67a6e212ec8267c7c61c710a43">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS                 7 </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga2d63dfdfd5a98f3b565bb389ded75d0b">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_ACK                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gad079f6deaa2bd753edf34e2dc3c22193">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ARB_ER_POS                   8 </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga9c775de88a357206c009c0941110bff9">  246</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ARB_ER                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ARB_ER_POS)) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga4fa1ebb4b37fa4e12b9f66cf0b7274da">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TO_ER_POS                    9 </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga7ced50b421bb2865809e77102527a608">  249</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TO_ER                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_TO_ER_POS)) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaae6d23ba52fc57d3fd022d14b5102073">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS             10 </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga5a141e253f96b063bec8e1fc31485235">  252</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaa324df81212a18b9060aa674c6179e62">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DATA_ER_POS                  11 </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga03c3239a1bbc77b4e7ed9b3117b04ca2">  255</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DATA_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_DATA_ER_POS)) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gacc878b1d4a818049f2398dcbe6065db9">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS           12 </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gabb2e392fc70c087049d4e6c8d129f4a9">  258</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga58e09c04c88777133ed95f8e9e71160a">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_START_ER_POS                 13 </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga89c3fa0544e725b278cc8d07999c0ec4">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_START_ER                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_START_ER_POS)) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga3a1b65b6e7c798094124401e00c1bd97">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP_ER_POS                  14 </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaca1f1827067881ea7e6b7a5d64cd2542">  264</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_STOP_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_STOP_ER_POS)) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga0727b6e19dc9a95f3b7f7b4c0a744f89">  266</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS              15 </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga5fdead37e2a3629ae1c817246c8cfbfe">  267</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga1c4ec0b26a053c9a0dd705cd70c5bdc8">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS            22 </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gaff15d4591805226703aab48f0c2ec838">  270</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#ga119324029d68867e4f849dc5aa6a9aa4">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS            23 </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL0.html#gae264b73126562104f77ff5fd4d03a8a9">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga678df8f1118121e20ff5a63bbe1634fa">  283</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DONE_POS                     0 </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga9eccbf7898a8c9fea30fdcf4c10ba83c">  284</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DONE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_DONE_POS)) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga3f3aaa84cd1383c994dbbb92b522de8c">  286</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_MODE_POS                  1 </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga386c3de6f74b2d17854303b1384a8738">  287</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_MODE                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_RX_MODE_POS)) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga8fe7637ff5c91c01f24e43da8dff5481">  289</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS            2 </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga30f538eba59f055279c00a3ee0c22e46">  290</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gab0ae99ac8cfcd5b541fb214ac5c3936b">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS               3 </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gacc9fba58c14468a6b5eee54340bae4ab">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_MATCH                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gabbc0b2e744f457b413187a888ee7cc07">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_THRESH_POS                4 </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gabca7f3de267ef44a329438718f71d023">  296</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_RX_THRESH_POS)) </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gad608233cbef83b3008fa0c1d4eb3a834">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_THRESH_POS                5 </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga8147b8722a48f5be771fa8a7e4147a9d">  299</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_TX_THRESH_POS)) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gab694a3a9a0305769a2683400fa9ed15b">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP_POS                     6 </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf4021b499cbe0726f219d7dde825253a">  302</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_STOP_POS)) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf940d4d08ebcc71620fd4b79effb7cd4">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS                 7 </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga76ab5649bcdc0774f9ffd57077dff0a6">  305</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ACK                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga82ecc62b84929de71259c6d1648187f6">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ARB_ER_POS                   8 </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga2d2f6eca9cb372090d02331600b3773b">  308</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ARB_ER                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ARB_ER_POS)) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga591ca9e47303cfb108570073889e0172">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TO_ER_POS                    9 </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf4102d1ae95372a11d29575291eefd40">  311</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TO_ER                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_TO_ER_POS)) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga0f3c07af5bcf9eee564854c16eaa4cb9">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ER_POS                  10 </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gabd93d451cac4053ca657a1b489feec5e">  314</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_ADDR_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_ADDR_ER_POS)) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga16ab8ea52281316fe11c5044cce24826">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DATA_ER_POS                  11 </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf994e2a4aec70a5f530e942b0c6a53b8">  317</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DATA_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_DATA_ER_POS)) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga029bcdf82564e32f49693947d5127aaa">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS           12 </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga512f007e7513667ddad911dbfc67a1a1">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) </span></div><div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gad257ebab768fb1860ca2631a607a05d1">  322</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_START_ER_POS                 13 </span></div><div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga2f904e26118b53e12aecc4f49abd3b2c">  323</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_START_ER                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_START_ER_POS)) </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga609700a3f42247a532b3193759507abb">  325</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP_ER_POS                  14 </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaf517da5ae427334ad38af7cdb09fd271">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_STOP_ER                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_STOP_ER_POS)) </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga49c5eb1dc116ecdab93d8fbebc1fa7f5">  328</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS              15 </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga4759fe60047ffb81879ef1f31d332c33">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga8b87d1dc1508fcd8b5d4121588723c87">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS            22 </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga511414f1d471f9869f4bb5e70ef3b1f5">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#gaa76482516e93666dbc75002a9e8f7386">  334</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS            23 </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN0.html#ga42bb9d06571b621f7d0e1a5e49bb8abd">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH                ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS)) </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga41e085b6fda3eef836cdad9a467c5de2">  345</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS              0 </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga9a5cf0178c8f11229f1bf33e9864158d">  346</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_RX_OVERFLOW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) </span></div><div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#gad27273c89970675523aafe2c7b2f67fb">  348</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS             1 </span></div><div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga69b32cfe3c3846de24e296e7f0c6f2e8">  349</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) </span></div><div class="line"><a name="l00351"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga25cc26693f6a4a5c3a92d13ca11d4946">  351</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_START_POS                    2 </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__I2C__INT__FL1.html#ga09d13fb9c3faa7994a6369a4e60c6450">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_FL1_START                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_FL1_START_POS)) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#gafc875c885df3a4d3d95d9b76d663640f">  362</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS              0 </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#ga9bf9eda8efc52023c268dad9ae57339c">  363</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_RX_OVERFLOW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) </span></div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#ga73fb0f04d4a70ed3cc0d8b19158a8100">  365</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS             1 </span></div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#gae7d0d8d7aa75c415be274b0320fee224">  366</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#ga75acf6309e89235c523774c9a4024cc8">  368</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_START_POS                    2 </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__I2C__INT__EN1.html#ga20e92b0de801cf8815b3b551cb1273f7">  369</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_INT_EN1_START                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_INT_EN1_START_POS)) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#ga8220af1cf67d545751c568a689b8818f">  379</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS                  0 </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#ga8c646d23e5ef61a6f5be09c5f09e5619">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_RX_LEN                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#gae5af1df06317ff9d2eb44f80ef562e69">  382</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS                  8 </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__I2C__FIFO__LEN.html#ga423ac93f02361022c642692cb7923cf3">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_LEN_TX_LEN                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga0eb1fe1f481c693d393a8c67444dc317">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_DNR_POS                     0 </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga1295653d9c2b1dbf8967aa353b7ab433">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_DNR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_RX_CTRL0_DNR_POS)) </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga70d478cb42c5db04fbe44f1498fb207b">  396</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS                7 </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga7e7606672ee72f92e7cae76056730cfa">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_FLUSH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#ga3bc60eb35253f38ab8a67de28fc7d058">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS               8 </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL0.html#gaccb253439880402feb8c4a2b1637ef97">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL0_RX_THRESH                   ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) </span></div><div class="line"><a name="l00410"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#gaba54fbecbfa00d6a1905e728c8b9f1ef">  410</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS                  0 </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#ga1b600c1a92ba679863effae2e58d86ce">  411</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_CNT                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) </span></div><div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#ga501355daeed99f17e71b078e3eec2220">  413</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS                 8 </span></div><div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group__I2C__RX__CTRL1.html#ga193a9126e9fa210cb25afa3e9899cf11">  414</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_RX_CTRL1_RX_FIFO                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga74630a954110bef5ec0a34c8e450c601">  424</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS              0 </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga90b0482fe14bbeae88f69d1fa8e8cf16">  425</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) </span></div><div class="line"><a name="l00427"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga3042941ff5a0bc134e586ce2fde5d9a9">  427</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS           1 </span></div><div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga26af00f81b0cd84aba67440058a022b8">  428</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) </span></div><div class="line"><a name="l00430"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga0923689f25a83e897638b658f0a16fd9">  430</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS             2 </span></div><div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga189de16f7f78a1d65e9aece0bd5d4116">  431</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS)) </span></div><div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga3e9fae8b136784898c9d6daf2f331cf4">  433</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS              3 </span></div><div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga4543f5eb5c086a1133d624b6162981f0">  434</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS)) </span></div><div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gaceb8864ca1bda9d0dec92142cae7211e">  436</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS              4 </span></div><div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga9746703e5e01e63d5496f33b1b200b92">  437</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS)) </span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gaa570eab7523c71331acccd2c130bcea1">  439</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS             5 </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga61fd78f35e387d504135528f4d08359e">  440</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS)) </span></div><div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gad48be875120e447870026e793f4218ac">  442</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS                7 </span></div><div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gaadd0eafb703ccd371b9dc8c03194e84a">  443</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_FLUSH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) </span></div><div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#gaad2d44565b2018ccb3f69d3d2fc3aa0b">  445</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS               8 </span></div><div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL0.html#ga7273cbba4414015d12e69105890a73de">  446</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL0_TX_THRESH                   ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) </span></div><div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga1212d37b1ba2f49ba58655f55886405d">  456</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_READY_POS                0 </span></div><div class="line"><a name="l00457"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga50a3b648fb07188c733c4650831858c9">  457</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_READY                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL1_TX_READY_POS)) </span></div><div class="line"><a name="l00459"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga2b1b92ecc76563de4569f95beb50dde1">  459</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS                 1 </span></div><div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#gae15106166c91a823f1afd28b1fd4b150">  460</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_LAST                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) </span></div><div class="line"><a name="l00462"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga72ddb30fa90dddd97658e6b0c94eb7b2">  462</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS                 8 </span></div><div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group__I2C__TX__CTRL1.html#ga4390142d222c29df100ccf5c9c0670cb">  463</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TX_CTRL1_TX_FIFO                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) </span></div><div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="group__I2C__FIFO.html#ga478326c531bd736d4cea31685c6d1a2d">  473</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_DATA_POS                        0 </span></div><div class="line"><a name="l00474"></a><span class="lineno"><a class="line" href="group__I2C__FIFO.html#gacbd19f71a81bee962102b5ca98d76de8">  474</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_FIFO_DATA                            ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_FIFO_DATA_POS)) </span></div><div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga18dfb884e33752231f87d0efbd5bfe09">  484</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_START_POS                0 </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gafa730baaf1e72bbe672060e5421b2304">  485</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_START                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_START_POS)) </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga16a37d78f018afcbf4c31985c9dba801">  487</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_RESTART_POS              1 </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga0206f1e9b654f910c34699da7b10a2c3">  488</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_RESTART                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_RESTART_POS)) </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga5262b9fab4a1b3d61c78b0f52d886629">  490</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_STOP_POS                 2 </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gadb0bb1a23f2f57615e06c3a2c1a9eed0">  491</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_STOP                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_STOP_POS)) </span></div><div class="line"><a name="l00493"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga2d43ee3c8189f595859b061e5205799c">  493</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS           7 </span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga05d40d5756b4f22f81da2420fec80d71">  494</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga61f14e29c9e2280c419aaf2a8b593bb3">  496</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS          8 </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gafcf0bfc40249df241290cbe623ad3f81">  497</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE              ((uint32_t)(0x7UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#ga2a0f153ddac5374cc1a2e2d66dd7903d">  499</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS         11 </span></div><div class="line"><a name="l00500"></a><span class="lineno"><a class="line" href="group__I2C__MASTER__CTRL.html#gab561d51abd933db62deea048c7a60628">  500</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP             ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) </span></div><div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group__I2C__CLK__LO.html#ga4adcf06b8c73fb66ab2d38331c5435fc">  510</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_LO_CLK_LO_POS                    0 </span></div><div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="group__I2C__CLK__LO.html#gaf2cede0f20feaa35fdefb97388c6956b">  511</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_LO_CLK_LO                        ((uint32_t)(0x1FFUL &lt;&lt; MXC_F_I2C_CLK_LO_CLK_LO_POS)) </span></div><div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group__I2C__CLK__HI.html#ga5539bfb7b33e486a17d6b5fe54c046ac">  521</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_HI_CKH_POS                       0 </span></div><div class="line"><a name="l00522"></a><span class="lineno"><a class="line" href="group__I2C__CLK__HI.html#ga2ed3220bae741613257865608a7818c5">  522</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_CLK_HI_CKH                           ((uint32_t)(0x1FFUL &lt;&lt; MXC_F_I2C_CLK_HI_CKH_POS)) </span></div><div class="line"><a name="l00532"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga1457a762d7e2e903204218a4acb0d7a5">  532</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS                 0 </span></div><div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga0f64333fb7515965765015e9385f3424">  533</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_LO                     ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) </span></div><div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga62466d0f8a60fde594ad9254e314fd96">  535</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS                 8 </span></div><div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group__I2C__HS__CLK.html#ga53f1e57e86392dd1498b2e41f6d34326">  536</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_HS_CLK_HS_CLK_HI                     ((uint32_t)(0xFFUL &lt;&lt; MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) </span></div><div class="line"><a name="l00546"></a><span class="lineno"><a class="line" href="group__I2C__TIMEOUT.html#gacaec72653bf4c5d0c4c2d2f44e981443">  546</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TIMEOUT_TO_POS                       0 </span></div><div class="line"><a name="l00547"></a><span class="lineno"><a class="line" href="group__I2C__TIMEOUT.html#ga3c69477fcc49ee1388a9b2a78d25dbc0">  547</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_TIMEOUT_TO                           ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_I2C_TIMEOUT_TO_POS)) </span></div><div class="line"><a name="l00557"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#ga456c86b3519c4c7f464dcfee939745af">  557</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_TX_EN_POS                        0 </span></div><div class="line"><a name="l00558"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#ga9679d9ae76ce2c083fcba8f5e070e39e">  558</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_TX_EN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_DMA_TX_EN_POS)) </span></div><div class="line"><a name="l00560"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#ga9242f64456c699657f8d7fc849933f9b">  560</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_RX_EN_POS                        1 </span></div><div class="line"><a name="l00561"></a><span class="lineno"><a class="line" href="group__I2C__DMA.html#gac99eefebbd24f16f50c871016d487595">  561</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_DMA_RX_EN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_DMA_RX_EN_POS)) </span></div><div class="line"><a name="l00571"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#gac46213e0f081bc639aad8428fe92078c">  571</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS            0 </span></div><div class="line"><a name="l00572"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#ga73690311b878c0ac6ed4e6f962966273">  572</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR                ((uint32_t)(0x3FFUL &lt;&lt; MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) </span></div><div class="line"><a name="l00574"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#ga33df07a4b21768c70fc4aeabcbd036f8">  574</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS               15 </span></div><div class="line"><a name="l00575"></a><span class="lineno"><a class="line" href="group__I2C__SLAVE__ADDR.html#gabbc2a157709891a5843c594d4353bc86">  575</a></span>&#160;<span class="preprocessor"> #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) </span></div><div class="line"><a name="l00579"></a><span class="lineno">  579</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00580"></a><span class="lineno">  580</span>&#160;}</div><div class="line"><a name="l00581"></a><span class="lineno">  581</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00582"></a><span class="lineno">  582</span>&#160;</div><div class="line"><a name="l00583"></a><span class="lineno">  583</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _I2C_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__i2c__regs__t_html_a8aae0d638a74fc50445c4f1a53fad3b5"><div class="ttname"><a href="structmxc__i2c__regs__t.html#a8aae0d638a74fc50445c4f1a53fad3b5">mxc_i2c_regs_t::int_en0</a></div><div class="ttdeci">__IO uint32_t int_en0</div><div class="ttdoc">0x0C: I2C INT_EN0 Register </div><div class="ttdef"><b>Definition:</b> i2c_regs.h:92</div></div>
 <div class="ttc" id="structmxc__i2c__regs__t_html_a53c06f1a9cfb978f4d424590ff3f165f"><div class="ttname"><a href="structmxc__i2c__regs__t.html#a53c06f1a9cfb978f4d424590ff3f165f">mxc_i2c_regs_t::master_ctrl</a></div><div class="ttdeci">__IO uint32_t master_ctrl</div><div class="ttdoc">0x30: I2C MASTER_CTRL Register </div><div class="ttdef"><b>Definition:</b> i2c_regs.h:101</div></div>
 <div class="ttc" id="structmxc__i2c__regs__t_html_aabae162e6b74c4cec4ba5b565737e09d"><div class="ttname"><a href="structmxc__i2c__regs__t.html#aabae162e6b74c4cec4ba5b565737e09d">mxc_i2c_regs_t::hs_clk</a></div><div class="ttdeci">__IO uint32_t hs_clk</div><div class="ttdoc">0x3C: I2C HS_CLK Register </div><div class="ttdef"><b>Definition:</b> i2c_regs.h:104</div></div>
 <div class="ttc" id="structmxc__i2c__regs__t_html_abfadfe9d39e2c853972587ee91fd522e"><div class="ttname"><a href="structmxc__i2c__regs__t.html#abfadfe9d39e2c853972587ee91fd522e">mxc_i2c_regs_t::dma</a></div><div class="ttdeci">__IO uint32_t dma</div><div class="ttdoc">0x48: I2C DMA Register </div><div class="ttdef"><b>Definition:</b> i2c_regs.h:107</div></div>
diff --git a/lib/sdk/Documentation/html/lp_8h_source.html b/lib/sdk/Documentation/html/lp_8h_source.html
index 6eae9f6fdaabd89eef537e3766f6d456220ef333..699bee0f13b35cf62bf9f3e3e8ed163a586feaec 100644
--- a/lib/sdk/Documentation/html/lp_8h_source.html
+++ b/lib/sdk/Documentation/html/lp_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('lp_8h_source.html','');});
 <div class="title">lp.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> * $Date: 2019-10-24 16:10:14 -0500 (Thu, 24 Oct 2019) $</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Revision: 48075 $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _LP_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _LP_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;gpio.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;pwrseq_regs.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;    RETAIN_NONE= <a class="code" href="group__PWRSEQ__LPCN.html#ga811ef7a873711a33eddeba4d8128d97b">MXC_S_PWRSEQ_LPCN_RAMRET_DIS</a>,</div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;    RETAIN_32k = <a class="code" href="group__PWRSEQ__LPCN.html#ga66ecb773cefefc1c878762e1983f18d4">MXC_S_PWRSEQ_LPCN_RAMRET_EN1</a>,</div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;    RETAIN_64k = <a class="code" href="group__PWRSEQ__LPCN.html#gaadc00f2c77465b203150b142ffbaff2b">MXC_S_PWRSEQ_LPCN_RAMRET_EN2</a>,</div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;    RETAIN_ALL = <a class="code" href="group__PWRSEQ__LPCN.html#ga3e61e0ce45ce806cb40284401b0c4e5c">MXC_S_PWRSEQ_LPCN_RAMRET_EN3</a> </div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;} ram_retained_t;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;</div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac614c906ed940ef7fb22567b1c5cc72d">LP_ClearWakeStatus</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;</div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab6778dd59ee5f749856a4ff679abb951">LP_EnableGPIOWakeup</a>(<a class="code" href="structgpio__cfg__t.html">gpio_cfg_t</a> *wu_pins);</div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;</div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga7c28d4b125d15e9ce116d3414c0e2b8e">LP_DisableGPIOWakeup</a>(<a class="code" href="structgpio__cfg__t.html">gpio_cfg_t</a> *wu_pins);</div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;</div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga2d84a22213c7b4b30e78688acf15eb76">LP_EnableRTCAlarmWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gae4046675176c716663bbe09b5091e0c9">LP_DisableRTCAlarmWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaf1475b51c8fbedfe32f46fe9df7a7ae2">LP_SysRam0LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;</div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac192f1fea2eb0d94f3a00eceafaa357f">LP_SysRam1LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;</div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga1822d5f1bf50cae78dcb3e4450343091">LP_SysRam2LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga38eee2d11cad7abef9a972b8ae0bc887">LP_SysRam3LightSleep</a>(<span class="keywordtype">void</span>);</div><div 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class="keywordtype">void</span>);</div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;</div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab45a807e83a151b169eac109e1afbe88">LP_SysRam0Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;</div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad90fb130eb75862d089cd5ae54c931e0">LP_SysRam1Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;</div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab7a732cd0441022435a1733548d0f5d0">LP_SysRam1Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;</div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gace758928e61a8328ed5fbd6640f0bcc9">LP_SysRam2Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;</div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gae24277199ddf7e36716cd31e2145fbbe">LP_SysRam2Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;</div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;<span 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class="lineno">  177</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga4ba254c5cece477a1a14b7129f1e85a8">LP_SysRam4Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;</div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga015bf4c8e81dc78fa436369190f3c841">LP_SysRam5Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;</div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaefdb01bafca712bc148ba8e1f8539488">LP_SysRam5Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;</div><div 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303</span>&#160;</div><div class="line"><a name="l00307"></a><span class="lineno">  307</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga95bfad7c2789941ab9f5f95f9d362c1d">LP_VDD4PowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00308"></a><span class="lineno">  308</span>&#160;</div><div class="line"><a name="l00312"></a><span class="lineno">  312</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga4b975f382d6218ee6b7aa9747eef951f">LP_VDD5PowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00313"></a><span class="lineno">  313</span>&#160;</div><div class="line"><a name="l00317"></a><span class="lineno">  317</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab577b58fa48339a71778fb2f4bf66439">LP_VDD5PowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;</div><div class="line"><a name="l00322"></a><span class="lineno">  322</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga31750804d931bf33b15837ef91ee628d">LP_SIMOVregBPowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00323"></a><span class="lineno">  323</span>&#160;</div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga697eb5c7d8f8c15a3e44a2cd462e4748">LP_SIMOVregBPowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00328"></a><span class="lineno">  328</span>&#160;</div><div class="line"><a name="l00332"></a><span class="lineno">  332</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaa4a0aa9c65ce4f80fd60bc601930b3bc">LP_SIMOVregDPowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00333"></a><span class="lineno">  333</span>&#160;</div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga49229c552d3967259372928cbca4a7d1">LP_SIMOVregDPowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;</div><div class="line"><a name="l00342"></a><span class="lineno">  342</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad220c8ddad383453141ef574981cbc3c">LP_FastWakeupEnable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00343"></a><span class="lineno">  343</span>&#160;</div><div class="line"><a name="l00347"></a><span class="lineno">  347</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga5b35b70a6fd4776c4760c4ec0af04fca">LP_FastWakeupDisable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00348"></a><span class="lineno">  348</span>&#160;</div><div class="line"><a name="l00352"></a><span class="lineno">  352</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gace76657f5a044a749e99555a14f92de1">LP_PowerFailMonitorEnable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00353"></a><span class="lineno">  353</span>&#160;</div><div class="line"><a name="l00357"></a><span class="lineno">  357</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga6ba4bad6a5dbe3136a29dee67adb5807">LP_PowerFailMonitorDisable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00358"></a><span class="lineno">  358</span>&#160;</div><div class="line"><a name="l00363"></a><span class="lineno">  363</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga26ea3f0e59f11a2cc0616cca1b35c84a">LP_SetRAMRetention</a>(ram_retained_t ramRetained);</div><div class="line"><a name="l00364"></a><span class="lineno">  364</span>&#160;</div><div class="line"><a name="l00368"></a><span class="lineno">  368</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gabf720bd39513c2d50c7546b176b0841a">LP_EnterSleepMode</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00369"></a><span class="lineno">  369</span>&#160;</div><div class="line"><a name="l00373"></a><span class="lineno">  373</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac3086f62dd9602db500a3166c43edc57">LP_EnterDeepSleepMode</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00374"></a><span class="lineno">  374</span>&#160;</div><div class="line"><a name="l00378"></a><span class="lineno">  378</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad6c1fc2e74ed537e1bbdc7515acb1d79">LP_EnterBackgroundMode</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00379"></a><span class="lineno">  379</span>&#160;</div><div class="line"><a name="l00388"></a><span class="lineno">  388</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga906e1ee68934b58e0d34293dc1d87a44">LP_EnterBackupMode</a>(<span class="keywordtype">void</span>* func(<span class="keywordtype">void</span>));</div><div class="line"><a name="l00389"></a><span class="lineno">  389</span>&#160;</div><div class="line"><a name="l00394"></a><span class="lineno">  394</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad6d8e503a9a33ba1a365ab6b7fb678f5">LP_EnterShutDownMode</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00395"></a><span class="lineno">  395</span>&#160;</div><div class="line"><a name="l00396"></a><span class="lineno">  396</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00397"></a><span class="lineno">  397</span>&#160;}</div><div class="line"><a name="l00398"></a><span class="lineno">  398</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00399"></a><span class="lineno">  399</span>&#160;</div><div class="line"><a name="l00400"></a><span class="lineno">  400</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _LP_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__pwrseq_html_ga49229c552d3967259372928cbca4a7d1"><div class="ttname"><a href="group__pwrseq.html#ga49229c552d3967259372928cbca4a7d1">LP_SIMOVregDPowerUp</a></div><div class="ttdeci">void LP_SIMOVregDPowerUp(void)</div><div class="ttdoc">Power Up SIMOV regD. </div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> * $Date: 2019-11-07 13:07:17 -0600 (Thu, 07 Nov 2019) $</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Revision: 48499 $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _LP_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _LP_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;gpio.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;pwrseq_regs.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;    RETAIN_NONE= <a class="code" href="group__PWRSEQ__LPCN.html#ga811ef7a873711a33eddeba4d8128d97b">MXC_S_PWRSEQ_LPCN_RAMRET_DIS</a>,</div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;    RETAIN_32k = <a class="code" href="group__PWRSEQ__LPCN.html#ga66ecb773cefefc1c878762e1983f18d4">MXC_S_PWRSEQ_LPCN_RAMRET_EN1</a>,</div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;    RETAIN_64k = <a class="code" href="group__PWRSEQ__LPCN.html#gaadc00f2c77465b203150b142ffbaff2b">MXC_S_PWRSEQ_LPCN_RAMRET_EN2</a>,</div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;    RETAIN_ALL = <a class="code" href="group__PWRSEQ__LPCN.html#ga3e61e0ce45ce806cb40284401b0c4e5c">MXC_S_PWRSEQ_LPCN_RAMRET_EN3</a> </div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;} ram_retained_t;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;</div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac614c906ed940ef7fb22567b1c5cc72d">LP_ClearWakeStatus</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;</div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab6778dd59ee5f749856a4ff679abb951">LP_EnableGPIOWakeup</a>(<a class="code" href="structgpio__cfg__t.html">gpio_cfg_t</a> *wu_pins);</div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;</div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga7c28d4b125d15e9ce116d3414c0e2b8e">LP_DisableGPIOWakeup</a>(<a class="code" href="structgpio__cfg__t.html">gpio_cfg_t</a> *wu_pins);</div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;</div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga2d84a22213c7b4b30e78688acf15eb76">LP_EnableRTCAlarmWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gae4046675176c716663bbe09b5091e0c9">LP_DisableRTCAlarmWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaf1475b51c8fbedfe32f46fe9df7a7ae2">LP_SysRam0LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;</div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac192f1fea2eb0d94f3a00eceafaa357f">LP_SysRam1LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;</div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga1822d5f1bf50cae78dcb3e4450343091">LP_SysRam2LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga38eee2d11cad7abef9a972b8ae0bc887">LP_SysRam3LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;</div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad90013fff9b129d88b017ff5553c0211">LP_SysRam4LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;</div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga2b9580fe72f33cb809682f5e87ea86d9">LP_SysRam5LightSleep</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;</div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga74277c69740cb3da434144596c8bb2cd">LP_SysRam0Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;</div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab45a807e83a151b169eac109e1afbe88">LP_SysRam0Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;</div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad90fb130eb75862d089cd5ae54c931e0">LP_SysRam1Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;</div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab7a732cd0441022435a1733548d0f5d0">LP_SysRam1Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;</div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gace758928e61a8328ed5fbd6640f0bcc9">LP_SysRam2Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;</div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gae24277199ddf7e36716cd31e2145fbbe">LP_SysRam2Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;</div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;<span 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class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga04eb533eedbcce50ee1b60e7569219cc">LP_ICacheShutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;</div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga382a78b1b09d5de75f4548315790a9ae">LP_ICacheWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;</div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga184f772b842efcbbc2ff531179899861">LP_ICacheXIPShutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;</div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga94210a5a0fb381a420e3b72081405075">LP_ICacheXIPWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00208"></a><span class="lineno">  208</span>&#160;</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac9839675a2c9a3b2c333ade0b52b4b22">LP_CryptoShutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;</div><div class="line"><a name="l00217"></a><span class="lineno">  217</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gafbeacdc9e0438f14f90b979f85834678">LP_CryptoWakeup</a>(<span class="keywordtype">void</span>);</div><div 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class="keywordtype">void</span>);</div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gac8a6544b82181e16ccd3b3b167c80bb4">LP_ROMWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;</div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga462afc91b57e00112bba92300689ef3f">LP_ROM1Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;</div><div class="line"><a name="l00247"></a><span class="lineno">  247</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga8e07d366f9e965eb63adc0676974e98d">LP_ROM1Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00248"></a><span class="lineno">  248</span>&#160;</div><div class="line"><a name="l00252"></a><span class="lineno">  252</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga4f3c8f0bb6a59e6662bd0d6f8b26e9f4">LP_ICache1Shutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00253"></a><span class="lineno">  253</span>&#160;</div><div class="line"><a name="l00257"></a><span class="lineno">  257</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga368a1d24a704e9de8e9a008d5b9afdfe">LP_ICache1Wakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00258"></a><span class="lineno">  258</span>&#160;</div><div class="line"><a name="l00262"></a><span class="lineno">  262</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga653528dc77396a0ff6795b00e47182be">LP_SysCacheShutdown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00263"></a><span class="lineno">  263</span>&#160;</div><div class="line"><a name="l00267"></a><span class="lineno">  267</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gae35a030d407fec4b83acaf9e31d48c16">LP_SysCacheWakeup</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00268"></a><span class="lineno">  268</span>&#160;</div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gae93aa782554fd51b6a64a1f75afe29e4">LP_USBSWLPDisable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;</div><div class="line"><a name="l00277"></a><span class="lineno">  277</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaeb2ad981aa1ca6ee31ef064652e1b7de">LP_USBSWLPEnable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00278"></a><span class="lineno">  278</span>&#160;</div><div class="line"><a name="l00282"></a><span class="lineno">  282</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaa7f05d4830c47398fc86ee061bdef21c">LP_VDD2PowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00283"></a><span class="lineno">  283</span>&#160;</div><div class="line"><a name="l00287"></a><span class="lineno">  287</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga7002456f829aa4aa12f3a6bedead7a72">LP_VDD2PowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00288"></a><span class="lineno">  288</span>&#160;</div><div class="line"><a name="l00292"></a><span class="lineno">  292</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga4dde39ed0a2b9eacb6b529c1b5f8e2c8">LP_VDD3PowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00293"></a><span class="lineno">  293</span>&#160;</div><div class="line"><a name="l00297"></a><span class="lineno">  297</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad81613d652563b7b9d392d90fdddf1ce">LP_VDD3PowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00298"></a><span class="lineno">  298</span>&#160;</div><div class="line"><a name="l00302"></a><span class="lineno">  302</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga3c53d01b0a94907cb9de106e7185e0db">LP_VDD4PowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00303"></a><span class="lineno">  303</span>&#160;</div><div class="line"><a name="l00307"></a><span class="lineno">  307</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga95bfad7c2789941ab9f5f95f9d362c1d">LP_VDD4PowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00308"></a><span class="lineno">  308</span>&#160;</div><div class="line"><a name="l00312"></a><span class="lineno">  312</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga4b975f382d6218ee6b7aa9747eef951f">LP_VDD5PowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00313"></a><span class="lineno">  313</span>&#160;</div><div class="line"><a name="l00317"></a><span class="lineno">  317</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gab577b58fa48339a71778fb2f4bf66439">LP_VDD5PowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;</div><div class="line"><a name="l00322"></a><span class="lineno">  322</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga31750804d931bf33b15837ef91ee628d">LP_SIMOVregBPowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00323"></a><span class="lineno">  323</span>&#160;</div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga697eb5c7d8f8c15a3e44a2cd462e4748">LP_SIMOVregBPowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00328"></a><span class="lineno">  328</span>&#160;</div><div class="line"><a name="l00332"></a><span class="lineno">  332</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gaa4a0aa9c65ce4f80fd60bc601930b3bc">LP_SIMOVregDPowerDown</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00333"></a><span class="lineno">  333</span>&#160;</div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#ga49229c552d3967259372928cbca4a7d1">LP_SIMOVregDPowerUp</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;</div><div class="line"><a name="l00342"></a><span class="lineno">  342</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad220c8ddad383453141ef574981cbc3c">LP_FastWakeupEnable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00343"></a><span class="lineno">  343</span>&#160;</div><div class="line"><a name="l00347"></a><span class="lineno">  347</span>&#160;<span class="keywordtype">void</span> <a class="code" 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379</span>&#160;</div><div class="line"><a name="l00384"></a><span class="lineno">  384</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__pwrseq.html#gad6d8e503a9a33ba1a365ab6b7fb678f5">LP_EnterShutDownMode</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00385"></a><span class="lineno">  385</span>&#160;</div><div class="line"><a name="l00386"></a><span class="lineno">  386</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00387"></a><span class="lineno">  387</span>&#160;}</div><div class="line"><a name="l00388"></a><span class="lineno">  388</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00389"></a><span class="lineno">  389</span>&#160;</div><div class="line"><a name="l00390"></a><span class="lineno">  390</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _LP_H_ */</span><span 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 <div class="ttc" id="structgpio__cfg__t_html"><div class="ttname"><a href="structgpio__cfg__t.html">gpio_cfg_t</a></div><div class="ttdoc">Structure type for configuring a GPIO port. </div><div class="ttdef"><b>Definition:</b> gpio.h:138</div></div>
 <div class="ttc" id="group__pwrseq_html_ga906e1ee68934b58e0d34293dc1d87a44"><div class="ttname"><a href="group__pwrseq.html#ga906e1ee68934b58e0d34293dc1d87a44">LP_EnterBackupMode</a></div><div class="ttdeci">void LP_EnterBackupMode(void *func(void))</div><div class="ttdoc">Places the device into BACKUP mode. </div></div>
 <div class="ttc" id="group__pwrseq_html_gae93aa782554fd51b6a64a1f75afe29e4"><div class="ttname"><a href="group__pwrseq.html#gae93aa782554fd51b6a64a1f75afe29e4">LP_USBSWLPDisable</a></div><div class="ttdeci">void LP_USBSWLPDisable(void)</div><div class="ttdoc">Disable USB Software Low Power. </div></div>
@@ -82,7 +82,7 @@ $(document).ready(function(){initNavTree('lp_8h_source.html','');});
 <div class="ttc" id="group__pwrseq_html_ga94210a5a0fb381a420e3b72081405075"><div class="ttname"><a href="group__pwrseq.html#ga94210a5a0fb381a420e3b72081405075">LP_ICacheXIPWakeup</a></div><div class="ttdeci">void LP_ICacheXIPWakeup(void)</div><div class="ttdoc">Wakeup Internal Cache XIP. </div></div>
 <div class="ttc" id="group__pwrseq_html_gac9839675a2c9a3b2c333ade0b52b4b22"><div class="ttname"><a href="group__pwrseq.html#gac9839675a2c9a3b2c333ade0b52b4b22">LP_CryptoShutdown</a></div><div class="ttdeci">void LP_CryptoShutdown(void)</div><div class="ttdoc">Shutdown Crypto. </div></div>
 <div class="ttc" id="group__pwrseq_html_gac614c906ed940ef7fb22567b1c5cc72d"><div class="ttname"><a href="group__pwrseq.html#gac614c906ed940ef7fb22567b1c5cc72d">LP_ClearWakeStatus</a></div><div class="ttdeci">void LP_ClearWakeStatus(void)</div><div class="ttdoc">Clears the wakup status bits. </div></div>
-<div class="ttc" id="group__PWRSEQ__LPCN_html_ga3e61e0ce45ce806cb40284401b0c4e5c"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#ga3e61e0ce45ce806cb40284401b0c4e5c">MXC_S_PWRSEQ_LPCN_RAMRET_EN3</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3</div><div class="ttdoc">LPCN_RAMRET_EN3 Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:151</div></div>
+<div class="ttc" id="group__PWRSEQ__LPCN_html_ga3e61e0ce45ce806cb40284401b0c4e5c"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#ga3e61e0ce45ce806cb40284401b0c4e5c">MXC_S_PWRSEQ_LPCN_RAMRET_EN3</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3</div><div class="ttdoc">LPCN_RAMRET_EN3 Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:139</div></div>
 <div class="ttc" id="group__pwrseq_html_gad6d8e503a9a33ba1a365ab6b7fb678f5"><div class="ttname"><a href="group__pwrseq.html#gad6d8e503a9a33ba1a365ab6b7fb678f5">LP_EnterShutDownMode</a></div><div class="ttdeci">void LP_EnterShutDownMode(void)</div><div class="ttdoc">Places the device into Shutdown mode. </div></div>
 <div class="ttc" id="group__pwrseq_html_gaefdb01bafca712bc148ba8e1f8539488"><div class="ttname"><a href="group__pwrseq.html#gaefdb01bafca712bc148ba8e1f8539488">LP_SysRam5Wakeup</a></div><div class="ttdeci">void LP_SysRam5Wakeup(void)</div><div class="ttdoc">Wakeup System Ram 5. </div></div>
 <div class="ttc" id="group__pwrseq_html_gad220c8ddad383453141ef574981cbc3c"><div class="ttname"><a href="group__pwrseq.html#gad220c8ddad383453141ef574981cbc3c">LP_FastWakeupEnable</a></div><div class="ttdeci">void LP_FastWakeupEnable(void)</div><div class="ttdoc">Enable Fast Wakeup. </div></div>
@@ -103,7 +103,6 @@ $(document).ready(function(){initNavTree('lp_8h_source.html','');});
 <div class="ttc" id="group__pwrseq_html_ga5b35b70a6fd4776c4760c4ec0af04fca"><div class="ttname"><a href="group__pwrseq.html#ga5b35b70a6fd4776c4760c4ec0af04fca">LP_FastWakeupDisable</a></div><div class="ttdeci">void LP_FastWakeupDisable(void)</div><div class="ttdoc">Disable Fast Wakeup. </div></div>
 <div class="ttc" id="group__pwrseq_html_gac8a6544b82181e16ccd3b3b167c80bb4"><div class="ttname"><a href="group__pwrseq.html#gac8a6544b82181e16ccd3b3b167c80bb4">LP_ROMWakeup</a></div><div class="ttdeci">void LP_ROMWakeup(void)</div><div class="ttdoc">Wakeup ROM. </div></div>
 <div class="ttc" id="group__pwrseq_html_ga26ea3f0e59f11a2cc0616cca1b35c84a"><div class="ttname"><a href="group__pwrseq.html#ga26ea3f0e59f11a2cc0616cca1b35c84a">LP_SetRAMRetention</a></div><div class="ttdeci">void LP_SetRAMRetention(ram_retained_t ramRetained)</div><div class="ttdoc">Enables the selected amount of RAM retention in backup mode Using any RAM retention removes the abili...</div></div>
-<div class="ttc" id="group__pwrseq_html_ga6ba4bad6a5dbe3136a29dee67adb5807"><div class="ttname"><a href="group__pwrseq.html#ga6ba4bad6a5dbe3136a29dee67adb5807">LP_PowerFailMonitorDisable</a></div><div class="ttdeci">void LP_PowerFailMonitorDisable(void)</div><div class="ttdoc">Disable Power Fail Monitor. </div></div>
 <div class="ttc" id="group__pwrseq_html_ga2b9580fe72f33cb809682f5e87ea86d9"><div class="ttname"><a href="group__pwrseq.html#ga2b9580fe72f33cb809682f5e87ea86d9">LP_SysRam5LightSleep</a></div><div class="ttdeci">void LP_SysRam5LightSleep(void)</div><div class="ttdoc">Puts System Ram 5 in light sleep. </div></div>
 <div class="ttc" id="group__pwrseq_html_gac192f1fea2eb0d94f3a00eceafaa357f"><div class="ttname"><a href="group__pwrseq.html#gac192f1fea2eb0d94f3a00eceafaa357f">LP_SysRam1LightSleep</a></div><div class="ttdeci">void LP_SysRam1LightSleep(void)</div><div class="ttdoc">Puts System Ram 1 in light sleep. </div></div>
 <div class="ttc" id="group__pwrseq_html_ga2d84a22213c7b4b30e78688acf15eb76"><div class="ttname"><a href="group__pwrseq.html#ga2d84a22213c7b4b30e78688acf15eb76">LP_EnableRTCAlarmWakeup</a></div><div class="ttdeci">void LP_EnableRTCAlarmWakeup(void)</div><div class="ttdoc">Enables the RTC alarm to wake up the device from any low power mode. </div></div>
@@ -122,7 +121,7 @@ $(document).ready(function(){initNavTree('lp_8h_source.html','');});
 <div class="ttc" id="group__pwrseq_html_gab6778dd59ee5f749856a4ff679abb951"><div class="ttname"><a href="group__pwrseq.html#gab6778dd59ee5f749856a4ff679abb951">LP_EnableGPIOWakeup</a></div><div class="ttdeci">void LP_EnableGPIOWakeup(gpio_cfg_t *wu_pins)</div><div class="ttdoc">Enables the selected GPIO port and its selected pins to wake up the device from any low power mode...</div></div>
 <div class="ttc" id="group__pwrseq_html_ga04eb533eedbcce50ee1b60e7569219cc"><div class="ttname"><a href="group__pwrseq.html#ga04eb533eedbcce50ee1b60e7569219cc">LP_ICacheShutdown</a></div><div class="ttdeci">void LP_ICacheShutdown(void)</div><div class="ttdoc">Shutdown Internal Cache. </div></div>
 <div class="ttc" id="group__pwrseq_html_gab577b58fa48339a71778fb2f4bf66439"><div class="ttname"><a href="group__pwrseq.html#gab577b58fa48339a71778fb2f4bf66439">LP_VDD5PowerUp</a></div><div class="ttdeci">void LP_VDD5PowerUp(void)</div><div class="ttdoc">Power Up VDD5. </div></div>
-<div class="ttc" id="group__PWRSEQ__LPCN_html_ga811ef7a873711a33eddeba4d8128d97b"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#ga811ef7a873711a33eddeba4d8128d97b">MXC_S_PWRSEQ_LPCN_RAMRET_DIS</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_DIS</div><div class="ttdoc">LPCN_RAMRET_DIS Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:145</div></div>
+<div class="ttc" id="group__PWRSEQ__LPCN_html_ga811ef7a873711a33eddeba4d8128d97b"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#ga811ef7a873711a33eddeba4d8128d97b">MXC_S_PWRSEQ_LPCN_RAMRET_DIS</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_DIS</div><div class="ttdoc">LPCN_RAMRET_DIS Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:133</div></div>
 <div class="ttc" id="group__pwrseq_html_gaa4a0aa9c65ce4f80fd60bc601930b3bc"><div class="ttname"><a href="group__pwrseq.html#gaa4a0aa9c65ce4f80fd60bc601930b3bc">LP_SIMOVregDPowerDown</a></div><div class="ttdeci">void LP_SIMOVregDPowerDown(void)</div><div class="ttdoc">Power Down SIMOV regD. </div></div>
 <div class="ttc" id="group__pwrseq_html_ga462afc91b57e00112bba92300689ef3f"><div class="ttname"><a href="group__pwrseq.html#ga462afc91b57e00112bba92300689ef3f">LP_ROM1Shutdown</a></div><div class="ttdeci">void LP_ROM1Shutdown(void)</div><div class="ttdoc">Shutdown ROM 1. </div></div>
 <div class="ttc" id="group__pwrseq_html_ga38eee2d11cad7abef9a972b8ae0bc887"><div class="ttname"><a href="group__pwrseq.html#ga38eee2d11cad7abef9a972b8ae0bc887">LP_SysRam3LightSleep</a></div><div class="ttdeci">void LP_SysRam3LightSleep(void)</div><div class="ttdoc">Puts System Ram 3 in light sleep. </div></div>
@@ -136,9 +135,8 @@ $(document).ready(function(){initNavTree('lp_8h_source.html','');});
 <div class="ttc" id="group__pwrseq_html_ga4f3c8f0bb6a59e6662bd0d6f8b26e9f4"><div class="ttname"><a href="group__pwrseq.html#ga4f3c8f0bb6a59e6662bd0d6f8b26e9f4">LP_ICache1Shutdown</a></div><div class="ttdeci">void LP_ICache1Shutdown(void)</div><div class="ttdoc">Shutdown Internal Cache 1. </div></div>
 <div class="ttc" id="group__pwrseq_html_gae24277199ddf7e36716cd31e2145fbbe"><div class="ttname"><a href="group__pwrseq.html#gae24277199ddf7e36716cd31e2145fbbe">LP_SysRam2Wakeup</a></div><div class="ttdeci">void LP_SysRam2Wakeup(void)</div><div class="ttdoc">Wakeup System Ram 2. </div></div>
 <div class="ttc" id="group__pwrseq_html_ga74277c69740cb3da434144596c8bb2cd"><div class="ttname"><a href="group__pwrseq.html#ga74277c69740cb3da434144596c8bb2cd">LP_SysRam0Shutdown</a></div><div class="ttdeci">void LP_SysRam0Shutdown(void)</div><div class="ttdoc">Shutdown System Ram 0. </div></div>
-<div class="ttc" id="group__pwrseq_html_gace76657f5a044a749e99555a14f92de1"><div class="ttname"><a href="group__pwrseq.html#gace76657f5a044a749e99555a14f92de1">LP_PowerFailMonitorEnable</a></div><div class="ttdeci">void LP_PowerFailMonitorEnable(void)</div><div class="ttdoc">Enable Power Fail Monitor. </div></div>
-<div class="ttc" id="group__PWRSEQ__LPCN_html_ga66ecb773cefefc1c878762e1983f18d4"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#ga66ecb773cefefc1c878762e1983f18d4">MXC_S_PWRSEQ_LPCN_RAMRET_EN1</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_EN1</div><div class="ttdoc">LPCN_RAMRET_EN1 Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:147</div></div>
-<div class="ttc" id="group__PWRSEQ__LPCN_html_gaadc00f2c77465b203150b142ffbaff2b"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#gaadc00f2c77465b203150b142ffbaff2b">MXC_S_PWRSEQ_LPCN_RAMRET_EN2</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_EN2</div><div class="ttdoc">LPCN_RAMRET_EN2 Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:149</div></div>
+<div class="ttc" id="group__PWRSEQ__LPCN_html_ga66ecb773cefefc1c878762e1983f18d4"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#ga66ecb773cefefc1c878762e1983f18d4">MXC_S_PWRSEQ_LPCN_RAMRET_EN1</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_EN1</div><div class="ttdoc">LPCN_RAMRET_EN1 Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:135</div></div>
+<div class="ttc" id="group__PWRSEQ__LPCN_html_gaadc00f2c77465b203150b142ffbaff2b"><div class="ttname"><a href="group__PWRSEQ__LPCN.html#gaadc00f2c77465b203150b142ffbaff2b">MXC_S_PWRSEQ_LPCN_RAMRET_EN2</a></div><div class="ttdeci">#define MXC_S_PWRSEQ_LPCN_RAMRET_EN2</div><div class="ttdoc">LPCN_RAMRET_EN2 Setting. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:137</div></div>
 </div><!-- fragment --></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
diff --git a/lib/sdk/Documentation/html/max32665_8h_source.html b/lib/sdk/Documentation/html/max32665_8h_source.html
index 34b1e3a09c17d304e15cb89fa9dd264894614ae8..5e4afff5d0d64053934492688850d09bb333f0dc 100644
--- a/lib/sdk/Documentation/html/max32665_8h_source.html
+++ b/lib/sdk/Documentation/html/max32665_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('max32665_8h_source.html','');});
 <div class="title">max32665.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * $Date: 2019-04-26 16:05:18 -0500 (Fri, 26 Apr 2019) $</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * $Revision: 42983 $</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> ******************************************************************************/</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;</div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="preprocessor">#ifndef _MAX32665_REGS_H_</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="preprocessor">#define _MAX32665_REGS_H_</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef TARGET_NUM</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define TARGET_NUM  32665</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="preprocessor">#endif </span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;</div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define MXC_NUMCORES 2</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#ifndef  FALSE</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="preprocessor">#define  FALSE      (0)</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#ifndef  TRUE</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="preprocessor">#define  TRUE       (1)</span></div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;</div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#if !defined ( __GNUC__ )</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="preprocessor">    #define CMSIS_VECTAB_VIRTUAL</span></div><div class="line"><a name="l00058"></a><span class="lineno">   58</span>&#160;<span class="preprocessor">    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE &quot;nvic_table.h&quot;</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="comment">/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#if defined ( __GNUC__ )</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;</div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#define __weak __attribute__((weak))</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#elif defined ( __CC_ARM)</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160; </div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define inline __inline</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#pragma anon_unions</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;</div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;</div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;    NonMaskableInt_IRQn    = -14,</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;    HardFault_IRQn         = -13,</div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;    MemoryManagement_IRQn  = -12,</div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;    BusFault_IRQn          = -11,</div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;    UsageFault_IRQn        = -10,</div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;    SVCall_IRQn            = -5,</div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;    DebugMonitor_IRQn      = -4,</div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;    PendSV_IRQn            = -2,</div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;    SysTick_IRQn           = -1,</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;</div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;    <span class="comment">/* Device-specific interrupt sources (external to ARM core)                 */</span></div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;    <span class="comment">/*                      table entry number                                  */</span></div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;    <span class="comment">/*                      ||||                                                */</span></div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;    <span class="comment">/*                      ||||  table offset address                          */</span></div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;    <span class="comment">/*                      vvvv  vvvvvv                                        */</span></div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;</div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;    PF_IRQn = 0,            <span class="comment">/* 0x10  0x0040  16: Power Fail */</span></div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;    WDT0_IRQn,              <span class="comment">/* 0x11  0x0044  17: Watchdog 0 */</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    USB_IRQn,               <span class="comment">/* 0x12  0x0048  18: USB */</span></div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    RTC_IRQn,               <span class="comment">/* 0x13  0x004C  19: RTC */</span></div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    TRNG_IRQn,              <span class="comment">/* 0x14  0x0050  20: True Random Number Generator */</span></div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;    TMR0_IRQn,              <span class="comment">/* 0x15  0x0054  21: Timer 0 */</span></div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;    TMR1_IRQn,              <span class="comment">/* 0x16  0x0058  22: Timer 1 */</span></div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    TMR2_IRQn,              <span class="comment">/* 0x17  0x005C  23: Timer 2 */</span></div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;    TMR3_IRQn,              <span class="comment">/* 0x18  0x0060  24: Timer 3*/</span></div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;    TMR4_IRQn,              <span class="comment">/* 0x19  0x0064  25: Timer 4*/</span></div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;    TMR5_IRQn,              <span class="comment">/* 0x1A  0x0068  26: Timer 5 */</span></div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    RSV11_IRQn,             <span class="comment">/* 0x1B  0x006C  27: Reserved */</span></div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;    RSV12_IRQn,             <span class="comment">/* 0x1C  0x0070  28: Reserved */</span></div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    I2C0_IRQn,              <span class="comment">/* 0x1D  0x0074  29: I2C0 */</span></div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;    UART0_IRQn,             <span class="comment">/* 0x1E  0x0078  30: UART 0 */</span></div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;    UART1_IRQn,             <span class="comment">/* 0x1F  0x007C  31: UART 1 */</span></div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;    SPI17Y1_IRQn,           <span class="comment">/* 0x20  0x0080  32: SPI17Y1 */</span></div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;    SPI17Y2_IRQn,           <span class="comment">/* 0x21  0x0084  33: SPI17Y2 */</span></div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    RSV18_IRQn,             <span class="comment">/* 0x22  0x0088  34: Reserved */</span></div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;    RSV19_IRQn,             <span class="comment">/* 0x23  0x008C  35: Reserved */</span></div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    ADC_IRQn,               <span class="comment">/* 0x24  0x0090  36: ADC */</span></div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    RSV21_IRQn,             <span class="comment">/* 0x25  0x0094  37: Reserved */</span></div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    RSV22_IRQn,             <span class="comment">/* 0x26  0x0098  38: Reserved */</span></div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;    FLC0_IRQn,               <span class="comment">/* 0x27  0x009C  39: Flash Controller 0 */</span></div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    GPIO0_IRQn,             <span class="comment">/* 0x28  0x00A0  40: GPIO0 */</span></div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;    GPIO1_IRQn,             <span class="comment">/* 0x29  0x00A4  41: GPIO1 */</span></div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    RSV26_IRQn,             <span class="comment">/* 0x2A  0x00A8  42: Reserved */</span></div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;    TPU_IRQn,               <span class="comment">/* 0x2B  0x00AC  43: Crypto */</span></div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    DMA0_IRQn,              <span class="comment">/* 0x2C  0x00B0  44: DMA0 */</span></div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;    DMA1_IRQn,              <span class="comment">/* 0x2D  0x00B4  45: DMA1 */</span></div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    DMA2_IRQn,              <span class="comment">/* 0x2E  0x00B8  46: DMA2 */</span></div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    DMA3_IRQn,              <span class="comment">/* 0x2F  0x00BC  47: DMA3 */</span></div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    RSV32_IRQn,             <span class="comment">/* 0x30  0x00C0  48: Reserved */</span></div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;    RSV33_IRQn,             <span class="comment">/* 0x31  0x00C4  49: Reserved */</span></div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    UART2_IRQn,             <span class="comment">/* 0x32  0x00C8  50: UART 2 */</span></div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;    RSV35_IRQn,             <span class="comment">/* 0x33  0x00CC  51: Reserved */</span></div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    I2C1_IRQn,              <span class="comment">/* 0x34  0x00D0  52: I2C1 */</span></div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    RSV36_IRQn,             <span class="comment">/* 0x35  0x00D4  53: Reserved */</span></div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    SPIXFC_IRQn,             <span class="comment">/* 0x36  0x00D8  54: SPI execute in place */</span></div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;    BTLE_TX_DONE_IRQn,      <span class="comment">/* 0x37  0x00DC  55: BTLE TX Done */</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    BTLE_RX_RCVD_IRQn,      <span class="comment">/* 0x38  0x00E0  56: BTLE RX Received */</span></div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;    BTLE_RX_ENG_DET_IRQn,   <span class="comment">/* 0x39  0x00E4  57: BTLE RX Energy Detected */</span></div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    BTLE_SFD_DET_IRQn,      <span class="comment">/* 0x3A  0x00E8  58: BTLE SFD Detected */</span></div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;    BTLE_SFD_TO_IRQn,       <span class="comment">/* 0x3B  0x00EC  59: BTLE SFD Timeout*/</span></div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;    BTLE_GP_EVENT_IRQn,     <span class="comment">/* 0x3C  0x00F0  60: BTLE Timestamp*/</span></div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;    BTLE_CFO_IRQn,          <span class="comment">/* 0x3D  0x00F4  61: BTLE CFO Done */</span></div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;    BTLE_SIG_DET_IRQn,      <span class="comment">/* 0x3E  0x00F8  62: BTLE Signal Detected */</span></div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;    BTLE_AGC_EVENT_IRQn,    <span class="comment">/* 0x3F  0x00FC  63: BTLE AGC Event */</span></div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;    BTLE_RFFE_SPIM_IRQn,    <span class="comment">/* 0x40  0x0100  64: BTLE RFFE SPIM Done */</span></div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;    BTLE_TX_AES_IRQn,       <span class="comment">/* 0x41  0x0104  65: BTLE TX AES Done */</span></div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;    BTLE_RX_AES_IRQn,       <span class="comment">/* 0x42  0x0108  66: BTLE RX AES Done */</span></div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;    BTLE_INV_APB_ADDR_IRQn, <span class="comment">/* 0x43  0x010C  67: BTLE Invalid APB Address*/</span></div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;    BTLE_IQ_DATA_VALID_IRQn,<span class="comment">/* 0x44  0x0110  68: BTLE IQ Data Valid */</span></div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;    WUT_IRQn,               <span class="comment">/* 0x45  0x0114  69: WUT Wakeup */</span></div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;    GPIOWAKE_IRQn,          <span class="comment">/* 0x46  0x0118  70: GPIO Wakeup */</span></div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;    RSV55_IRQn,             <span class="comment">/* 0x47  0x011C  71: Reserved */</span></div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;    SPI17Y0_IRQn,           <span class="comment">/* 0x48  0x0120  72: SPI17Y0  AHB*/</span></div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;    WDT1_IRQn,              <span class="comment">/* 0x49  0x0124  73: Watchdog 1 */</span></div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;    RSV58_IRQn,             <span class="comment">/* 0x4A  0x0128  74: Reserved */</span></div><div class="line"><a name="l00149"></a><span class="lineno">  149</span>&#160;    PT_IRQn,                <span class="comment">/* 0x4B  0x012C  75: Pulse train */</span></div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;    SDMA_IRQn,              <span class="comment">/* 0x4C  0x0130  76: Smart DMA 0 */</span></div><div class="line"><a name="l00151"></a><span class="lineno">  151</span>&#160;    RSV61_IRQn,             <span class="comment">/* 0x4D  0x0134  77: Reserved */</span></div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;    I2C2_IRQn,              <span class="comment">/* 0x4E  0x0138  78: I2C 2 */</span></div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;    RSV63_IRQn,             <span class="comment">/* 0x4F  0x013C  79: Reserved */</span></div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;    RSV64_IRQn,             <span class="comment">/* 0x50  0x0140  80: Reserved */</span></div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;    RSV65_IRQn,             <span class="comment">/* 0x51  0x0144  81: Reserved */</span></div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;    SDHC_IRQn,              <span class="comment">/* 0x52  0x0148  82: SDIO/SDHC */</span></div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;    OWM_IRQn,               <span class="comment">/* 0x53  0x014C  83: One Wire Master */</span></div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;    DMA4_IRQn,              <span class="comment">/* 0x54  0x0150  84: DMA4 */</span></div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;    DMA5_IRQn,              <span class="comment">/* 0x55  0x0154  85: DMA5 */</span></div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;    DMA6_IRQn,              <span class="comment">/* 0x56  0x0158  86: DMA6 */</span></div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;    DMA7_IRQn,              <span class="comment">/* 0x57  0x015C  87: DMA7 */</span></div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;    DMA8_IRQn,              <span class="comment">/* 0x58  0x0160  88: DMA8 */</span></div><div class="line"><a name="l00163"></a><span class="lineno">  163</span>&#160;    DMA9_IRQn,              <span class="comment">/* 0x59  0x0164  89: DMA9 */</span></div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;    DMA10_IRQn,             <span class="comment">/* 0x5A  0x0168  90: DMA10 */</span></div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;    DMA11_IRQn,             <span class="comment">/* 0x5B  0x016C  91: DMA11 */</span></div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;    DMA12_IRQn,             <span class="comment">/* 0x5C  0x0170  92: DMA12 */</span></div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;    DMA13_IRQn,             <span class="comment">/* 0x5D  0x0174  93: DMA13 */</span></div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;    DMA14_IRQn,             <span class="comment">/* 0x5E  0x0178  94: DMA14 */</span></div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;    DMA15_IRQn,             <span class="comment">/* 0x5F  0x017C  95: DMA15 */</span></div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;    USBDMA_IRQn,            <span class="comment">/* 0x60  0x0180  96: USB DMA */</span></div><div class="line"><a name="l00171"></a><span class="lineno">  171</span>&#160;    WDT2_IRQn,              <span class="comment">/* 0x61  0x0184  97: Watchdog Timer 2 */</span></div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;    ECC_IRQn,               <span class="comment">/* 0x62  0x0188  98: Error Correction */</span></div><div class="line"><a name="l00173"></a><span class="lineno">  173</span>&#160;    DVS_IRQn,               <span class="comment">/* 0x63  0x018C  99: DVS Controller */</span></div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;    SIMO_IRQn,              <span class="comment">/* 0x64 0x0190  100: SIMO Controller */</span></div><div class="line"><a name="l00175"></a><span class="lineno">  175</span>&#160;    RPU_IRQn,               <span class="comment">/* 0x65  0x0194  101: RPU */</span></div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;    AUDIO_IRQn,             <span class="comment">/* 0x66  0x0198  102: Audio subsystem */</span></div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;    FLC1_IRQn,              <span class="comment">/* 0x67  0x019C  103: Flash Control 1 */</span></div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;    UART3_IRQn,             <span class="comment">/* 0x68  0x01A0  104: UART 3 */</span></div><div class="line"><a name="l00179"></a><span class="lineno">  179</span>&#160;    UART4_IRQn,             <span class="comment">/* 0x69  0x01A4  105: UART 4 */</span></div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;    UART5_IRQn,             <span class="comment">/* 0x6A  0x01A8  106: UART 5 */</span></div><div class="line"><a name="l00181"></a><span class="lineno">  181</span>&#160;    CameraIF_IRQn,          <span class="comment">/* 0x6B  0x01AC  107: Camera IF */</span></div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;    I3C_IRQn,               <span class="comment">/* 0x6C  0x01B0  108: I3C */</span></div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;    HTMR0_IRQn,           <span class="comment">/* 0x6D  0x01B4  109: HTimer0 */</span></div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;    HTMR1_IRQn,           <span class="comment">/* 0x6E  0x01B8  110: HTimer1 */</span></div><div class="line"><a name="l00185"></a><span class="lineno">  185</span>&#160;    MXC_IRQ_EXT_COUNT </div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;} IRQn_Type;</div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;</div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;<span class="preprocessor">#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)</span></div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;</div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;<span class="comment">/* ================      Processor and Core Peripheral Section     ================ */</span></div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;</div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;<span class="comment">/* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */</span></div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;<span class="preprocessor">#define __CM4_REV                       0x0100          </span></div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;<span class="preprocessor">#define __MPU_PRESENT                   1               </span></div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;<span class="preprocessor">#define __NVIC_PRIO_BITS                3               </span></div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="preprocessor">#define __Vendor_SysTickConfig          0               </span></div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;<span class="preprocessor">#define __FPU_PRESENT                   1               </span></div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;<span class="preprocessor">#ifndef __CROSSWORKS</span></div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;<span class="preprocessor">#include &lt;core_cm4.h&gt;</span>                                   </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;<span class="preprocessor">#include &quot;max32665_sdma.h&quot;</span></div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;</div><div class="line"><a name="l00208"></a><span class="lineno">  208</span>&#160;<span class="preprocessor">#include &quot;system_max32665.h&quot;</span>                            </div><div class="line"><a name="l00211"></a><span class="lineno">  211</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="comment">/* ==================       Device Specific Memory Section       ================== */</span></div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00214"></a><span class="lineno">  214</span>&#160;</div><div class="line"><a name="l00215"></a><span class="lineno">  215</span>&#160;<span class="preprocessor">#define MXC_ROM_MEM_BASE                0x00000000UL</span></div><div class="line"><a name="l00216"></a><span class="lineno">  216</span>&#160;<span class="preprocessor">#define MXC_ROM_MEM_SIZE                0x00020000UL</span></div><div class="line"><a name="l00217"></a><span class="lineno">  217</span>&#160;<span class="preprocessor">#define MXC_XIP_MEM_BASE                0x08000000UL</span></div><div class="line"><a name="l00218"></a><span class="lineno">  218</span>&#160;<span class="preprocessor">#define MXC_XIP_MEM_SIZE                0x08000000UL</span></div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;<span class="preprocessor">#define MXC_FLASH0_MEM_BASE             0x10000000UL</span></div><div class="line"><a name="l00220"></a><span class="lineno">  220</span>&#160;<span class="preprocessor">#define MXC_FLASH1_MEM_BASE             0x10080000UL</span></div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;<span class="preprocessor">#define MXC_FLASH_MEM_BASE              MXC_FLASH0_MEM_BASE</span></div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;<span class="preprocessor">#define MXC_FLASH_PAGE_SIZE             0x00002000UL</span></div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;<span class="preprocessor">#define MXC_FLASH_MEM_SIZE              0x00080000UL</span></div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;<span class="preprocessor">#define MXC_INFO0_MEM_BASE              0x10800000UL</span></div><div class="line"><a name="l00225"></a><span class="lineno">  225</span>&#160;<span class="preprocessor">#define MXC_INFO1_MEM_BASE              0x10804000UL</span></div><div class="line"><a name="l00226"></a><span class="lineno">  226</span>&#160;<span class="preprocessor">#define MXC_INFO_MEM_BASE               MXC_INFO0_MEM_BASE</span></div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;<span class="preprocessor">#define MXC_INFO_MEM_SIZE               0x00004000UL</span></div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;<span class="preprocessor">#define MXC_SRAM_MEM_BASE               0x20000000UL</span></div><div class="line"><a name="l00229"></a><span class="lineno">  229</span>&#160;<span class="preprocessor">#define MXC_SRAM_MEM_SIZE               0x0008C000UL</span></div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="preprocessor">#define MXC_XIP_DATA_MEM_BASE           0x80000000UL</span></div><div class="line"><a name="l00231"></a><span class="lineno">  231</span>&#160;<span class="preprocessor">#define MXC_XIP_DATA_MEM_SIZE           0x20000000UL</span></div><div class="line"><a name="l00232"></a><span class="lineno">  232</span>&#160;</div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00234"></a><span class="lineno">  234</span>&#160;<span class="comment">/* ================       Device Specific Peripheral Section       ================ */</span></div><div class="line"><a name="l00235"></a><span class="lineno">  235</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00236"></a><span class="lineno">  236</span>&#160;</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;<span class="comment">   Base addresses and configuration settings for all MAX32665 peripheral modules.</span></div><div class="line"><a name="l00239"></a><span class="lineno">  239</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00240"></a><span class="lineno">  240</span>&#160;</div><div class="line"><a name="l00241"></a><span class="lineno">  241</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;<span class="comment">/*                                                             Global control */</span></div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;<span class="preprocessor">#define MXC_BASE_GCR                    ((uint32_t)0x40000000UL)</span></div><div class="line"><a name="l00244"></a><span class="lineno">  244</span>&#160;<span class="preprocessor">#define MXC_GCR                         ((mxc_gcr_regs_t*)MXC_BASE_GCR)</span></div><div class="line"><a name="l00245"></a><span class="lineno">  245</span>&#160;</div><div class="line"><a name="l00246"></a><span class="lineno">  246</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00247"></a><span class="lineno">  247</span>&#160;<span class="comment">/*                                            Non-battery backed SI Registers */</span></div><div class="line"><a name="l00248"></a><span class="lineno">  248</span>&#160;<span class="preprocessor">#define MXC_BASE_SIR                    ((uint32_t)0x40000400UL)</span></div><div class="line"><a name="l00249"></a><span class="lineno">  249</span>&#160;<span class="preprocessor">#define MXC_SIR                         ((mxc_sir_regs_t*)MXC_BASE_SIR)</span></div><div class="line"><a name="l00250"></a><span class="lineno">  250</span>&#160;</div><div class="line"><a name="l00251"></a><span class="lineno">  251</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00252"></a><span class="lineno">  252</span>&#160;<span class="comment">/*                                        Non-battery backed Function Control */</span></div><div class="line"><a name="l00253"></a><span class="lineno">  253</span>&#160;<span class="preprocessor">#define MXC_BASE_FCR                  ((uint32_t)0x40000800UL)</span></div><div class="line"><a name="l00254"></a><span class="lineno">  254</span>&#160;<span class="preprocessor">#define MXC_FCR                       ((mxc_fcr_regs_t*)MXC_BASE_FCR)</span></div><div class="line"><a name="l00255"></a><span class="lineno">  255</span>&#160;</div><div class="line"><a name="l00256"></a><span class="lineno">  256</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00257"></a><span class="lineno">  257</span>&#160;<span class="comment">/*                                                      Trust Protection Unit */</span></div><div class="line"><a name="l00258"></a><span class="lineno">  258</span>&#160;<span class="preprocessor">#define MXC_BASE_TPU                    ((uint32_t)0x40001000UL)</span></div><div class="line"><a name="l00259"></a><span class="lineno">  259</span>&#160;<span class="preprocessor">#define MXC_TPU                         ((mxc_tpu_regs_t*)MXC_BASE_TPU)</span></div><div class="line"><a name="l00260"></a><span class="lineno">  260</span>&#160;</div><div class="line"><a name="l00261"></a><span class="lineno">  261</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00262"></a><span class="lineno">  262</span>&#160;<span class="comment">/*                                                                   Watchdog */</span></div><div class="line"><a name="l00263"></a><span class="lineno">  263</span>&#160;<span class="preprocessor">#define MXC_BASE_WDT0                   ((uint32_t)0x40003000UL)</span></div><div class="line"><a name="l00264"></a><span class="lineno">  264</span>&#160;<span class="preprocessor">#define MXC_WDT0                        ((mxc_wdt_regs_t*)MXC_BASE_WDT0)</span></div><div class="line"><a name="l00265"></a><span class="lineno">  265</span>&#160;<span class="preprocessor">#define MXC_BASE_WDT1                   ((uint32_t)0x40003400UL)</span></div><div class="line"><a name="l00266"></a><span class="lineno">  266</span>&#160;<span class="preprocessor">#define MXC_WDT1                        ((mxc_wdt_regs_t*)MXC_BASE_WDT1)</span></div><div class="line"><a name="l00267"></a><span class="lineno">  267</span>&#160;<span class="preprocessor">#define MXC_BASE_WDT2                   ((uint32_t)0x40003800UL)</span></div><div class="line"><a name="l00268"></a><span class="lineno">  268</span>&#160;<span class="preprocessor">#define MXC_WDT2                        ((mxc_wdt_regs_t*)MXC_BASE_WDT2)</span></div><div class="line"><a name="l00269"></a><span class="lineno">  269</span>&#160;</div><div class="line"><a name="l00270"></a><span class="lineno">  270</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00271"></a><span class="lineno">  271</span>&#160;<span class="comment">/*                                                           Security Monitor */</span></div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;<span class="preprocessor">#define MXC_BASE_SMON                   ((uint32_t)0x40004000UL)</span></div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;<span class="preprocessor">#define MXC_SMON                        ((mxc_smon_regs_t*)MXC_BASE_SMON)</span></div><div class="line"><a name="l00274"></a><span class="lineno">  274</span>&#160;</div><div class="line"><a name="l00275"></a><span class="lineno">  275</span>&#160;</div><div class="line"><a name="l00276"></a><span class="lineno">  276</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00277"></a><span class="lineno">  277</span>&#160;<span class="comment">/*                                                                       SIMO */</span></div><div class="line"><a name="l00278"></a><span class="lineno">  278</span>&#160;<span class="preprocessor">#define MXC_BASE_SIMO                   ((uint32_t)0x40004400UL)</span></div><div class="line"><a name="l00279"></a><span class="lineno">  279</span>&#160;<span class="preprocessor">#define MXC_SIMO                        ((mxc_simo_regs_t*)MXC_BASE_SIMO)</span></div><div class="line"><a name="l00280"></a><span class="lineno">  280</span>&#160;</div><div class="line"><a name="l00281"></a><span class="lineno">  281</span>&#160;</div><div class="line"><a name="l00282"></a><span class="lineno">  282</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00283"></a><span class="lineno">  283</span>&#160;<span class="comment">/*                                                                         DVS*/</span></div><div class="line"><a name="l00284"></a><span class="lineno">  284</span>&#160;<span class="preprocessor">#define MXC_BASE_DVS                   ((uint32_t)0x40004800UL)</span></div><div class="line"><a name="l00285"></a><span class="lineno">  285</span>&#160;<span class="preprocessor">#define MXC_DVS                        ((mxc_dvs_regs_t*)MXC_BASE_DVS)</span></div><div class="line"><a name="l00286"></a><span class="lineno">  286</span>&#160;</div><div class="line"><a name="l00287"></a><span class="lineno">  287</span>&#160;</div><div class="line"><a name="l00288"></a><span class="lineno">  288</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00289"></a><span class="lineno">  289</span>&#160;<span class="comment">/*                                                           Security Monitor */</span></div><div class="line"><a name="l00290"></a><span class="lineno">  290</span>&#160;<span class="preprocessor">#define MXC_BASE_SMON                   ((uint32_t)0x40004000UL)</span></div><div class="line"><a name="l00291"></a><span class="lineno">  291</span>&#160;<span class="preprocessor">#define MXC_SMON                        ((mxc_smon_regs_t*)MXC_BASE_SMON)</span></div><div class="line"><a name="l00292"></a><span class="lineno">  292</span>&#160;</div><div class="line"><a name="l00293"></a><span class="lineno">  293</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00294"></a><span class="lineno">  294</span>&#160;<span class="comment">/*                                                            Real Time Clock */</span></div><div class="line"><a name="l00295"></a><span class="lineno">  295</span>&#160;<span class="preprocessor">#define MXC_BASE_RTC                    ((uint32_t)0x40006000UL)</span></div><div class="line"><a name="l00296"></a><span class="lineno">  296</span>&#160;<span class="preprocessor">#define MXC_RTC                         ((mxc_rtc_regs_t*)MXC_BASE_RTC)</span></div><div class="line"><a name="l00297"></a><span class="lineno">  297</span>&#160;</div><div class="line"><a name="l00298"></a><span class="lineno">  298</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00299"></a><span class="lineno">  299</span>&#160;<span class="comment">/*                                                               Wakeup Timer */</span></div><div class="line"><a name="l00300"></a><span class="lineno">  300</span>&#160;<span class="preprocessor">#define MXC_BASE_WUT                    ((uint32_t)0x40006400UL)</span></div><div class="line"><a name="l00301"></a><span class="lineno">  301</span>&#160;<span class="preprocessor">#define MXC_WUT                         ((mxc_wut_regs_t*)MXC_BASE_WUT)</span></div><div class="line"><a name="l00302"></a><span class="lineno">  302</span>&#160;</div><div class="line"><a name="l00303"></a><span class="lineno">  303</span>&#160;</div><div class="line"><a name="l00304"></a><span class="lineno">  304</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00305"></a><span class="lineno">  305</span>&#160;<span class="comment">/*                                                            Power Sequencer */</span></div><div class="line"><a name="l00306"></a><span class="lineno">  306</span>&#160;<span class="preprocessor">#define MXC_BASE_PWRSEQ                 ((uint32_t)0x40006800UL)</span></div><div class="line"><a name="l00307"></a><span class="lineno">  307</span>&#160;<span class="preprocessor">#define MXC_PWRSEQ                      ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)</span></div><div class="line"><a name="l00308"></a><span class="lineno">  308</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00309"></a><span class="lineno">  309</span>&#160;<span class="comment">/*                                                            Power Sequencer */</span></div><div class="line"><a name="l00310"></a><span class="lineno">  310</span>&#160;<span class="preprocessor">#define MXC_BASE_MCR                    ((uint32_t)0x40006C00UL)</span></div><div class="line"><a name="l00311"></a><span class="lineno">  311</span>&#160;<span class="preprocessor">#define MXC_MCR                         ((mxc_mcr_regs_t*)MXC_BASE_MCR)</span></div><div class="line"><a name="l00312"></a><span class="lineno">  312</span>&#160;</div><div class="line"><a name="l00313"></a><span class="lineno">  313</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00314"></a><span class="lineno">  314</span>&#160;<span class="comment">/*                                                                       GPIO */</span></div><div class="line"><a name="l00315"></a><span class="lineno">  315</span>&#160;<span class="preprocessor">#define MXC_CFG_GPIO_INSTANCES          (2)</span></div><div class="line"><a name="l00316"></a><span class="lineno">  316</span>&#160;<span class="preprocessor">#define MXC_CFG_GPIO_PINS_PORT          (32)</span></div><div class="line"><a name="l00317"></a><span class="lineno">  317</span>&#160;</div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;<span class="preprocessor">#define MXC_BASE_GPIO0                  ((uint32_t)0x40008000UL)</span></div><div class="line"><a name="l00319"></a><span class="lineno">  319</span>&#160;<span class="preprocessor">#define MXC_GPIO0                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)</span></div><div class="line"><a name="l00320"></a><span class="lineno">  320</span>&#160;<span class="preprocessor">#define MXC_BASE_GPIO1                  ((uint32_t)0x40009000UL)</span></div><div class="line"><a name="l00321"></a><span class="lineno">  321</span>&#160;<span class="preprocessor">#define MXC_GPIO1                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)</span></div><div class="line"><a name="l00322"></a><span class="lineno">  322</span>&#160;</div><div class="line"><a name="l00323"></a><span class="lineno">  323</span>&#160;<span class="preprocessor">#define MXC_GPIO_GET_IDX(p)             ((p) == MXC_GPIO0 ? 0 :                \</span></div><div class="line"><a name="l00324"></a><span class="lineno">  324</span>&#160;<span class="preprocessor">                                            (p) == MXC_GPIO1 ? 1 : -1)</span></div><div class="line"><a name="l00325"></a><span class="lineno">  325</span>&#160;</div><div class="line"><a name="l00326"></a><span class="lineno">  326</span>&#160;<span class="preprocessor">#define MXC_GPIO_GET_GPIO(i)            ((i) == 0 ? MXC_GPIO0 :                \</span></div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_GPIO1 : 0)</span></div><div class="line"><a name="l00328"></a><span class="lineno">  328</span>&#160;</div><div class="line"><a name="l00329"></a><span class="lineno">  329</span>&#160;<span class="preprocessor">#define MXC_GPIO_GET_IRQ(i)             ((i) == 0 ? GPIO0_IRQn :               \</span></div><div class="line"><a name="l00330"></a><span class="lineno">  330</span>&#160;<span class="preprocessor">                                            (i) == 1 ? GPIO1_IRQn : (IRQn_Type) 0)</span></div><div class="line"><a name="l00331"></a><span class="lineno">  331</span>&#160;</div><div class="line"><a name="l00332"></a><span class="lineno">  332</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00333"></a><span class="lineno">  333</span>&#160;<span class="comment">/*                                                                      Timer */</span></div><div class="line"><a name="l00334"></a><span class="lineno">  334</span>&#160;<span class="preprocessor">#define MXC_CFG_TMR_INSTANCES           (6)</span></div><div class="line"><a name="l00335"></a><span class="lineno">  335</span>&#160;</div><div class="line"><a name="l00336"></a><span class="lineno">  336</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR0                   ((uint32_t)0x40010000UL)</span></div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;<span class="preprocessor">#define MXC_TMR0                        ((mxc_tmr_regs_t*)MXC_BASE_TMR0)</span></div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR1                   ((uint32_t)0x40011000UL)</span></div><div class="line"><a name="l00339"></a><span class="lineno">  339</span>&#160;<span class="preprocessor">#define MXC_TMR1                        ((mxc_tmr_regs_t*)MXC_BASE_TMR1)</span></div><div class="line"><a name="l00340"></a><span class="lineno">  340</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR2                   ((uint32_t)0x40012000UL)</span></div><div class="line"><a name="l00341"></a><span class="lineno">  341</span>&#160;<span class="preprocessor">#define MXC_TMR2                        ((mxc_tmr_regs_t*)MXC_BASE_TMR2)</span></div><div class="line"><a name="l00342"></a><span class="lineno">  342</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR3                   ((uint32_t)0x40013000UL)</span></div><div class="line"><a name="l00343"></a><span class="lineno">  343</span>&#160;<span class="preprocessor">#define MXC_TMR3                        ((mxc_tmr_regs_t*)MXC_BASE_TMR3)</span></div><div class="line"><a name="l00344"></a><span class="lineno">  344</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR4                   ((uint32_t)0x40014000UL)</span></div><div class="line"><a name="l00345"></a><span class="lineno">  345</span>&#160;<span class="preprocessor">#define MXC_TMR4                        ((mxc_tmr_regs_t*)MXC_BASE_TMR4)</span></div><div class="line"><a name="l00346"></a><span class="lineno">  346</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR5                   ((uint32_t)0x40015000UL)</span></div><div class="line"><a name="l00347"></a><span class="lineno">  347</span>&#160;<span class="preprocessor">#define MXC_TMR5                        ((mxc_tmr_regs_t*)MXC_BASE_TMR5)</span></div><div class="line"><a name="l00348"></a><span class="lineno">  348</span>&#160;</div><div class="line"><a name="l00349"></a><span class="lineno">  349</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? TMR0_IRQn :     \</span></div><div class="line"><a name="l00350"></a><span class="lineno">  350</span>&#160;<span class="preprocessor">                                            (i) == 1 ? TMR1_IRQn :             \</span></div><div class="line"><a name="l00351"></a><span class="lineno">  351</span>&#160;<span class="preprocessor">                                            (i) == 2 ? TMR2_IRQn :             \</span></div><div class="line"><a name="l00352"></a><span class="lineno">  352</span>&#160;<span class="preprocessor">                                            (i) == 3 ? TMR3_IRQn :             \</span></div><div class="line"><a name="l00353"></a><span class="lineno">  353</span>&#160;<span class="preprocessor">                                            (i) == 4 ? TMR4_IRQn :             \</span></div><div class="line"><a name="l00354"></a><span class="lineno">  354</span>&#160;<span class="preprocessor">                                            (i) == 5 ? TMR5_IRQn : 0)</span></div><div class="line"><a name="l00355"></a><span class="lineno">  355</span>&#160;</div><div class="line"><a name="l00356"></a><span class="lineno">  356</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_BASE(i)             ((i) == 0 ? MXC_BASE_TMR0 :            \</span></div><div class="line"><a name="l00357"></a><span class="lineno">  357</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_TMR1 :         \</span></div><div class="line"><a name="l00358"></a><span class="lineno">  358</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_BASE_TMR2 :         \</span></div><div class="line"><a name="l00359"></a><span class="lineno">  359</span>&#160;<span class="preprocessor">                                            (i) == 3 ? MXC_BASE_TMR3 :         \</span></div><div class="line"><a name="l00360"></a><span class="lineno">  360</span>&#160;<span class="preprocessor">                                            (i) == 4 ? MXC_BASE_TMR4 :         \</span></div><div class="line"><a name="l00361"></a><span class="lineno">  361</span>&#160;<span class="preprocessor">                                            (i) == 5 ? MXC_BASE_TMR5 : 0)</span></div><div class="line"><a name="l00362"></a><span class="lineno">  362</span>&#160;</div><div class="line"><a name="l00363"></a><span class="lineno">  363</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_TMR(i)              ((i) == 0 ? MXC_TMR0 :                 \</span></div><div class="line"><a name="l00364"></a><span class="lineno">  364</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_TMR1 :              \</span></div><div class="line"><a name="l00365"></a><span class="lineno">  365</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_TMR2 :              \</span></div><div class="line"><a name="l00366"></a><span class="lineno">  366</span>&#160;<span class="preprocessor">                                            (i) == 3 ? MXC_TMR3 :              \</span></div><div class="line"><a name="l00367"></a><span class="lineno">  367</span>&#160;<span class="preprocessor">                                            (i) == 4 ? MXC_TMR4 :              \</span></div><div class="line"><a name="l00368"></a><span class="lineno">  368</span>&#160;<span class="preprocessor">                                            (i) == 5 ? MXC_TMR5 : 0)</span></div><div class="line"><a name="l00369"></a><span class="lineno">  369</span>&#160;</div><div class="line"><a name="l00370"></a><span class="lineno">  370</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_IDX(p)              ((p) == MXC_TMR0 ? 0 :                 \</span></div><div class="line"><a name="l00371"></a><span class="lineno">  371</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR1 ? 1 :              \</span></div><div class="line"><a name="l00372"></a><span class="lineno">  372</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR2 ? 2 :              \</span></div><div class="line"><a name="l00373"></a><span class="lineno">  373</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR3 ? 3 :              \</span></div><div class="line"><a name="l00374"></a><span class="lineno">  374</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR4 ? 4 :              \</span></div><div class="line"><a name="l00375"></a><span class="lineno">  375</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR5 ? 5 : -1)</span></div><div class="line"><a name="l00376"></a><span class="lineno">  376</span>&#160;</div><div class="line"><a name="l00377"></a><span class="lineno">  377</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00378"></a><span class="lineno">  378</span>&#160;<span class="comment">/*                                                           High Speed Timer */</span></div><div class="line"><a name="l00379"></a><span class="lineno">  379</span>&#160;<span class="preprocessor">#define MXC_BASE_HTMR0                    ((uint32_t)0x4001B000UL)</span></div><div class="line"><a name="l00380"></a><span class="lineno">  380</span>&#160;<span class="preprocessor">#define MXC_HTMR0                         ((mxc_htmr_regs_t*)MXC_BASE_HTMR0)</span></div><div class="line"><a name="l00381"></a><span class="lineno">  381</span>&#160;<span class="preprocessor">#define MXC_BASE_HTMR1                    ((uint32_t)0x4001C000UL)</span></div><div class="line"><a name="l00382"></a><span class="lineno">  382</span>&#160;<span class="preprocessor">#define MXC_HTMR1                         ((mxc_htmr_regs_t*)MXC_BASE_HTMR1)</span></div><div class="line"><a name="l00383"></a><span class="lineno">  383</span>&#160;</div><div class="line"><a name="l00384"></a><span class="lineno">  384</span>&#160;</div><div class="line"><a name="l00385"></a><span class="lineno">  385</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00386"></a><span class="lineno">  386</span>&#160;<span class="comment">/*                                                                        I2C */</span></div><div class="line"><a name="l00387"></a><span class="lineno">  387</span>&#160;<span class="preprocessor">#define MXC_I2C_INSTANCES               (3)</span></div><div class="line"><a name="l00388"></a><span class="lineno">  388</span>&#160;</div><div class="line"><a name="l00389"></a><span class="lineno">  389</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C0_BUS0                   ((uint32_t)0x4001D000UL)</span></div><div class="line"><a name="l00390"></a><span class="lineno">  390</span>&#160;<span class="preprocessor">#define MXC_I2C0_BUS0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS0)</span></div><div class="line"><a name="l00391"></a><span class="lineno">  391</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C1_BUS0                   ((uint32_t)0x4001E000UL)</span></div><div class="line"><a name="l00392"></a><span class="lineno">  392</span>&#160;<span class="preprocessor">#define MXC_I2C1_BUS0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS0)</span></div><div class="line"><a name="l00393"></a><span class="lineno">  393</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C2_BUS0                   ((uint32_t)0x4001F000UL)</span></div><div class="line"><a name="l00394"></a><span class="lineno">  394</span>&#160;<span class="preprocessor">#define MXC_I2C2_BUS0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS0)</span></div><div class="line"><a name="l00395"></a><span class="lineno">  395</span>&#160;</div><div class="line"><a name="l00396"></a><span class="lineno">  396</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C0_BUS1                   ((uint32_t)0x4011D000UL)</span></div><div class="line"><a name="l00397"></a><span class="lineno">  397</span>&#160;<span class="preprocessor">#define MXC_I2C0_BUS1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS1)</span></div><div class="line"><a name="l00398"></a><span class="lineno">  398</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C1_BUS1                   ((uint32_t)0x4011E000UL)</span></div><div class="line"><a name="l00399"></a><span class="lineno">  399</span>&#160;<span class="preprocessor">#define MXC_I2C1_BUS1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS1)</span></div><div class="line"><a name="l00400"></a><span class="lineno">  400</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C2_BUS1                   ((uint32_t)0x4011F000UL)</span></div><div class="line"><a name="l00401"></a><span class="lineno">  401</span>&#160;<span class="preprocessor">#define MXC_I2C2_BUS1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS1)</span></div><div class="line"><a name="l00402"></a><span class="lineno">  402</span>&#160;</div><div class="line"><a name="l00403"></a><span class="lineno">  403</span>&#160;</div><div class="line"><a name="l00404"></a><span class="lineno">  404</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_IRQ(i)              (IRQn_Type)((i) == 0x0 ? I2C0_IRQn :     \</span></div><div class="line"><a name="l00405"></a><span class="lineno">  405</span>&#160;<span class="preprocessor">                                            (i) == 0x1 ? I2C1_IRQn :             \</span></div><div class="line"><a name="l00406"></a><span class="lineno">  406</span>&#160;<span class="preprocessor">                                            (i) == 0x2 ? I2C2_IRQn :             \</span></div><div class="line"><a name="l00407"></a><span class="lineno">  407</span>&#160;<span class="preprocessor">                                            (i) == 0x8000 ? I2C0_IRQn :            \</span></div><div class="line"><a name="l00408"></a><span class="lineno">  408</span>&#160;<span class="preprocessor">                                            (i) == 0x8001 ? I2C1_IRQn :            \</span></div><div class="line"><a name="l00409"></a><span class="lineno">  409</span>&#160;<span class="preprocessor">                                            (i) == 0x8002 ? I2C2_IRQn : 0)</span></div><div class="line"><a name="l00410"></a><span class="lineno">  410</span>&#160;</div><div class="line"><a name="l00411"></a><span class="lineno">  411</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_BASE(i)             ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 :            \</span></div><div class="line"><a name="l00412"></a><span class="lineno">  412</span>&#160;<span class="preprocessor">                                            (i) == 0x1 ? MXC_BASE_I2C1_BUS0 :         \</span></div><div class="line"><a name="l00413"></a><span class="lineno">  413</span>&#160;<span class="preprocessor">                                            (i) == 0x2 ? MXC_BASE_I2C2_BUS0 :         \</span></div><div class="line"><a name="l00414"></a><span class="lineno">  414</span>&#160;<span class="preprocessor">                                            (i) == 0x8000 ? MXC_BASE_I2C0_BUS1 :        \</span></div><div class="line"><a name="l00415"></a><span class="lineno">  415</span>&#160;<span class="preprocessor">                                            (i) == 0x8001 ? MXC_BASE_I2C1_BUS1 :        \</span></div><div class="line"><a name="l00416"></a><span class="lineno">  416</span>&#160;<span class="preprocessor">                                            (i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : 0)</span></div><div class="line"><a name="l00417"></a><span class="lineno">  417</span>&#160;</div><div class="line"><a name="l00418"></a><span class="lineno">  418</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_IDX(p)              ((p) == MXC_I2C0_BUS0 ? 0x0 :                 \</span></div><div class="line"><a name="l00419"></a><span class="lineno">  419</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C1_BUS0 ? 0x1 :              \</span></div><div class="line"><a name="l00420"></a><span class="lineno">  420</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C2_BUS0 ? 0x2 :              \</span></div><div class="line"><a name="l00421"></a><span class="lineno">  421</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C0_BUS1 ? 0x8000 :             \</span></div><div class="line"><a name="l00422"></a><span class="lineno">  422</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C1_BUS1 ? 0x8001 :             \</span></div><div class="line"><a name="l00423"></a><span class="lineno">  423</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C2_BUS1 ? 0x8002 : -1)</span></div><div class="line"><a name="l00424"></a><span class="lineno">  424</span>&#160;</div><div class="line"><a name="l00425"></a><span class="lineno">  425</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_I2C(p)              ((p) == 0x0 ? MXC_I2C0_BUS0 :                 \</span></div><div class="line"><a name="l00426"></a><span class="lineno">  426</span>&#160;<span class="preprocessor">                                            (p) == 0x1 ? MXC_I2C1_BUS0 :              \</span></div><div class="line"><a name="l00427"></a><span class="lineno">  427</span>&#160;<span class="preprocessor">                                            (p) == 0x2 ? MXC_I2C2_BUS0 :              \</span></div><div class="line"><a name="l00428"></a><span class="lineno">  428</span>&#160;<span class="preprocessor">                                            (p) == 0x8000 ? MXC_I2C0_BUS1 :             \</span></div><div class="line"><a name="l00429"></a><span class="lineno">  429</span>&#160;<span class="preprocessor">                                            (p) == 0x8001 ? MXC_I2C1_BUS1 :             \</span></div><div class="line"><a name="l00430"></a><span class="lineno">  430</span>&#160;<span class="preprocessor">                                            (p) == 0x8002? MXC_I2C2_BUS1 : 0)</span></div><div class="line"><a name="l00431"></a><span class="lineno">  431</span>&#160;<span class="preprocessor">#define MXC_I2C_FIFO_DEPTH              (8)</span></div><div class="line"><a name="l00432"></a><span class="lineno">  432</span>&#160;</div><div class="line"><a name="l00433"></a><span class="lineno">  433</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00434"></a><span class="lineno">  434</span>&#160;<span class="comment">/*                                                      SPI Execute in Place  */</span></div><div class="line"><a name="l00435"></a><span class="lineno">  435</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXF                   ((uint32_t)0x40026000UL)</span></div><div class="line"><a name="l00436"></a><span class="lineno">  436</span>&#160;<span class="preprocessor">#define MXC_SPIXF                        ((mxc_spixf_regs_t*)MXC_BASE_SPIXF)</span></div><div class="line"><a name="l00437"></a><span class="lineno">  437</span>&#160;</div><div class="line"><a name="l00438"></a><span class="lineno">  438</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXF_FIFO             ((uint32_t)0x400BC000UL)</span></div><div class="line"><a name="l00439"></a><span class="lineno">  439</span>&#160;<span class="preprocessor">#define MXC_SPIXF_FIFO                  ((mxc_spixf_fifo_regs_t*)MXC_BASE_SPIXF_FIFO)</span></div><div class="line"><a name="l00440"></a><span class="lineno">  440</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00441"></a><span class="lineno">  441</span>&#160;<span class="comment">/*                                                SPI Execute in Place Master */</span></div><div class="line"><a name="l00442"></a><span class="lineno">  442</span>&#160;</div><div class="line"><a name="l00443"></a><span class="lineno">  443</span>&#160;<span class="preprocessor">#define MXC_CFG_SPIXFC_FIFO_DEPTH          (16)</span></div><div class="line"><a name="l00444"></a><span class="lineno">  444</span>&#160;</div><div class="line"><a name="l00445"></a><span class="lineno">  445</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXFC                  ((uint32_t)0x40027000UL)</span></div><div class="line"><a name="l00446"></a><span class="lineno">  446</span>&#160;<span class="preprocessor">#define MXC_SPIXFC                       ((mxc_spixfc_regs_t*)MXC_BASE_SPIXFC)</span></div><div class="line"><a name="l00447"></a><span class="lineno">  447</span>&#160;</div><div class="line"><a name="l00448"></a><span class="lineno">  448</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00449"></a><span class="lineno">  449</span>&#160;<span class="comment">/*                                                                        DMA */</span></div><div class="line"><a name="l00450"></a><span class="lineno">  450</span>&#160;<span class="preprocessor">#define MXC_DMA_CHANNELS                (16)</span></div><div class="line"><a name="l00451"></a><span class="lineno">  451</span>&#160;<span class="preprocessor">#define MXC_DMA_INSTANCES               (2)</span></div><div class="line"><a name="l00452"></a><span class="lineno">  452</span>&#160;</div><div class="line"><a name="l00453"></a><span class="lineno">  453</span>&#160;<span class="preprocessor">#define MXC_BASE_DMA0                    ((uint32_t)0x40028000UL)</span></div><div class="line"><a name="l00454"></a><span class="lineno">  454</span>&#160;<span class="preprocessor">#define MXC_DMA0                         ((mxc_dma_regs_t*)MXC_BASE_DMA0)</span></div><div class="line"><a name="l00455"></a><span class="lineno">  455</span>&#160;<span class="preprocessor">#define MXC_BASE_DMA1                    ((uint32_t)0x40035000UL)</span></div><div class="line"><a name="l00456"></a><span class="lineno">  456</span>&#160;<span class="preprocessor">#define MXC_DMA1                         ((mxc_dma_regs_t*)MXC_BASE_DMA1)</span></div><div class="line"><a name="l00457"></a><span class="lineno">  457</span>&#160;</div><div class="line"><a name="l00458"></a><span class="lineno">  458</span>&#160;<span class="comment">// TODO: remove this when creating drivers to accept two instance of these.</span></div><div class="line"><a name="l00459"></a><span class="lineno">  459</span>&#160;<span class="preprocessor">#define MXC_DMA     MXC_DMA0</span></div><div class="line"><a name="l00460"></a><span class="lineno">  460</span>&#160;</div><div class="line"><a name="l00461"></a><span class="lineno">  461</span>&#160;<span class="preprocessor">#define MXC_DMA_GET_BASE(i)            ((i) == 0 ? MXC_BASE_DMA0 :           \</span></div><div class="line"><a name="l00462"></a><span class="lineno">  462</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_DMA1 : 0)</span></div><div class="line"><a name="l00463"></a><span class="lineno">  463</span>&#160;</div><div class="line"><a name="l00464"></a><span class="lineno">  464</span>&#160;<span class="preprocessor">#define MXC_DMA_GET_DMA(i)            ((i) == 0 ? MXC_DMA0 :                \</span></div><div class="line"><a name="l00465"></a><span class="lineno">  465</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_DMA1 : 0)</span></div><div class="line"><a name="l00466"></a><span class="lineno">  466</span>&#160;</div><div class="line"><a name="l00467"></a><span class="lineno">  467</span>&#160;<span class="preprocessor">#define MXC_DMA_GET_IDX(p)             ((p) == MXC_DMA0 ? 0 :                \</span></div><div class="line"><a name="l00468"></a><span class="lineno">  468</span>&#160;<span class="preprocessor">                                            (p) == MXC_DMA1 ? 1 : -1)</span></div><div class="line"><a name="l00469"></a><span class="lineno">  469</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00470"></a><span class="lineno">  470</span>&#160;<span class="comment">/*                                                                        FLC */</span></div><div class="line"><a name="l00471"></a><span class="lineno">  471</span>&#160;<span class="preprocessor">#define MXC_FLC_INSTANCES               (2)</span></div><div class="line"><a name="l00472"></a><span class="lineno">  472</span>&#160;</div><div class="line"><a name="l00473"></a><span class="lineno">  473</span>&#160;<span class="preprocessor">#define MXC_BASE_FLC0                    ((uint32_t)0x40029000UL)</span></div><div class="line"><a name="l00474"></a><span class="lineno">  474</span>&#160;<span class="preprocessor">#define MXC_FLC0                         ((mxc_flc_regs_t*)MXC_BASE_FLC0)</span></div><div class="line"><a name="l00475"></a><span class="lineno">  475</span>&#160;<span class="preprocessor">#define MXC_BASE_FLC1                    ((uint32_t)0x40029400UL)</span></div><div class="line"><a name="l00476"></a><span class="lineno">  476</span>&#160;<span class="preprocessor">#define MXC_FLC1                         ((mxc_flc_regs_t*)MXC_BASE_FLC1)</span></div><div class="line"><a name="l00477"></a><span class="lineno">  477</span>&#160;</div><div class="line"><a name="l00478"></a><span class="lineno">  478</span>&#160;<span class="comment">// TODO: remove this when creating drivers to accept two instance of these.</span></div><div class="line"><a name="l00479"></a><span class="lineno">  479</span>&#160;<span class="comment">// #define MXC_FLC     MXC_FLC0</span></div><div class="line"><a name="l00480"></a><span class="lineno">  480</span>&#160;</div><div class="line"><a name="l00481"></a><span class="lineno">  481</span>&#160;</div><div class="line"><a name="l00482"></a><span class="lineno">  482</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? FLC0_IRQn :    \</span></div><div class="line"><a name="l00483"></a><span class="lineno">  483</span>&#160;<span class="preprocessor">                                            (i) == 1 ? FLC1_IRQn :0)</span></div><div class="line"><a name="l00484"></a><span class="lineno">  484</span>&#160;</div><div class="line"><a name="l00485"></a><span class="lineno">  485</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_BASE(i)            ((i) == 0 ? MXC_BASE_FLC0 :           \</span></div><div class="line"><a name="l00486"></a><span class="lineno">  486</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_FLC1 : 0)</span></div><div class="line"><a name="l00487"></a><span class="lineno">  487</span>&#160;</div><div class="line"><a name="l00488"></a><span class="lineno">  488</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_FLC(i)            ((i) == 0 ? MXC_FLC0 :                \</span></div><div class="line"><a name="l00489"></a><span class="lineno">  489</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_FLC1 : 0)</span></div><div class="line"><a name="l00490"></a><span class="lineno">  490</span>&#160;</div><div class="line"><a name="l00491"></a><span class="lineno">  491</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_IDX(p)             ((p) == MXC_FLC0 ? 0 :                \</span></div><div class="line"><a name="l00492"></a><span class="lineno">  492</span>&#160;<span class="preprocessor">                                            (p) == MXC_FLC1 ? 1 : -1)</span></div><div class="line"><a name="l00493"></a><span class="lineno">  493</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00494"></a><span class="lineno">  494</span>&#160;<span class="comment">/*                                                          Instruction Cache */</span></div><div class="line"><a name="l00495"></a><span class="lineno">  495</span>&#160;<span class="preprocessor">#define MXC_ICC_INSTANCES               (2)</span></div><div class="line"><a name="l00496"></a><span class="lineno">  496</span>&#160;</div><div class="line"><a name="l00497"></a><span class="lineno">  497</span>&#160;<span class="preprocessor">#define MXC_BASE_ICC0                    ((uint32_t)0x4002A000UL)</span></div><div class="line"><a name="l00498"></a><span class="lineno">  498</span>&#160;<span class="preprocessor">#define MXC_ICC0                         ((mxc_icc_regs_t*)MXC_BASE_ICC0)</span></div><div class="line"><a name="l00499"></a><span class="lineno">  499</span>&#160;<span class="preprocessor">#define MXC_BASE_ICC1                    ((uint32_t)0x4002A800UL)</span></div><div class="line"><a name="l00500"></a><span class="lineno">  500</span>&#160;<span class="preprocessor">#define MXC_ICC1                         ((mxc_icc_regs_t*)MXC_BASE_ICC1)</span></div><div class="line"><a name="l00501"></a><span class="lineno">  501</span>&#160;</div><div class="line"><a name="l00502"></a><span class="lineno">  502</span>&#160;<span class="comment">// TODO: remove this when creating drivers to accept two instance of these.</span></div><div class="line"><a name="l00503"></a><span class="lineno">  503</span>&#160;<span class="preprocessor">#define MXC_ICC     MXC_ICC0</span></div><div class="line"><a name="l00504"></a><span class="lineno">  504</span>&#160;</div><div class="line"><a name="l00505"></a><span class="lineno">  505</span>&#160;</div><div class="line"><a name="l00506"></a><span class="lineno">  506</span>&#160;<span class="preprocessor">#define MXC_ICC_GET_BASE(i)            ((i) == 0 ? MXC_BASE_ICC0 :           \</span></div><div class="line"><a name="l00507"></a><span class="lineno">  507</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_ICC1 : 0)</span></div><div class="line"><a name="l00508"></a><span class="lineno">  508</span>&#160;</div><div class="line"><a name="l00509"></a><span class="lineno">  509</span>&#160;<span class="preprocessor">#define MXC_ICC_GET_ICC(i)            ((i) == 0 ? MXC_ICC0 :                \</span></div><div class="line"><a name="l00510"></a><span class="lineno">  510</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_ICC1 : 0)</span></div><div class="line"><a name="l00511"></a><span class="lineno">  511</span>&#160;</div><div class="line"><a name="l00512"></a><span class="lineno">  512</span>&#160;<span class="preprocessor">#define MXC_ICC_GET_IDX(p)             ((p) == MXC_ICC0 ? 0 :                \</span></div><div class="line"><a name="l00513"></a><span class="lineno">  513</span>&#160;<span class="preprocessor">                                            (p) == MXC_ICC1 ? 1 : -1)</span></div><div class="line"><a name="l00514"></a><span class="lineno">  514</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00515"></a><span class="lineno">  515</span>&#160;<span class="comment">/*                                                      Instruction Cache XIP */</span></div><div class="line"><a name="l00516"></a><span class="lineno">  516</span>&#160;<span class="preprocessor">#define MXC_BASE_ICX                    ((uint32_t)0x4002F000UL)</span></div><div class="line"><a name="l00517"></a><span class="lineno">  517</span>&#160;<span class="preprocessor">#define MXC_ICX                         ((mxc_icc_regs_t*)MXC_BASE_ICX)</span></div><div class="line"><a name="l00518"></a><span class="lineno">  518</span>&#160;</div><div class="line"><a name="l00519"></a><span class="lineno">  519</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00520"></a><span class="lineno">  520</span>&#160;<span class="comment">/*                                                                 Data Cache */</span></div><div class="line"><a name="l00521"></a><span class="lineno">  521</span>&#160;<span class="preprocessor">#define MXC_BASE_EMCC                    ((uint32_t)0x40033000UL)</span></div><div class="line"><a name="l00522"></a><span class="lineno">  522</span>&#160;<span class="preprocessor">#define MXC_EMCC                         ((mxc_emcc_regs_t*)MXC_BASE_EMCC)</span></div><div class="line"><a name="l00523"></a><span class="lineno">  523</span>&#160;</div><div class="line"><a name="l00524"></a><span class="lineno">  524</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00525"></a><span class="lineno">  525</span>&#160;<span class="comment">/*                                                                        ADC */</span></div><div class="line"><a name="l00526"></a><span class="lineno">  526</span>&#160;<span class="preprocessor">#define MXC_BASE_ADC                    ((uint32_t)0x40034000UL)</span></div><div class="line"><a name="l00527"></a><span class="lineno">  527</span>&#160;<span class="preprocessor">#define MXC_ADC                         ((mxc_adc_regs_t*)MXC_BASE_ADC)</span></div><div class="line"><a name="l00528"></a><span class="lineno">  528</span>&#160;<span class="preprocessor">#define MXC_ADC_MAX_CLOCK               8000000 // Maximum ADC clock in Hz</span></div><div class="line"><a name="l00529"></a><span class="lineno">  529</span>&#160;</div><div class="line"><a name="l00530"></a><span class="lineno">  530</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00531"></a><span class="lineno">  531</span>&#160;<span class="comment">/*                                                                        USB */</span></div><div class="line"><a name="l00532"></a><span class="lineno">  532</span>&#160;<span class="preprocessor">#define MXC_BASE_USBHS                  ((uint32_t)0x400B1000UL)</span></div><div class="line"><a name="l00533"></a><span class="lineno">  533</span>&#160;<span class="preprocessor">#define MXC_USBHS                       ((mxc_usbhs_regs_t*)MXC_BASE_USBHS)</span></div><div class="line"><a name="l00534"></a><span class="lineno">  534</span>&#160;<span class="preprocessor">#define MXC_USBHS_NUM_EP                12 </span><span class="comment">/* HW must have at least EP 0 CONTROL + 11 IN/OUT */</span><span class="preprocessor"></span></div><div class="line"><a name="l00535"></a><span class="lineno">  535</span>&#160;<span class="preprocessor">#define MXC_USBHS_NUM_DMA                8 </span><span class="comment">/* HW must have at least this many DMA channels */</span><span class="preprocessor"></span></div><div class="line"><a name="l00536"></a><span class="lineno">  536</span>&#160;<span class="preprocessor">#define MXC_USBHS_MAX_PACKET            512</span></div><div class="line"><a name="l00537"></a><span class="lineno">  537</span>&#160;</div><div class="line"><a name="l00538"></a><span class="lineno">  538</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00539"></a><span class="lineno">  539</span>&#160;<span class="comment">/*                                                                  Smart DMA */</span></div><div class="line"><a name="l00540"></a><span class="lineno">  540</span>&#160;<span class="preprocessor">#define MXC_BASE_SDMA                   ((uint32_t)0x40036000UL)</span></div><div class="line"><a name="l00541"></a><span class="lineno">  541</span>&#160;<span class="preprocessor">#define MXC_SDMA                        ((mxc_sdma_regs_t*)MXC_BASE_SDMA)</span></div><div class="line"><a name="l00542"></a><span class="lineno">  542</span>&#160;</div><div class="line"><a name="l00543"></a><span class="lineno">  543</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00544"></a><span class="lineno">  544</span>&#160;<span class="comment">/*                                                               SPI XIP Data */</span></div><div class="line"><a name="l00545"></a><span class="lineno">  545</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXR                   ((uint32_t)0x4003A000UL)</span></div><div class="line"><a name="l00546"></a><span class="lineno">  546</span>&#160;<span class="preprocessor">#define MXC_SPIXR                        ((mxc_spixr_regs_t*)MXC_BASE_SPIXR)</span></div><div class="line"><a name="l00547"></a><span class="lineno">  547</span>&#160;</div><div class="line"><a name="l00548"></a><span class="lineno">  548</span>&#160;<span class="comment">/*******************************************************************************/</span></div><div class="line"><a name="l00549"></a><span class="lineno">  549</span>&#160;<span class="comment">/*                                                      Pulse Train Generation */</span></div><div class="line"><a name="l00550"></a><span class="lineno">  550</span>&#160;</div><div class="line"><a name="l00551"></a><span class="lineno">  551</span>&#160;<span class="preprocessor">#define MXC_CFG_PT_INSTANCES                  (16)</span></div><div class="line"><a name="l00552"></a><span class="lineno">  552</span>&#160;</div><div class="line"><a name="l00553"></a><span class="lineno">  553</span>&#160;<span class="preprocessor">#define MXC_BASE_PTG_BUS0                     ((uint32_t)0x4003C000UL)</span></div><div class="line"><a name="l00554"></a><span class="lineno">  554</span>&#160;<span class="preprocessor">#define MXC_PTG_BUS0                          ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0)</span></div><div class="line"><a name="l00555"></a><span class="lineno">  555</span>&#160;<span class="preprocessor">#define MXC_BASE_PT0_BUS0                     ((uint32_t)0x4003C020UL)</span></div><div class="line"><a name="l00556"></a><span class="lineno">  556</span>&#160;<span class="preprocessor">#define MXC_PT0_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0)</span></div><div class="line"><a name="l00557"></a><span class="lineno">  557</span>&#160;<span class="preprocessor">#define MXC_BASE_PT1_BUS0                     ((uint32_t)0x4003C040UL)</span></div><div class="line"><a name="l00558"></a><span class="lineno">  558</span>&#160;<span class="preprocessor">#define MXC_PT1_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0)</span></div><div class="line"><a name="l00559"></a><span class="lineno">  559</span>&#160;<span class="preprocessor">#define MXC_BASE_PT2_BUS0                     ((uint32_t)0x4003C060UL)</span></div><div class="line"><a name="l00560"></a><span class="lineno">  560</span>&#160;<span class="preprocessor">#define MXC_PT2_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0)</span></div><div class="line"><a name="l00561"></a><span class="lineno">  561</span>&#160;<span class="preprocessor">#define MXC_BASE_PT3_BUS0                     ((uint32_t)0x4003C080UL)</span></div><div class="line"><a name="l00562"></a><span class="lineno">  562</span>&#160;<span class="preprocessor">#define MXC_PT3_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0)</span></div><div class="line"><a name="l00563"></a><span class="lineno">  563</span>&#160;<span class="preprocessor">#define MXC_BASE_PT4_BUS0                     ((uint32_t)0x4003C0A0UL)</span></div><div class="line"><a name="l00564"></a><span class="lineno">  564</span>&#160;<span class="preprocessor">#define MXC_PT4_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0)</span></div><div class="line"><a name="l00565"></a><span class="lineno">  565</span>&#160;<span class="preprocessor">#define MXC_BASE_PT5_BUS0                     ((uint32_t)0x4003C0C0UL)</span></div><div class="line"><a name="l00566"></a><span class="lineno">  566</span>&#160;<span class="preprocessor">#define MXC_PT5_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0)</span></div><div class="line"><a name="l00567"></a><span class="lineno">  567</span>&#160;<span class="preprocessor">#define MXC_BASE_PT6_BUS0                     ((uint32_t)0x4003C0E0UL)</span></div><div class="line"><a name="l00568"></a><span class="lineno">  568</span>&#160;<span class="preprocessor">#define MXC_PT6_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0)</span></div><div class="line"><a name="l00569"></a><span class="lineno">  569</span>&#160;<span class="preprocessor">#define MXC_BASE_PT7_BUS0                     ((uint32_t)0x4003C100UL)</span></div><div class="line"><a name="l00570"></a><span class="lineno">  570</span>&#160;<span class="preprocessor">#define MXC_PT7_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0)</span></div><div class="line"><a name="l00571"></a><span class="lineno">  571</span>&#160;<span class="preprocessor">#define MXC_BASE_PT8_BUS0                     ((uint32_t)0x4003C120UL)</span></div><div class="line"><a name="l00572"></a><span class="lineno">  572</span>&#160;<span class="preprocessor">#define MXC_PT8_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0)</span></div><div class="line"><a name="l00573"></a><span class="lineno">  573</span>&#160;<span class="preprocessor">#define MXC_BASE_PT9_BUS0                     ((uint32_t)0x4003C140UL)</span></div><div class="line"><a name="l00574"></a><span class="lineno">  574</span>&#160;<span class="preprocessor">#define MXC_PT9_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0)</span></div><div class="line"><a name="l00575"></a><span class="lineno">  575</span>&#160;<span class="preprocessor">#define MXC_BASE_PT10_BUS0                    ((uint32_t)0x4003C160UL)</span></div><div class="line"><a name="l00576"></a><span class="lineno">  576</span>&#160;<span class="preprocessor">#define MXC_PT10_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0)</span></div><div class="line"><a name="l00577"></a><span class="lineno">  577</span>&#160;<span class="preprocessor">#define MXC_BASE_PT11_BUS0                    ((uint32_t)0x4003C180UL)</span></div><div class="line"><a name="l00578"></a><span class="lineno">  578</span>&#160;<span class="preprocessor">#define MXC_PT11_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0)</span></div><div class="line"><a name="l00579"></a><span class="lineno">  579</span>&#160;<span class="preprocessor">#define MXC_BASE_PT12_BUS0                    ((uint32_t)0x4003C1A0UL)</span></div><div class="line"><a name="l00580"></a><span class="lineno">  580</span>&#160;<span class="preprocessor">#define MXC_PT12_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0)</span></div><div class="line"><a name="l00581"></a><span class="lineno">  581</span>&#160;<span class="preprocessor">#define MXC_BASE_PT13_BUS0                    ((uint32_t)0x4003C1C0UL)</span></div><div class="line"><a name="l00582"></a><span class="lineno">  582</span>&#160;<span class="preprocessor">#define MXC_PT13_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0)</span></div><div class="line"><a name="l00583"></a><span class="lineno">  583</span>&#160;<span class="preprocessor">#define MXC_BASE_PT14_BUS0                    ((uint32_t)0x4003C1E0UL)</span></div><div class="line"><a name="l00584"></a><span class="lineno">  584</span>&#160;<span class="preprocessor">#define MXC_PT14_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0)</span></div><div class="line"><a name="l00585"></a><span class="lineno">  585</span>&#160;<span class="preprocessor">#define MXC_BASE_PT15_BUS0                    ((uint32_t)0x4003C200UL)</span></div><div class="line"><a name="l00586"></a><span class="lineno">  586</span>&#160;<span class="preprocessor">#define MXC_PT15_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0)</span></div><div class="line"><a name="l00587"></a><span class="lineno">  587</span>&#160;</div><div class="line"><a name="l00588"></a><span class="lineno">  588</span>&#160;</div><div class="line"><a name="l00589"></a><span class="lineno">  589</span>&#160;<span class="preprocessor">#define MXC_BASE_PTG_BUS1                     ((uint32_t)0x4013C000UL)</span></div><div class="line"><a name="l00590"></a><span class="lineno">  590</span>&#160;<span class="preprocessor">#define MXC_PTG_BUS1                          ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1)</span></div><div class="line"><a name="l00591"></a><span class="lineno">  591</span>&#160;<span class="preprocessor">#define MXC_BASE_PT0_BUS1                     ((uint32_t)0x4013C020UL)</span></div><div class="line"><a name="l00592"></a><span class="lineno">  592</span>&#160;<span class="preprocessor">#define MXC_PT0_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1)</span></div><div class="line"><a name="l00593"></a><span class="lineno">  593</span>&#160;<span class="preprocessor">#define MXC_BASE_PT1_BUS1                     ((uint32_t)0x4013C040UL)</span></div><div class="line"><a name="l00594"></a><span class="lineno">  594</span>&#160;<span class="preprocessor">#define MXC_PT1_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1)</span></div><div class="line"><a name="l00595"></a><span class="lineno">  595</span>&#160;<span class="preprocessor">#define MXC_BASE_PT2_BUS1                     ((uint32_t)0x4013C060UL)</span></div><div class="line"><a name="l00596"></a><span class="lineno">  596</span>&#160;<span class="preprocessor">#define MXC_PT2_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1)</span></div><div class="line"><a name="l00597"></a><span class="lineno">  597</span>&#160;<span class="preprocessor">#define MXC_BASE_PT3_BUS1                     ((uint32_t)0x4013C080UL)</span></div><div class="line"><a name="l00598"></a><span class="lineno">  598</span>&#160;<span class="preprocessor">#define MXC_PT3_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1)</span></div><div class="line"><a name="l00599"></a><span class="lineno">  599</span>&#160;<span class="preprocessor">#define MXC_BASE_PT4_BUS1                     ((uint32_t)0x4013C0A0UL)</span></div><div class="line"><a name="l00600"></a><span class="lineno">  600</span>&#160;<span class="preprocessor">#define MXC_PT4_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1)</span></div><div class="line"><a name="l00601"></a><span class="lineno">  601</span>&#160;<span class="preprocessor">#define MXC_BASE_PT5_BUS1                     ((uint32_t)0x4013C0C0UL)</span></div><div class="line"><a name="l00602"></a><span class="lineno">  602</span>&#160;<span class="preprocessor">#define MXC_PT5_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1)</span></div><div class="line"><a name="l00603"></a><span class="lineno">  603</span>&#160;<span class="preprocessor">#define MXC_BASE_PT6_BUS1                     ((uint32_t)0x4013C0E0UL)</span></div><div class="line"><a name="l00604"></a><span class="lineno">  604</span>&#160;<span class="preprocessor">#define MXC_PT6_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1)</span></div><div class="line"><a name="l00605"></a><span class="lineno">  605</span>&#160;<span class="preprocessor">#define MXC_BASE_PT7_BUS1                     ((uint32_t)0x4013C100UL)</span></div><div class="line"><a name="l00606"></a><span class="lineno">  606</span>&#160;<span class="preprocessor">#define MXC_PT7_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1)</span></div><div class="line"><a name="l00607"></a><span class="lineno">  607</span>&#160;<span class="preprocessor">#define MXC_BASE_PT8_BUS1                     ((uint32_t)0x4013C120UL)</span></div><div class="line"><a name="l00608"></a><span class="lineno">  608</span>&#160;<span class="preprocessor">#define MXC_PT8_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1)</span></div><div class="line"><a name="l00609"></a><span class="lineno">  609</span>&#160;<span class="preprocessor">#define MXC_BASE_PT9_BUS1                     ((uint32_t)0x4013C140UL)</span></div><div class="line"><a name="l00610"></a><span class="lineno">  610</span>&#160;<span class="preprocessor">#define MXC_PT9_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1)</span></div><div class="line"><a name="l00611"></a><span class="lineno">  611</span>&#160;<span class="preprocessor">#define MXC_BASE_PT10_BUS1                    ((uint32_t)0x4013C160UL)</span></div><div class="line"><a name="l00612"></a><span class="lineno">  612</span>&#160;<span class="preprocessor">#define MXC_PT10_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1)</span></div><div class="line"><a name="l00613"></a><span class="lineno">  613</span>&#160;<span class="preprocessor">#define MXC_BASE_PT11_BUS1                    ((uint32_t)0x4013C180UL)</span></div><div class="line"><a name="l00614"></a><span class="lineno">  614</span>&#160;<span class="preprocessor">#define MXC_PT11_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1)</span></div><div class="line"><a name="l00615"></a><span class="lineno">  615</span>&#160;<span class="preprocessor">#define MXC_BASE_PT12_BUS1                    ((uint32_t)0x4013C1A0UL)</span></div><div class="line"><a name="l00616"></a><span class="lineno">  616</span>&#160;<span class="preprocessor">#define MXC_PT12_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1)</span></div><div class="line"><a name="l00617"></a><span class="lineno">  617</span>&#160;<span class="preprocessor">#define MXC_BASE_PT13_BUS1                    ((uint32_t)0x4013C1C0UL)</span></div><div class="line"><a name="l00618"></a><span class="lineno">  618</span>&#160;<span class="preprocessor">#define MXC_PT13_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1)</span></div><div class="line"><a name="l00619"></a><span class="lineno">  619</span>&#160;<span class="preprocessor">#define MXC_BASE_PT14_BUS1                    ((uint32_t)0x4013C1E0UL)</span></div><div class="line"><a name="l00620"></a><span class="lineno">  620</span>&#160;<span class="preprocessor">#define MXC_PT14_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1)</span></div><div class="line"><a name="l00621"></a><span class="lineno">  621</span>&#160;<span class="preprocessor">#define MXC_BASE_PT15_BUS1                    ((uint32_t)0x4013C200UL)</span></div><div class="line"><a name="l00622"></a><span class="lineno">  622</span>&#160;<span class="preprocessor">#define MXC_PT15_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1)</span></div><div class="line"><a name="l00623"></a><span class="lineno">  623</span>&#160;</div><div class="line"><a name="l00624"></a><span class="lineno">  624</span>&#160;<span class="preprocessor">#define MXC_PT_GET_BASE(i)               ((i) == 0x0  ? MXC_BASE_PT0_BUS0  :   \</span></div><div class="line"><a name="l00625"></a><span class="lineno">  625</span>&#160;<span class="preprocessor">                                          (i) == 0x1  ? MXC_BASE_PT1_BUS0  :           \</span></div><div class="line"><a name="l00626"></a><span class="lineno">  626</span>&#160;<span class="preprocessor">                                          (i) == 0x2  ? MXC_BASE_PT2_BUS0  :           \</span></div><div class="line"><a name="l00627"></a><span class="lineno">  627</span>&#160;<span class="preprocessor">                                          (i) == 0x3  ? MXC_BASE_PT3_BUS0  :           \</span></div><div class="line"><a name="l00628"></a><span class="lineno">  628</span>&#160;<span class="preprocessor">                                          (i) == 0x4  ? MXC_BASE_PT4_BUS0  :           \</span></div><div class="line"><a name="l00629"></a><span class="lineno">  629</span>&#160;<span class="preprocessor">                                          (i) == 0x5  ? MXC_BASE_PT5_BUS0  :           \</span></div><div class="line"><a name="l00630"></a><span class="lineno">  630</span>&#160;<span class="preprocessor">                                          (i) == 0x6  ? MXC_BASE_PT6_BUS0  :           \</span></div><div class="line"><a name="l00631"></a><span class="lineno">  631</span>&#160;<span class="preprocessor">                                          (i) == 0x7  ? MXC_BASE_PT7_BUS0  :           \</span></div><div class="line"><a name="l00632"></a><span class="lineno">  632</span>&#160;<span class="preprocessor">                                          (i) == 0x8  ? MXC_BASE_PT8_BUS0  :           \</span></div><div class="line"><a name="l00633"></a><span class="lineno">  633</span>&#160;<span class="preprocessor">                                          (i) == 0x9  ? MXC_BASE_PT9_BUS0  :           \</span></div><div class="line"><a name="l00634"></a><span class="lineno">  634</span>&#160;<span class="preprocessor">                                          (i) == 0xA  ? MXC_BASE_PT10_BUS0 :           \</span></div><div class="line"><a name="l00635"></a><span class="lineno">  635</span>&#160;<span class="preprocessor">                                          (i) == 0xB  ? MXC_BASE_PT11_BUS0 :           \</span></div><div class="line"><a name="l00636"></a><span class="lineno">  636</span>&#160;<span class="preprocessor">                                          (i) == 0xC  ? MXC_BASE_PT12_BUS0 :           \</span></div><div class="line"><a name="l00637"></a><span class="lineno">  637</span>&#160;<span class="preprocessor">                                          (i) == 0xD  ? MXC_BASE_PT13_BUS0 :           \</span></div><div class="line"><a name="l00638"></a><span class="lineno">  638</span>&#160;<span class="preprocessor">                                          (i) == 0xE  ? MXC_BASE_PT14_BUS0 :           \</span></div><div class="line"><a name="l00639"></a><span class="lineno">  639</span>&#160;<span class="preprocessor">                                          (i) == 0xF  ? MXC_BASE_PT15_BUS0 :           \</span></div><div class="line"><a name="l00640"></a><span class="lineno">  640</span>&#160;<span class="preprocessor">                                          (i) == 0x8000  ? MXC_BASE_PT0_BUS1  :      \</span></div><div class="line"><a name="l00641"></a><span class="lineno">  641</span>&#160;<span class="preprocessor">                                          (i) == 0x8001  ? MXC_BASE_PT1_BUS1  :      \</span></div><div class="line"><a name="l00642"></a><span class="lineno">  642</span>&#160;<span class="preprocessor">                                          (i) == 0x8002  ? MXC_BASE_PT2_BUS1  :      \</span></div><div class="line"><a name="l00643"></a><span class="lineno">  643</span>&#160;<span class="preprocessor">                                          (i) == 0x8003  ? MXC_BASE_PT3_BUS1  :      \</span></div><div class="line"><a name="l00644"></a><span class="lineno">  644</span>&#160;<span class="preprocessor">                                          (i) == 0x8004  ? MXC_BASE_PT4_BUS1  :      \</span></div><div class="line"><a name="l00645"></a><span class="lineno">  645</span>&#160;<span class="preprocessor">                                          (i) == 0x8005  ? MXC_BASE_PT5_BUS1  :      \</span></div><div class="line"><a name="l00646"></a><span class="lineno">  646</span>&#160;<span class="preprocessor">                                          (i) == 0x8006  ? MXC_BASE_PT6_BUS1  :      \</span></div><div class="line"><a name="l00647"></a><span class="lineno">  647</span>&#160;<span class="preprocessor">                                          (i) == 0x8007  ? MXC_BASE_PT7_BUS1  :      \</span></div><div class="line"><a name="l00648"></a><span class="lineno">  648</span>&#160;<span class="preprocessor">                                          (i) == 0x8008  ? MXC_BASE_PT8_BUS1  :      \</span></div><div class="line"><a name="l00649"></a><span class="lineno">  649</span>&#160;<span class="preprocessor">                                          (i) == 0x8009  ? MXC_BASE_PT9_BUS1  :      \</span></div><div class="line"><a name="l00650"></a><span class="lineno">  650</span>&#160;<span class="preprocessor">                                          (i) == 0x800A ? MXC_BASE_PT10_BUS1 :       \</span></div><div class="line"><a name="l00651"></a><span class="lineno">  651</span>&#160;<span class="preprocessor">                                          (i) == 0x800B ? MXC_BASE_PT11_BUS1 :       \</span></div><div class="line"><a name="l00652"></a><span class="lineno">  652</span>&#160;<span class="preprocessor">                                          (i) == 0x800C ? MXC_BASE_PT12_BUS1 :       \</span></div><div class="line"><a name="l00653"></a><span class="lineno">  653</span>&#160;<span class="preprocessor">                                          (i) == 0x800D ? MXC_BASE_PT13_BUS1 :       \</span></div><div class="line"><a name="l00654"></a><span class="lineno">  654</span>&#160;<span class="preprocessor">                                          (i) == 0x800E ? MXC_BASE_PT14_BUS1 :       \</span></div><div class="line"><a name="l00655"></a><span class="lineno">  655</span>&#160;<span class="preprocessor">                                          (i) == 0x800F ? MXC_BASE_PT15_BUS1 : 0)</span></div><div class="line"><a name="l00656"></a><span class="lineno">  656</span>&#160;</div><div class="line"><a name="l00657"></a><span class="lineno">  657</span>&#160;<span class="preprocessor">#define MXC_PT_GET_PT(i)                 ((i) == 0x0  ? MXC_PT0_BUS0  :    \</span></div><div class="line"><a name="l00658"></a><span class="lineno">  658</span>&#160;<span class="preprocessor">                                          (i) == 0x1  ? MXC_PT1_BUS0  :                \</span></div><div class="line"><a name="l00659"></a><span class="lineno">  659</span>&#160;<span class="preprocessor">                                          (i) == 0x2  ? MXC_PT2_BUS0  :                \</span></div><div class="line"><a name="l00660"></a><span class="lineno">  660</span>&#160;<span class="preprocessor">                                          (i) == 0x3  ? MXC_PT3_BUS0  :                \</span></div><div class="line"><a name="l00661"></a><span class="lineno">  661</span>&#160;<span class="preprocessor">                                          (i) == 0x4  ? MXC_PT4_BUS0  :                \</span></div><div class="line"><a name="l00662"></a><span class="lineno">  662</span>&#160;<span class="preprocessor">                                          (i) == 0x5  ? MXC_PT5_BUS0  :                \</span></div><div class="line"><a name="l00663"></a><span class="lineno">  663</span>&#160;<span class="preprocessor">                                          (i) == 0x6  ? MXC_PT6_BUS0  :                \</span></div><div class="line"><a name="l00664"></a><span class="lineno">  664</span>&#160;<span class="preprocessor">                                          (i) == 0x7  ? MXC_PT7_BUS0  :                \</span></div><div class="line"><a name="l00665"></a><span class="lineno">  665</span>&#160;<span class="preprocessor">                                          (i) == 0x8  ? MXC_PT8_BUS0  :                \</span></div><div class="line"><a name="l00666"></a><span class="lineno">  666</span>&#160;<span class="preprocessor">                                          (i) == 0x9  ? MXC_PT9_BUS0  :                \</span></div><div class="line"><a name="l00667"></a><span class="lineno">  667</span>&#160;<span class="preprocessor">                                          (i) == 0xA  ? MXC_PT10_BUS0 :                \</span></div><div class="line"><a name="l00668"></a><span class="lineno">  668</span>&#160;<span class="preprocessor">                                          (i) == 0xB  ? MXC_PT11_BUS0 :                \</span></div><div class="line"><a name="l00669"></a><span class="lineno">  669</span>&#160;<span class="preprocessor">                                          (i) == 0xC  ? MXC_PT12_BUS0 :                \</span></div><div class="line"><a name="l00670"></a><span class="lineno">  670</span>&#160;<span class="preprocessor">                                          (i) == 0xD  ? MXC_PT13_BUS0 :                \</span></div><div class="line"><a name="l00671"></a><span class="lineno">  671</span>&#160;<span class="preprocessor">                                          (i) == 0xE  ? MXC_PT14_BUS0 :                \</span></div><div class="line"><a name="l00672"></a><span class="lineno">  672</span>&#160;<span class="preprocessor">                                          (i) == 0xF  ? MXC_PT15_BUS0 :                \</span></div><div class="line"><a name="l00673"></a><span class="lineno">  673</span>&#160;<span class="preprocessor">                                          (i) == 0x8000  ? MXC_PT0_BUS1  :             \</span></div><div class="line"><a name="l00674"></a><span class="lineno">  674</span>&#160;<span class="preprocessor">                                          (i) == 0x8001  ? MXC_PT1_BUS1  :             \</span></div><div class="line"><a name="l00675"></a><span class="lineno">  675</span>&#160;<span class="preprocessor">                                          (i) == 0x8002  ? MXC_PT2_BUS1  :             \</span></div><div class="line"><a name="l00676"></a><span class="lineno">  676</span>&#160;<span class="preprocessor">                                          (i) == 0x8003  ? MXC_PT3_BUS1  :             \</span></div><div class="line"><a name="l00677"></a><span class="lineno">  677</span>&#160;<span class="preprocessor">                                          (i) == 0x8004  ? MXC_PT4_BUS1  :             \</span></div><div class="line"><a name="l00678"></a><span class="lineno">  678</span>&#160;<span class="preprocessor">                                          (i) == 0x8005  ? MXC_PT5_BUS1  :             \</span></div><div class="line"><a name="l00679"></a><span class="lineno">  679</span>&#160;<span class="preprocessor">                                          (i) == 0x8006  ? MXC_PT6_BUS1  :             \</span></div><div class="line"><a name="l00680"></a><span class="lineno">  680</span>&#160;<span class="preprocessor">                                          (i) == 0x8007  ? MXC_PT7_BUS1  :             \</span></div><div class="line"><a name="l00681"></a><span class="lineno">  681</span>&#160;<span class="preprocessor">                                          (i) == 0x8008  ? MXC_PT8_BUS1  :             \</span></div><div class="line"><a name="l00682"></a><span class="lineno">  682</span>&#160;<span class="preprocessor">                                          (i) == 0x8009  ? MXC_PT9_BUS1  :             \</span></div><div class="line"><a name="l00683"></a><span class="lineno">  683</span>&#160;<span class="preprocessor">                                          (i) == 0x800A  ? MXC_PT10_BUS1 :             \</span></div><div class="line"><a name="l00684"></a><span class="lineno">  684</span>&#160;<span class="preprocessor">                                          (i) == 0x800B  ? MXC_PT11_BUS1 :             \</span></div><div class="line"><a name="l00685"></a><span class="lineno">  685</span>&#160;<span class="preprocessor">                                          (i) == 0x800C  ? MXC_PT12_BUS1 :             \</span></div><div class="line"><a name="l00686"></a><span class="lineno">  686</span>&#160;<span class="preprocessor">                                          (i) == 0x800D  ? MXC_PT13_BUS1 :             \</span></div><div class="line"><a name="l00687"></a><span class="lineno">  687</span>&#160;<span class="preprocessor">                                          (i) == 0x800E  ? MXC_PT14_BUS1 :             \</span></div><div class="line"><a name="l00688"></a><span class="lineno">  688</span>&#160;<span class="preprocessor">                                          (i) == 0x800F  ? MXC_PT15_BUS1 : 0)</span></div><div class="line"><a name="l00689"></a><span class="lineno">  689</span>&#160;</div><div class="line"><a name="l00690"></a><span class="lineno">  690</span>&#160;<span class="preprocessor">#define MXC_PT_GET_IDX(p)                ((p) == MXC_PT0_BUS0  ? 0x0     :                \</span></div><div class="line"><a name="l00691"></a><span class="lineno">  691</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT1_BUS0  ? 0x1     :                \</span></div><div class="line"><a name="l00692"></a><span class="lineno">  692</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT2_BUS0  ? 0x2     :                \</span></div><div class="line"><a name="l00693"></a><span class="lineno">  693</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT3_BUS0  ? 0x3     :                \</span></div><div class="line"><a name="l00694"></a><span class="lineno">  694</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT4_BUS0  ? 0x4     :                \</span></div><div class="line"><a name="l00695"></a><span class="lineno">  695</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT5_BUS0  ? 0x5     :                \</span></div><div class="line"><a name="l00696"></a><span class="lineno">  696</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT6_BUS0  ? 0x6     :                \</span></div><div class="line"><a name="l00697"></a><span class="lineno">  697</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT7_BUS0  ? 0x7     :                \</span></div><div class="line"><a name="l00698"></a><span class="lineno">  698</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT8_BUS0  ? 0x8     :                \</span></div><div class="line"><a name="l00699"></a><span class="lineno">  699</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT9_BUS0  ? 0x9     :                \</span></div><div class="line"><a name="l00700"></a><span class="lineno">  700</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT10_BUS0 ? 0xA     :                \</span></div><div class="line"><a name="l00701"></a><span class="lineno">  701</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT11_BUS0 ? 0xB     :                \</span></div><div class="line"><a name="l00702"></a><span class="lineno">  702</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT12_BUS0 ? 0xC     :                \</span></div><div class="line"><a name="l00703"></a><span class="lineno">  703</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT13_BUS0 ? 0xD     :                \</span></div><div class="line"><a name="l00704"></a><span class="lineno">  704</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT14_BUS0 ? 0xE     :                \</span></div><div class="line"><a name="l00705"></a><span class="lineno">  705</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT15_BUS0 ? 0xF     :                \</span></div><div class="line"><a name="l00706"></a><span class="lineno">  706</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT0_BUS1  ? 0x8000  :                \</span></div><div class="line"><a name="l00707"></a><span class="lineno">  707</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT1_BUS1  ? 0x8001  :                \</span></div><div class="line"><a name="l00708"></a><span class="lineno">  708</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT2_BUS1  ? 0x8002  :                \</span></div><div class="line"><a name="l00709"></a><span class="lineno">  709</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT3_BUS1  ? 0x8003  :                \</span></div><div class="line"><a name="l00710"></a><span class="lineno">  710</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT4_BUS1  ? 0x8004  :                \</span></div><div class="line"><a name="l00711"></a><span class="lineno">  711</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT5_BUS1  ? 0x8005  :                \</span></div><div class="line"><a name="l00712"></a><span class="lineno">  712</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT6_BUS1  ? 0x8006  :                \</span></div><div class="line"><a name="l00713"></a><span class="lineno">  713</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT7_BUS1  ? 0x8007  :                \</span></div><div class="line"><a name="l00714"></a><span class="lineno">  714</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT8_BUS1  ? 0x8008  :                \</span></div><div class="line"><a name="l00715"></a><span class="lineno">  715</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT9_BUS1  ? 0x8009  :                \</span></div><div class="line"><a name="l00716"></a><span class="lineno">  716</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT10_BUS1 ? 0x800A  :                \</span></div><div class="line"><a name="l00717"></a><span class="lineno">  717</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT11_BUS1 ? 0x800B  :                \</span></div><div class="line"><a name="l00718"></a><span class="lineno">  718</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT12_BUS1 ? 0x800C  :                \</span></div><div class="line"><a name="l00719"></a><span class="lineno">  719</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT13_BUS1 ? 0x800D  :                \</span></div><div class="line"><a name="l00720"></a><span class="lineno">  720</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT14_BUS1 ? 0x800E  :                \</span></div><div class="line"><a name="l00721"></a><span class="lineno">  721</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT15_BUS1 ? 0x800F  : -1)</span></div><div class="line"><a name="l00722"></a><span class="lineno">  722</span>&#160;</div><div class="line"><a name="l00723"></a><span class="lineno">  723</span>&#160;<span class="preprocessor">#define MXC_PT_GET_BUS(i)                (((i) &amp; 0x00100000UL)&gt;&gt;20)</span></div><div class="line"><a name="l00724"></a><span class="lineno">  724</span>&#160;</div><div class="line"><a name="l00725"></a><span class="lineno">  725</span>&#160;<span class="preprocessor">#define MXC_PTG_GET_PTG(i)  (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 :  \</span></div><div class="line"><a name="l00726"></a><span class="lineno">  726</span>&#160;<span class="preprocessor">                             MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0)</span></div><div class="line"><a name="l00727"></a><span class="lineno">  727</span>&#160;</div><div class="line"><a name="l00728"></a><span class="lineno">  728</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00729"></a><span class="lineno">  729</span>&#160;<span class="comment">/*                                                            One Wire Master */</span></div><div class="line"><a name="l00730"></a><span class="lineno">  730</span>&#160;<span class="preprocessor">#define MXC_BASE_OWM                    ((uint32_t)0x4003D000UL)</span></div><div class="line"><a name="l00731"></a><span class="lineno">  731</span>&#160;<span class="preprocessor">#define MXC_OWM                         ((mxc_owm_regs_t*)MXC_BASE_OWM)</span></div><div class="line"><a name="l00732"></a><span class="lineno">  732</span>&#160;</div><div class="line"><a name="l00733"></a><span class="lineno">  733</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00734"></a><span class="lineno">  734</span>&#160;<span class="comment">/*                                                                  Semaphore */</span></div><div class="line"><a name="l00735"></a><span class="lineno">  735</span>&#160;<span class="preprocessor">#define MXC_CFG_SEMA_INSTANCES          (8)</span></div><div class="line"><a name="l00736"></a><span class="lineno">  736</span>&#160;</div><div class="line"><a name="l00737"></a><span class="lineno">  737</span>&#160;<span class="preprocessor">#define MXC_BASE_SEMA                   ((uint32_t)0x4003E000UL)</span></div><div class="line"><a name="l00738"></a><span class="lineno">  738</span>&#160;<span class="preprocessor">#define MXC_SEMA                        ((mxc_sema_regs_t*)MXC_BASE_SEMA)</span></div><div class="line"><a name="l00739"></a><span class="lineno">  739</span>&#160;</div><div class="line"><a name="l00740"></a><span class="lineno">  740</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00741"></a><span class="lineno">  741</span>&#160;<span class="comment">/*                                               UART / Serial Port Interface */</span></div><div class="line"><a name="l00742"></a><span class="lineno">  742</span>&#160;</div><div class="line"><a name="l00743"></a><span class="lineno">  743</span>&#160;<span class="preprocessor">#define MXC_UART_INSTANCES              (3)</span></div><div class="line"><a name="l00744"></a><span class="lineno">  744</span>&#160;<span class="preprocessor">#define MXC_UART_FIFO_DEPTH             (32)</span></div><div class="line"><a name="l00745"></a><span class="lineno">  745</span>&#160;</div><div class="line"><a name="l00746"></a><span class="lineno">  746</span>&#160;<span class="preprocessor">#define MXC_BASE_UART0                  ((uint32_t)0x40042000UL)</span></div><div class="line"><a name="l00747"></a><span class="lineno">  747</span>&#160;<span class="preprocessor">#define MXC_UART0                       ((mxc_uart_regs_t*)MXC_BASE_UART0)</span></div><div class="line"><a name="l00748"></a><span class="lineno">  748</span>&#160;<span class="preprocessor">#define MXC_BASE_UART1                  ((uint32_t)0x40043000UL)</span></div><div class="line"><a name="l00749"></a><span class="lineno">  749</span>&#160;<span class="preprocessor">#define MXC_UART1                       ((mxc_uart_regs_t*)MXC_BASE_UART1)</span></div><div class="line"><a name="l00750"></a><span class="lineno">  750</span>&#160;<span class="preprocessor">#define MXC_BASE_UART2                  ((uint32_t)0x40044000UL)</span></div><div class="line"><a name="l00751"></a><span class="lineno">  751</span>&#160;<span class="preprocessor">#define MXC_UART2                       ((mxc_uart_regs_t*)MXC_BASE_UART2)</span></div><div class="line"><a name="l00752"></a><span class="lineno">  752</span>&#160;</div><div class="line"><a name="l00753"></a><span class="lineno">  753</span>&#160;<span class="preprocessor">#define MXC_UART_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? UART0_IRQn :    \</span></div><div class="line"><a name="l00754"></a><span class="lineno">  754</span>&#160;<span class="preprocessor">                                            (i) == 1 ? UART1_IRQn :            \</span></div><div class="line"><a name="l00755"></a><span class="lineno">  755</span>&#160;<span class="preprocessor">                                            (i) == 2 ? UART2_IRQn : 0)</span></div><div class="line"><a name="l00756"></a><span class="lineno">  756</span>&#160;</div><div class="line"><a name="l00757"></a><span class="lineno">  757</span>&#160;<span class="preprocessor">#define MXC_UART_GET_BASE(i)            ((i) == 0 ? MXC_BASE_UART0 :           \</span></div><div class="line"><a name="l00758"></a><span class="lineno">  758</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_UART1 :        \</span></div><div class="line"><a name="l00759"></a><span class="lineno">  759</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_BASE_UART2 : 0)</span></div><div class="line"><a name="l00760"></a><span class="lineno">  760</span>&#160;</div><div class="line"><a name="l00761"></a><span class="lineno">  761</span>&#160;<span class="preprocessor">#define MXC_UART_GET_UART(i)            ((i) == 0 ? MXC_UART0 :                \</span></div><div class="line"><a name="l00762"></a><span class="lineno">  762</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_UART1 :             \</span></div><div class="line"><a name="l00763"></a><span class="lineno">  763</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_UART2 : 0)</span></div><div class="line"><a name="l00764"></a><span class="lineno">  764</span>&#160;</div><div class="line"><a name="l00765"></a><span class="lineno">  765</span>&#160;<span class="preprocessor">#define MXC_UART_GET_IDX(p)             ((p) == MXC_UART0 ? 0 :                \</span></div><div class="line"><a name="l00766"></a><span class="lineno">  766</span>&#160;<span class="preprocessor">                                            (p) == MXC_UART1 ? 1 :             \</span></div><div class="line"><a name="l00767"></a><span class="lineno">  767</span>&#160;<span class="preprocessor">                                            (p) == MXC_UART2 ? 2 : -1)</span></div><div class="line"><a name="l00768"></a><span class="lineno">  768</span>&#160;</div><div class="line"><a name="l00769"></a><span class="lineno">  769</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00770"></a><span class="lineno">  770</span>&#160;<span class="comment">/*                                                                     SPI17Y */</span></div><div class="line"><a name="l00771"></a><span class="lineno">  771</span>&#160;</div><div class="line"><a name="l00772"></a><span class="lineno">  772</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_INSTANCES               (3)</span></div><div class="line"><a name="l00773"></a><span class="lineno">  773</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_SS_INSTANCES            (4)</span></div><div class="line"><a name="l00774"></a><span class="lineno">  774</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_FIFO_DEPTH              (32)</span></div><div class="line"><a name="l00775"></a><span class="lineno">  775</span>&#160;</div><div class="line"><a name="l00776"></a><span class="lineno">  776</span>&#160;<span class="preprocessor">#define MXC_BASE_SPI17Y0                   ((uint32_t)0x400BE000UL)</span></div><div class="line"><a name="l00777"></a><span class="lineno">  777</span>&#160;<span class="preprocessor">#define MXC_SPI17Y0                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y0)</span></div><div class="line"><a name="l00778"></a><span class="lineno">  778</span>&#160;<span class="preprocessor">#define MXC_BASE_SPI17Y1                   ((uint32_t)0x40046000UL)</span></div><div class="line"><a name="l00779"></a><span class="lineno">  779</span>&#160;<span class="preprocessor">#define MXC_SPI17Y1                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y1)</span></div><div class="line"><a name="l00780"></a><span class="lineno">  780</span>&#160;<span class="preprocessor">#define MXC_BASE_SPI17Y2                   ((uint32_t)0x40047000UL)</span></div><div class="line"><a name="l00781"></a><span class="lineno">  781</span>&#160;<span class="preprocessor">#define MXC_SPI17Y2                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y2)</span></div><div class="line"><a name="l00782"></a><span class="lineno">  782</span>&#160;</div><div class="line"><a name="l00783"></a><span class="lineno">  783</span>&#160;</div><div class="line"><a name="l00784"></a><span class="lineno">  784</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_IDX(p)            ((p) == MXC_SPI17Y0 ? 0 :              \</span></div><div class="line"><a name="l00785"></a><span class="lineno">  785</span>&#160;<span class="preprocessor">                                          (p) == MXC_SPI17Y1 ? 1 :              \</span></div><div class="line"><a name="l00786"></a><span class="lineno">  786</span>&#160;<span class="preprocessor">                                          (p) == MXC_SPI17Y2 ? 2 :  -1)</span></div><div class="line"><a name="l00787"></a><span class="lineno">  787</span>&#160;</div><div class="line"><a name="l00788"></a><span class="lineno">  788</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_BASE(i)           ((i) == 0 ? MXC_BASE_SPI17Y0 :         \</span></div><div class="line"><a name="l00789"></a><span class="lineno">  789</span>&#160;<span class="preprocessor">                                          (i) == 1 ? MXC_BASE_SPI17Y1 :         \</span></div><div class="line"><a name="l00790"></a><span class="lineno">  790</span>&#160;<span class="preprocessor">                                          (i) == 2 ? MXC_BASE_SPI17Y2 : 0)</span></div><div class="line"><a name="l00791"></a><span class="lineno">  791</span>&#160;</div><div class="line"><a name="l00792"></a><span class="lineno">  792</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_SPI17Y(i)         ((i) == 0 ? MXC_SPI17Y0 :              \</span></div><div class="line"><a name="l00793"></a><span class="lineno">  793</span>&#160;<span class="preprocessor">                                          (i) == 1 ? MXC_SPI17Y1 :              \</span></div><div class="line"><a name="l00794"></a><span class="lineno">  794</span>&#160;<span class="preprocessor">                                          (i) == 2 ? MXC_SPI17Y2 : 0)</span></div><div class="line"><a name="l00795"></a><span class="lineno">  795</span>&#160;</div><div class="line"><a name="l00796"></a><span class="lineno">  796</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_IRQ(i)           (IRQn_Type)((i) == 0 ? SPI17Y0_IRQn :   \</span></div><div class="line"><a name="l00797"></a><span class="lineno">  797</span>&#160;<span class="preprocessor">                                          (i) == 1 ? SPI17Y1_IRQn :             \</span></div><div class="line"><a name="l00798"></a><span class="lineno">  798</span>&#160;<span class="preprocessor">                                          (i) == 2 ? SPI17Y2_IRQn : 0)</span></div><div class="line"><a name="l00799"></a><span class="lineno">  799</span>&#160;</div><div class="line"><a name="l00800"></a><span class="lineno">  800</span>&#160;</div><div class="line"><a name="l00801"></a><span class="lineno">  801</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00802"></a><span class="lineno">  802</span>&#160;<span class="comment">/*                                                                       TRNG */</span></div><div class="line"><a name="l00803"></a><span class="lineno">  803</span>&#160;<span class="preprocessor">#define MXC_BASE_TRNG                   ((uint32_t)0x4004D000UL)</span></div><div class="line"><a name="l00804"></a><span class="lineno">  804</span>&#160;<span class="preprocessor">#define MXC_TRNG                        ((mxc_trng_regs_t*)MXC_BASE_TRNG)</span></div><div class="line"><a name="l00805"></a><span class="lineno">  805</span>&#160;</div><div class="line"><a name="l00806"></a><span class="lineno">  806</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00807"></a><span class="lineno">  807</span>&#160;<span class="comment">/*                                                                       SDHC */</span></div><div class="line"><a name="l00808"></a><span class="lineno">  808</span>&#160;<span class="preprocessor">#define MXC_BASE_SDHC                   ((uint32_t)0x400B6000UL)</span></div><div class="line"><a name="l00809"></a><span class="lineno">  809</span>&#160;<span class="preprocessor">#define MXC_SDHC                        ((mxc_sdhc_regs_t*)MXC_BASE_SDHC)</span></div><div class="line"><a name="l00810"></a><span class="lineno">  810</span>&#160;</div><div class="line"><a name="l00811"></a><span class="lineno">  811</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00812"></a><span class="lineno">  812</span>&#160;<span class="comment">/*                                                                        RPU */</span></div><div class="line"><a name="l00813"></a><span class="lineno">  813</span>&#160;<span class="preprocessor">#define MXC_BASE_RPU                    ((uint32_t)0x40002300UL)</span></div><div class="line"><a name="l00814"></a><span class="lineno">  814</span>&#160;<span class="preprocessor">#define MXC_RPU                         ((mxc_rpu_regs_t*)MXC_BASE_RPU)</span></div><div class="line"><a name="l00815"></a><span class="lineno">  815</span>&#160;<span class="preprocessor">#define MXC_RPU_NUM_BUS_MASTERS         9</span></div><div class="line"><a name="l00816"></a><span class="lineno">  816</span>&#160;</div><div class="line"><a name="l00817"></a><span class="lineno">  817</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00818"></a><span class="lineno">  818</span>&#160;<span class="comment">/*                                                            Audio Subsystem */</span></div><div class="line"><a name="l00819"></a><span class="lineno">  819</span>&#160;<span class="preprocessor">#define MXC_BASE_AUDIO                    ((uint32_t)0x4004C000UL)</span></div><div class="line"><a name="l00820"></a><span class="lineno">  820</span>&#160;<span class="preprocessor">#define MXC_AUDIO                         ((mxc_audio_regs_t*)MXC_BASE_AUDIO)</span></div><div class="line"><a name="l00821"></a><span class="lineno">  821</span>&#160;</div><div class="line"><a name="l00822"></a><span class="lineno">  822</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00823"></a><span class="lineno">  823</span>&#160;<span class="comment">/*                                                       Bluetooth Low Energy */</span></div><div class="line"><a name="l00824"></a><span class="lineno">  824</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE                    (0x40050000UL)</span></div><div class="line"><a name="l00825"></a><span class="lineno">  825</span>&#160;<span class="preprocessor">#define MXC_BTLE                         ((mxc_btle_regs_t*)MXC_BASE_BTLE)</span></div><div class="line"><a name="l00826"></a><span class="lineno">  826</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_CTRL           (MXC_BASE_BTLE + 0x1000)</span></div><div class="line"><a name="l00827"></a><span class="lineno">  827</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_TX             (MXC_BASE_BTLE + 0x2000)</span></div><div class="line"><a name="l00828"></a><span class="lineno">  828</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_RX             (MXC_BASE_BTLE + 0x3000)</span></div><div class="line"><a name="l00829"></a><span class="lineno">  829</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_EXT_RFFE       (MXC_BASE_BTLE + 0x8000)</span></div><div class="line"><a name="l00830"></a><span class="lineno">  830</span>&#160;</div><div class="line"><a name="l00831"></a><span class="lineno">  831</span>&#160;<span class="comment">// Base address definitions needed for DBB register definitions in BTLE stack</span></div><div class="line"><a name="l00832"></a><span class="lineno">  832</span>&#160;<span class="preprocessor">#define DBB_CTRL_BASE                    MXC_BASE_BTLE_DBB_CTRL</span></div><div class="line"><a name="l00833"></a><span class="lineno">  833</span>&#160;<span class="preprocessor">#define DBB_TX_BASE                      MXC_BASE_BTLE_DBB_TX</span></div><div class="line"><a name="l00834"></a><span class="lineno">  834</span>&#160;<span class="preprocessor">#define DBB_RX_BASE                      MXC_BASE_BTLE_DBB_RX</span></div><div class="line"><a name="l00835"></a><span class="lineno">  835</span>&#160;<span class="preprocessor">#define DBB_EXT_RFFE_BASE                MXC_BASE_BTLE_DBB_EXT_RFFE</span></div><div class="line"><a name="l00836"></a><span class="lineno">  836</span>&#160;</div><div class="line"><a name="l00837"></a><span class="lineno">  837</span>&#160;</div><div class="line"><a name="l00838"></a><span class="lineno">  838</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00839"></a><span class="lineno">  839</span>&#160;<span class="comment">/*                                                               Bit Shifting */</span></div><div class="line"><a name="l00840"></a><span class="lineno">  840</span>&#160;</div><div class="line"><a name="l00841"></a><span class="lineno">  841</span>&#160;<span class="preprocessor">#define MXC_F_BIT_0                     (1 &lt;&lt; 0)</span></div><div class="line"><a name="l00842"></a><span class="lineno">  842</span>&#160;<span class="preprocessor">#define MXC_F_BIT_1                     (1 &lt;&lt; 1)</span></div><div class="line"><a name="l00843"></a><span class="lineno">  843</span>&#160;<span class="preprocessor">#define MXC_F_BIT_2                     (1 &lt;&lt; 2)</span></div><div class="line"><a name="l00844"></a><span class="lineno">  844</span>&#160;<span class="preprocessor">#define MXC_F_BIT_3                     (1 &lt;&lt; 3)</span></div><div class="line"><a name="l00845"></a><span class="lineno">  845</span>&#160;<span class="preprocessor">#define MXC_F_BIT_4                     (1 &lt;&lt; 4)</span></div><div class="line"><a name="l00846"></a><span class="lineno">  846</span>&#160;<span class="preprocessor">#define MXC_F_BIT_5                     (1 &lt;&lt; 5)</span></div><div class="line"><a name="l00847"></a><span class="lineno">  847</span>&#160;<span class="preprocessor">#define MXC_F_BIT_6                     (1 &lt;&lt; 6)</span></div><div class="line"><a name="l00848"></a><span class="lineno">  848</span>&#160;<span class="preprocessor">#define MXC_F_BIT_7                     (1 &lt;&lt; 7)</span></div><div class="line"><a name="l00849"></a><span class="lineno">  849</span>&#160;<span class="preprocessor">#define MXC_F_BIT_8                     (1 &lt;&lt; 8)</span></div><div class="line"><a name="l00850"></a><span class="lineno">  850</span>&#160;<span class="preprocessor">#define MXC_F_BIT_9                     (1 &lt;&lt; 9)</span></div><div class="line"><a name="l00851"></a><span class="lineno">  851</span>&#160;<span class="preprocessor">#define MXC_F_BIT_10                    (1 &lt;&lt; 10)</span></div><div class="line"><a name="l00852"></a><span class="lineno">  852</span>&#160;<span class="preprocessor">#define MXC_F_BIT_11                    (1 &lt;&lt; 11)</span></div><div class="line"><a name="l00853"></a><span class="lineno">  853</span>&#160;<span class="preprocessor">#define MXC_F_BIT_12                    (1 &lt;&lt; 12)</span></div><div class="line"><a name="l00854"></a><span class="lineno">  854</span>&#160;<span class="preprocessor">#define MXC_F_BIT_13                    (1 &lt;&lt; 13)</span></div><div class="line"><a name="l00855"></a><span class="lineno">  855</span>&#160;<span class="preprocessor">#define MXC_F_BIT_14                    (1 &lt;&lt; 14)</span></div><div class="line"><a name="l00856"></a><span class="lineno">  856</span>&#160;<span class="preprocessor">#define MXC_F_BIT_15                    (1 &lt;&lt; 15)</span></div><div class="line"><a name="l00857"></a><span class="lineno">  857</span>&#160;<span class="preprocessor">#define MXC_F_BIT_16                    (1 &lt;&lt; 16)</span></div><div class="line"><a name="l00858"></a><span class="lineno">  858</span>&#160;<span class="preprocessor">#define MXC_F_BIT_17                    (1 &lt;&lt; 17)</span></div><div class="line"><a name="l00859"></a><span class="lineno">  859</span>&#160;<span class="preprocessor">#define MXC_F_BIT_18                    (1 &lt;&lt; 18)</span></div><div class="line"><a name="l00860"></a><span class="lineno">  860</span>&#160;<span class="preprocessor">#define MXC_F_BIT_19                    (1 &lt;&lt; 19)</span></div><div class="line"><a name="l00861"></a><span class="lineno">  861</span>&#160;<span class="preprocessor">#define MXC_F_BIT_20                    (1 &lt;&lt; 20)</span></div><div class="line"><a name="l00862"></a><span class="lineno">  862</span>&#160;<span class="preprocessor">#define MXC_F_BIT_21                    (1 &lt;&lt; 21)</span></div><div class="line"><a name="l00863"></a><span class="lineno">  863</span>&#160;<span class="preprocessor">#define MXC_F_BIT_22                    (1 &lt;&lt; 22)</span></div><div class="line"><a name="l00864"></a><span class="lineno">  864</span>&#160;<span class="preprocessor">#define MXC_F_BIT_23                    (1 &lt;&lt; 23)</span></div><div class="line"><a name="l00865"></a><span class="lineno">  865</span>&#160;<span class="preprocessor">#define MXC_F_BIT_24                    (1 &lt;&lt; 24)</span></div><div class="line"><a name="l00866"></a><span class="lineno">  866</span>&#160;<span class="preprocessor">#define MXC_F_BIT_25                    (1 &lt;&lt; 25)</span></div><div class="line"><a name="l00867"></a><span class="lineno">  867</span>&#160;<span class="preprocessor">#define MXC_F_BIT_26                    (1 &lt;&lt; 26)</span></div><div class="line"><a name="l00868"></a><span class="lineno">  868</span>&#160;<span class="preprocessor">#define MXC_F_BIT_27                    (1 &lt;&lt; 27)</span></div><div class="line"><a name="l00869"></a><span class="lineno">  869</span>&#160;<span class="preprocessor">#define MXC_F_BIT_28                    (1 &lt;&lt; 28)</span></div><div class="line"><a name="l00870"></a><span class="lineno">  870</span>&#160;<span class="preprocessor">#define MXC_F_BIT_29                    (1 &lt;&lt; 29)</span></div><div class="line"><a name="l00871"></a><span class="lineno">  871</span>&#160;<span class="preprocessor">#define MXC_F_BIT_30                    (1 &lt;&lt; 30)</span></div><div class="line"><a name="l00872"></a><span class="lineno">  872</span>&#160;<span class="preprocessor">#define MXC_F_BIT_31                    (1 &lt;&lt; 31)</span></div><div class="line"><a name="l00873"></a><span class="lineno">  873</span>&#160;</div><div class="line"><a name="l00874"></a><span class="lineno">  874</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00875"></a><span class="lineno">  875</span>&#160;<span class="comment">/*                                                               Bit Banding  */</span></div><div class="line"><a name="l00876"></a><span class="lineno">  876</span>&#160;</div><div class="line"><a name="l00877"></a><span class="lineno">  877</span>&#160;</div><div class="line"><a name="l00878"></a><span class="lineno">  878</span>&#160;<span class="preprocessor">#define BITBAND(reg, bit)               ((0xf0000000 &amp; (uint32_t)(reg)) + 0x2000000 + \</span></div><div class="line"><a name="l00879"></a><span class="lineno">  879</span>&#160;<span class="preprocessor">                                            (((uint32_t)(reg) &amp; 0x0fffffff) &lt;&lt; 5) + ((bit) &lt;&lt; 2))</span></div><div class="line"><a name="l00880"></a><span class="lineno">  880</span>&#160;</div><div class="line"><a name="l00881"></a><span class="lineno">  881</span>&#160;<span class="preprocessor">#define MXC_CLRBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 0)</span></div><div class="line"><a name="l00882"></a><span class="lineno">  882</span>&#160;<span class="preprocessor">#define MXC_SETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 1)</span></div><div class="line"><a name="l00883"></a><span class="lineno">  883</span>&#160;<span class="preprocessor">#define MXC_GETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit))</span></div><div class="line"><a name="l00884"></a><span class="lineno">  884</span>&#160;</div><div class="line"><a name="l00885"></a><span class="lineno">  885</span>&#160;<span class="preprocessor">#define MXC_SETFIELD(reg, mask, setting)  (reg = (reg &amp; ~mask) | (setting &amp; mask))</span></div><div class="line"><a name="l00886"></a><span class="lineno">  886</span>&#160;</div><div class="line"><a name="l00887"></a><span class="lineno">  887</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00888"></a><span class="lineno">  888</span>&#160;<span class="comment">/*                                                                  SCB CPACR */</span></div><div class="line"><a name="l00889"></a><span class="lineno">  889</span>&#160;</div><div class="line"><a name="l00890"></a><span class="lineno">  890</span>&#160;<span class="comment">/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */</span></div><div class="line"><a name="l00891"></a><span class="lineno">  891</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP10_Pos              20                              </span></div><div class="line"><a name="l00892"></a><span class="lineno">  892</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP10_Msk              (0x3UL &lt;&lt; SCB_CPACR_CP10_Pos)   </span></div><div class="line"><a name="l00893"></a><span class="lineno">  893</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP11_Pos              22                              </span></div><div class="line"><a name="l00894"></a><span class="lineno">  894</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP11_Msk              (0x3UL &lt;&lt; SCB_CPACR_CP11_Pos)   </span></div><div class="line"><a name="l00896"></a><span class="lineno">  896</span>&#160;<span class="preprocessor">#endif  </span><span class="comment">/* _MAX32665_REGS_H_ */</span><span class="preprocessor"></span></div></div><!-- fragment --></div><!-- contents -->
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * $Date: 2020-01-16 11:18:21 -0600 (Thu, 16 Jan 2020) $</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * $Revision: 50703 $</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> ******************************************************************************/</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;</div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="preprocessor">#ifndef _MAX32665_REGS_H_</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="preprocessor">#define _MAX32665_REGS_H_</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef TARGET_NUM</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define TARGET_NUM  32665</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="preprocessor">#endif </span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;</div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define MXC_NUMCORES 2</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#ifndef  FALSE</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="preprocessor">#define  FALSE      (0)</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#ifndef  TRUE</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="preprocessor">#define  TRUE       (1)</span></div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;</div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#if !defined ( __GNUC__ )</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="preprocessor">    #define CMSIS_VECTAB_VIRTUAL</span></div><div class="line"><a name="l00058"></a><span class="lineno">   58</span>&#160;<span class="preprocessor">    #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE &quot;nvic_table.h&quot;</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="comment">/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#if defined ( __GNUC__ )</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;</div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#define __weak __attribute__((weak))</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#elif defined ( __CC_ARM)</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160; </div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define inline __inline</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#pragma anon_unions</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;</div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;</div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;    NonMaskableInt_IRQn    = -14,</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;    HardFault_IRQn         = -13,</div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;    MemoryManagement_IRQn  = -12,</div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;    BusFault_IRQn          = -11,</div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;    UsageFault_IRQn        = -10,</div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;    SVCall_IRQn            = -5,</div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;    DebugMonitor_IRQn      = -4,</div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;    PendSV_IRQn            = -2,</div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;    SysTick_IRQn           = -1,</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;</div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;    <span class="comment">/* Device-specific interrupt sources (external to ARM core)                 */</span></div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;    <span class="comment">/*                      table entry number                                  */</span></div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;    <span class="comment">/*                      ||||                                                */</span></div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;    <span class="comment">/*                      ||||  table offset address                          */</span></div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;    <span class="comment">/*                      vvvv  vvvvvv                                        */</span></div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;</div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;    PF_IRQn = 0,            <span class="comment">/* 0x10  0x0040  16: Power Fail */</span></div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;    WDT0_IRQn,              <span class="comment">/* 0x11  0x0044  17: Watchdog 0 */</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    USB_IRQn,               <span class="comment">/* 0x12  0x0048  18: USB */</span></div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    RTC_IRQn,               <span class="comment">/* 0x13  0x004C  19: RTC */</span></div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    TRNG_IRQn,              <span class="comment">/* 0x14  0x0050  20: True Random Number Generator */</span></div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;    TMR0_IRQn,              <span class="comment">/* 0x15  0x0054  21: Timer 0 */</span></div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;    TMR1_IRQn,              <span class="comment">/* 0x16  0x0058  22: Timer 1 */</span></div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    TMR2_IRQn,              <span class="comment">/* 0x17  0x005C  23: Timer 2 */</span></div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;    TMR3_IRQn,              <span class="comment">/* 0x18  0x0060  24: Timer 3*/</span></div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;    TMR4_IRQn,              <span class="comment">/* 0x19  0x0064  25: Timer 4*/</span></div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;    TMR5_IRQn,              <span class="comment">/* 0x1A  0x0068  26: Timer 5 */</span></div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    RSV11_IRQn,             <span class="comment">/* 0x1B  0x006C  27: Reserved */</span></div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;    RSV12_IRQn,             <span class="comment">/* 0x1C  0x0070  28: Reserved */</span></div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    I2C0_IRQn,              <span class="comment">/* 0x1D  0x0074  29: I2C0 */</span></div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;    UART0_IRQn,             <span class="comment">/* 0x1E  0x0078  30: UART 0 */</span></div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;    UART1_IRQn,             <span class="comment">/* 0x1F  0x007C  31: UART 1 */</span></div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;    SPI17Y1_IRQn,           <span class="comment">/* 0x20  0x0080  32: SPI17Y1 */</span></div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;    SPI17Y2_IRQn,           <span class="comment">/* 0x21  0x0084  33: SPI17Y2 */</span></div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    RSV18_IRQn,             <span class="comment">/* 0x22  0x0088  34: Reserved */</span></div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;    RSV19_IRQn,             <span class="comment">/* 0x23  0x008C  35: Reserved */</span></div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    ADC_IRQn,               <span class="comment">/* 0x24  0x0090  36: ADC */</span></div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    RSV21_IRQn,             <span class="comment">/* 0x25  0x0094  37: Reserved */</span></div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    RSV22_IRQn,             <span class="comment">/* 0x26  0x0098  38: Reserved */</span></div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;    FLC0_IRQn,               <span class="comment">/* 0x27  0x009C  39: Flash Controller 0 */</span></div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    GPIO0_IRQn,             <span class="comment">/* 0x28  0x00A0  40: GPIO0 */</span></div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;    GPIO1_IRQn,             <span class="comment">/* 0x29  0x00A4  41: GPIO1 */</span></div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    RSV26_IRQn,             <span class="comment">/* 0x2A  0x00A8  42: Reserved */</span></div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;    TPU_IRQn,               <span class="comment">/* 0x2B  0x00AC  43: Crypto */</span></div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    DMA0_IRQn,              <span class="comment">/* 0x2C  0x00B0  44: DMA0 */</span></div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;    DMA1_IRQn,              <span class="comment">/* 0x2D  0x00B4  45: DMA1 */</span></div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    DMA2_IRQn,              <span class="comment">/* 0x2E  0x00B8  46: DMA2 */</span></div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    DMA3_IRQn,              <span class="comment">/* 0x2F  0x00BC  47: DMA3 */</span></div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    RSV32_IRQn,             <span class="comment">/* 0x30  0x00C0  48: Reserved */</span></div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;    RSV33_IRQn,             <span class="comment">/* 0x31  0x00C4  49: Reserved */</span></div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    UART2_IRQn,             <span class="comment">/* 0x32  0x00C8  50: UART 2 */</span></div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;    RSV35_IRQn,             <span class="comment">/* 0x33  0x00CC  51: Reserved */</span></div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    I2C1_IRQn,              <span class="comment">/* 0x34  0x00D0  52: I2C1 */</span></div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    RSV36_IRQn,             <span class="comment">/* 0x35  0x00D4  53: Reserved */</span></div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    SPIXFC_IRQn,             <span class="comment">/* 0x36  0x00D8  54: SPI execute in place */</span></div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;    BTLE_TX_DONE_IRQn,      <span class="comment">/* 0x37  0x00DC  55: BTLE TX Done */</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    BTLE_RX_RCVD_IRQn,      <span class="comment">/* 0x38  0x00E0  56: BTLE RX Received */</span></div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;    BTLE_RX_ENG_DET_IRQn,   <span class="comment">/* 0x39  0x00E4  57: BTLE RX Energy Detected */</span></div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    BTLE_SFD_DET_IRQn,      <span class="comment">/* 0x3A  0x00E8  58: BTLE SFD Detected */</span></div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;    BTLE_SFD_TO_IRQn,       <span class="comment">/* 0x3B  0x00EC  59: BTLE SFD Timeout*/</span></div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;    BTLE_GP_EVENT_IRQn,     <span class="comment">/* 0x3C  0x00F0  60: BTLE Timestamp*/</span></div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;    BTLE_CFO_IRQn,          <span class="comment">/* 0x3D  0x00F4  61: BTLE CFO Done */</span></div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;    BTLE_SIG_DET_IRQn,      <span class="comment">/* 0x3E  0x00F8  62: BTLE Signal Detected */</span></div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;    BTLE_AGC_EVENT_IRQn,    <span class="comment">/* 0x3F  0x00FC  63: BTLE AGC Event */</span></div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;    BTLE_RFFE_SPIM_IRQn,    <span class="comment">/* 0x40  0x0100  64: BTLE RFFE SPIM Done */</span></div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;    BTLE_TX_AES_IRQn,       <span class="comment">/* 0x41  0x0104  65: BTLE TX AES Done */</span></div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;    BTLE_RX_AES_IRQn,       <span class="comment">/* 0x42  0x0108  66: BTLE RX AES Done */</span></div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;    BTLE_INV_APB_ADDR_IRQn, <span class="comment">/* 0x43  0x010C  67: BTLE Invalid APB Address*/</span></div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;    BTLE_IQ_DATA_VALID_IRQn,<span class="comment">/* 0x44  0x0110  68: BTLE IQ Data Valid */</span></div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;    WUT_IRQn,               <span class="comment">/* 0x45  0x0114  69: WUT Wakeup */</span></div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;    GPIOWAKE_IRQn,          <span class="comment">/* 0x46  0x0118  70: GPIO Wakeup */</span></div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;    RSV55_IRQn,             <span class="comment">/* 0x47  0x011C  71: Reserved */</span></div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;    SPI17Y0_IRQn,           <span class="comment">/* 0x48  0x0120  72: SPI17Y0  AHB*/</span></div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;    WDT1_IRQn,              <span class="comment">/* 0x49  0x0124  73: Watchdog 1 */</span></div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;    RSV58_IRQn,             <span class="comment">/* 0x4A  0x0128  74: Reserved */</span></div><div class="line"><a name="l00149"></a><span class="lineno">  149</span>&#160;    PT_IRQn,                <span class="comment">/* 0x4B  0x012C  75: Pulse train */</span></div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;    SDMA_IRQn,              <span class="comment">/* 0x4C  0x0130  76: Smart DMA 0 */</span></div><div class="line"><a name="l00151"></a><span class="lineno">  151</span>&#160;    RSV61_IRQn,             <span class="comment">/* 0x4D  0x0134  77: Reserved */</span></div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;    I2C2_IRQn,              <span class="comment">/* 0x4E  0x0138  78: I2C 2 */</span></div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;    RSV63_IRQn,             <span class="comment">/* 0x4F  0x013C  79: Reserved */</span></div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;    RSV64_IRQn,             <span class="comment">/* 0x50  0x0140  80: Reserved */</span></div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;    RSV65_IRQn,             <span class="comment">/* 0x51  0x0144  81: Reserved */</span></div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;    SDHC_IRQn,              <span class="comment">/* 0x52  0x0148  82: SDIO/SDHC */</span></div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;    OWM_IRQn,               <span class="comment">/* 0x53  0x014C  83: One Wire Master */</span></div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;    DMA4_IRQn,              <span class="comment">/* 0x54  0x0150  84: DMA4 */</span></div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;    DMA5_IRQn,              <span class="comment">/* 0x55  0x0154  85: DMA5 */</span></div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;    DMA6_IRQn,              <span class="comment">/* 0x56  0x0158  86: DMA6 */</span></div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;    DMA7_IRQn,              <span class="comment">/* 0x57  0x015C  87: DMA7 */</span></div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;    DMA8_IRQn,              <span class="comment">/* 0x58  0x0160  88: DMA8 */</span></div><div class="line"><a name="l00163"></a><span class="lineno">  163</span>&#160;    DMA9_IRQn,              <span class="comment">/* 0x59  0x0164  89: DMA9 */</span></div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;    DMA10_IRQn,             <span class="comment">/* 0x5A  0x0168  90: DMA10 */</span></div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;    DMA11_IRQn,             <span class="comment">/* 0x5B  0x016C  91: DMA11 */</span></div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;    DMA12_IRQn,             <span class="comment">/* 0x5C  0x0170  92: DMA12 */</span></div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;    DMA13_IRQn,             <span class="comment">/* 0x5D  0x0174  93: DMA13 */</span></div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;    DMA14_IRQn,             <span class="comment">/* 0x5E  0x0178  94: DMA14 */</span></div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;    DMA15_IRQn,             <span class="comment">/* 0x5F  0x017C  95: DMA15 */</span></div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;    USBDMA_IRQn,            <span class="comment">/* 0x60  0x0180  96: USB DMA */</span></div><div class="line"><a name="l00171"></a><span class="lineno">  171</span>&#160;    WDT2_IRQn,              <span class="comment">/* 0x61  0x0184  97: Watchdog Timer 2 */</span></div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;    ECC_IRQn,               <span class="comment">/* 0x62  0x0188  98: Error Correction */</span></div><div class="line"><a name="l00173"></a><span class="lineno">  173</span>&#160;    DVS_IRQn,               <span class="comment">/* 0x63  0x018C  99: DVS Controller */</span></div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;    SIMO_IRQn,              <span class="comment">/* 0x64 0x0190  100: SIMO Controller */</span></div><div class="line"><a name="l00175"></a><span class="lineno">  175</span>&#160;    SCA_IRQn,               <span class="comment">/* 0x65  0x0194  101: SCA */</span></div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;    AUDIO_IRQn,             <span class="comment">/* 0x66  0x0198  102: Audio subsystem */</span></div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;    FLC1_IRQn,              <span class="comment">/* 0x67  0x019C  103: Flash Control 1 */</span></div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;    UART3_IRQn,             <span class="comment">/* 0x68  0x01A0  104: UART 3 */</span></div><div class="line"><a name="l00179"></a><span class="lineno">  179</span>&#160;    UART4_IRQn,             <span class="comment">/* 0x69  0x01A4  105: UART 4 */</span></div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;    UART5_IRQn,             <span class="comment">/* 0x6A  0x01A8  106: UART 5 */</span></div><div class="line"><a name="l00181"></a><span class="lineno">  181</span>&#160;    CameraIF_IRQn,          <span class="comment">/* 0x6B  0x01AC  107: Camera IF */</span></div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;    I3C_IRQn,               <span class="comment">/* 0x6C  0x01B0  108: I3C */</span></div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;    HTMR0_IRQn,           <span class="comment">/* 0x6D  0x01B4  109: HTimer0 */</span></div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;    HTMR1_IRQn,           <span class="comment">/* 0x6E  0x01B8  110: HTimer1 */</span></div><div class="line"><a name="l00185"></a><span class="lineno">  185</span>&#160;    MXC_IRQ_EXT_COUNT </div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;} IRQn_Type;</div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;</div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;<span class="preprocessor">#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)</span></div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;</div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;<span class="comment">/* ================      Processor and Core Peripheral Section     ================ */</span></div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;</div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;<span class="comment">/* ----------------------  Configuration of the Cortex-M Processor and Core Peripherals  ---------------------- */</span></div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;<span class="preprocessor">#define __CM4_REV                       0x0100          </span></div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;<span class="preprocessor">#define __MPU_PRESENT                   1               </span></div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;<span class="preprocessor">#define __NVIC_PRIO_BITS                3               </span></div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="preprocessor">#define __Vendor_SysTickConfig          0               </span></div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;<span class="preprocessor">#define __FPU_PRESENT                   1               </span></div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;<span class="preprocessor">#ifndef __CROSSWORKS</span></div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;<span class="preprocessor">#include &lt;core_cm4.h&gt;</span>                                   </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;<span class="preprocessor">#else</span></div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;<span class="preprocessor">#include &quot;max32665_sdma.h&quot;</span></div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;</div><div class="line"><a name="l00208"></a><span class="lineno">  208</span>&#160;<span class="preprocessor">#include &quot;system_max32665.h&quot;</span>                            </div><div class="line"><a name="l00211"></a><span class="lineno">  211</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="comment">/* ==================       Device Specific Memory Section       ================== */</span></div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00214"></a><span class="lineno">  214</span>&#160;</div><div class="line"><a name="l00215"></a><span class="lineno">  215</span>&#160;<span class="preprocessor">#define MXC_ROM_MEM_BASE                0x00000000UL</span></div><div class="line"><a name="l00216"></a><span class="lineno">  216</span>&#160;<span class="preprocessor">#define MXC_ROM_MEM_SIZE                0x00020000UL</span></div><div class="line"><a name="l00217"></a><span class="lineno">  217</span>&#160;<span class="preprocessor">#define MXC_XIP_MEM_BASE                0x08000000UL</span></div><div class="line"><a name="l00218"></a><span class="lineno">  218</span>&#160;<span class="preprocessor">#define MXC_XIP_MEM_SIZE                0x08000000UL</span></div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;<span class="preprocessor">#define MXC_FLASH0_MEM_BASE             0x10000000UL</span></div><div class="line"><a name="l00220"></a><span class="lineno">  220</span>&#160;<span class="preprocessor">#define MXC_FLASH1_MEM_BASE             0x10080000UL</span></div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;<span class="preprocessor">#define MXC_FLASH_MEM_BASE              MXC_FLASH0_MEM_BASE</span></div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;<span class="preprocessor">#define MXC_FLASH_PAGE_SIZE             0x00002000UL</span></div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;<span class="preprocessor">#define MXC_FLASH_MEM_SIZE              0x00080000UL</span></div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;<span class="preprocessor">#define MXC_INFO0_MEM_BASE              0x10800000UL</span></div><div class="line"><a name="l00225"></a><span class="lineno">  225</span>&#160;<span class="preprocessor">#define MXC_INFO1_MEM_BASE              0x10804000UL</span></div><div class="line"><a name="l00226"></a><span class="lineno">  226</span>&#160;<span class="preprocessor">#define MXC_INFO_MEM_BASE               MXC_INFO0_MEM_BASE</span></div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;<span class="preprocessor">#define MXC_INFO_MEM_SIZE               0x00004000UL</span></div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;<span class="preprocessor">#define MXC_SRAM_MEM_BASE               0x20000000UL</span></div><div class="line"><a name="l00229"></a><span class="lineno">  229</span>&#160;<span class="preprocessor">#define MXC_SRAM_MEM_SIZE               0x0008C000UL</span></div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="preprocessor">#define MXC_XIP_DATA_MEM_BASE           0x80000000UL</span></div><div class="line"><a name="l00231"></a><span class="lineno">  231</span>&#160;<span class="preprocessor">#define MXC_XIP_DATA_MEM_SIZE           0x20000000UL</span></div><div class="line"><a name="l00232"></a><span class="lineno">  232</span>&#160;</div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00234"></a><span class="lineno">  234</span>&#160;<span class="comment">/* ================       Device Specific Peripheral Section       ================ */</span></div><div class="line"><a name="l00235"></a><span class="lineno">  235</span>&#160;<span class="comment">/* ================================================================================ */</span></div><div class="line"><a name="l00236"></a><span class="lineno">  236</span>&#160;</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;<span class="comment">   Base addresses and configuration settings for all MAX32665 peripheral modules.</span></div><div class="line"><a name="l00239"></a><span class="lineno">  239</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00240"></a><span class="lineno">  240</span>&#160;</div><div class="line"><a name="l00241"></a><span class="lineno">  241</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;<span class="comment">/*                                                             Global control */</span></div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;<span class="preprocessor">#define MXC_BASE_GCR                    ((uint32_t)0x40000000UL)</span></div><div class="line"><a name="l00244"></a><span class="lineno">  244</span>&#160;<span class="preprocessor">#define MXC_GCR                         ((mxc_gcr_regs_t*)MXC_BASE_GCR)</span></div><div class="line"><a name="l00245"></a><span class="lineno">  245</span>&#160;</div><div class="line"><a name="l00246"></a><span class="lineno">  246</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00247"></a><span class="lineno">  247</span>&#160;<span class="comment">/*                                            Non-battery backed SI Registers */</span></div><div class="line"><a name="l00248"></a><span class="lineno">  248</span>&#160;<span class="preprocessor">#define MXC_BASE_SIR                    ((uint32_t)0x40000400UL)</span></div><div class="line"><a name="l00249"></a><span class="lineno">  249</span>&#160;<span class="preprocessor">#define MXC_SIR                         ((mxc_sir_regs_t*)MXC_BASE_SIR)</span></div><div class="line"><a name="l00250"></a><span class="lineno">  250</span>&#160;</div><div class="line"><a name="l00251"></a><span class="lineno">  251</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00252"></a><span class="lineno">  252</span>&#160;<span class="comment">/*                                        Non-battery backed Function Control */</span></div><div class="line"><a name="l00253"></a><span class="lineno">  253</span>&#160;<span class="preprocessor">#define MXC_BASE_FCR                  ((uint32_t)0x40000800UL)</span></div><div class="line"><a name="l00254"></a><span class="lineno">  254</span>&#160;<span class="preprocessor">#define MXC_FCR                       ((mxc_fcr_regs_t*)MXC_BASE_FCR)</span></div><div class="line"><a name="l00255"></a><span class="lineno">  255</span>&#160;</div><div class="line"><a name="l00256"></a><span class="lineno">  256</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00257"></a><span class="lineno">  257</span>&#160;<span class="comment">/*                                                      Trust Protection Unit */</span></div><div class="line"><a name="l00258"></a><span class="lineno">  258</span>&#160;<span class="preprocessor">#define MXC_BASE_TPU                    ((uint32_t)0x40001000UL)</span></div><div class="line"><a name="l00259"></a><span class="lineno">  259</span>&#160;<span class="preprocessor">#define MXC_TPU                         ((mxc_tpu_regs_t*)MXC_BASE_TPU)</span></div><div class="line"><a name="l00260"></a><span class="lineno">  260</span>&#160;</div><div class="line"><a name="l00261"></a><span class="lineno">  261</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00262"></a><span class="lineno">  262</span>&#160;<span class="comment">/*                                                                   Watchdog */</span></div><div class="line"><a name="l00263"></a><span class="lineno">  263</span>&#160;<span class="preprocessor">#define MXC_BASE_WDT0                   ((uint32_t)0x40003000UL)</span></div><div class="line"><a name="l00264"></a><span class="lineno">  264</span>&#160;<span class="preprocessor">#define MXC_WDT0                        ((mxc_wdt_regs_t*)MXC_BASE_WDT0)</span></div><div class="line"><a name="l00265"></a><span class="lineno">  265</span>&#160;<span class="preprocessor">#define MXC_BASE_WDT1                   ((uint32_t)0x40003400UL)</span></div><div class="line"><a name="l00266"></a><span class="lineno">  266</span>&#160;<span class="preprocessor">#define MXC_WDT1                        ((mxc_wdt_regs_t*)MXC_BASE_WDT1)</span></div><div class="line"><a name="l00267"></a><span class="lineno">  267</span>&#160;<span class="preprocessor">#define MXC_BASE_WDT2                   ((uint32_t)0x40003800UL)</span></div><div class="line"><a name="l00268"></a><span class="lineno">  268</span>&#160;<span class="preprocessor">#define MXC_WDT2                        ((mxc_wdt_regs_t*)MXC_BASE_WDT2)</span></div><div class="line"><a name="l00269"></a><span class="lineno">  269</span>&#160;</div><div class="line"><a name="l00270"></a><span class="lineno">  270</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00271"></a><span class="lineno">  271</span>&#160;<span class="comment">/*                                                           Security Monitor */</span></div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;<span class="preprocessor">#define MXC_BASE_SMON                   ((uint32_t)0x40004000UL)</span></div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;<span class="preprocessor">#define MXC_SMON                        ((mxc_smon_regs_t*)MXC_BASE_SMON)</span></div><div class="line"><a name="l00274"></a><span class="lineno">  274</span>&#160;</div><div class="line"><a name="l00275"></a><span class="lineno">  275</span>&#160;</div><div class="line"><a name="l00276"></a><span class="lineno">  276</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00277"></a><span class="lineno">  277</span>&#160;<span class="comment">/*                                                                       SIMO */</span></div><div class="line"><a name="l00278"></a><span class="lineno">  278</span>&#160;<span class="preprocessor">#define MXC_BASE_SIMO                   ((uint32_t)0x40004400UL)</span></div><div class="line"><a name="l00279"></a><span class="lineno">  279</span>&#160;<span class="preprocessor">#define MXC_SIMO                        ((mxc_simo_regs_t*)MXC_BASE_SIMO)</span></div><div class="line"><a name="l00280"></a><span class="lineno">  280</span>&#160;</div><div class="line"><a name="l00281"></a><span class="lineno">  281</span>&#160;</div><div class="line"><a name="l00282"></a><span class="lineno">  282</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00283"></a><span class="lineno">  283</span>&#160;<span class="comment">/*                                                                         DVS*/</span></div><div class="line"><a name="l00284"></a><span class="lineno">  284</span>&#160;<span class="preprocessor">#define MXC_BASE_DVS                   ((uint32_t)0x40004800UL)</span></div><div class="line"><a name="l00285"></a><span class="lineno">  285</span>&#160;<span class="preprocessor">#define MXC_DVS                        ((mxc_dvs_regs_t*)MXC_BASE_DVS)</span></div><div class="line"><a name="l00286"></a><span class="lineno">  286</span>&#160;</div><div class="line"><a name="l00287"></a><span class="lineno">  287</span>&#160;</div><div class="line"><a name="l00288"></a><span class="lineno">  288</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00289"></a><span class="lineno">  289</span>&#160;<span class="comment">/*                                                           Security Monitor */</span></div><div class="line"><a name="l00290"></a><span class="lineno">  290</span>&#160;<span class="preprocessor">#define MXC_BASE_SMON                   ((uint32_t)0x40004000UL)</span></div><div class="line"><a name="l00291"></a><span class="lineno">  291</span>&#160;<span class="preprocessor">#define MXC_SMON                        ((mxc_smon_regs_t*)MXC_BASE_SMON)</span></div><div class="line"><a name="l00292"></a><span class="lineno">  292</span>&#160;</div><div class="line"><a name="l00293"></a><span class="lineno">  293</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00294"></a><span class="lineno">  294</span>&#160;<span class="comment">/*                                                            Real Time Clock */</span></div><div class="line"><a name="l00295"></a><span class="lineno">  295</span>&#160;<span class="preprocessor">#define MXC_BASE_RTC                    ((uint32_t)0x40006000UL)</span></div><div class="line"><a name="l00296"></a><span class="lineno">  296</span>&#160;<span class="preprocessor">#define MXC_RTC                         ((mxc_rtc_regs_t*)MXC_BASE_RTC)</span></div><div class="line"><a name="l00297"></a><span class="lineno">  297</span>&#160;</div><div class="line"><a name="l00298"></a><span class="lineno">  298</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00299"></a><span class="lineno">  299</span>&#160;<span class="comment">/*                                                               Wakeup Timer */</span></div><div class="line"><a name="l00300"></a><span class="lineno">  300</span>&#160;<span class="preprocessor">#define MXC_BASE_WUT                    ((uint32_t)0x40006400UL)</span></div><div class="line"><a name="l00301"></a><span class="lineno">  301</span>&#160;<span class="preprocessor">#define MXC_WUT                         ((mxc_wut_regs_t*)MXC_BASE_WUT)</span></div><div class="line"><a name="l00302"></a><span class="lineno">  302</span>&#160;</div><div class="line"><a name="l00303"></a><span class="lineno">  303</span>&#160;</div><div class="line"><a name="l00304"></a><span class="lineno">  304</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00305"></a><span class="lineno">  305</span>&#160;<span class="comment">/*                                                            Power Sequencer */</span></div><div class="line"><a name="l00306"></a><span class="lineno">  306</span>&#160;<span class="preprocessor">#define MXC_BASE_PWRSEQ                 ((uint32_t)0x40006800UL)</span></div><div class="line"><a name="l00307"></a><span class="lineno">  307</span>&#160;<span class="preprocessor">#define MXC_PWRSEQ                      ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)</span></div><div class="line"><a name="l00308"></a><span class="lineno">  308</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00309"></a><span class="lineno">  309</span>&#160;<span class="comment">/*                                                            Power Sequencer */</span></div><div class="line"><a name="l00310"></a><span class="lineno">  310</span>&#160;<span class="preprocessor">#define MXC_BASE_MCR                    ((uint32_t)0x40006C00UL)</span></div><div class="line"><a name="l00311"></a><span class="lineno">  311</span>&#160;<span class="preprocessor">#define MXC_MCR                         ((mxc_mcr_regs_t*)MXC_BASE_MCR)</span></div><div class="line"><a name="l00312"></a><span class="lineno">  312</span>&#160;</div><div class="line"><a name="l00313"></a><span class="lineno">  313</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00314"></a><span class="lineno">  314</span>&#160;<span class="comment">/*                                                                       GPIO */</span></div><div class="line"><a name="l00315"></a><span class="lineno">  315</span>&#160;<span class="preprocessor">#define MXC_CFG_GPIO_INSTANCES          (2)</span></div><div class="line"><a name="l00316"></a><span class="lineno">  316</span>&#160;<span class="preprocessor">#define MXC_CFG_GPIO_PINS_PORT          (32)</span></div><div class="line"><a name="l00317"></a><span class="lineno">  317</span>&#160;</div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;<span class="preprocessor">#define MXC_BASE_GPIO0                  ((uint32_t)0x40008000UL)</span></div><div class="line"><a name="l00319"></a><span class="lineno">  319</span>&#160;<span class="preprocessor">#define MXC_GPIO0                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)</span></div><div class="line"><a name="l00320"></a><span class="lineno">  320</span>&#160;<span class="preprocessor">#define MXC_BASE_GPIO1                  ((uint32_t)0x40009000UL)</span></div><div class="line"><a name="l00321"></a><span class="lineno">  321</span>&#160;<span class="preprocessor">#define MXC_GPIO1                       ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)</span></div><div class="line"><a name="l00322"></a><span class="lineno">  322</span>&#160;</div><div class="line"><a name="l00323"></a><span class="lineno">  323</span>&#160;<span class="preprocessor">#define MXC_GPIO_GET_IDX(p)             ((p) == MXC_GPIO0 ? 0 :                \</span></div><div class="line"><a name="l00324"></a><span class="lineno">  324</span>&#160;<span class="preprocessor">                                            (p) == MXC_GPIO1 ? 1 : -1)</span></div><div class="line"><a name="l00325"></a><span class="lineno">  325</span>&#160;</div><div class="line"><a name="l00326"></a><span class="lineno">  326</span>&#160;<span class="preprocessor">#define MXC_GPIO_GET_GPIO(i)            ((i) == 0 ? MXC_GPIO0 :                \</span></div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_GPIO1 : 0)</span></div><div class="line"><a name="l00328"></a><span class="lineno">  328</span>&#160;</div><div class="line"><a name="l00329"></a><span class="lineno">  329</span>&#160;<span class="preprocessor">#define MXC_GPIO_GET_IRQ(i)             ((i) == 0 ? GPIO0_IRQn :               \</span></div><div class="line"><a name="l00330"></a><span class="lineno">  330</span>&#160;<span class="preprocessor">                                            (i) == 1 ? GPIO1_IRQn : (IRQn_Type) 0)</span></div><div class="line"><a name="l00331"></a><span class="lineno">  331</span>&#160;</div><div class="line"><a name="l00332"></a><span class="lineno">  332</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00333"></a><span class="lineno">  333</span>&#160;<span class="comment">/*                                                                      Timer */</span></div><div class="line"><a name="l00334"></a><span class="lineno">  334</span>&#160;<span class="preprocessor">#define MXC_CFG_TMR_INSTANCES           (6)</span></div><div class="line"><a name="l00335"></a><span class="lineno">  335</span>&#160;</div><div class="line"><a name="l00336"></a><span class="lineno">  336</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR0                   ((uint32_t)0x40010000UL)</span></div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;<span class="preprocessor">#define MXC_TMR0                        ((mxc_tmr_regs_t*)MXC_BASE_TMR0)</span></div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR1                   ((uint32_t)0x40011000UL)</span></div><div class="line"><a name="l00339"></a><span class="lineno">  339</span>&#160;<span class="preprocessor">#define MXC_TMR1                        ((mxc_tmr_regs_t*)MXC_BASE_TMR1)</span></div><div class="line"><a name="l00340"></a><span class="lineno">  340</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR2                   ((uint32_t)0x40012000UL)</span></div><div class="line"><a name="l00341"></a><span class="lineno">  341</span>&#160;<span class="preprocessor">#define MXC_TMR2                        ((mxc_tmr_regs_t*)MXC_BASE_TMR2)</span></div><div class="line"><a name="l00342"></a><span class="lineno">  342</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR3                   ((uint32_t)0x40013000UL)</span></div><div class="line"><a name="l00343"></a><span class="lineno">  343</span>&#160;<span class="preprocessor">#define MXC_TMR3                        ((mxc_tmr_regs_t*)MXC_BASE_TMR3)</span></div><div class="line"><a name="l00344"></a><span class="lineno">  344</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR4                   ((uint32_t)0x40014000UL)</span></div><div class="line"><a name="l00345"></a><span class="lineno">  345</span>&#160;<span class="preprocessor">#define MXC_TMR4                        ((mxc_tmr_regs_t*)MXC_BASE_TMR4)</span></div><div class="line"><a name="l00346"></a><span class="lineno">  346</span>&#160;<span class="preprocessor">#define MXC_BASE_TMR5                   ((uint32_t)0x40015000UL)</span></div><div class="line"><a name="l00347"></a><span class="lineno">  347</span>&#160;<span class="preprocessor">#define MXC_TMR5                        ((mxc_tmr_regs_t*)MXC_BASE_TMR5)</span></div><div class="line"><a name="l00348"></a><span class="lineno">  348</span>&#160;</div><div class="line"><a name="l00349"></a><span class="lineno">  349</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_IRQ(i)              (IRQn_Type)((i) == 0 ? TMR0_IRQn :     \</span></div><div class="line"><a name="l00350"></a><span class="lineno">  350</span>&#160;<span class="preprocessor">                                            (i) == 1 ? TMR1_IRQn :             \</span></div><div class="line"><a name="l00351"></a><span class="lineno">  351</span>&#160;<span class="preprocessor">                                            (i) == 2 ? TMR2_IRQn :             \</span></div><div class="line"><a name="l00352"></a><span class="lineno">  352</span>&#160;<span class="preprocessor">                                            (i) == 3 ? TMR3_IRQn :             \</span></div><div class="line"><a name="l00353"></a><span class="lineno">  353</span>&#160;<span class="preprocessor">                                            (i) == 4 ? TMR4_IRQn :             \</span></div><div class="line"><a name="l00354"></a><span class="lineno">  354</span>&#160;<span class="preprocessor">                                            (i) == 5 ? TMR5_IRQn : 0)</span></div><div class="line"><a name="l00355"></a><span class="lineno">  355</span>&#160;</div><div class="line"><a name="l00356"></a><span class="lineno">  356</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_BASE(i)             ((i) == 0 ? MXC_BASE_TMR0 :            \</span></div><div class="line"><a name="l00357"></a><span class="lineno">  357</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_TMR1 :         \</span></div><div class="line"><a name="l00358"></a><span class="lineno">  358</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_BASE_TMR2 :         \</span></div><div class="line"><a name="l00359"></a><span class="lineno">  359</span>&#160;<span class="preprocessor">                                            (i) == 3 ? MXC_BASE_TMR3 :         \</span></div><div class="line"><a name="l00360"></a><span class="lineno">  360</span>&#160;<span class="preprocessor">                                            (i) == 4 ? MXC_BASE_TMR4 :         \</span></div><div class="line"><a name="l00361"></a><span class="lineno">  361</span>&#160;<span class="preprocessor">                                            (i) == 5 ? MXC_BASE_TMR5 : 0)</span></div><div class="line"><a name="l00362"></a><span class="lineno">  362</span>&#160;</div><div class="line"><a name="l00363"></a><span class="lineno">  363</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_TMR(i)              ((i) == 0 ? MXC_TMR0 :                 \</span></div><div class="line"><a name="l00364"></a><span class="lineno">  364</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_TMR1 :              \</span></div><div class="line"><a name="l00365"></a><span class="lineno">  365</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_TMR2 :              \</span></div><div class="line"><a name="l00366"></a><span class="lineno">  366</span>&#160;<span class="preprocessor">                                            (i) == 3 ? MXC_TMR3 :              \</span></div><div class="line"><a name="l00367"></a><span class="lineno">  367</span>&#160;<span class="preprocessor">                                            (i) == 4 ? MXC_TMR4 :              \</span></div><div class="line"><a name="l00368"></a><span class="lineno">  368</span>&#160;<span class="preprocessor">                                            (i) == 5 ? MXC_TMR5 : 0)</span></div><div class="line"><a name="l00369"></a><span class="lineno">  369</span>&#160;</div><div class="line"><a name="l00370"></a><span class="lineno">  370</span>&#160;<span class="preprocessor">#define MXC_TMR_GET_IDX(p)              ((p) == MXC_TMR0 ? 0 :                 \</span></div><div class="line"><a name="l00371"></a><span class="lineno">  371</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR1 ? 1 :              \</span></div><div class="line"><a name="l00372"></a><span class="lineno">  372</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR2 ? 2 :              \</span></div><div class="line"><a name="l00373"></a><span class="lineno">  373</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR3 ? 3 :              \</span></div><div class="line"><a name="l00374"></a><span class="lineno">  374</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR4 ? 4 :              \</span></div><div class="line"><a name="l00375"></a><span class="lineno">  375</span>&#160;<span class="preprocessor">                                            (p) == MXC_TMR5 ? 5 : -1)</span></div><div class="line"><a name="l00376"></a><span class="lineno">  376</span>&#160;</div><div class="line"><a name="l00377"></a><span class="lineno">  377</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00378"></a><span class="lineno">  378</span>&#160;<span class="comment">/*                                                           High Speed Timer */</span></div><div class="line"><a name="l00379"></a><span class="lineno">  379</span>&#160;<span class="preprocessor">#define MXC_BASE_HTMR0                    ((uint32_t)0x4001B000UL)</span></div><div class="line"><a name="l00380"></a><span class="lineno">  380</span>&#160;<span class="preprocessor">#define MXC_HTMR0                         ((mxc_htmr_regs_t*)MXC_BASE_HTMR0)</span></div><div class="line"><a name="l00381"></a><span class="lineno">  381</span>&#160;<span class="preprocessor">#define MXC_BASE_HTMR1                    ((uint32_t)0x4001C000UL)</span></div><div class="line"><a name="l00382"></a><span class="lineno">  382</span>&#160;<span class="preprocessor">#define MXC_HTMR1                         ((mxc_htmr_regs_t*)MXC_BASE_HTMR1)</span></div><div class="line"><a name="l00383"></a><span class="lineno">  383</span>&#160;</div><div class="line"><a name="l00384"></a><span class="lineno">  384</span>&#160;</div><div class="line"><a name="l00385"></a><span class="lineno">  385</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00386"></a><span class="lineno">  386</span>&#160;<span class="comment">/*                                                                        I2C */</span></div><div class="line"><a name="l00387"></a><span class="lineno">  387</span>&#160;<span class="preprocessor">#define MXC_I2C_INSTANCES               (3)</span></div><div class="line"><a name="l00388"></a><span class="lineno">  388</span>&#160;</div><div class="line"><a name="l00389"></a><span class="lineno">  389</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C0_BUS0                   ((uint32_t)0x4001D000UL)</span></div><div class="line"><a name="l00390"></a><span class="lineno">  390</span>&#160;<span class="preprocessor">#define MXC_I2C0_BUS0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS0)</span></div><div class="line"><a name="l00391"></a><span class="lineno">  391</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C1_BUS0                   ((uint32_t)0x4001E000UL)</span></div><div class="line"><a name="l00392"></a><span class="lineno">  392</span>&#160;<span class="preprocessor">#define MXC_I2C1_BUS0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS0)</span></div><div class="line"><a name="l00393"></a><span class="lineno">  393</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C2_BUS0                   ((uint32_t)0x4001F000UL)</span></div><div class="line"><a name="l00394"></a><span class="lineno">  394</span>&#160;<span class="preprocessor">#define MXC_I2C2_BUS0                        ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS0)</span></div><div class="line"><a name="l00395"></a><span class="lineno">  395</span>&#160;</div><div class="line"><a name="l00396"></a><span class="lineno">  396</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C0_BUS1                   ((uint32_t)0x4011D000UL)</span></div><div class="line"><a name="l00397"></a><span class="lineno">  397</span>&#160;<span class="preprocessor">#define MXC_I2C0_BUS1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS1)</span></div><div class="line"><a name="l00398"></a><span class="lineno">  398</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C1_BUS1                   ((uint32_t)0x4011E000UL)</span></div><div class="line"><a name="l00399"></a><span class="lineno">  399</span>&#160;<span class="preprocessor">#define MXC_I2C1_BUS1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS1)</span></div><div class="line"><a name="l00400"></a><span class="lineno">  400</span>&#160;<span class="preprocessor">#define MXC_BASE_I2C2_BUS1                   ((uint32_t)0x4011F000UL)</span></div><div class="line"><a name="l00401"></a><span class="lineno">  401</span>&#160;<span class="preprocessor">#define MXC_I2C2_BUS1                        ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS1)</span></div><div class="line"><a name="l00402"></a><span class="lineno">  402</span>&#160;</div><div class="line"><a name="l00403"></a><span class="lineno">  403</span>&#160;</div><div class="line"><a name="l00404"></a><span class="lineno">  404</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_IRQ(i)              (IRQn_Type)((i) == 0x0 ? I2C0_IRQn :     \</span></div><div class="line"><a name="l00405"></a><span class="lineno">  405</span>&#160;<span class="preprocessor">                                            (i) == 0x1 ? I2C1_IRQn :             \</span></div><div class="line"><a name="l00406"></a><span class="lineno">  406</span>&#160;<span class="preprocessor">                                            (i) == 0x2 ? I2C2_IRQn :             \</span></div><div class="line"><a name="l00407"></a><span class="lineno">  407</span>&#160;<span class="preprocessor">                                            (i) == 0x8000 ? I2C0_IRQn :            \</span></div><div class="line"><a name="l00408"></a><span class="lineno">  408</span>&#160;<span class="preprocessor">                                            (i) == 0x8001 ? I2C1_IRQn :            \</span></div><div class="line"><a name="l00409"></a><span class="lineno">  409</span>&#160;<span class="preprocessor">                                            (i) == 0x8002 ? I2C2_IRQn : 0)</span></div><div class="line"><a name="l00410"></a><span class="lineno">  410</span>&#160;</div><div class="line"><a name="l00411"></a><span class="lineno">  411</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_BASE(i)             ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 :            \</span></div><div class="line"><a name="l00412"></a><span class="lineno">  412</span>&#160;<span class="preprocessor">                                            (i) == 0x1 ? MXC_BASE_I2C1_BUS0 :         \</span></div><div class="line"><a name="l00413"></a><span class="lineno">  413</span>&#160;<span class="preprocessor">                                            (i) == 0x2 ? MXC_BASE_I2C2_BUS0 :         \</span></div><div class="line"><a name="l00414"></a><span class="lineno">  414</span>&#160;<span class="preprocessor">                                            (i) == 0x8000 ? MXC_BASE_I2C0_BUS1 :        \</span></div><div class="line"><a name="l00415"></a><span class="lineno">  415</span>&#160;<span class="preprocessor">                                            (i) == 0x8001 ? MXC_BASE_I2C1_BUS1 :        \</span></div><div class="line"><a name="l00416"></a><span class="lineno">  416</span>&#160;<span class="preprocessor">                                            (i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : 0)</span></div><div class="line"><a name="l00417"></a><span class="lineno">  417</span>&#160;</div><div class="line"><a name="l00418"></a><span class="lineno">  418</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_IDX(p)              ((p) == MXC_I2C0_BUS0 ? 0x0 :                 \</span></div><div class="line"><a name="l00419"></a><span class="lineno">  419</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C1_BUS0 ? 0x1 :              \</span></div><div class="line"><a name="l00420"></a><span class="lineno">  420</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C2_BUS0 ? 0x2 :              \</span></div><div class="line"><a name="l00421"></a><span class="lineno">  421</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C0_BUS1 ? 0x8000 :             \</span></div><div class="line"><a name="l00422"></a><span class="lineno">  422</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C1_BUS1 ? 0x8001 :             \</span></div><div class="line"><a name="l00423"></a><span class="lineno">  423</span>&#160;<span class="preprocessor">                                            (p) == MXC_I2C2_BUS1 ? 0x8002 : -1)</span></div><div class="line"><a name="l00424"></a><span class="lineno">  424</span>&#160;</div><div class="line"><a name="l00425"></a><span class="lineno">  425</span>&#160;<span class="preprocessor">#define MXC_I2C_GET_I2C(p)              ((p) == 0x0 ? MXC_I2C0_BUS0 :                 \</span></div><div class="line"><a name="l00426"></a><span class="lineno">  426</span>&#160;<span class="preprocessor">                                            (p) == 0x1 ? MXC_I2C1_BUS0 :              \</span></div><div class="line"><a name="l00427"></a><span class="lineno">  427</span>&#160;<span class="preprocessor">                                            (p) == 0x2 ? MXC_I2C2_BUS0 :              \</span></div><div class="line"><a name="l00428"></a><span class="lineno">  428</span>&#160;<span class="preprocessor">                                            (p) == 0x8000 ? MXC_I2C0_BUS1 :             \</span></div><div class="line"><a name="l00429"></a><span class="lineno">  429</span>&#160;<span class="preprocessor">                                            (p) == 0x8001 ? MXC_I2C1_BUS1 :             \</span></div><div class="line"><a name="l00430"></a><span class="lineno">  430</span>&#160;<span class="preprocessor">                                            (p) == 0x8002? MXC_I2C2_BUS1 : 0)</span></div><div class="line"><a name="l00431"></a><span class="lineno">  431</span>&#160;<span class="preprocessor">#define MXC_I2C_FIFO_DEPTH              (8)</span></div><div class="line"><a name="l00432"></a><span class="lineno">  432</span>&#160;</div><div class="line"><a name="l00433"></a><span class="lineno">  433</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00434"></a><span class="lineno">  434</span>&#160;<span class="comment">/*                                                      SPI Execute in Place  */</span></div><div class="line"><a name="l00435"></a><span class="lineno">  435</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXF                   ((uint32_t)0x40026000UL)</span></div><div class="line"><a name="l00436"></a><span class="lineno">  436</span>&#160;<span class="preprocessor">#define MXC_SPIXF                        ((mxc_spixf_regs_t*)MXC_BASE_SPIXF)</span></div><div class="line"><a name="l00437"></a><span class="lineno">  437</span>&#160;</div><div class="line"><a name="l00438"></a><span class="lineno">  438</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXF_FIFO             ((uint32_t)0x400BC000UL)</span></div><div class="line"><a name="l00439"></a><span class="lineno">  439</span>&#160;<span class="preprocessor">#define MXC_SPIXF_FIFO                  ((mxc_spixf_fifo_regs_t*)MXC_BASE_SPIXF_FIFO)</span></div><div class="line"><a name="l00440"></a><span class="lineno">  440</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00441"></a><span class="lineno">  441</span>&#160;<span class="comment">/*                                                SPI Execute in Place Master */</span></div><div class="line"><a name="l00442"></a><span class="lineno">  442</span>&#160;</div><div class="line"><a name="l00443"></a><span class="lineno">  443</span>&#160;<span class="preprocessor">#define MXC_CFG_SPIXFC_FIFO_DEPTH          (16)</span></div><div class="line"><a name="l00444"></a><span class="lineno">  444</span>&#160;</div><div class="line"><a name="l00445"></a><span class="lineno">  445</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXFC                  ((uint32_t)0x40027000UL)</span></div><div class="line"><a name="l00446"></a><span class="lineno">  446</span>&#160;<span class="preprocessor">#define MXC_SPIXFC                       ((mxc_spixfc_regs_t*)MXC_BASE_SPIXFC)</span></div><div class="line"><a name="l00447"></a><span class="lineno">  447</span>&#160;</div><div class="line"><a name="l00448"></a><span class="lineno">  448</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00449"></a><span class="lineno">  449</span>&#160;<span class="comment">/*                                                                        DMA */</span></div><div class="line"><a name="l00450"></a><span class="lineno">  450</span>&#160;<span class="preprocessor">#define MXC_DMA_CHANNELS                (16)</span></div><div class="line"><a name="l00451"></a><span class="lineno">  451</span>&#160;<span class="preprocessor">#define MXC_DMA_INSTANCES               (2)</span></div><div class="line"><a name="l00452"></a><span class="lineno">  452</span>&#160;</div><div class="line"><a name="l00453"></a><span class="lineno">  453</span>&#160;<span class="preprocessor">#define MXC_BASE_DMA0                    ((uint32_t)0x40028000UL)</span></div><div class="line"><a name="l00454"></a><span class="lineno">  454</span>&#160;<span class="preprocessor">#define MXC_DMA0                         ((mxc_dma_regs_t*)MXC_BASE_DMA0)</span></div><div class="line"><a name="l00455"></a><span class="lineno">  455</span>&#160;<span class="preprocessor">#define MXC_BASE_DMA1                    ((uint32_t)0x40035000UL)</span></div><div class="line"><a name="l00456"></a><span class="lineno">  456</span>&#160;<span class="preprocessor">#define MXC_DMA1                         ((mxc_dma_regs_t*)MXC_BASE_DMA1)</span></div><div class="line"><a name="l00457"></a><span class="lineno">  457</span>&#160;</div><div class="line"><a name="l00458"></a><span class="lineno">  458</span>&#160;<span class="comment">// TODO: remove this when creating drivers to accept two instance of these.</span></div><div class="line"><a name="l00459"></a><span class="lineno">  459</span>&#160;<span class="preprocessor">#define MXC_DMA     MXC_DMA0</span></div><div class="line"><a name="l00460"></a><span class="lineno">  460</span>&#160;</div><div class="line"><a name="l00461"></a><span class="lineno">  461</span>&#160;<span class="preprocessor">#define MXC_DMA_GET_BASE(i)            ((i) == 0 ? MXC_BASE_DMA0 :           \</span></div><div class="line"><a name="l00462"></a><span class="lineno">  462</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_DMA1 : 0)</span></div><div class="line"><a name="l00463"></a><span class="lineno">  463</span>&#160;</div><div class="line"><a name="l00464"></a><span class="lineno">  464</span>&#160;<span class="preprocessor">#define MXC_DMA_GET_DMA(i)            ((i) == 0 ? MXC_DMA0 :                \</span></div><div class="line"><a name="l00465"></a><span class="lineno">  465</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_DMA1 : 0)</span></div><div class="line"><a name="l00466"></a><span class="lineno">  466</span>&#160;</div><div class="line"><a name="l00467"></a><span class="lineno">  467</span>&#160;<span class="preprocessor">#define MXC_DMA_GET_IDX(p)             ((p) == MXC_DMA0 ? 0 :                \</span></div><div class="line"><a name="l00468"></a><span class="lineno">  468</span>&#160;<span class="preprocessor">                                            (p) == MXC_DMA1 ? 1 : -1)</span></div><div class="line"><a name="l00469"></a><span class="lineno">  469</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00470"></a><span class="lineno">  470</span>&#160;<span class="comment">/*                                                                        FLC */</span></div><div class="line"><a name="l00471"></a><span class="lineno">  471</span>&#160;<span class="preprocessor">#define MXC_FLC_INSTANCES               (2)</span></div><div class="line"><a name="l00472"></a><span class="lineno">  472</span>&#160;</div><div class="line"><a name="l00473"></a><span class="lineno">  473</span>&#160;<span class="preprocessor">#define MXC_BASE_FLC0                    ((uint32_t)0x40029000UL)</span></div><div class="line"><a name="l00474"></a><span class="lineno">  474</span>&#160;<span class="preprocessor">#define MXC_FLC0                         ((mxc_flc_regs_t*)MXC_BASE_FLC0)</span></div><div class="line"><a name="l00475"></a><span class="lineno">  475</span>&#160;<span class="preprocessor">#define MXC_BASE_FLC1                    ((uint32_t)0x40029400UL)</span></div><div class="line"><a name="l00476"></a><span class="lineno">  476</span>&#160;<span class="preprocessor">#define MXC_FLC1                         ((mxc_flc_regs_t*)MXC_BASE_FLC1)</span></div><div class="line"><a name="l00477"></a><span class="lineno">  477</span>&#160;</div><div class="line"><a name="l00478"></a><span class="lineno">  478</span>&#160;<span class="comment">// TODO: remove this when creating drivers to accept two instance of these.</span></div><div class="line"><a name="l00479"></a><span class="lineno">  479</span>&#160;<span class="comment">// #define MXC_FLC     MXC_FLC0</span></div><div class="line"><a name="l00480"></a><span class="lineno">  480</span>&#160;</div><div class="line"><a name="l00481"></a><span class="lineno">  481</span>&#160;</div><div class="line"><a name="l00482"></a><span class="lineno">  482</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? FLC0_IRQn :    \</span></div><div class="line"><a name="l00483"></a><span class="lineno">  483</span>&#160;<span class="preprocessor">                                            (i) == 1 ? FLC1_IRQn :0)</span></div><div class="line"><a name="l00484"></a><span class="lineno">  484</span>&#160;</div><div class="line"><a name="l00485"></a><span class="lineno">  485</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_BASE(i)            ((i) == 0 ? MXC_BASE_FLC0 :           \</span></div><div class="line"><a name="l00486"></a><span class="lineno">  486</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_FLC1 : 0)</span></div><div class="line"><a name="l00487"></a><span class="lineno">  487</span>&#160;</div><div class="line"><a name="l00488"></a><span class="lineno">  488</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_FLC(i)            ((i) == 0 ? MXC_FLC0 :                \</span></div><div class="line"><a name="l00489"></a><span class="lineno">  489</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_FLC1 : 0)</span></div><div class="line"><a name="l00490"></a><span class="lineno">  490</span>&#160;</div><div class="line"><a name="l00491"></a><span class="lineno">  491</span>&#160;<span class="preprocessor">#define MXC_FLC_GET_IDX(p)             ((p) == MXC_FLC0 ? 0 :                \</span></div><div class="line"><a name="l00492"></a><span class="lineno">  492</span>&#160;<span class="preprocessor">                                            (p) == MXC_FLC1 ? 1 : -1)</span></div><div class="line"><a name="l00493"></a><span class="lineno">  493</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00494"></a><span class="lineno">  494</span>&#160;<span class="comment">/*                                                          Instruction Cache */</span></div><div class="line"><a name="l00495"></a><span class="lineno">  495</span>&#160;<span class="preprocessor">#define MXC_ICC_INSTANCES               (2)</span></div><div class="line"><a name="l00496"></a><span class="lineno">  496</span>&#160;</div><div class="line"><a name="l00497"></a><span class="lineno">  497</span>&#160;<span class="preprocessor">#define MXC_BASE_ICC0                    ((uint32_t)0x4002A000UL)</span></div><div class="line"><a name="l00498"></a><span class="lineno">  498</span>&#160;<span class="preprocessor">#define MXC_ICC0                         ((mxc_icc_regs_t*)MXC_BASE_ICC0)</span></div><div class="line"><a name="l00499"></a><span class="lineno">  499</span>&#160;<span class="preprocessor">#define MXC_BASE_ICC1                    ((uint32_t)0x4002A800UL)</span></div><div class="line"><a name="l00500"></a><span class="lineno">  500</span>&#160;<span class="preprocessor">#define MXC_ICC1                         ((mxc_icc_regs_t*)MXC_BASE_ICC1)</span></div><div class="line"><a name="l00501"></a><span class="lineno">  501</span>&#160;</div><div class="line"><a name="l00502"></a><span class="lineno">  502</span>&#160;<span class="comment">// TODO: remove this when creating drivers to accept two instance of these.</span></div><div class="line"><a name="l00503"></a><span class="lineno">  503</span>&#160;<span class="preprocessor">#define MXC_ICC     MXC_ICC0</span></div><div class="line"><a name="l00504"></a><span class="lineno">  504</span>&#160;</div><div class="line"><a name="l00505"></a><span class="lineno">  505</span>&#160;</div><div class="line"><a name="l00506"></a><span class="lineno">  506</span>&#160;<span class="preprocessor">#define MXC_ICC_GET_BASE(i)            ((i) == 0 ? MXC_BASE_ICC0 :           \</span></div><div class="line"><a name="l00507"></a><span class="lineno">  507</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_ICC1 : 0)</span></div><div class="line"><a name="l00508"></a><span class="lineno">  508</span>&#160;</div><div class="line"><a name="l00509"></a><span class="lineno">  509</span>&#160;<span class="preprocessor">#define MXC_ICC_GET_ICC(i)            ((i) == 0 ? MXC_ICC0 :                \</span></div><div class="line"><a name="l00510"></a><span class="lineno">  510</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_ICC1 : 0)</span></div><div class="line"><a name="l00511"></a><span class="lineno">  511</span>&#160;</div><div class="line"><a name="l00512"></a><span class="lineno">  512</span>&#160;<span class="preprocessor">#define MXC_ICC_GET_IDX(p)             ((p) == MXC_ICC0 ? 0 :                \</span></div><div class="line"><a name="l00513"></a><span class="lineno">  513</span>&#160;<span class="preprocessor">                                            (p) == MXC_ICC1 ? 1 : -1)</span></div><div class="line"><a name="l00514"></a><span class="lineno">  514</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00515"></a><span class="lineno">  515</span>&#160;<span class="comment">/*                                                      Instruction Cache XIP */</span></div><div class="line"><a name="l00516"></a><span class="lineno">  516</span>&#160;<span class="preprocessor">#define MXC_BASE_SFCC                    ((uint32_t)0x4002F000UL)</span></div><div class="line"><a name="l00517"></a><span class="lineno">  517</span>&#160;<span class="preprocessor">#define MXC_SFCC                         ((mxc_icc_regs_t*)MXC_BASE_SFCC)</span></div><div class="line"><a name="l00518"></a><span class="lineno">  518</span>&#160;</div><div class="line"><a name="l00519"></a><span class="lineno">  519</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00520"></a><span class="lineno">  520</span>&#160;<span class="comment">/*                                                                 Data Cache */</span></div><div class="line"><a name="l00521"></a><span class="lineno">  521</span>&#160;<span class="preprocessor">#define MXC_BASE_SRCC                    ((uint32_t)0x40033000UL)</span></div><div class="line"><a name="l00522"></a><span class="lineno">  522</span>&#160;<span class="preprocessor">#define MXC_SRCC                         ((mxc_srcc_regs_t*)MXC_BASE_SRCC)</span></div><div class="line"><a name="l00523"></a><span class="lineno">  523</span>&#160;</div><div class="line"><a name="l00524"></a><span class="lineno">  524</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00525"></a><span class="lineno">  525</span>&#160;<span class="comment">/*                                                                        ADC */</span></div><div class="line"><a name="l00526"></a><span class="lineno">  526</span>&#160;<span class="preprocessor">#define MXC_BASE_ADC                    ((uint32_t)0x40034000UL)</span></div><div class="line"><a name="l00527"></a><span class="lineno">  527</span>&#160;<span class="preprocessor">#define MXC_ADC                         ((mxc_adc_regs_t*)MXC_BASE_ADC)</span></div><div class="line"><a name="l00528"></a><span class="lineno">  528</span>&#160;<span class="preprocessor">#define MXC_ADC_MAX_CLOCK               8000000 // Maximum ADC clock in Hz</span></div><div class="line"><a name="l00529"></a><span class="lineno">  529</span>&#160;</div><div class="line"><a name="l00530"></a><span class="lineno">  530</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00531"></a><span class="lineno">  531</span>&#160;<span class="comment">/*                                                                        USB */</span></div><div class="line"><a name="l00532"></a><span class="lineno">  532</span>&#160;<span class="preprocessor">#define MXC_BASE_USBHS                  ((uint32_t)0x400B1000UL)</span></div><div class="line"><a name="l00533"></a><span class="lineno">  533</span>&#160;<span class="preprocessor">#define MXC_USBHS                       ((mxc_usbhs_regs_t*)MXC_BASE_USBHS)</span></div><div class="line"><a name="l00534"></a><span class="lineno">  534</span>&#160;<span class="preprocessor">#define MXC_USBHS_NUM_EP                12 </span><span class="comment">/* HW must have at least EP 0 CONTROL + 11 IN/OUT */</span><span class="preprocessor"></span></div><div class="line"><a name="l00535"></a><span class="lineno">  535</span>&#160;<span class="preprocessor">#define MXC_USBHS_NUM_DMA                8 </span><span class="comment">/* HW must have at least this many DMA channels */</span><span class="preprocessor"></span></div><div class="line"><a name="l00536"></a><span class="lineno">  536</span>&#160;<span class="preprocessor">#define MXC_USBHS_MAX_PACKET            512</span></div><div class="line"><a name="l00537"></a><span class="lineno">  537</span>&#160;</div><div class="line"><a name="l00538"></a><span class="lineno">  538</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00539"></a><span class="lineno">  539</span>&#160;<span class="comment">/*                                                                  Smart DMA */</span></div><div class="line"><a name="l00540"></a><span class="lineno">  540</span>&#160;<span class="preprocessor">#define MXC_BASE_SDMA                   ((uint32_t)0x40036000UL)</span></div><div class="line"><a name="l00541"></a><span class="lineno">  541</span>&#160;<span class="preprocessor">#define MXC_SDMA                        ((mxc_sdma_regs_t*)MXC_BASE_SDMA)</span></div><div class="line"><a name="l00542"></a><span class="lineno">  542</span>&#160;</div><div class="line"><a name="l00543"></a><span class="lineno">  543</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00544"></a><span class="lineno">  544</span>&#160;<span class="comment">/*                                                               SPI XIP Data */</span></div><div class="line"><a name="l00545"></a><span class="lineno">  545</span>&#160;<span class="preprocessor">#define MXC_BASE_SPIXR                   ((uint32_t)0x4003A000UL)</span></div><div class="line"><a name="l00546"></a><span class="lineno">  546</span>&#160;<span class="preprocessor">#define MXC_SPIXR                        ((mxc_spixr_regs_t*)MXC_BASE_SPIXR)</span></div><div class="line"><a name="l00547"></a><span class="lineno">  547</span>&#160;</div><div class="line"><a name="l00548"></a><span class="lineno">  548</span>&#160;<span class="comment">/*******************************************************************************/</span></div><div class="line"><a name="l00549"></a><span class="lineno">  549</span>&#160;<span class="comment">/*                                                      Pulse Train Generation */</span></div><div class="line"><a name="l00550"></a><span class="lineno">  550</span>&#160;</div><div class="line"><a name="l00551"></a><span class="lineno">  551</span>&#160;<span class="preprocessor">#define MXC_CFG_PT_INSTANCES                  (16)</span></div><div class="line"><a name="l00552"></a><span class="lineno">  552</span>&#160;</div><div class="line"><a name="l00553"></a><span class="lineno">  553</span>&#160;<span class="preprocessor">#define MXC_BASE_PTG_BUS0                     ((uint32_t)0x4003C000UL)</span></div><div class="line"><a name="l00554"></a><span class="lineno">  554</span>&#160;<span class="preprocessor">#define MXC_PTG_BUS0                          ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0)</span></div><div class="line"><a name="l00555"></a><span class="lineno">  555</span>&#160;<span class="preprocessor">#define MXC_BASE_PT0_BUS0                     ((uint32_t)0x4003C020UL)</span></div><div class="line"><a name="l00556"></a><span class="lineno">  556</span>&#160;<span class="preprocessor">#define MXC_PT0_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0)</span></div><div class="line"><a name="l00557"></a><span class="lineno">  557</span>&#160;<span class="preprocessor">#define MXC_BASE_PT1_BUS0                     ((uint32_t)0x4003C040UL)</span></div><div class="line"><a name="l00558"></a><span class="lineno">  558</span>&#160;<span class="preprocessor">#define MXC_PT1_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0)</span></div><div class="line"><a name="l00559"></a><span class="lineno">  559</span>&#160;<span class="preprocessor">#define MXC_BASE_PT2_BUS0                     ((uint32_t)0x4003C060UL)</span></div><div class="line"><a name="l00560"></a><span class="lineno">  560</span>&#160;<span class="preprocessor">#define MXC_PT2_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0)</span></div><div class="line"><a name="l00561"></a><span class="lineno">  561</span>&#160;<span class="preprocessor">#define MXC_BASE_PT3_BUS0                     ((uint32_t)0x4003C080UL)</span></div><div class="line"><a name="l00562"></a><span class="lineno">  562</span>&#160;<span class="preprocessor">#define MXC_PT3_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0)</span></div><div class="line"><a name="l00563"></a><span class="lineno">  563</span>&#160;<span class="preprocessor">#define MXC_BASE_PT4_BUS0                     ((uint32_t)0x4003C0A0UL)</span></div><div class="line"><a name="l00564"></a><span class="lineno">  564</span>&#160;<span class="preprocessor">#define MXC_PT4_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0)</span></div><div class="line"><a name="l00565"></a><span class="lineno">  565</span>&#160;<span class="preprocessor">#define MXC_BASE_PT5_BUS0                     ((uint32_t)0x4003C0C0UL)</span></div><div class="line"><a name="l00566"></a><span class="lineno">  566</span>&#160;<span class="preprocessor">#define MXC_PT5_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0)</span></div><div class="line"><a name="l00567"></a><span class="lineno">  567</span>&#160;<span class="preprocessor">#define MXC_BASE_PT6_BUS0                     ((uint32_t)0x4003C0E0UL)</span></div><div class="line"><a name="l00568"></a><span class="lineno">  568</span>&#160;<span class="preprocessor">#define MXC_PT6_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0)</span></div><div class="line"><a name="l00569"></a><span class="lineno">  569</span>&#160;<span class="preprocessor">#define MXC_BASE_PT7_BUS0                     ((uint32_t)0x4003C100UL)</span></div><div class="line"><a name="l00570"></a><span class="lineno">  570</span>&#160;<span class="preprocessor">#define MXC_PT7_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0)</span></div><div class="line"><a name="l00571"></a><span class="lineno">  571</span>&#160;<span class="preprocessor">#define MXC_BASE_PT8_BUS0                     ((uint32_t)0x4003C120UL)</span></div><div class="line"><a name="l00572"></a><span class="lineno">  572</span>&#160;<span class="preprocessor">#define MXC_PT8_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0)</span></div><div class="line"><a name="l00573"></a><span class="lineno">  573</span>&#160;<span class="preprocessor">#define MXC_BASE_PT9_BUS0                     ((uint32_t)0x4003C140UL)</span></div><div class="line"><a name="l00574"></a><span class="lineno">  574</span>&#160;<span class="preprocessor">#define MXC_PT9_BUS0                          ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0)</span></div><div class="line"><a name="l00575"></a><span class="lineno">  575</span>&#160;<span class="preprocessor">#define MXC_BASE_PT10_BUS0                    ((uint32_t)0x4003C160UL)</span></div><div class="line"><a name="l00576"></a><span class="lineno">  576</span>&#160;<span class="preprocessor">#define MXC_PT10_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0)</span></div><div class="line"><a name="l00577"></a><span class="lineno">  577</span>&#160;<span class="preprocessor">#define MXC_BASE_PT11_BUS0                    ((uint32_t)0x4003C180UL)</span></div><div class="line"><a name="l00578"></a><span class="lineno">  578</span>&#160;<span class="preprocessor">#define MXC_PT11_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0)</span></div><div class="line"><a name="l00579"></a><span class="lineno">  579</span>&#160;<span class="preprocessor">#define MXC_BASE_PT12_BUS0                    ((uint32_t)0x4003C1A0UL)</span></div><div class="line"><a name="l00580"></a><span class="lineno">  580</span>&#160;<span class="preprocessor">#define MXC_PT12_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0)</span></div><div class="line"><a name="l00581"></a><span class="lineno">  581</span>&#160;<span class="preprocessor">#define MXC_BASE_PT13_BUS0                    ((uint32_t)0x4003C1C0UL)</span></div><div class="line"><a name="l00582"></a><span class="lineno">  582</span>&#160;<span class="preprocessor">#define MXC_PT13_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0)</span></div><div class="line"><a name="l00583"></a><span class="lineno">  583</span>&#160;<span class="preprocessor">#define MXC_BASE_PT14_BUS0                    ((uint32_t)0x4003C1E0UL)</span></div><div class="line"><a name="l00584"></a><span class="lineno">  584</span>&#160;<span class="preprocessor">#define MXC_PT14_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0)</span></div><div class="line"><a name="l00585"></a><span class="lineno">  585</span>&#160;<span class="preprocessor">#define MXC_BASE_PT15_BUS0                    ((uint32_t)0x4003C200UL)</span></div><div class="line"><a name="l00586"></a><span class="lineno">  586</span>&#160;<span class="preprocessor">#define MXC_PT15_BUS0                         ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0)</span></div><div class="line"><a name="l00587"></a><span class="lineno">  587</span>&#160;</div><div class="line"><a name="l00588"></a><span class="lineno">  588</span>&#160;</div><div class="line"><a name="l00589"></a><span class="lineno">  589</span>&#160;<span class="preprocessor">#define MXC_BASE_PTG_BUS1                     ((uint32_t)0x4013C000UL)</span></div><div class="line"><a name="l00590"></a><span class="lineno">  590</span>&#160;<span class="preprocessor">#define MXC_PTG_BUS1                          ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1)</span></div><div class="line"><a name="l00591"></a><span class="lineno">  591</span>&#160;<span class="preprocessor">#define MXC_BASE_PT0_BUS1                     ((uint32_t)0x4013C020UL)</span></div><div class="line"><a name="l00592"></a><span class="lineno">  592</span>&#160;<span class="preprocessor">#define MXC_PT0_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1)</span></div><div class="line"><a name="l00593"></a><span class="lineno">  593</span>&#160;<span class="preprocessor">#define MXC_BASE_PT1_BUS1                     ((uint32_t)0x4013C040UL)</span></div><div class="line"><a name="l00594"></a><span class="lineno">  594</span>&#160;<span class="preprocessor">#define MXC_PT1_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1)</span></div><div class="line"><a name="l00595"></a><span class="lineno">  595</span>&#160;<span class="preprocessor">#define MXC_BASE_PT2_BUS1                     ((uint32_t)0x4013C060UL)</span></div><div class="line"><a name="l00596"></a><span class="lineno">  596</span>&#160;<span class="preprocessor">#define MXC_PT2_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1)</span></div><div class="line"><a name="l00597"></a><span class="lineno">  597</span>&#160;<span class="preprocessor">#define MXC_BASE_PT3_BUS1                     ((uint32_t)0x4013C080UL)</span></div><div class="line"><a name="l00598"></a><span class="lineno">  598</span>&#160;<span class="preprocessor">#define MXC_PT3_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1)</span></div><div class="line"><a name="l00599"></a><span class="lineno">  599</span>&#160;<span class="preprocessor">#define MXC_BASE_PT4_BUS1                     ((uint32_t)0x4013C0A0UL)</span></div><div class="line"><a name="l00600"></a><span class="lineno">  600</span>&#160;<span class="preprocessor">#define MXC_PT4_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1)</span></div><div class="line"><a name="l00601"></a><span class="lineno">  601</span>&#160;<span class="preprocessor">#define MXC_BASE_PT5_BUS1                     ((uint32_t)0x4013C0C0UL)</span></div><div class="line"><a name="l00602"></a><span class="lineno">  602</span>&#160;<span class="preprocessor">#define MXC_PT5_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1)</span></div><div class="line"><a name="l00603"></a><span class="lineno">  603</span>&#160;<span class="preprocessor">#define MXC_BASE_PT6_BUS1                     ((uint32_t)0x4013C0E0UL)</span></div><div class="line"><a name="l00604"></a><span class="lineno">  604</span>&#160;<span class="preprocessor">#define MXC_PT6_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1)</span></div><div class="line"><a name="l00605"></a><span class="lineno">  605</span>&#160;<span class="preprocessor">#define MXC_BASE_PT7_BUS1                     ((uint32_t)0x4013C100UL)</span></div><div class="line"><a name="l00606"></a><span class="lineno">  606</span>&#160;<span class="preprocessor">#define MXC_PT7_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1)</span></div><div class="line"><a name="l00607"></a><span class="lineno">  607</span>&#160;<span class="preprocessor">#define MXC_BASE_PT8_BUS1                     ((uint32_t)0x4013C120UL)</span></div><div class="line"><a name="l00608"></a><span class="lineno">  608</span>&#160;<span class="preprocessor">#define MXC_PT8_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1)</span></div><div class="line"><a name="l00609"></a><span class="lineno">  609</span>&#160;<span class="preprocessor">#define MXC_BASE_PT9_BUS1                     ((uint32_t)0x4013C140UL)</span></div><div class="line"><a name="l00610"></a><span class="lineno">  610</span>&#160;<span class="preprocessor">#define MXC_PT9_BUS1                          ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1)</span></div><div class="line"><a name="l00611"></a><span class="lineno">  611</span>&#160;<span class="preprocessor">#define MXC_BASE_PT10_BUS1                    ((uint32_t)0x4013C160UL)</span></div><div class="line"><a name="l00612"></a><span class="lineno">  612</span>&#160;<span class="preprocessor">#define MXC_PT10_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1)</span></div><div class="line"><a name="l00613"></a><span class="lineno">  613</span>&#160;<span class="preprocessor">#define MXC_BASE_PT11_BUS1                    ((uint32_t)0x4013C180UL)</span></div><div class="line"><a name="l00614"></a><span class="lineno">  614</span>&#160;<span class="preprocessor">#define MXC_PT11_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1)</span></div><div class="line"><a name="l00615"></a><span class="lineno">  615</span>&#160;<span class="preprocessor">#define MXC_BASE_PT12_BUS1                    ((uint32_t)0x4013C1A0UL)</span></div><div class="line"><a name="l00616"></a><span class="lineno">  616</span>&#160;<span class="preprocessor">#define MXC_PT12_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1)</span></div><div class="line"><a name="l00617"></a><span class="lineno">  617</span>&#160;<span class="preprocessor">#define MXC_BASE_PT13_BUS1                    ((uint32_t)0x4013C1C0UL)</span></div><div class="line"><a name="l00618"></a><span class="lineno">  618</span>&#160;<span class="preprocessor">#define MXC_PT13_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1)</span></div><div class="line"><a name="l00619"></a><span class="lineno">  619</span>&#160;<span class="preprocessor">#define MXC_BASE_PT14_BUS1                    ((uint32_t)0x4013C1E0UL)</span></div><div class="line"><a name="l00620"></a><span class="lineno">  620</span>&#160;<span class="preprocessor">#define MXC_PT14_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1)</span></div><div class="line"><a name="l00621"></a><span class="lineno">  621</span>&#160;<span class="preprocessor">#define MXC_BASE_PT15_BUS1                    ((uint32_t)0x4013C200UL)</span></div><div class="line"><a name="l00622"></a><span class="lineno">  622</span>&#160;<span class="preprocessor">#define MXC_PT15_BUS1                         ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1)</span></div><div class="line"><a name="l00623"></a><span class="lineno">  623</span>&#160;</div><div class="line"><a name="l00624"></a><span class="lineno">  624</span>&#160;<span class="preprocessor">#define MXC_PT_GET_BASE(i)               ((i) == 0x0  ? MXC_BASE_PT0_BUS0  :   \</span></div><div class="line"><a name="l00625"></a><span class="lineno">  625</span>&#160;<span class="preprocessor">                                          (i) == 0x1  ? MXC_BASE_PT1_BUS0  :           \</span></div><div class="line"><a name="l00626"></a><span class="lineno">  626</span>&#160;<span class="preprocessor">                                          (i) == 0x2  ? MXC_BASE_PT2_BUS0  :           \</span></div><div class="line"><a name="l00627"></a><span class="lineno">  627</span>&#160;<span class="preprocessor">                                          (i) == 0x3  ? MXC_BASE_PT3_BUS0  :           \</span></div><div class="line"><a name="l00628"></a><span class="lineno">  628</span>&#160;<span class="preprocessor">                                          (i) == 0x4  ? MXC_BASE_PT4_BUS0  :           \</span></div><div class="line"><a name="l00629"></a><span class="lineno">  629</span>&#160;<span class="preprocessor">                                          (i) == 0x5  ? MXC_BASE_PT5_BUS0  :           \</span></div><div class="line"><a name="l00630"></a><span class="lineno">  630</span>&#160;<span class="preprocessor">                                          (i) == 0x6  ? MXC_BASE_PT6_BUS0  :           \</span></div><div class="line"><a name="l00631"></a><span class="lineno">  631</span>&#160;<span class="preprocessor">                                          (i) == 0x7  ? MXC_BASE_PT7_BUS0  :           \</span></div><div class="line"><a name="l00632"></a><span class="lineno">  632</span>&#160;<span class="preprocessor">                                          (i) == 0x8  ? MXC_BASE_PT8_BUS0  :           \</span></div><div class="line"><a name="l00633"></a><span class="lineno">  633</span>&#160;<span class="preprocessor">                                          (i) == 0x9  ? MXC_BASE_PT9_BUS0  :           \</span></div><div class="line"><a name="l00634"></a><span class="lineno">  634</span>&#160;<span class="preprocessor">                                          (i) == 0xA  ? MXC_BASE_PT10_BUS0 :           \</span></div><div class="line"><a name="l00635"></a><span class="lineno">  635</span>&#160;<span class="preprocessor">                                          (i) == 0xB  ? MXC_BASE_PT11_BUS0 :           \</span></div><div class="line"><a name="l00636"></a><span class="lineno">  636</span>&#160;<span class="preprocessor">                                          (i) == 0xC  ? MXC_BASE_PT12_BUS0 :           \</span></div><div class="line"><a name="l00637"></a><span class="lineno">  637</span>&#160;<span class="preprocessor">                                          (i) == 0xD  ? MXC_BASE_PT13_BUS0 :           \</span></div><div class="line"><a name="l00638"></a><span class="lineno">  638</span>&#160;<span class="preprocessor">                                          (i) == 0xE  ? MXC_BASE_PT14_BUS0 :           \</span></div><div class="line"><a name="l00639"></a><span class="lineno">  639</span>&#160;<span class="preprocessor">                                          (i) == 0xF  ? MXC_BASE_PT15_BUS0 :           \</span></div><div class="line"><a name="l00640"></a><span class="lineno">  640</span>&#160;<span class="preprocessor">                                          (i) == 0x8000  ? MXC_BASE_PT0_BUS1  :      \</span></div><div class="line"><a name="l00641"></a><span class="lineno">  641</span>&#160;<span class="preprocessor">                                          (i) == 0x8001  ? MXC_BASE_PT1_BUS1  :      \</span></div><div class="line"><a name="l00642"></a><span class="lineno">  642</span>&#160;<span class="preprocessor">                                          (i) == 0x8002  ? MXC_BASE_PT2_BUS1  :      \</span></div><div class="line"><a name="l00643"></a><span class="lineno">  643</span>&#160;<span class="preprocessor">                                          (i) == 0x8003  ? MXC_BASE_PT3_BUS1  :      \</span></div><div class="line"><a name="l00644"></a><span class="lineno">  644</span>&#160;<span class="preprocessor">                                          (i) == 0x8004  ? MXC_BASE_PT4_BUS1  :      \</span></div><div class="line"><a name="l00645"></a><span class="lineno">  645</span>&#160;<span class="preprocessor">                                          (i) == 0x8005  ? MXC_BASE_PT5_BUS1  :      \</span></div><div class="line"><a name="l00646"></a><span class="lineno">  646</span>&#160;<span class="preprocessor">                                          (i) == 0x8006  ? MXC_BASE_PT6_BUS1  :      \</span></div><div class="line"><a name="l00647"></a><span class="lineno">  647</span>&#160;<span class="preprocessor">                                          (i) == 0x8007  ? MXC_BASE_PT7_BUS1  :      \</span></div><div class="line"><a name="l00648"></a><span class="lineno">  648</span>&#160;<span class="preprocessor">                                          (i) == 0x8008  ? MXC_BASE_PT8_BUS1  :      \</span></div><div class="line"><a name="l00649"></a><span class="lineno">  649</span>&#160;<span class="preprocessor">                                          (i) == 0x8009  ? MXC_BASE_PT9_BUS1  :      \</span></div><div class="line"><a name="l00650"></a><span class="lineno">  650</span>&#160;<span class="preprocessor">                                          (i) == 0x800A ? MXC_BASE_PT10_BUS1 :       \</span></div><div class="line"><a name="l00651"></a><span class="lineno">  651</span>&#160;<span class="preprocessor">                                          (i) == 0x800B ? MXC_BASE_PT11_BUS1 :       \</span></div><div class="line"><a name="l00652"></a><span class="lineno">  652</span>&#160;<span class="preprocessor">                                          (i) == 0x800C ? MXC_BASE_PT12_BUS1 :       \</span></div><div class="line"><a name="l00653"></a><span class="lineno">  653</span>&#160;<span class="preprocessor">                                          (i) == 0x800D ? MXC_BASE_PT13_BUS1 :       \</span></div><div class="line"><a name="l00654"></a><span class="lineno">  654</span>&#160;<span class="preprocessor">                                          (i) == 0x800E ? MXC_BASE_PT14_BUS1 :       \</span></div><div class="line"><a name="l00655"></a><span class="lineno">  655</span>&#160;<span class="preprocessor">                                          (i) == 0x800F ? MXC_BASE_PT15_BUS1 : 0)</span></div><div class="line"><a name="l00656"></a><span class="lineno">  656</span>&#160;</div><div class="line"><a name="l00657"></a><span class="lineno">  657</span>&#160;<span class="preprocessor">#define MXC_PT_GET_PT(i)                 ((i) == 0x0  ? MXC_PT0_BUS0  :    \</span></div><div class="line"><a name="l00658"></a><span class="lineno">  658</span>&#160;<span class="preprocessor">                                          (i) == 0x1  ? MXC_PT1_BUS0  :                \</span></div><div class="line"><a name="l00659"></a><span class="lineno">  659</span>&#160;<span class="preprocessor">                                          (i) == 0x2  ? MXC_PT2_BUS0  :                \</span></div><div class="line"><a name="l00660"></a><span class="lineno">  660</span>&#160;<span class="preprocessor">                                          (i) == 0x3  ? MXC_PT3_BUS0  :                \</span></div><div class="line"><a name="l00661"></a><span class="lineno">  661</span>&#160;<span class="preprocessor">                                          (i) == 0x4  ? MXC_PT4_BUS0  :                \</span></div><div class="line"><a name="l00662"></a><span class="lineno">  662</span>&#160;<span class="preprocessor">                                          (i) == 0x5  ? MXC_PT5_BUS0  :                \</span></div><div class="line"><a name="l00663"></a><span class="lineno">  663</span>&#160;<span class="preprocessor">                                          (i) == 0x6  ? MXC_PT6_BUS0  :                \</span></div><div class="line"><a name="l00664"></a><span class="lineno">  664</span>&#160;<span class="preprocessor">                                          (i) == 0x7  ? MXC_PT7_BUS0  :                \</span></div><div class="line"><a name="l00665"></a><span class="lineno">  665</span>&#160;<span class="preprocessor">                                          (i) == 0x8  ? MXC_PT8_BUS0  :                \</span></div><div class="line"><a name="l00666"></a><span class="lineno">  666</span>&#160;<span class="preprocessor">                                          (i) == 0x9  ? MXC_PT9_BUS0  :                \</span></div><div class="line"><a name="l00667"></a><span class="lineno">  667</span>&#160;<span class="preprocessor">                                          (i) == 0xA  ? MXC_PT10_BUS0 :                \</span></div><div class="line"><a name="l00668"></a><span class="lineno">  668</span>&#160;<span class="preprocessor">                                          (i) == 0xB  ? MXC_PT11_BUS0 :                \</span></div><div class="line"><a name="l00669"></a><span class="lineno">  669</span>&#160;<span class="preprocessor">                                          (i) == 0xC  ? MXC_PT12_BUS0 :                \</span></div><div class="line"><a name="l00670"></a><span class="lineno">  670</span>&#160;<span class="preprocessor">                                          (i) == 0xD  ? MXC_PT13_BUS0 :                \</span></div><div class="line"><a name="l00671"></a><span class="lineno">  671</span>&#160;<span class="preprocessor">                                          (i) == 0xE  ? MXC_PT14_BUS0 :                \</span></div><div class="line"><a name="l00672"></a><span class="lineno">  672</span>&#160;<span class="preprocessor">                                          (i) == 0xF  ? MXC_PT15_BUS0 :                \</span></div><div class="line"><a name="l00673"></a><span class="lineno">  673</span>&#160;<span class="preprocessor">                                          (i) == 0x8000  ? MXC_PT0_BUS1  :             \</span></div><div class="line"><a name="l00674"></a><span class="lineno">  674</span>&#160;<span class="preprocessor">                                          (i) == 0x8001  ? MXC_PT1_BUS1  :             \</span></div><div class="line"><a name="l00675"></a><span class="lineno">  675</span>&#160;<span class="preprocessor">                                          (i) == 0x8002  ? MXC_PT2_BUS1  :             \</span></div><div class="line"><a name="l00676"></a><span class="lineno">  676</span>&#160;<span class="preprocessor">                                          (i) == 0x8003  ? MXC_PT3_BUS1  :             \</span></div><div class="line"><a name="l00677"></a><span class="lineno">  677</span>&#160;<span class="preprocessor">                                          (i) == 0x8004  ? MXC_PT4_BUS1  :             \</span></div><div class="line"><a name="l00678"></a><span class="lineno">  678</span>&#160;<span class="preprocessor">                                          (i) == 0x8005  ? MXC_PT5_BUS1  :             \</span></div><div class="line"><a name="l00679"></a><span class="lineno">  679</span>&#160;<span class="preprocessor">                                          (i) == 0x8006  ? MXC_PT6_BUS1  :             \</span></div><div class="line"><a name="l00680"></a><span class="lineno">  680</span>&#160;<span class="preprocessor">                                          (i) == 0x8007  ? MXC_PT7_BUS1  :             \</span></div><div class="line"><a name="l00681"></a><span class="lineno">  681</span>&#160;<span class="preprocessor">                                          (i) == 0x8008  ? MXC_PT8_BUS1  :             \</span></div><div class="line"><a name="l00682"></a><span class="lineno">  682</span>&#160;<span class="preprocessor">                                          (i) == 0x8009  ? MXC_PT9_BUS1  :             \</span></div><div class="line"><a name="l00683"></a><span class="lineno">  683</span>&#160;<span class="preprocessor">                                          (i) == 0x800A  ? MXC_PT10_BUS1 :             \</span></div><div class="line"><a name="l00684"></a><span class="lineno">  684</span>&#160;<span class="preprocessor">                                          (i) == 0x800B  ? MXC_PT11_BUS1 :             \</span></div><div class="line"><a name="l00685"></a><span class="lineno">  685</span>&#160;<span class="preprocessor">                                          (i) == 0x800C  ? MXC_PT12_BUS1 :             \</span></div><div class="line"><a name="l00686"></a><span class="lineno">  686</span>&#160;<span class="preprocessor">                                          (i) == 0x800D  ? MXC_PT13_BUS1 :             \</span></div><div class="line"><a name="l00687"></a><span class="lineno">  687</span>&#160;<span class="preprocessor">                                          (i) == 0x800E  ? MXC_PT14_BUS1 :             \</span></div><div class="line"><a name="l00688"></a><span class="lineno">  688</span>&#160;<span class="preprocessor">                                          (i) == 0x800F  ? MXC_PT15_BUS1 : 0)</span></div><div class="line"><a name="l00689"></a><span class="lineno">  689</span>&#160;</div><div class="line"><a name="l00690"></a><span class="lineno">  690</span>&#160;<span class="preprocessor">#define MXC_PT_GET_IDX(p)                ((p) == MXC_PT0_BUS0  ? 0x0     :                \</span></div><div class="line"><a name="l00691"></a><span class="lineno">  691</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT1_BUS0  ? 0x1     :                \</span></div><div class="line"><a name="l00692"></a><span class="lineno">  692</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT2_BUS0  ? 0x2     :                \</span></div><div class="line"><a name="l00693"></a><span class="lineno">  693</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT3_BUS0  ? 0x3     :                \</span></div><div class="line"><a name="l00694"></a><span class="lineno">  694</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT4_BUS0  ? 0x4     :                \</span></div><div class="line"><a name="l00695"></a><span class="lineno">  695</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT5_BUS0  ? 0x5     :                \</span></div><div class="line"><a name="l00696"></a><span class="lineno">  696</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT6_BUS0  ? 0x6     :                \</span></div><div class="line"><a name="l00697"></a><span class="lineno">  697</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT7_BUS0  ? 0x7     :                \</span></div><div class="line"><a name="l00698"></a><span class="lineno">  698</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT8_BUS0  ? 0x8     :                \</span></div><div class="line"><a name="l00699"></a><span class="lineno">  699</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT9_BUS0  ? 0x9     :                \</span></div><div class="line"><a name="l00700"></a><span class="lineno">  700</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT10_BUS0 ? 0xA     :                \</span></div><div class="line"><a name="l00701"></a><span class="lineno">  701</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT11_BUS0 ? 0xB     :                \</span></div><div class="line"><a name="l00702"></a><span class="lineno">  702</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT12_BUS0 ? 0xC     :                \</span></div><div class="line"><a name="l00703"></a><span class="lineno">  703</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT13_BUS0 ? 0xD     :                \</span></div><div class="line"><a name="l00704"></a><span class="lineno">  704</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT14_BUS0 ? 0xE     :                \</span></div><div class="line"><a name="l00705"></a><span class="lineno">  705</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT15_BUS0 ? 0xF     :                \</span></div><div class="line"><a name="l00706"></a><span class="lineno">  706</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT0_BUS1  ? 0x8000  :                \</span></div><div class="line"><a name="l00707"></a><span class="lineno">  707</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT1_BUS1  ? 0x8001  :                \</span></div><div class="line"><a name="l00708"></a><span class="lineno">  708</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT2_BUS1  ? 0x8002  :                \</span></div><div class="line"><a name="l00709"></a><span class="lineno">  709</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT3_BUS1  ? 0x8003  :                \</span></div><div class="line"><a name="l00710"></a><span class="lineno">  710</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT4_BUS1  ? 0x8004  :                \</span></div><div class="line"><a name="l00711"></a><span class="lineno">  711</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT5_BUS1  ? 0x8005  :                \</span></div><div class="line"><a name="l00712"></a><span class="lineno">  712</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT6_BUS1  ? 0x8006  :                \</span></div><div class="line"><a name="l00713"></a><span class="lineno">  713</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT7_BUS1  ? 0x8007  :                \</span></div><div class="line"><a name="l00714"></a><span class="lineno">  714</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT8_BUS1  ? 0x8008  :                \</span></div><div class="line"><a name="l00715"></a><span class="lineno">  715</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT9_BUS1  ? 0x8009  :                \</span></div><div class="line"><a name="l00716"></a><span class="lineno">  716</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT10_BUS1 ? 0x800A  :                \</span></div><div class="line"><a name="l00717"></a><span class="lineno">  717</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT11_BUS1 ? 0x800B  :                \</span></div><div class="line"><a name="l00718"></a><span class="lineno">  718</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT12_BUS1 ? 0x800C  :                \</span></div><div class="line"><a name="l00719"></a><span class="lineno">  719</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT13_BUS1 ? 0x800D  :                \</span></div><div class="line"><a name="l00720"></a><span class="lineno">  720</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT14_BUS1 ? 0x800E  :                \</span></div><div class="line"><a name="l00721"></a><span class="lineno">  721</span>&#160;<span class="preprocessor">                                          (p) == MXC_PT15_BUS1 ? 0x800F  : -1)</span></div><div class="line"><a name="l00722"></a><span class="lineno">  722</span>&#160;</div><div class="line"><a name="l00723"></a><span class="lineno">  723</span>&#160;<span class="preprocessor">#define MXC_PT_GET_BUS(i)                (((i) &amp; 0x00100000UL)&gt;&gt;20)</span></div><div class="line"><a name="l00724"></a><span class="lineno">  724</span>&#160;</div><div class="line"><a name="l00725"></a><span class="lineno">  725</span>&#160;<span class="preprocessor">#define MXC_PTG_GET_PTG(i)  (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 :  \</span></div><div class="line"><a name="l00726"></a><span class="lineno">  726</span>&#160;<span class="preprocessor">                             MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0)</span></div><div class="line"><a name="l00727"></a><span class="lineno">  727</span>&#160;</div><div class="line"><a name="l00728"></a><span class="lineno">  728</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00729"></a><span class="lineno">  729</span>&#160;<span class="comment">/*                                                            One Wire Master */</span></div><div class="line"><a name="l00730"></a><span class="lineno">  730</span>&#160;<span class="preprocessor">#define MXC_BASE_OWM                    ((uint32_t)0x4003D000UL)</span></div><div class="line"><a name="l00731"></a><span class="lineno">  731</span>&#160;<span class="preprocessor">#define MXC_OWM                         ((mxc_owm_regs_t*)MXC_BASE_OWM)</span></div><div class="line"><a name="l00732"></a><span class="lineno">  732</span>&#160;</div><div class="line"><a name="l00733"></a><span class="lineno">  733</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00734"></a><span class="lineno">  734</span>&#160;<span class="comment">/*                                                                  Semaphore */</span></div><div class="line"><a name="l00735"></a><span class="lineno">  735</span>&#160;<span class="preprocessor">#define MXC_CFG_SEMA_INSTANCES          (8)</span></div><div class="line"><a name="l00736"></a><span class="lineno">  736</span>&#160;</div><div class="line"><a name="l00737"></a><span class="lineno">  737</span>&#160;<span class="preprocessor">#define MXC_BASE_SEMA                   ((uint32_t)0x4003E000UL)</span></div><div class="line"><a name="l00738"></a><span class="lineno">  738</span>&#160;<span class="preprocessor">#define MXC_SEMA                        ((mxc_sema_regs_t*)MXC_BASE_SEMA)</span></div><div class="line"><a name="l00739"></a><span class="lineno">  739</span>&#160;</div><div class="line"><a name="l00740"></a><span class="lineno">  740</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00741"></a><span class="lineno">  741</span>&#160;<span class="comment">/*                                               UART / Serial Port Interface */</span></div><div class="line"><a name="l00742"></a><span class="lineno">  742</span>&#160;</div><div class="line"><a name="l00743"></a><span class="lineno">  743</span>&#160;<span class="preprocessor">#define MXC_UART_INSTANCES              (3)</span></div><div class="line"><a name="l00744"></a><span class="lineno">  744</span>&#160;<span class="preprocessor">#define MXC_UART_FIFO_DEPTH             (32)</span></div><div class="line"><a name="l00745"></a><span class="lineno">  745</span>&#160;</div><div class="line"><a name="l00746"></a><span class="lineno">  746</span>&#160;<span class="preprocessor">#define MXC_BASE_UART0                  ((uint32_t)0x40042000UL)</span></div><div class="line"><a name="l00747"></a><span class="lineno">  747</span>&#160;<span class="preprocessor">#define MXC_UART0                       ((mxc_uart_regs_t*)MXC_BASE_UART0)</span></div><div class="line"><a name="l00748"></a><span class="lineno">  748</span>&#160;<span class="preprocessor">#define MXC_BASE_UART1                  ((uint32_t)0x40043000UL)</span></div><div class="line"><a name="l00749"></a><span class="lineno">  749</span>&#160;<span class="preprocessor">#define MXC_UART1                       ((mxc_uart_regs_t*)MXC_BASE_UART1)</span></div><div class="line"><a name="l00750"></a><span class="lineno">  750</span>&#160;<span class="preprocessor">#define MXC_BASE_UART2                  ((uint32_t)0x40044000UL)</span></div><div class="line"><a name="l00751"></a><span class="lineno">  751</span>&#160;<span class="preprocessor">#define MXC_UART2                       ((mxc_uart_regs_t*)MXC_BASE_UART2)</span></div><div class="line"><a name="l00752"></a><span class="lineno">  752</span>&#160;</div><div class="line"><a name="l00753"></a><span class="lineno">  753</span>&#160;<span class="preprocessor">#define MXC_UART_GET_IRQ(i)             (IRQn_Type)((i) == 0 ? UART0_IRQn :    \</span></div><div class="line"><a name="l00754"></a><span class="lineno">  754</span>&#160;<span class="preprocessor">                                            (i) == 1 ? UART1_IRQn :            \</span></div><div class="line"><a name="l00755"></a><span class="lineno">  755</span>&#160;<span class="preprocessor">                                            (i) == 2 ? UART2_IRQn : 0)</span></div><div class="line"><a name="l00756"></a><span class="lineno">  756</span>&#160;</div><div class="line"><a name="l00757"></a><span class="lineno">  757</span>&#160;<span class="preprocessor">#define MXC_UART_GET_BASE(i)            ((i) == 0 ? MXC_BASE_UART0 :           \</span></div><div class="line"><a name="l00758"></a><span class="lineno">  758</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_BASE_UART1 :        \</span></div><div class="line"><a name="l00759"></a><span class="lineno">  759</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_BASE_UART2 : 0)</span></div><div class="line"><a name="l00760"></a><span class="lineno">  760</span>&#160;</div><div class="line"><a name="l00761"></a><span class="lineno">  761</span>&#160;<span class="preprocessor">#define MXC_UART_GET_UART(i)            ((i) == 0 ? MXC_UART0 :                \</span></div><div class="line"><a name="l00762"></a><span class="lineno">  762</span>&#160;<span class="preprocessor">                                            (i) == 1 ? MXC_UART1 :             \</span></div><div class="line"><a name="l00763"></a><span class="lineno">  763</span>&#160;<span class="preprocessor">                                            (i) == 2 ? MXC_UART2 : 0)</span></div><div class="line"><a name="l00764"></a><span class="lineno">  764</span>&#160;</div><div class="line"><a name="l00765"></a><span class="lineno">  765</span>&#160;<span class="preprocessor">#define MXC_UART_GET_IDX(p)             ((p) == MXC_UART0 ? 0 :                \</span></div><div class="line"><a name="l00766"></a><span class="lineno">  766</span>&#160;<span class="preprocessor">                                            (p) == MXC_UART1 ? 1 :             \</span></div><div class="line"><a name="l00767"></a><span class="lineno">  767</span>&#160;<span class="preprocessor">                                            (p) == MXC_UART2 ? 2 : -1)</span></div><div class="line"><a name="l00768"></a><span class="lineno">  768</span>&#160;</div><div class="line"><a name="l00769"></a><span class="lineno">  769</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00770"></a><span class="lineno">  770</span>&#160;<span class="comment">/*                                                                     SPI17Y */</span></div><div class="line"><a name="l00771"></a><span class="lineno">  771</span>&#160;</div><div class="line"><a name="l00772"></a><span class="lineno">  772</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_INSTANCES               (3)</span></div><div class="line"><a name="l00773"></a><span class="lineno">  773</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_SS_INSTANCES            (4)</span></div><div class="line"><a name="l00774"></a><span class="lineno">  774</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_FIFO_DEPTH              (32)</span></div><div class="line"><a name="l00775"></a><span class="lineno">  775</span>&#160;</div><div class="line"><a name="l00776"></a><span class="lineno">  776</span>&#160;<span class="preprocessor">#define MXC_BASE_SPI17Y0                   ((uint32_t)0x400BE000UL)</span></div><div class="line"><a name="l00777"></a><span class="lineno">  777</span>&#160;<span class="preprocessor">#define MXC_SPI17Y0                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y0)</span></div><div class="line"><a name="l00778"></a><span class="lineno">  778</span>&#160;<span class="preprocessor">#define MXC_BASE_SPI17Y1                   ((uint32_t)0x40046000UL)</span></div><div class="line"><a name="l00779"></a><span class="lineno">  779</span>&#160;<span class="preprocessor">#define MXC_SPI17Y1                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y1)</span></div><div class="line"><a name="l00780"></a><span class="lineno">  780</span>&#160;<span class="preprocessor">#define MXC_BASE_SPI17Y2                   ((uint32_t)0x40047000UL)</span></div><div class="line"><a name="l00781"></a><span class="lineno">  781</span>&#160;<span class="preprocessor">#define MXC_SPI17Y2                        ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y2)</span></div><div class="line"><a name="l00782"></a><span class="lineno">  782</span>&#160;</div><div class="line"><a name="l00783"></a><span class="lineno">  783</span>&#160;</div><div class="line"><a name="l00784"></a><span class="lineno">  784</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_IDX(p)            ((p) == MXC_SPI17Y0 ? 0 :              \</span></div><div class="line"><a name="l00785"></a><span class="lineno">  785</span>&#160;<span class="preprocessor">                                          (p) == MXC_SPI17Y1 ? 1 :              \</span></div><div class="line"><a name="l00786"></a><span class="lineno">  786</span>&#160;<span class="preprocessor">                                          (p) == MXC_SPI17Y2 ? 2 :  -1)</span></div><div class="line"><a name="l00787"></a><span class="lineno">  787</span>&#160;</div><div class="line"><a name="l00788"></a><span class="lineno">  788</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_BASE(i)           ((i) == 0 ? MXC_BASE_SPI17Y0 :         \</span></div><div class="line"><a name="l00789"></a><span class="lineno">  789</span>&#160;<span class="preprocessor">                                          (i) == 1 ? MXC_BASE_SPI17Y1 :         \</span></div><div class="line"><a name="l00790"></a><span class="lineno">  790</span>&#160;<span class="preprocessor">                                          (i) == 2 ? MXC_BASE_SPI17Y2 : 0)</span></div><div class="line"><a name="l00791"></a><span class="lineno">  791</span>&#160;</div><div class="line"><a name="l00792"></a><span class="lineno">  792</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_SPI17Y(i)         ((i) == 0 ? MXC_SPI17Y0 :              \</span></div><div class="line"><a name="l00793"></a><span class="lineno">  793</span>&#160;<span class="preprocessor">                                          (i) == 1 ? MXC_SPI17Y1 :              \</span></div><div class="line"><a name="l00794"></a><span class="lineno">  794</span>&#160;<span class="preprocessor">                                          (i) == 2 ? MXC_SPI17Y2 : 0)</span></div><div class="line"><a name="l00795"></a><span class="lineno">  795</span>&#160;</div><div class="line"><a name="l00796"></a><span class="lineno">  796</span>&#160;<span class="preprocessor">#define MXC_SPI17Y_GET_IRQ(i)           (IRQn_Type)((i) == 0 ? SPI17Y0_IRQn :   \</span></div><div class="line"><a name="l00797"></a><span class="lineno">  797</span>&#160;<span class="preprocessor">                                          (i) == 1 ? SPI17Y1_IRQn :             \</span></div><div class="line"><a name="l00798"></a><span class="lineno">  798</span>&#160;<span class="preprocessor">                                          (i) == 2 ? SPI17Y2_IRQn : 0)</span></div><div class="line"><a name="l00799"></a><span class="lineno">  799</span>&#160;</div><div class="line"><a name="l00800"></a><span class="lineno">  800</span>&#160;</div><div class="line"><a name="l00801"></a><span class="lineno">  801</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00802"></a><span class="lineno">  802</span>&#160;<span class="comment">/*                                                                       TRNG */</span></div><div class="line"><a name="l00803"></a><span class="lineno">  803</span>&#160;<span class="preprocessor">#define MXC_BASE_TRNG                   ((uint32_t)0x4004D000UL)</span></div><div class="line"><a name="l00804"></a><span class="lineno">  804</span>&#160;<span class="preprocessor">#define MXC_TRNG                        ((mxc_trng_regs_t*)MXC_BASE_TRNG)</span></div><div class="line"><a name="l00805"></a><span class="lineno">  805</span>&#160;</div><div class="line"><a name="l00806"></a><span class="lineno">  806</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00807"></a><span class="lineno">  807</span>&#160;<span class="comment">/*                                                                       SDHC */</span></div><div class="line"><a name="l00808"></a><span class="lineno">  808</span>&#160;<span class="preprocessor">#define MXC_BASE_SDHC                   ((uint32_t)0x400B6000UL)</span></div><div class="line"><a name="l00809"></a><span class="lineno">  809</span>&#160;<span class="preprocessor">#define MXC_SDHC                        ((mxc_sdhc_regs_t*)MXC_BASE_SDHC)</span></div><div class="line"><a name="l00810"></a><span class="lineno">  810</span>&#160;</div><div class="line"><a name="l00811"></a><span class="lineno">  811</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00812"></a><span class="lineno">  812</span>&#160;<span class="comment">/*                                                                        RPU */</span></div><div class="line"><a name="l00813"></a><span class="lineno">  813</span>&#160;<span class="preprocessor">#define MXC_BASE_RPU                    ((uint32_t)0x40002000UL)</span></div><div class="line"><a name="l00814"></a><span class="lineno">  814</span>&#160;<span class="preprocessor">#define MXC_RPU                         ((mxc_rpu_regs_t*)MXC_BASE_RPU)</span></div><div class="line"><a name="l00815"></a><span class="lineno">  815</span>&#160;<span class="preprocessor">#define MXC_RPU_NUM_BUS_MASTERS         9</span></div><div class="line"><a name="l00816"></a><span class="lineno">  816</span>&#160;</div><div class="line"><a name="l00817"></a><span class="lineno">  817</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00818"></a><span class="lineno">  818</span>&#160;<span class="comment">/*                                                            Audio Subsystem */</span></div><div class="line"><a name="l00819"></a><span class="lineno">  819</span>&#160;<span class="preprocessor">#define MXC_BASE_AUDIO                    ((uint32_t)0x4004C000UL)</span></div><div class="line"><a name="l00820"></a><span class="lineno">  820</span>&#160;<span class="preprocessor">#define MXC_AUDIO                         ((mxc_audio_regs_t*)MXC_BASE_AUDIO)</span></div><div class="line"><a name="l00821"></a><span class="lineno">  821</span>&#160;</div><div class="line"><a name="l00822"></a><span class="lineno">  822</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00823"></a><span class="lineno">  823</span>&#160;<span class="comment">/*                                                       Bluetooth Low Energy */</span></div><div class="line"><a name="l00824"></a><span class="lineno">  824</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE                    (0x40050000UL)</span></div><div class="line"><a name="l00825"></a><span class="lineno">  825</span>&#160;<span class="preprocessor">#define MXC_BTLE                         ((mxc_btle_regs_t*)MXC_BASE_BTLE)</span></div><div class="line"><a name="l00826"></a><span class="lineno">  826</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_CTRL           (MXC_BASE_BTLE + 0x1000)</span></div><div class="line"><a name="l00827"></a><span class="lineno">  827</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_TX             (MXC_BASE_BTLE + 0x2000)</span></div><div class="line"><a name="l00828"></a><span class="lineno">  828</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_RX             (MXC_BASE_BTLE + 0x3000)</span></div><div class="line"><a name="l00829"></a><span class="lineno">  829</span>&#160;<span class="preprocessor">#define MXC_BASE_BTLE_DBB_EXT_RFFE       (MXC_BASE_BTLE + 0x8000)</span></div><div class="line"><a name="l00830"></a><span class="lineno">  830</span>&#160;</div><div class="line"><a name="l00831"></a><span class="lineno">  831</span>&#160;<span class="comment">// Base address definitions needed for DBB register definitions in BTLE stack</span></div><div class="line"><a name="l00832"></a><span class="lineno">  832</span>&#160;<span class="preprocessor">#define DBB_CTRL_BASE                    MXC_BASE_BTLE_DBB_CTRL</span></div><div class="line"><a name="l00833"></a><span class="lineno">  833</span>&#160;<span class="preprocessor">#define DBB_TX_BASE                      MXC_BASE_BTLE_DBB_TX</span></div><div class="line"><a name="l00834"></a><span class="lineno">  834</span>&#160;<span class="preprocessor">#define DBB_RX_BASE                      MXC_BASE_BTLE_DBB_RX</span></div><div class="line"><a name="l00835"></a><span class="lineno">  835</span>&#160;<span class="preprocessor">#define DBB_EXT_RFFE_BASE                MXC_BASE_BTLE_DBB_EXT_RFFE</span></div><div class="line"><a name="l00836"></a><span class="lineno">  836</span>&#160;</div><div class="line"><a name="l00837"></a><span class="lineno">  837</span>&#160;</div><div class="line"><a name="l00838"></a><span class="lineno">  838</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00839"></a><span class="lineno">  839</span>&#160;<span class="comment">/*                                                               Bit Shifting */</span></div><div class="line"><a name="l00840"></a><span class="lineno">  840</span>&#160;</div><div class="line"><a name="l00841"></a><span class="lineno">  841</span>&#160;<span class="preprocessor">#define MXC_F_BIT_0                     (1 &lt;&lt; 0)</span></div><div class="line"><a name="l00842"></a><span class="lineno">  842</span>&#160;<span class="preprocessor">#define MXC_F_BIT_1                     (1 &lt;&lt; 1)</span></div><div class="line"><a name="l00843"></a><span class="lineno">  843</span>&#160;<span class="preprocessor">#define MXC_F_BIT_2                     (1 &lt;&lt; 2)</span></div><div class="line"><a name="l00844"></a><span class="lineno">  844</span>&#160;<span class="preprocessor">#define MXC_F_BIT_3                     (1 &lt;&lt; 3)</span></div><div class="line"><a name="l00845"></a><span class="lineno">  845</span>&#160;<span class="preprocessor">#define MXC_F_BIT_4                     (1 &lt;&lt; 4)</span></div><div class="line"><a name="l00846"></a><span class="lineno">  846</span>&#160;<span class="preprocessor">#define MXC_F_BIT_5                     (1 &lt;&lt; 5)</span></div><div class="line"><a name="l00847"></a><span class="lineno">  847</span>&#160;<span class="preprocessor">#define MXC_F_BIT_6                     (1 &lt;&lt; 6)</span></div><div class="line"><a name="l00848"></a><span class="lineno">  848</span>&#160;<span class="preprocessor">#define MXC_F_BIT_7                     (1 &lt;&lt; 7)</span></div><div class="line"><a name="l00849"></a><span class="lineno">  849</span>&#160;<span class="preprocessor">#define MXC_F_BIT_8                     (1 &lt;&lt; 8)</span></div><div class="line"><a name="l00850"></a><span class="lineno">  850</span>&#160;<span class="preprocessor">#define MXC_F_BIT_9                     (1 &lt;&lt; 9)</span></div><div class="line"><a name="l00851"></a><span class="lineno">  851</span>&#160;<span class="preprocessor">#define MXC_F_BIT_10                    (1 &lt;&lt; 10)</span></div><div class="line"><a name="l00852"></a><span class="lineno">  852</span>&#160;<span class="preprocessor">#define MXC_F_BIT_11                    (1 &lt;&lt; 11)</span></div><div class="line"><a name="l00853"></a><span class="lineno">  853</span>&#160;<span class="preprocessor">#define MXC_F_BIT_12                    (1 &lt;&lt; 12)</span></div><div class="line"><a name="l00854"></a><span class="lineno">  854</span>&#160;<span class="preprocessor">#define MXC_F_BIT_13                    (1 &lt;&lt; 13)</span></div><div class="line"><a name="l00855"></a><span class="lineno">  855</span>&#160;<span class="preprocessor">#define MXC_F_BIT_14                    (1 &lt;&lt; 14)</span></div><div class="line"><a name="l00856"></a><span class="lineno">  856</span>&#160;<span class="preprocessor">#define MXC_F_BIT_15                    (1 &lt;&lt; 15)</span></div><div class="line"><a name="l00857"></a><span class="lineno">  857</span>&#160;<span class="preprocessor">#define MXC_F_BIT_16                    (1 &lt;&lt; 16)</span></div><div class="line"><a name="l00858"></a><span class="lineno">  858</span>&#160;<span class="preprocessor">#define MXC_F_BIT_17                    (1 &lt;&lt; 17)</span></div><div class="line"><a name="l00859"></a><span class="lineno">  859</span>&#160;<span class="preprocessor">#define MXC_F_BIT_18                    (1 &lt;&lt; 18)</span></div><div class="line"><a name="l00860"></a><span class="lineno">  860</span>&#160;<span class="preprocessor">#define MXC_F_BIT_19                    (1 &lt;&lt; 19)</span></div><div class="line"><a name="l00861"></a><span class="lineno">  861</span>&#160;<span class="preprocessor">#define MXC_F_BIT_20                    (1 &lt;&lt; 20)</span></div><div class="line"><a name="l00862"></a><span class="lineno">  862</span>&#160;<span class="preprocessor">#define MXC_F_BIT_21                    (1 &lt;&lt; 21)</span></div><div class="line"><a name="l00863"></a><span class="lineno">  863</span>&#160;<span class="preprocessor">#define MXC_F_BIT_22                    (1 &lt;&lt; 22)</span></div><div class="line"><a name="l00864"></a><span class="lineno">  864</span>&#160;<span class="preprocessor">#define MXC_F_BIT_23                    (1 &lt;&lt; 23)</span></div><div class="line"><a name="l00865"></a><span class="lineno">  865</span>&#160;<span class="preprocessor">#define MXC_F_BIT_24                    (1 &lt;&lt; 24)</span></div><div class="line"><a name="l00866"></a><span class="lineno">  866</span>&#160;<span class="preprocessor">#define MXC_F_BIT_25                    (1 &lt;&lt; 25)</span></div><div class="line"><a name="l00867"></a><span class="lineno">  867</span>&#160;<span class="preprocessor">#define MXC_F_BIT_26                    (1 &lt;&lt; 26)</span></div><div class="line"><a name="l00868"></a><span class="lineno">  868</span>&#160;<span class="preprocessor">#define MXC_F_BIT_27                    (1 &lt;&lt; 27)</span></div><div class="line"><a name="l00869"></a><span class="lineno">  869</span>&#160;<span class="preprocessor">#define MXC_F_BIT_28                    (1 &lt;&lt; 28)</span></div><div class="line"><a name="l00870"></a><span class="lineno">  870</span>&#160;<span class="preprocessor">#define MXC_F_BIT_29                    (1 &lt;&lt; 29)</span></div><div class="line"><a name="l00871"></a><span class="lineno">  871</span>&#160;<span class="preprocessor">#define MXC_F_BIT_30                    (1 &lt;&lt; 30)</span></div><div class="line"><a name="l00872"></a><span class="lineno">  872</span>&#160;<span class="preprocessor">#define MXC_F_BIT_31                    (1 &lt;&lt; 31)</span></div><div class="line"><a name="l00873"></a><span class="lineno">  873</span>&#160;</div><div class="line"><a name="l00874"></a><span class="lineno">  874</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00875"></a><span class="lineno">  875</span>&#160;<span class="comment">/*                                                               Bit Banding  */</span></div><div class="line"><a name="l00876"></a><span class="lineno">  876</span>&#160;</div><div class="line"><a name="l00877"></a><span class="lineno">  877</span>&#160;</div><div class="line"><a name="l00878"></a><span class="lineno">  878</span>&#160;<span class="preprocessor">#define BITBAND(reg, bit)               ((0xf0000000 &amp; (uint32_t)(reg)) + 0x2000000 + \</span></div><div class="line"><a name="l00879"></a><span class="lineno">  879</span>&#160;<span class="preprocessor">                                            (((uint32_t)(reg) &amp; 0x0fffffff) &lt;&lt; 5) + ((bit) &lt;&lt; 2))</span></div><div class="line"><a name="l00880"></a><span class="lineno">  880</span>&#160;</div><div class="line"><a name="l00881"></a><span class="lineno">  881</span>&#160;<span class="preprocessor">#define MXC_CLRBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 0)</span></div><div class="line"><a name="l00882"></a><span class="lineno">  882</span>&#160;<span class="preprocessor">#define MXC_SETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit) = 1)</span></div><div class="line"><a name="l00883"></a><span class="lineno">  883</span>&#160;<span class="preprocessor">#define MXC_GETBIT(reg, bit)            (*(volatile uint32_t *)BITBAND(reg, bit))</span></div><div class="line"><a name="l00884"></a><span class="lineno">  884</span>&#160;</div><div class="line"><a name="l00885"></a><span class="lineno">  885</span>&#160;<span class="preprocessor">#define MXC_SETFIELD(reg, mask, setting)  (reg = (reg &amp; ~mask) | (setting &amp; mask))</span></div><div class="line"><a name="l00886"></a><span class="lineno">  886</span>&#160;</div><div class="line"><a name="l00887"></a><span class="lineno">  887</span>&#160;<span class="comment">/******************************************************************************/</span></div><div class="line"><a name="l00888"></a><span class="lineno">  888</span>&#160;<span class="comment">/*                                                                  SCB CPACR */</span></div><div class="line"><a name="l00889"></a><span class="lineno">  889</span>&#160;</div><div class="line"><a name="l00890"></a><span class="lineno">  890</span>&#160;<span class="comment">/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */</span></div><div class="line"><a name="l00891"></a><span class="lineno">  891</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP10_Pos              20                              </span></div><div class="line"><a name="l00892"></a><span class="lineno">  892</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP10_Msk              (0x3UL &lt;&lt; SCB_CPACR_CP10_Pos)   </span></div><div class="line"><a name="l00893"></a><span class="lineno">  893</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP11_Pos              22                              </span></div><div class="line"><a name="l00894"></a><span class="lineno">  894</span>&#160;<span class="preprocessor">#define SCB_CPACR_CP11_Msk              (0x3UL &lt;&lt; SCB_CPACR_CP11_Pos)   </span></div><div class="line"><a name="l00896"></a><span class="lineno">  896</span>&#160;<span class="preprocessor">#endif  </span><span class="comment">/* _MAX32665_REGS_H_ */</span><span class="preprocessor"></span></div></div><!-- fragment --></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
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diff --git a/lib/sdk/Documentation/html/menudata.js b/lib/sdk/Documentation/html/menudata.js
index a78c2806cf8b8b8894d40d043ae0efa7989c7b9f..f09ceea141a779f567e56217b0612d0450d86341 100644
--- a/lib/sdk/Documentation/html/menudata.js
+++ b/lib/sdk/Documentation/html/menudata.js
@@ -21,7 +21,6 @@ var menudata={children:[
 {text:"n",url:"functions_n.html#index_n"},
 {text:"o",url:"functions_o.html#index_o"},
 {text:"p",url:"functions_p.html#index_p"},
-{text:"q",url:"functions_q.html#index_q"},
 {text:"r",url:"functions_r.html#index_r"},
 {text:"s",url:"functions_s.html#index_s"},
 {text:"t",url:"functions_t.html#index_t"},
@@ -44,7 +43,6 @@ var menudata={children:[
 {text:"n",url:"functions_vars_n.html#index_n"},
 {text:"o",url:"functions_vars_o.html#index_o"},
 {text:"p",url:"functions_vars_p.html#index_p"},
-{text:"q",url:"functions_vars_q.html#index_q"},
 {text:"r",url:"functions_vars_r.html#index_r"},
 {text:"s",url:"functions_vars_s.html#index_s"},
 {text:"t",url:"functions_vars_t.html#index_t"},
diff --git a/lib/sdk/Documentation/html/modules.html b/lib/sdk/Documentation/html/modules.html
index 9eb9ab5033d3f90d1cdd5fae08ae12c1f43319ee..b8f87613e1547b14a17d4a52c61d3e8ed2389e7e 100644
--- a/lib/sdk/Documentation/html/modules.html
+++ b/lib/sdk/Documentation/html/modules.html
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+<tr id="row_8_1_13_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__IN__EN.html" target="_self">GPIO_IN_EN</a></td><td class="desc">GPIO Port Input Enable </td></tr>
+<tr id="row_8_1_14_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__INT__EN.html" target="_self">GPIO_INT_EN</a></td><td class="desc">GPIO Interrupt Enable Register </td></tr>
+<tr id="row_8_1_15_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__INT__EN__SET.html" target="_self">GPIO_INT_EN_SET</a></td><td class="desc">GPIO Interrupt Enable Set </td></tr>
+<tr id="row_8_1_16_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__INT__EN__CLR.html" target="_self">GPIO_INT_EN_CLR</a></td><td class="desc">GPIO Interrupt Enable Clear </td></tr>
+<tr id="row_8_1_17_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__INT__STAT.html" target="_self">GPIO_INT_STAT</a></td><td class="desc">GPIO Interrupt Status Register </td></tr>
+<tr id="row_8_1_18_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__INT__CLR.html" target="_self">GPIO_INT_CLR</a></td><td class="desc">GPIO Status Clear </td></tr>
+<tr id="row_8_1_19_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__WAKE__EN.html" target="_self">GPIO_WAKE_EN</a></td><td class="desc">GPIO Wake Enable Register </td></tr>
+<tr id="row_8_1_20_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__WAKE__EN__SET.html" target="_self">GPIO_WAKE_EN_SET</a></td><td class="desc">GPIO Wake Enable Set </td></tr>
+<tr id="row_8_1_21_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__WAKE__EN__CLR.html" target="_self">GPIO_WAKE_EN_CLR</a></td><td class="desc">GPIO Wake Enable Clear </td></tr>
+<tr id="row_8_1_22_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__INT__DUAL__EDGE.html" target="_self">GPIO_INT_DUAL_EDGE</a></td><td class="desc">GPIO Interrupt Dual Edge Mode Register </td></tr>
+<tr id="row_8_1_23_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__PAD__CFG1.html" target="_self">GPIO_PAD_CFG1</a></td><td class="desc">GPIO Input Mode Config 1 </td></tr>
+<tr id="row_8_1_24_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__PAD__CFG2.html" target="_self">GPIO_PAD_CFG2</a></td><td class="desc">GPIO Input Mode Config 2 </td></tr>
+<tr id="row_8_1_25_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__EN1.html" target="_self">GPIO_EN1</a></td><td class="desc">GPIO Alternate Function Enable Register </td></tr>
+<tr id="row_8_1_26_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__EN1__SET.html" target="_self">GPIO_EN1_SET</a></td><td class="desc">GPIO Alternate Function Set </td></tr>
+<tr id="row_8_1_27_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__EN1__CLR.html" target="_self">GPIO_EN1_CLR</a></td><td class="desc">GPIO Alternate Function Clear </td></tr>
+<tr id="row_8_1_28_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__EN2.html" target="_self">GPIO_EN2</a></td><td class="desc">GPIO Alternate Function Enable Register </td></tr>
+<tr id="row_8_1_29_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__EN2__SET.html" target="_self">GPIO_EN2_SET</a></td><td class="desc">GPIO Alternate Function 2 Set </td></tr>
+<tr id="row_8_1_30_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__EN2__CLR.html" target="_self">GPIO_EN2_CLR</a></td><td class="desc">GPIO Wake Alternate Function Clear </td></tr>
+<tr id="row_8_1_31_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__DS.html" target="_self">GPIO_DS</a></td><td class="desc">GPIO Drive Strength Register </td></tr>
+<tr id="row_8_1_32_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__DS1.html" target="_self">GPIO_DS1</a></td><td class="desc">GPIO Drive Strength 1 Register </td></tr>
+<tr id="row_8_1_33_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__PS.html" target="_self">GPIO_PS</a></td><td class="desc">GPIO Pull Select Mode </td></tr>
+<tr id="row_8_1_34_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__GPIO__VSSEL.html" target="_self">GPIO_VSSEL</a></td><td class="desc">GPIO Voltage Select </td></tr>
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+<tr id="row_9_0_1_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__HTMR__SEC.html" target="_self">HTMR_SEC</a></td><td class="desc">HTimer Long-Interval Counter </td></tr>
+<tr id="row_9_0_2_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__HTMR__SSEC.html" target="_self">HTMR_SSEC</a></td><td class="desc">HTimer Short Interval Counter </td></tr>
+<tr id="row_9_0_3_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__HTMR__RAS.html" target="_self">HTMR_RAS</a></td><td class="desc">Long Interval Alarm </td></tr>
+<tr id="row_9_0_4_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__HTMR__RSSA.html" target="_self">HTMR_RSSA</a></td><td class="desc">HTimer Short Interval Alarm </td></tr>
+<tr id="row_9_0_5_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__HTMR__CTRL.html" target="_self">HTMR_CTRL</a></td><td class="desc">HTimer Control Register </td></tr>
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+<tr id="row_16_0_3_" class="even" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__RTC__SSECA.html" target="_self">RTC_SSECA</a></td><td class="desc">RTC sub-second alarm </td></tr>
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@@ -394,6 +399,7 @@ $(document).ready(function(){initNavTree('modules.html','');});
 <tr id="row_20_0_5_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXF__SCLK__FB__CTRL.html" target="_self">SPIXF_SCLK_FB_CTRL</a></td><td class="desc">SPIX Feedback Control Register </td></tr>
 <tr id="row_20_0_6_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXF__IO__CTRL.html" target="_self">SPIXF_IO_CTRL</a></td><td class="desc">SPIX IO Control Register </td></tr>
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+<tr id="row_20_0_8_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXF__BUS__IDLE.html" target="_self">SPIXF_BUS_IDLE</a></td><td class="desc">SPIXF Bus Idle Detection </td></tr>
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@@ -415,14 +421,13 @@ $(document).ready(function(){initNavTree('modules.html','');});
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-<tr id="row_22_0_14_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__WAKEE.html" target="_self">SPIXR_WAKEE</a></td><td class="desc">Register for wake up enable </td></tr>
-<tr id="row_22_0_15_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__STAT.html" target="_self">SPIXR_STAT</a></td><td class="desc">SPI Status register </td></tr>
-<tr id="row_22_0_16_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__XMEM__CTRL.html" target="_self">SPIXR_XMEM_CTRL</a></td><td class="desc">Register to control external memory </td></tr>
+<tr id="row_22_0_9_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__DMA.html" target="_self">SPIXR_DMA</a></td><td class="desc">Register for controlling DMA </td></tr>
+<tr id="row_22_0_10_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__IRQ.html" target="_self">SPIXR_IRQ</a></td><td class="desc">Register for reading and clearing interrupt flags </td></tr>
+<tr id="row_22_0_11_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__IRQE.html" target="_self">SPIXR_IRQE</a></td><td class="desc">Register for enabling interrupts </td></tr>
+<tr id="row_22_0_12_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__WAKE.html" target="_self">SPIXR_WAKE</a></td><td class="desc">Register for wake up flags </td></tr>
+<tr id="row_22_0_13_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__WAKEE.html" target="_self">SPIXR_WAKEE</a></td><td class="desc">Register for wake up enable </td></tr>
+<tr id="row_22_0_14_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__STAT.html" target="_self">SPIXR_STAT</a></td><td class="desc">SPI Status register </td></tr>
+<tr id="row_22_0_15_" style="display:none;"><td class="entry"><span style="width:48px;display:inline-block;">&#160;</span><a class="el" href="group__SPIXR__XMEM__CTRL.html" target="_self">SPIXR_XMEM_CTRL</a></td><td class="desc">Register to control external memory </td></tr>
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diff --git a/lib/sdk/Documentation/html/mxc__sys_8h_source.html b/lib/sdk/Documentation/html/mxc__sys_8h_source.html
index b82eae139bf2827b7959df7fdf2777963c2c0ed6..23b7eb739835682e8085b10bbc730d2f5f74b53f 100644
--- a/lib/sdk/Documentation/html/mxc__sys_8h_source.html
+++ b/lib/sdk/Documentation/html/mxc__sys_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('mxc__sys_8h_source.html','');});
 <div class="title">mxc_sys.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="comment"> * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * $Date: 2019-10-25 14:21:06 -0500 (Fri, 25 Oct 2019) $</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * $Revision: 48094 $</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> ******************************************************************************/</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="preprocessor">#ifndef _MXC_SYS_H_</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#define _MXC_SYS_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;</div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#include &quot;uart_regs.h&quot;</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;i2c_regs.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;ptg_regs.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="preprocessor">#include &quot;pt_regs.h&quot;</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#include &quot;gcr_regs.h&quot;</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">#include &quot;tmr_regs.h&quot;</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#include &quot;gpio.h&quot;</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="preprocessor">#include &quot;sdhc_regs.h&quot;</span></div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#include &quot;flc_regs.h&quot;</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">#include &quot;spixfc_regs.h&quot;</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#include &quot;spi17y_regs.h&quot;</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="preprocessor">#include &quot;htmr_regs.h&quot;</span></div><div class="line"><a name="l00058"></a><span class="lineno">   58</span>&#160;<span class="preprocessor">#include &quot;wdt_regs.h&quot;</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="preprocessor">#include &quot;dma.h&quot;</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;    SYS_RESET_DMA       = MXC_F_GCR_RSTR0_DMA_POS,         </div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;    SYS_RESET_WDT       = MXC_F_GCR_RSTR0_WDT_POS,         </div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;    SYS_RESET_GPIO0     = MXC_F_GCR_RSTR0_GPIO0_POS,       </div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;    SYS_RESET_GPIO1     = MXC_F_GCR_RSTR0_GPIO1_POS,       </div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;    SYS_RESET_TIMER0    = MXC_F_GCR_RSTR0_TIMER0_POS,      </div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;    SYS_RESET_TIMER1    = MXC_F_GCR_RSTR0_TIMER1_POS,      </div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;    SYS_RESET_TIMER2    = MXC_F_GCR_RSTR0_TIMER2_POS,      </div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;    SYS_RESET_TIMER3    = MXC_F_GCR_RSTR0_TIMER3_POS,      </div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;    SYS_RESET_TIMER4    = MXC_F_GCR_RSTR0_TIMER4_POS,      </div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;    SYS_RESET_TIMER5    = MXC_F_GCR_RSTR0_TIMER5_POS,      </div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;    SYS_RESET_UART0     = MXC_F_GCR_RSTR0_UART0_POS,       </div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;    SYS_RESET_UART1     = MXC_F_GCR_RSTR0_UART1_POS,       </div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;    SYS_RESET_SPI1      = MXC_F_GCR_RSTR0_SPI0_POS,        </div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;    SYS_RESET_SPI2      = MXC_F_GCR_RSTR0_SPI1_POS,        </div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;    SYS_RESET_I2C0      = MXC_F_GCR_RSTR0_I2C0_POS,        </div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;    SYS_RESET_RTC       = MXC_F_GCR_RSTR0_RTC_POS,         </div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;    SYS_RESET_CRYPTO    = MXC_F_GCR_RSTR0_CRYPTO_POS,      </div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;    SYS_RESET_USB       = MXC_F_GCR_RSTR0_USB_POS,         </div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;    SYS_RESET_TRNG      = MXC_F_GCR_RSTR0_TRNG_POS,        </div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;    SYS_RESET_ADC       = MXC_F_GCR_RSTR0_ADC_POS,         </div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;    SYS_RESET_UART2     = MXC_F_GCR_RSTR0_UART2_POS,       </div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;    SYS_RESET_SRST      = MXC_F_GCR_RSTR0_SRST_POS,        </div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;    SYS_RESET_PRST      = MXC_F_GCR_RSTR0_PRST_POS,        </div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;    SYS_RESET_SYSTEM    = MXC_F_GCR_RSTR0_SYSTEM_POS,      </div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;    <span class="comment">/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    SYS_RESET_I2C1      = (MXC_F_GCR_RSTR1_I2C1_POS + 32),        </div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    SYS_RESET_PT        = (MXC_F_GCR_RSTR1_PT_POS + 32),          </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    SYS_RESET_SPIXIP    = (MXC_F_GCR_RSTR1_SPIXIP_POS + 32),      </div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;    SYS_RESET_XSPIM     = (MXC_F_GCR_RSTR1_XSPIM_POS + 32),       </div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;    SYS_RESET_SDHC      = (MXC_F_GCR_RSTR1_SDHC_POS + 32),        </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    SYS_RESET_OWIRE     = (MXC_F_GCR_RSTR1_OWIRE_POS + 32),       </div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;    SYS_RESET_HTR0      = (MXC_F_GCR_RSTR1_HTMR0_POS + 32),        </div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;    SYS_RESET_HTMR1     = (MXC_F_GCR_RSTR1_HTMR1_POS + 32),        </div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;    SYS_RESET_WDT1      = (MXC_F_GCR_RSTR1_WDT1_POS + 32),        </div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    SYS_RESET_SPI0      = (MXC_F_GCR_RSTR1_QSPI0_AHB_POS + 32),   </div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;    SYS_RESET_SPIXMEM   = (MXC_F_GCR_RSTR1_SPIXMEM_POS + 32),     </div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    SYS_RESET_SMPHR     = (MXC_F_GCR_RSTR1_SMPHR_POS + 32)        </div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;} sys_reset_t;</div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;</div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    SYS_PERIPH_CLOCK_GPIO0       = MXC_F_GCR_PERCKCN0_GPIO0D_POS,                    </div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;    SYS_PERIPH_CLOCK_GPIO1       = MXC_F_GCR_PERCKCN0_GPIO1D_POS,                    </div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    SYS_PERIPH_CLOCK_USB         = MXC_F_GCR_PERCKCN0_USBD_POS,                      </div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    SYS_PERIPH_CLOCK_DMA         = MXC_F_GCR_PERCKCN0_DMAD_POS,                      </div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    SYS_PERIPH_CLOCK_SPI1        = MXC_F_GCR_PERCKCN0_SPI0D_POS,                     </div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;    SYS_PERIPH_CLOCK_SPI2        = MXC_F_GCR_PERCKCN0_SPI1D_POS,                     </div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    SYS_PERIPH_CLOCK_UART0       = MXC_F_GCR_PERCKCN0_UART0D_POS,                    </div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;    SYS_PERIPH_CLOCK_UART1       = MXC_F_GCR_PERCKCN0_UART1D_POS,                    </div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    SYS_PERIPH_CLOCK_I2C0        = MXC_F_GCR_PERCKCN0_I2C0D_POS,                     </div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;    SYS_PERIPH_CLOCK_TPU         = MXC_F_GCR_PERCKCN0_CRYPTOD_POS,                   </div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    SYS_PERIPH_CLOCK_T0          = MXC_F_GCR_PERCKCN0_T0D_POS,                       </div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;    SYS_PERIPH_CLOCK_T1          = MXC_F_GCR_PERCKCN0_T1D_POS,                       </div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    SYS_PERIPH_CLOCK_T2          = MXC_F_GCR_PERCKCN0_T2D_POS,                       </div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    SYS_PERIPH_CLOCK_T3          = MXC_F_GCR_PERCKCN0_T3D_POS,                       </div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    SYS_PERIPH_CLOCK_T4          = MXC_F_GCR_PERCKCN0_T4D_POS,                       </div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;    SYS_PERIPH_CLOCK_T5          = MXC_F_GCR_PERCKCN0_T5D_POS,                       </div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    SYS_PERIPH_CLOCK_ADC         = MXC_F_GCR_PERCKCN0_ADCD_POS,                      </div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;    SYS_PERIPH_CLOCK_I2C1        = MXC_F_GCR_PERCKCN0_I2C1D_POS,                     </div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    SYS_PERIPH_CLOCK_PT          = MXC_F_GCR_PERCKCN0_PTD_POS,                       </div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    SYS_PERIPH_CLOCK_SPIXIP      = MXC_F_GCR_PERCKCN0_SPIXIPD_POS,                   </div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    SYS_PERIPH_CLOCK_SPIXFC       = MXC_F_GCR_PERCKCN0_SPIMD_POS,                     </div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;    <span class="comment">/* PERCKCN1 Below this line we add 32 to separate PERCKCN0 and PERCKCN1 */</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    SYS_PERIPH_CLOCK_BTLE        =(MXC_F_GCR_PERCKCN1_BTLED_POS + 32),</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;    SYS_PERIPH_CLOCK_UART2       =(MXC_F_GCR_PERCKCN1_UART2D_POS + 32),            </div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    SYS_PERIPH_CLOCK_TRNG        =(MXC_F_GCR_PERCKCN1_TRNGD_POS + 32),             </div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;    SYS_PERIPH_CLOCK_SCACHE      =(MXC_F_GCR_PERCKCN1_SCACHED_POS + 32),           </div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;    SYS_PERIPH_CLOCK_SDMA        =(MXC_F_GCR_PERCKCN1_SDMAD_POS + 32),             </div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;    SYS_PERIPH_CLOCK_SMPHR       =(MXC_F_GCR_PERCKCN1_SMPHRD_POS + 32),            </div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;    SYS_PERIPH_CLOCK_SDHC        =(MXC_F_GCR_PERCKCN1_SDHCD_POS + 32),             </div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;    SYS_PERIPH_CLOCK_ICACHEXIP   =(MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS + 32),        </div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;    SYS_PERIPH_CLOCK_OWIRE       =(MXC_F_GCR_PERCKCN1_OWIRED_POS + 32),            </div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;    SYS_PERIPH_CLOCK_SPI0        =(MXC_F_GCR_PERCKCN1_SPI3D_POS + 32),             </div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;    SYS_PERIPH_CLOCK_SPIXIPD     =(MXC_F_GCR_PERCKCN1_SPIXIPDD_POS + 32),</div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;    SYS_PERIPH_CLOCK_DMA1        =(MXC_F_GCR_PERCKCN1_DMA1_POS + 32),</div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;    SYS_PERIPH_CLOCK_AUDIO       =(MXC_F_GCR_PERCKCN1_AUDIO_POS + 32),</div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;    SYS_PERIPH_CLOCK_I2C2        =(MXC_F_GCR_PERCKCN1_I2C2_POS + 32),</div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;    SYS_PERIPH_CLOCK_HTMR0       =(MXC_F_GCR_PERCKCN1_HTMR0_POS + 32),           </div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;    SYS_PERIPH_CLOCK_HTMR1       =(MXC_F_GCR_PERCKCN1_HTMR1_POS + 32),           </div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;    SYS_PERIPH_CLOCK_WDT0        =(MXC_F_GCR_PERCKCN1_WDT0_POS + 32),</div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;    SYS_PERIPH_CLOCK_WDT1        =(MXC_F_GCR_PERCKCN1_WDT1_POS + 32),</div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;    SYS_PERIPH_CLOCK_WDT2        =(MXC_F_GCR_PERCKCN1_WDT2_POS + 32),</div><div class="line"><a name="l00149"></a><span class="lineno">  149</span>&#160;    SYS_PERIPH_CLOCK_CPU1        =(MXC_F_GCR_PERCKCN1_CPU1_POS + 32) </div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;} sys_periph_clock_t;</div><div class="line"><a name="l00151"></a><span class="lineno">  151</span>&#160;</div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;    SYS_CLOCK_HIRC96    = MXC_V_GCR_CLKCN_CLKSEL_HIRC96,</div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;    SYS_CLOCK_HIRC8     = MXC_V_GCR_CLKCN_CLKSEL_HIRC8,</div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;    SYS_CLOCK_HIRC      = MXC_V_GCR_CLKCN_CLKSEL_HIRC,</div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;    SYS_CLOCK_XTAL32M   = MXC_V_GCR_CLKCN_CLKSEL_XTAL32M,</div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;    SYS_CLOCK_LIRC8K    = MXC_V_GCR_CLKCN_CLKSEL_LIRC8,</div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;    SYS_CLOCK_XTAL32K   = MXC_V_GCR_CLKCN_CLKSEL_XTAL32K </div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;} sys_system_clock_t;</div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;</div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;<span class="preprocessor">#define SYS_SCACHE_CLK 1  // Enable SCACHE CLK</span></div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;<span class="preprocessor">#define SYS_CRYPTO_CLK 1  // Enable CRYPTO CLK</span></div><div class="line"><a name="l00163"></a><span class="lineno">  163</span>&#160;</div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;<span class="preprocessor">#define SYS_USN_CHECKSUM_LEN    16</span></div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;</div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;    MAP_A,</div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;    MAP_B</div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;} sys_map_t;</div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00173"></a><span class="lineno">  173</span>&#160;    Disable,</div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;    Enable</div><div class="line"><a name="l00175"></a><span class="lineno">  175</span>&#160;} sys_control_t;</div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;<span class="keyword">typedef</span> <span class="keywordtype">void</span>* sys_cfg_t;</div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;</div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="structsys__cfg__spi17y__t.html">  179</a></span>&#160;<span class="keyword">typedef</span>  <span class="keyword">struct </span></div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;{</div><div class="line"><a name="l00181"></a><span class="lineno">  181</span>&#160;    sys_map_t map;</div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;    sys_control_t ss0;   </div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;    sys_control_t ss1;   </div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;    sys_control_t ss2;   </div><div class="line"><a name="l00185"></a><span class="lineno">  185</span>&#160;} <a class="code" href="structsys__cfg__spi17y__t.html">sys_cfg_spi17y_t</a>;</div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;</div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="structsys__cfg__uart__t.html">  188</a></span>&#160;<span class="keyword">typedef</span>  <span class="keyword">struct </span></div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;{</div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;    sys_map_t map;</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;    sys_control_t flow; </div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;} <a class="code" href="structsys__cfg__uart__t.html">sys_cfg_uart_t</a>;</div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;</div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="structsys__cfg__spixr__t.html">  195</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct</span></div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;{</div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;    uint8_t scache_flag;</div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;    uint8_t crypto_flag;</div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;} <a class="code" href="structsys__cfg__spixr__t.html">sys_cfg_spixr_t</a>;</div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;</div><div class="line"><a name="l00201"></a><span class="lineno">  201</span>&#160;</div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_i2c_t; </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_sdhc_t; </div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;</div><div class="line"><a name="l00209"></a><span class="lineno">  209</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_owm_t; </div><div class="line"><a name="l00210"></a><span class="lineno">  210</span>&#160;</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_scache_t; </div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;</div><div class="line"><a name="l00215"></a><span class="lineno">  215</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_usbhs_t; </div><div class="line"><a name="l00216"></a><span class="lineno">  216</span>&#160;</div><div class="line"><a name="l00218"></a><span class="lineno">  218</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_rtc_t; </div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;</div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_tpu_t; </div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;</div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_tmr_t; </div><div class="line"><a name="l00225"></a><span class="lineno">  225</span>&#160;</div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_adc_t; </div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;</div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_flc_t; </div><div class="line"><a name="l00231"></a><span class="lineno">  231</span>&#160;</div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_trng_t; </div><div class="line"><a name="l00234"></a><span class="lineno">  234</span>&#160;</div><div class="line"><a name="l00236"></a><span class="lineno">  236</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_spixfc_t;</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;</div><div class="line"><a name="l00239"></a><span class="lineno">  239</span>&#160;<span class="keyword">typedef</span> <a class="code" href="structgpio__cfg__t.html">gpio_cfg_t</a> <a class="code" href="structgpio__cfg__t.html">sys_cfg_pt_t</a>;</div><div class="line"><a name="l00240"></a><span class="lineno">  240</span>&#160;</div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_ptg_t;</div><div class="line"><a name="l00243"></a><span class="lineno">  243</span>&#160;</div><div class="line"><a name="l00245"></a><span class="lineno">  245</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_htmr_t;</div><div class="line"><a name="l00246"></a><span class="lineno">  246</span>&#160;</div><div class="line"><a name="l00248"></a><span class="lineno">  248</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_sema_t;</div><div class="line"><a name="l00249"></a><span class="lineno">  249</span>&#160;</div><div class="line"><a name="l00251"></a><span class="lineno">  251</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_wdt_t;</div><div class="line"><a name="l00252"></a><span class="lineno">  252</span>&#160;</div><div class="line"><a name="l00254"></a><span class="lineno">  254</span>&#160;<span class="keyword">typedef</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> sys_pt_clk_scale;</div><div class="line"><a name="l00255"></a><span class="lineno">  255</span>&#160;  </div><div class="line"><a name="l00256"></a><span class="lineno">  256</span>&#160;<span class="comment">/***** Function Prototypes *****/</span></div><div class="line"><a name="l00257"></a><span class="lineno">  257</span>&#160;</div><div class="line"><a name="l00265"></a><span class="lineno">  265</span>&#160;<span class="keywordtype">int</span> SYS_GetUSN(uint8_t *usn, uint8_t *checksum);</div><div class="line"><a name="l00266"></a><span class="lineno">  266</span>&#160;</div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;<span class="keywordtype">int</span> SYS_IsClockEnabled(sys_periph_clock_t clock);</div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;</div><div class="line"><a name="l00278"></a><span class="lineno">  278</span>&#160;<span class="keywordtype">void</span> SYS_ClockDisable(sys_periph_clock_t clock);</div><div class="line"><a name="l00279"></a><span class="lineno">  279</span>&#160;</div><div class="line"><a name="l00284"></a><span class="lineno">  284</span>&#160;<span class="keywordtype">void</span> SYS_ClockEnable(sys_periph_clock_t clock);</div><div class="line"><a name="l00285"></a><span class="lineno">  285</span>&#160;</div><div class="line"><a name="l00290"></a><span class="lineno">  290</span>&#160;<span class="keywordtype">void</span> SYS_RTCClockEnable(sys_cfg_rtc_t *sys_cfg);</div><div class="line"><a name="l00291"></a><span class="lineno">  291</span>&#160;</div><div class="line"><a name="l00296"></a><span class="lineno">  296</span>&#160;<span class="keywordtype">int</span> SYS_RTCClockDisable(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00297"></a><span class="lineno">  297</span>&#160;  </div><div class="line"><a name="l00303"></a><span class="lineno">  303</span>&#160;<span class="keywordtype">int</span> SYS_ClockSourceEnable(sys_system_clock_t clock);</div><div class="line"><a name="l00304"></a><span class="lineno">  304</span>&#160;</div><div class="line"><a name="l00310"></a><span class="lineno">  310</span>&#160;<span class="keywordtype">int</span> SYS_ClockSourceDisable(sys_system_clock_t clock);</div><div class="line"><a name="l00311"></a><span class="lineno">  311</span>&#160;</div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;<span class="keywordtype">int</span> SYS_Clock_Select(sys_system_clock_t clock, <a class="code" href="structmxc__tmr__regs__t.html">mxc_tmr_regs_t</a>* tmr);</div><div class="line"><a name="l00319"></a><span class="lineno">  319</span>&#160;</div><div class="line"><a name="l00326"></a><span class="lineno">  326</span>&#160;<span class="keywordtype">int</span> SYS_UART_Init(<a class="code" href="structmxc__uart__regs__t.html">mxc_uart_regs_t</a> *uart, <span class="keyword">const</span> <a class="code" href="structsys__cfg__uart__t.html">sys_cfg_uart_t</a>* sys_cfg);</div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;</div><div class="line"><a name="l00334"></a><span class="lineno">  334</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__uart.html#ga5262e16899bd46be969661cc9bf89492">SYS_UART_Shutdown</a>(<a class="code" href="structmxc__uart__regs__t.html">mxc_uart_regs_t</a> *uart);</div><div class="line"><a name="l00335"></a><span class="lineno">  335</span>&#160;</div><div class="line"><a name="l00336"></a><span class="lineno">  336</span>&#160;</div><div class="line"><a name="l00343"></a><span class="lineno">  343</span>&#160;<span class="keywordtype">int</span> SYS_I2C_Init(<a class="code" href="structmxc__i2c__regs__t.html">mxc_i2c_regs_t</a> *i2c, <span class="keyword">const</span> sys_cfg_i2c_t* sys_cfg);</div><div class="line"><a name="l00344"></a><span class="lineno">  344</span>&#160;</div><div class="line"><a name="l00350"></a><span class="lineno">  350</span>&#160;<span class="keywordtype">int</span> SYS_I2C_Shutdown(<a class="code" href="structmxc__i2c__regs__t.html">mxc_i2c_regs_t</a> *i2c);</div><div class="line"><a name="l00351"></a><span class="lineno">  351</span>&#160;</div><div class="line"><a name="l00357"></a><span class="lineno">  357</span>&#160;<span class="keywordtype">unsigned</span> SYS_I2C_GetFreq(<a class="code" href="structmxc__i2c__regs__t.html">mxc_i2c_regs_t</a> *i2c);</div><div class="line"><a name="l00358"></a><span class="lineno">  358</span>&#160;</div><div class="line"><a name="l00364"></a><span class="lineno">  364</span>&#160;<span class="keywordtype">int</span> SYS_PT_Config(<a class="code" href="structmxc__pt__regs__t.html">mxc_pt_regs_t</a> *pt, <span class="keyword">const</span> sys_cfg_pt_t *cfg);</div><div class="line"><a name="l00365"></a><span class="lineno">  365</span>&#160;</div><div class="line"><a name="l00370"></a><span class="lineno">  370</span>&#160;<span class="keywordtype">void</span> SYS_PT_Init(<span class="keyword">const</span> sys_cfg_ptg_t* sys_cfg);</div><div class="line"><a name="l00371"></a><span class="lineno">  371</span>&#160;</div><div class="line"><a name="l00375"></a><span class="lineno">  375</span>&#160;<span class="keywordtype">void</span> SYS_PT_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00376"></a><span class="lineno">  376</span>&#160;</div><div class="line"><a name="l00381"></a><span class="lineno">  381</span>&#160;<span class="keywordtype">unsigned</span> SYS_PT_GetFreq(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00382"></a><span class="lineno">  382</span>&#160;</div><div class="line"><a name="l00387"></a><span class="lineno">  387</span>&#160;<span class="keywordtype">unsigned</span> SYS_TMR_GetFreq(<a class="code" href="structmxc__tmr__regs__t.html">mxc_tmr_regs_t</a> *tmr);</div><div class="line"><a name="l00391"></a><span class="lineno">  391</span>&#160;<span class="keywordtype">void</span> SYS_Flash_Operation(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00396"></a><span class="lineno">  396</span>&#160;<span class="keywordtype">void</span> SYS_Reset_Periph(sys_reset_t reset);</div><div class="line"><a name="l00402"></a><span class="lineno">  402</span>&#160;<span class="keywordtype">int</span> SYS_SDHC_Init(<span class="keyword">const</span> sys_cfg_sdhc_t* sys_cfg);</div><div class="line"><a name="l00403"></a><span class="lineno">  403</span>&#160;</div><div class="line"><a name="l00408"></a><span class="lineno">  408</span>&#160;<span class="keywordtype">int</span> SYS_SDHC_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00409"></a><span class="lineno">  409</span>&#160;</div><div class="line"><a name="l00414"></a><span class="lineno">  414</span>&#160;<span class="keywordtype">int</span> SYS_SEMA_Init(<span class="keyword">const</span> sys_cfg_sema_t* sys_cfg);</div><div class="line"><a name="l00415"></a><span class="lineno">  415</span>&#160;</div><div class="line"><a name="l00420"></a><span class="lineno">  420</span>&#160;<span class="keywordtype">int</span> SYS_SEMA_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00421"></a><span class="lineno">  421</span>&#160;</div><div class="line"><a name="l00428"></a><span class="lineno">  428</span>&#160;<span class="keywordtype">int</span> SYS_SPIXFC_Init(<a class="code" href="structmxc__spixfc__regs__t.html">mxc_spixfc_regs_t</a> *spixfc, <span class="keyword">const</span> sys_cfg_spixfc_t* sys_cfg);</div><div class="line"><a name="l00429"></a><span class="lineno">  429</span>&#160;</div><div class="line"><a name="l00435"></a><span class="lineno">  435</span>&#160;<span class="keywordtype">int</span> SYS_SPIXFC_Shutdown(<a class="code" href="structmxc__spixfc__regs__t.html">mxc_spixfc_regs_t</a> *spixfc);</div><div class="line"><a name="l00436"></a><span class="lineno">  436</span>&#160;</div><div class="line"><a name="l00437"></a><span class="lineno">  437</span>&#160;</div><div class="line"><a name="l00443"></a><span class="lineno">  443</span>&#160;<span class="keywordtype">int</span> SYS_SPIXFC_GetFreq(<a class="code" href="structmxc__spixfc__regs__t.html">mxc_spixfc_regs_t</a> *spixfc);</div><div class="line"><a name="l00444"></a><span class="lineno">  444</span>&#160;</div><div class="line"><a name="l00445"></a><span class="lineno">  445</span>&#160;</div><div class="line"><a name="l00451"></a><span class="lineno">  451</span>&#160;uint32_t SYS_OWM_Init(<span class="keyword">const</span> sys_cfg_owm_t* sys_cfg);</div><div class="line"><a name="l00452"></a><span class="lineno">  452</span>&#160;</div><div class="line"><a name="l00456"></a><span class="lineno">  456</span>&#160;<span class="keywordtype">void</span> SYS_OWM_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00457"></a><span class="lineno">  457</span>&#160;</div><div class="line"><a name="l00462"></a><span class="lineno">  462</span>&#160;uint32_t SYS_OWM_GetFreq(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00463"></a><span class="lineno">  463</span>&#160;</div><div class="line"><a name="l00469"></a><span class="lineno">  469</span>&#160;<span class="keywordtype">int</span> SYS_SPIXR_Init(<span class="keyword">const</span> <a class="code" href="structsys__cfg__spixr__t.html">sys_cfg_spixr_t</a>* sys_cfg);</div><div class="line"><a name="l00470"></a><span class="lineno">  470</span>&#160;</div><div class="line"><a name="l00474"></a><span class="lineno">  474</span>&#160;<span class="keywordtype">void</span> SYS_SPIXR_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00475"></a><span class="lineno">  475</span>&#160;</div><div class="line"><a name="l00480"></a><span class="lineno">  480</span>&#160;<span class="keywordtype">void</span> SYS_SCACHE_Init(<span class="keyword">const</span> sys_cfg_scache_t* sys_cfg);</div><div class="line"><a name="l00481"></a><span class="lineno">  481</span>&#160;</div><div class="line"><a name="l00485"></a><span class="lineno">  485</span>&#160;<span class="keywordtype">void</span> SYS_SCACHE_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00486"></a><span class="lineno">  486</span>&#160;</div><div class="line"><a name="l00487"></a><span class="lineno">  487</span>&#160;</div><div class="line"><a name="l00493"></a><span class="lineno">  493</span>&#160;<span class="keywordtype">int</span> SYS_SPI17Y_Init( <a class="code" href="structmxc__spi17y__regs__t.html">mxc_spi17y_regs_t</a> *spi, <span class="keyword">const</span> <a class="code" href="structsys__cfg__spi17y__t.html">sys_cfg_spi17y_t</a>* sys_cfg);</div><div class="line"><a name="l00494"></a><span class="lineno">  494</span>&#160;</div><div class="line"><a name="l00499"></a><span class="lineno">  499</span>&#160;<span class="keywordtype">int</span> SYS_SPI17Y_Shutdown(<a class="code" href="structmxc__spi17y__regs__t.html">mxc_spi17y_regs_t</a> *spi);</div><div class="line"><a name="l00500"></a><span class="lineno">  500</span>&#160;</div><div class="line"><a name="l00505"></a><span class="lineno">  505</span>&#160;<span class="keywordtype">void</span> SYS_RTC_SqwavInit(<span class="keyword">const</span> sys_cfg_rtc_t* sys_cfg);</div><div class="line"><a name="l00506"></a><span class="lineno">  506</span>&#160;</div><div class="line"><a name="l00507"></a><span class="lineno">  507</span>&#160;</div><div class="line"><a name="l00512"></a><span class="lineno">  512</span>&#160;<span class="keywordtype">int</span> SYS_USBHS_Init(<span class="keyword">const</span> sys_cfg_usbhs_t* sys_cfg);</div><div class="line"><a name="l00513"></a><span class="lineno">  513</span>&#160;</div><div class="line"><a name="l00518"></a><span class="lineno">  518</span>&#160;<span class="keywordtype">int</span> SYS_USBHS_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00522"></a><span class="lineno">  522</span>&#160;<span class="keywordtype">void</span> SYS_DMA_Init(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00523"></a><span class="lineno">  523</span>&#160;</div><div class="line"><a name="l00527"></a><span class="lineno">  527</span>&#160;<span class="keywordtype">void</span> SYS_DMA_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00528"></a><span class="lineno">  528</span>&#160;</div><div class="line"><a name="l00533"></a><span class="lineno">  533</span>&#160;<span class="keywordtype">int</span> SYS_TMR_Init(<a class="code" href="structmxc__tmr__regs__t.html">mxc_tmr_regs_t</a> *tmr, <span class="keyword">const</span> sys_cfg_tmr_t* sys_cfg);</div><div class="line"><a name="l00534"></a><span class="lineno">  534</span>&#160;</div><div class="line"><a name="l00538"></a><span class="lineno">  538</span>&#160;<span class="keywordtype">int</span> SYS_TMR_Shutdown(<a class="code" href="structmxc__tmr__regs__t.html">mxc_tmr_regs_t</a> *tmr);</div><div class="line"><a name="l00539"></a><span class="lineno">  539</span>&#160;</div><div class="line"><a name="l00544"></a><span class="lineno">  544</span>&#160;<span class="keywordtype">int</span> SYS_TPU_Init(<span class="keyword">const</span> sys_cfg_tpu_t* sys_cfg);</div><div class="line"><a name="l00545"></a><span class="lineno">  545</span>&#160;</div><div class="line"><a name="l00549"></a><span class="lineno">  549</span>&#160;<span class="keywordtype">int</span> SYS_TPU_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00550"></a><span class="lineno">  550</span>&#160;</div><div class="line"><a name="l00555"></a><span class="lineno">  555</span>&#160;<span class="keywordtype">int</span> SYS_ADC_Init(<span class="keyword">const</span> sys_cfg_adc_t* sys_cfg);</div><div class="line"><a name="l00556"></a><span class="lineno">  556</span>&#160;</div><div class="line"><a name="l00560"></a><span class="lineno">  560</span>&#160;<span class="keywordtype">int</span> SYS_ADC_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00561"></a><span class="lineno">  561</span>&#160;</div><div class="line"><a name="l00565"></a><span class="lineno">  565</span>&#160;<span class="keywordtype">int</span> SYS_FLC_Init(<span class="keyword">const</span> sys_cfg_flc_t* sys_cfg);</div><div class="line"><a name="l00574"></a><span class="lineno">  574</span>&#160;<span class="keywordtype">int</span> SYS_FLC_GetByAddress(<a class="code" href="structmxc__flc__regs__t.html">mxc_flc_regs_t</a> **flc, uint32_t addr);</div><div class="line"><a name="l00575"></a><span class="lineno">  575</span>&#160;</div><div class="line"><a name="l00584"></a><span class="lineno">  584</span>&#160;<span class="keywordtype">int</span> SYS_FLC_GetPhysicalAddress( uint32_t addr, uint32_t *result);</div><div class="line"><a name="l00585"></a><span class="lineno">  585</span>&#160;</div><div class="line"><a name="l00589"></a><span class="lineno">  589</span>&#160;<span class="keywordtype">int</span> SYS_FLC_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00590"></a><span class="lineno">  590</span>&#160;</div><div class="line"><a name="l00595"></a><span class="lineno">  595</span>&#160;<span class="keywordtype">int</span> SYS_TRNG_Init(<span class="keyword">const</span> sys_cfg_trng_t* sys_cfg);</div><div class="line"><a name="l00596"></a><span class="lineno">  596</span>&#160;</div><div class="line"><a name="l00600"></a><span class="lineno">  600</span>&#160;<span class="keywordtype">int</span> SYS_TRNG_Shutdown(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00601"></a><span class="lineno">  601</span>&#160;</div><div class="line"><a name="l00606"></a><span class="lineno">  606</span>&#160;<span class="keywordtype">int</span> SYS_HTMR_Init(<a class="code" href="structmxc__htmr__regs__t.html">mxc_htmr_regs_t</a> *htmr);</div><div class="line"><a name="l00607"></a><span class="lineno">  607</span>&#160;</div><div class="line"><a name="l00612"></a><span class="lineno">  612</span>&#160;<span class="keywordtype">int</span> SYS_HTMR_Shutdown(<a class="code" href="structmxc__htmr__regs__t.html">mxc_htmr_regs_t</a> *htmr);</div><div class="line"><a name="l00613"></a><span class="lineno">  613</span>&#160;</div><div class="line"><a name="l00619"></a><span class="lineno">  619</span>&#160;<span class="keywordtype">int</span> SYS_WDT_Init(<a class="code" href="structmxc__wdt__regs__t.html">mxc_wdt_regs_t</a> *wdt, <span class="keyword">const</span> sys_cfg_wdt_t* sys_cfg);</div><div class="line"><a name="l00620"></a><span class="lineno">  620</span>&#160;</div><div class="line"><a name="l00625"></a><span class="lineno">  625</span>&#160;uint32_t SYS_WUT_GetFreq(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00626"></a><span class="lineno">  626</span>&#160;</div><div class="line"><a name="l00627"></a><span class="lineno">  627</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00628"></a><span class="lineno">  628</span>&#160;}</div><div class="line"><a name="l00629"></a><span class="lineno">  629</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00630"></a><span class="lineno">  630</span>&#160;</div><div class="line"><a name="l00631"></a><span class="lineno">  631</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _MXC_SYS_H_*/</span><span class="preprocessor"></span></div><div class="ttc" id="structgpio__cfg__t_html"><div class="ttname"><a href="structgpio__cfg__t.html">gpio_cfg_t</a></div><div class="ttdoc">Structure type for configuring a GPIO port. </div><div class="ttdef"><b>Definition:</b> gpio.h:138</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;<span class="comment">/*******************************************************************************</span></div><div class="line"><a name="l00002"></a><span class="lineno">    2</span>&#160;<span class="comment"> * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00003"></a><span class="lineno">    3</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00004"></a><span class="lineno">    4</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00005"></a><span class="lineno">    5</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * $Date: 2020-01-16 08:38:14 -0600 (Thu, 16 Jan 2020) $</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * $Revision: 50696 $</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> ******************************************************************************/</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="preprocessor">#ifndef _MXC_SYS_H_</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#define _MXC_SYS_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;</div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#include &quot;uart_regs.h&quot;</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;i2c_regs.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;ptg_regs.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="preprocessor">#include &quot;pt_regs.h&quot;</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#include &quot;gcr_regs.h&quot;</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">#include &quot;tmr_regs.h&quot;</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#include &quot;gpio.h&quot;</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="preprocessor">#include &quot;sdhc_regs.h&quot;</span></div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#include &quot;flc_regs.h&quot;</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">#include &quot;spixfc_regs.h&quot;</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#include &quot;spi17y_regs.h&quot;</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="preprocessor">#include &quot;htmr_regs.h&quot;</span></div><div class="line"><a name="l00058"></a><span class="lineno">   58</span>&#160;<span class="preprocessor">#include &quot;wdt_regs.h&quot;</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="preprocessor">#include &quot;dma.h&quot;</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;    SYS_RESET_DMA       = MXC_F_GCR_RSTR0_DMA_POS,         </div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;    SYS_RESET_WDT       = MXC_F_GCR_RSTR0_WDT0_POS,         </div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;    SYS_RESET_GPIO0     = MXC_F_GCR_RSTR0_GPIO0_POS,       </div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;    SYS_RESET_GPIO1     = MXC_F_GCR_RSTR0_GPIO1_POS,       </div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;    SYS_RESET_TIMER0    = MXC_F_GCR_RSTR0_TIMER0_POS,      </div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;    SYS_RESET_TIMER1    = MXC_F_GCR_RSTR0_TIMER1_POS,      </div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;    SYS_RESET_TIMER2    = MXC_F_GCR_RSTR0_TIMER2_POS,      </div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;    SYS_RESET_TIMER3    = MXC_F_GCR_RSTR0_TIMER3_POS,      </div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;    SYS_RESET_TIMER4    = MXC_F_GCR_RSTR0_TIMER4_POS,      </div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;    SYS_RESET_TIMER5    = MXC_F_GCR_RSTR0_TIMER5_POS,      </div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;    SYS_RESET_UART0     = MXC_F_GCR_RSTR0_UART0_POS,       </div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;    SYS_RESET_UART1     = MXC_F_GCR_RSTR0_UART1_POS,       </div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;    SYS_RESET_SPI1      = MXC_F_GCR_RSTR0_SPI1_POS,        </div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;    SYS_RESET_SPI2      = MXC_F_GCR_RSTR0_SPI2_POS,        </div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;    SYS_RESET_I2C0      = MXC_F_GCR_RSTR0_I2C0_POS,        </div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;    SYS_RESET_RTC       = MXC_F_GCR_RSTR0_RTC_POS,         </div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;    SYS_RESET_CRYPTO    = MXC_F_GCR_RSTR0_CRYPTO_POS,      </div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;    SYS_RESET_USB       = MXC_F_GCR_RSTR0_USB_POS,         </div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;    SYS_RESET_TRNG      = MXC_F_GCR_RSTR0_TRNG_POS,        </div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;    SYS_RESET_ADC       = MXC_F_GCR_RSTR0_ADC_POS,         </div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;    SYS_RESET_UART2     = MXC_F_GCR_RSTR0_UART2_POS,       </div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;    SYS_RESET_SRST      = MXC_F_GCR_RSTR0_SRST_POS,        </div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;    SYS_RESET_PRST      = MXC_F_GCR_RSTR0_PRST_POS,        </div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;    SYS_RESET_SYSTEM    = MXC_F_GCR_RSTR0_SYSTEM_POS,      </div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;    <span class="comment">/* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */</span></div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    SYS_RESET_I2C1      = (MXC_F_GCR_RSTR1_I2C1_POS + 32),        </div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    SYS_RESET_PT        = (MXC_F_GCR_RSTR1_PT_POS + 32),          </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    SYS_RESET_SPIXIP    = (MXC_F_GCR_RSTR1_SPIXIP_POS + 32),      </div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;    SYS_RESET_XSPIM     = (MXC_F_GCR_RSTR1_XSPIM_POS + 32),       </div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;    SYS_RESET_SDHC      = (MXC_F_GCR_RSTR1_SDHC_POS + 32),        </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    SYS_RESET_OWIRE     = (MXC_F_GCR_RSTR1_OWIRE_POS + 32),       </div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;    SYS_RESET_HTR0      = (MXC_F_GCR_RSTR1_HTMR0_POS + 32),        </div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;    SYS_RESET_HTMR1     = (MXC_F_GCR_RSTR1_HTMR1_POS + 32),        </div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;    SYS_RESET_WDT1      = (MXC_F_GCR_RSTR1_WDT1_POS + 32),        </div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    SYS_RESET_SPI0      = (MXC_F_GCR_RSTR1_SPI0_POS + 32),   </div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;    SYS_RESET_SPIXMEM   = (MXC_F_GCR_RSTR1_SPIXMEM_POS + 32),     </div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    SYS_RESET_SMPHR     = (MXC_F_GCR_RSTR1_SMPHR_POS + 32)        </div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;} sys_reset_t;</div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;</div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    SYS_PERIPH_CLOCK_GPIO0       = MXC_F_GCR_PERCKCN0_GPIO0D_POS,                    </div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;    SYS_PERIPH_CLOCK_GPIO1       = MXC_F_GCR_PERCKCN0_GPIO1D_POS,                    </div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    SYS_PERIPH_CLOCK_USB         = MXC_F_GCR_PERCKCN0_USBD_POS,                      </div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    SYS_PERIPH_CLOCK_DMA         = MXC_F_GCR_PERCKCN0_DMAD_POS,                      </div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    SYS_PERIPH_CLOCK_SPI1        = MXC_F_GCR_PERCKCN0_SPI1D_POS,                     </div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;    SYS_PERIPH_CLOCK_SPI2        = MXC_F_GCR_PERCKCN0_SPI2D_POS,                     </div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    SYS_PERIPH_CLOCK_UART0       = MXC_F_GCR_PERCKCN0_UART0D_POS,                    </div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;    SYS_PERIPH_CLOCK_UART1       = MXC_F_GCR_PERCKCN0_UART1D_POS,                    </div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    SYS_PERIPH_CLOCK_I2C0        = MXC_F_GCR_PERCKCN0_I2C0D_POS,                     </div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;    SYS_PERIPH_CLOCK_TPU         = MXC_F_GCR_PERCKCN0_CRYPTOD_POS,                   </div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    SYS_PERIPH_CLOCK_T0          = MXC_F_GCR_PERCKCN0_TIMER0D_POS,                       </div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;    SYS_PERIPH_CLOCK_T1          = MXC_F_GCR_PERCKCN0_TIMER1D_POS,                       </div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    SYS_PERIPH_CLOCK_T2          = MXC_F_GCR_PERCKCN0_TIMER2D_POS,                       </div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    SYS_PERIPH_CLOCK_T3          = MXC_F_GCR_PERCKCN0_TIMER3D_POS,                       </div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    SYS_PERIPH_CLOCK_T4          = MXC_F_GCR_PERCKCN0_TIMER4D_POS,                       </div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;    SYS_PERIPH_CLOCK_T5          = MXC_F_GCR_PERCKCN0_TIMER5D_POS,                       </div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    SYS_PERIPH_CLOCK_ADC         = MXC_F_GCR_PERCKCN0_ADCD_POS,                      </div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;    SYS_PERIPH_CLOCK_I2C1        = MXC_F_GCR_PERCKCN0_I2C1D_POS,                     </div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    SYS_PERIPH_CLOCK_PT          = MXC_F_GCR_PERCKCN0_PTD_POS,                       </div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    SYS_PERIPH_CLOCK_SPIXIP      = MXC_F_GCR_PERCKCN0_SPIXIPD_POS,                   </div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    SYS_PERIPH_CLOCK_SPIXFC       = MXC_F_GCR_PERCKCN0_SPIMD_POS,                     </div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;    <span class="comment">/* PERCKCN1 Below this line we add 32 to separate PERCKCN0 and PERCKCN1 */</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    SYS_PERIPH_CLOCK_BTLE        =(MXC_F_GCR_PERCKCN1_BTLED_POS + 32),</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;    SYS_PERIPH_CLOCK_UART2       =(MXC_F_GCR_PERCKCN1_UART2D_POS + 32),            </div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    SYS_PERIPH_CLOCK_TRNG        =(MXC_F_GCR_PERCKCN1_TRNGD_POS + 32),             </div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;    SYS_PERIPH_CLOCK_SCACHE      =(MXC_F_GCR_PERCKCN1_SCACHED_POS + 32),           </div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;    SYS_PERIPH_CLOCK_SDMA        =(MXC_F_GCR_PERCKCN1_SDMAD_POS + 32),             </div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;    SYS_PERIPH_CLOCK_SMPHR       =(MXC_F_GCR_PERCKCN1_SMPHRD_POS + 32),            </div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;    SYS_PERIPH_CLOCK_SDHC        =(MXC_F_GCR_PERCKCN1_SDHCD_POS + 32),             </div><div class="line"><a name="l00137"></a><span class="lineno">  137</span>&#160;    SYS_PERIPH_CLOCK_ICACHEXIP   =(MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS + 32),        </div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;    SYS_PERIPH_CLOCK_OWIRE       =(MXC_F_GCR_PERCKCN1_OWIRED_POS + 32),            </div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;    SYS_PERIPH_CLOCK_SPI0        =(MXC_F_GCR_PERCKCN1_SPI0D_POS + 32),             </div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;    SYS_PERIPH_CLOCK_SPIXIPD     =(MXC_F_GCR_PERCKCN1_SPIXIPDD_POS + 32),</div><div class="line"><a name="l00141"></a><span class="lineno">  141</span>&#160;    SYS_PERIPH_CLOCK_DMA1        =(MXC_F_GCR_PERCKCN1_DMA1_POS + 32),</div><div class="line"><a name="l00142"></a><span class="lineno">  142</span>&#160;    SYS_PERIPH_CLOCK_AUDIO       =(MXC_F_GCR_PERCKCN1_AUDIO_POS + 32),</div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;    SYS_PERIPH_CLOCK_I2C2        =(MXC_F_GCR_PERCKCN1_I2C2_POS + 32),</div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;    SYS_PERIPH_CLOCK_HTMR0       =(MXC_F_GCR_PERCKCN1_HTMR0_POS + 32),           </div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;    SYS_PERIPH_CLOCK_HTMR1       =(MXC_F_GCR_PERCKCN1_HTMR1_POS + 32),           </div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;    SYS_PERIPH_CLOCK_WDT0        =(MXC_F_GCR_PERCKCN1_WDT0_POS + 32),</div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;    SYS_PERIPH_CLOCK_WDT1        =(MXC_F_GCR_PERCKCN1_WDT1_POS + 32),</div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160; 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class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;    SYS_CLOCK_XTAL32M   = MXC_V_GCR_CLKCN_CLKSEL_XTAL32M,</div><div class="line"><a name="l00157"></a><span class="lineno">  157</span>&#160;    SYS_CLOCK_LIRC8K    = MXC_V_GCR_CLKCN_CLKSEL_LIRC8,</div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;    SYS_CLOCK_XTAL32K   = MXC_V_GCR_CLKCN_CLKSEL_XTAL32K </div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;} sys_system_clock_t;</div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;</div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;<span class="preprocessor">#define SYS_SCACHE_CLK 1  // Enable SCACHE CLK</span></div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;<span class="preprocessor">#define SYS_CRYPTO_CLK 1  // Enable CRYPTO CLK</span></div><div class="line"><a name="l00163"></a><span class="lineno">  163</span>&#160;</div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;<span class="preprocessor">#define SYS_USN_CHECKSUM_LEN    16</span></div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;</div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;    MAP_A,</div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;    MAP_B</div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;} sys_map_t;</div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00173"></a><span class="lineno">  173</span>&#160;    Disable,</div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;    Enable</div><div class="line"><a name="l00175"></a><span class="lineno">  175</span>&#160;} sys_control_t;</div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;<span class="keyword">typedef</span> <span class="keywordtype">void</span>* sys_cfg_t;</div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;</div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="structsys__cfg__spi17y__t.html">  179</a></span>&#160;<span class="keyword">typedef</span>  <span class="keyword">struct </span></div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;{</div><div class="line"><a name="l00181"></a><span class="lineno">  181</span>&#160;    sys_map_t map;</div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;    sys_control_t ss0;   </div><div class="line"><a name="l00183"></a><span class="lineno">  183</span>&#160;    sys_control_t ss1;   </div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;    sys_control_t ss2;   </div><div class="line"><a name="l00185"></a><span class="lineno">  185</span>&#160;} <a class="code" href="structsys__cfg__spi17y__t.html">sys_cfg_spi17y_t</a>;</div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;</div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="structsys__cfg__uart__t.html">  188</a></span>&#160;<span class="keyword">typedef</span>  <span class="keyword">struct </span></div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;{</div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;    sys_map_t map;</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;    sys_control_t flow; </div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;} <a class="code" href="structsys__cfg__uart__t.html">sys_cfg_uart_t</a>;</div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;</div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="structsys__cfg__spixr__t.html">  195</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct</span></div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;{</div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;    uint8_t scache_flag;</div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;    uint8_t crypto_flag;</div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;} <a class="code" href="structsys__cfg__spixr__t.html">sys_cfg_spixr_t</a>;</div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;</div><div class="line"><a name="l00201"></a><span class="lineno">  201</span>&#160;</div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_i2c_t; </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_sdhc_t; </div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;</div><div class="line"><a name="l00209"></a><span class="lineno">  209</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_owm_t; </div><div class="line"><a name="l00210"></a><span class="lineno">  210</span>&#160;</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_scache_t; </div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;</div><div class="line"><a name="l00215"></a><span class="lineno">  215</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_usbhs_t; </div><div class="line"><a name="l00216"></a><span class="lineno">  216</span>&#160;</div><div class="line"><a name="l00218"></a><span class="lineno">  218</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_rtc_t; </div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;</div><div class="line"><a name="l00221"></a><span class="lineno">  221</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_tpu_t; </div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;</div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_tmr_t; </div><div class="line"><a name="l00225"></a><span class="lineno">  225</span>&#160;</div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;<span class="keyword">typedef</span> sys_cfg_t sys_cfg_adc_t; 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name="l00252"></a><span class="lineno">  252</span>&#160;</div><div class="line"><a name="l00254"></a><span class="lineno">  254</span>&#160;<span class="keyword">typedef</span> <span class="keywordtype">unsigned</span> <span class="keywordtype">int</span> sys_pt_clk_scale;</div><div class="line"><a name="l00255"></a><span class="lineno">  255</span>&#160;  </div><div class="line"><a name="l00256"></a><span class="lineno">  256</span>&#160;<span class="comment">/***** Function Prototypes *****/</span></div><div class="line"><a name="l00257"></a><span class="lineno">  257</span>&#160;</div><div class="line"><a name="l00265"></a><span class="lineno">  265</span>&#160;<span class="keywordtype">int</span> SYS_GetUSN(uint8_t *usn, uint8_t *checksum);</div><div class="line"><a name="l00266"></a><span class="lineno">  266</span>&#160;</div><div class="line"><a name="l00272"></a><span class="lineno">  272</span>&#160;<span class="keywordtype">int</span> SYS_IsClockEnabled(sys_periph_clock_t clock);</div><div class="line"><a name="l00273"></a><span class="lineno">  273</span>&#160;</div><div class="line"><a name="l00278"></a><span class="lineno">  278</span>&#160;<span class="keywordtype">void</span> SYS_ClockDisable(sys_periph_clock_t clock);</div><div class="line"><a name="l00279"></a><span class="lineno">  279</span>&#160;</div><div class="line"><a name="l00284"></a><span class="lineno">  284</span>&#160;<span class="keywordtype">void</span> SYS_ClockEnable(sys_periph_clock_t clock);</div><div class="line"><a name="l00285"></a><span class="lineno">  285</span>&#160;</div><div class="line"><a name="l00290"></a><span class="lineno">  290</span>&#160;<span class="keywordtype">void</span> SYS_RTCClockEnable(sys_cfg_rtc_t *sys_cfg);</div><div class="line"><a name="l00291"></a><span class="lineno">  291</span>&#160;</div><div class="line"><a name="l00296"></a><span class="lineno">  296</span>&#160;<span class="keywordtype">int</span> SYS_RTCClockDisable(<span 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name="l00326"></a><span class="lineno">  326</span>&#160;<span class="keywordtype">int</span> SYS_UART_Init(<a class="code" href="structmxc__uart__regs__t.html">mxc_uart_regs_t</a> *uart, <span class="keyword">const</span> <a class="code" href="structsys__cfg__uart__t.html">sys_cfg_uart_t</a>* sys_cfg);</div><div class="line"><a name="l00327"></a><span class="lineno">  327</span>&#160;</div><div class="line"><a name="l00334"></a><span class="lineno">  334</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__uart.html#ga5262e16899bd46be969661cc9bf89492">SYS_UART_Shutdown</a>(<a class="code" href="structmxc__uart__regs__t.html">mxc_uart_regs_t</a> *uart);</div><div class="line"><a name="l00335"></a><span class="lineno">  335</span>&#160;</div><div class="line"><a name="l00336"></a><span class="lineno">  336</span>&#160;</div><div class="line"><a name="l00343"></a><span class="lineno">  343</span>&#160;<span class="keywordtype">int</span> SYS_I2C_Init(<a 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382</span>&#160;</div><div class="line"><a name="l00387"></a><span class="lineno">  387</span>&#160;<span class="keywordtype">unsigned</span> SYS_TMR_GetFreq(<a class="code" href="structmxc__tmr__regs__t.html">mxc_tmr_regs_t</a> *tmr);</div><div class="line"><a name="l00391"></a><span class="lineno">  391</span>&#160;<span class="keywordtype">void</span> SYS_Flash_Operation(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00396"></a><span class="lineno">  396</span>&#160;<span class="keywordtype">void</span> SYS_Reset_Periph(sys_reset_t reset);</div><div class="line"><a name="l00402"></a><span class="lineno">  402</span>&#160;<span class="keywordtype">int</span> SYS_SDHC_Init(<span class="keyword">const</span> sys_cfg_sdhc_t* sys_cfg);</div><div class="line"><a name="l00403"></a><span class="lineno">  403</span>&#160;</div><div class="line"><a name="l00408"></a><span class="lineno">  408</span>&#160;<span class="keywordtype">int</span> SYS_SDHC_Shutdown(<span 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 <div class="ttc" id="structmxc__wdt__regs__t_html"><div class="ttname"><a href="structmxc__wdt__regs__t.html">mxc_wdt_regs_t</a></div><div class="ttdoc">Structure type to access the WDT Registers. </div><div class="ttdef"><b>Definition:</b> wdt_regs.h:88</div></div>
 <div class="ttc" id="structsys__cfg__uart__t_html"><div class="ttname"><a href="structsys__cfg__uart__t.html">sys_cfg_uart_t</a></div><div class="ttdoc">UART Configuration Object. </div><div class="ttdef"><b>Definition:</b> mxc_sys.h:188</div></div>
 <div class="ttc" id="structsys__cfg__spixr__t_html"><div class="ttname"><a href="structsys__cfg__spixr__t.html">sys_cfg_spixr_t</a></div><div class="ttdoc">SPIXR Configuration Object. </div><div class="ttdef"><b>Definition:</b> mxc_sys.h:195</div></div>
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diff --git a/lib/sdk/Documentation/html/owm__regs_8h_source.html b/lib/sdk/Documentation/html/owm__regs_8h_source.html
index b274401e3581abea5baed589f14ce1df571d7629..faa7ae9faec5eb285f67a67237af213b7c9aee2c 100644
--- a/lib/sdk/Documentation/html/owm__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/owm__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('owm__regs_8h_source.html','');});
 <div class="title">owm_regs.h</div>  </div>
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 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _OWM_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _OWM_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a46aff78e2a2038bc9c31b84d32c7162a">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a46aff78e2a2038bc9c31b84d32c7162a">cfg</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a9060c026e1eaa09e3143d85334c903d4">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a9060c026e1eaa09e3143d85334c903d4">clk_div_1us</a>;          </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#ae18c74e27313661f85be4399d304330e">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#ae18c74e27313661f85be4399d304330e">ctrl_stat</a>;            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#aec433ec13a578383425c8a27283591c3">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#aec433ec13a578383425c8a27283591c3">data</a>;                 </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a565df1f4a31f7a9fcfbc2e1c2ba6aec2">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a565df1f4a31f7a9fcfbc2e1c2ba6aec2">intfl</a>;                </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a9863448b6682d87b14c91f3e37d57985">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a9863448b6682d87b14c91f3e37d57985">inten</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;} <a class="code" href="structmxc__owm__regs__t.html">mxc_owm_regs_t</a>;</div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="comment">/* Register offsets for module OWM */</span></div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gaf71959160df0e6d962a85821f0ee1218">  104</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_CFG                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#ga03703f2e768a76a4760f36a8ce48aa64">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_CLK_DIV_1US              ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gabbdcfbc9d613854b6b9bc7b84e5637fb">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_CTRL_STAT                ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gae5e11768b15868be3f7c064c5a86634a">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_DATA                     ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#ga5901f76138b8307f5a688a7929627e80">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_INTFL                    ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gaa8ae9ac3ecec8f29116fe2b5e63d9a63">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_INTEN                    ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga8ca7f597319b12e41bcc0170d7f3b66e">  118</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS               0 </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gacc9b7bc4b82abaf39332b1be8ca55c70">  119</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_LONG_LINE_MODE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gaf10b5f42e52735537752dfb438259c8b">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS               1 </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga6db90ad7761039738dde5ac3388a5efc">  122</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_FORCE_PRES_DET                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga9d8d48ce930629655269978225277d55">  124</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_BIT_BANG_EN_POS                  2 </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga1aa3076f3e26555096bf0316f633b2e7">  125</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_BIT_BANG_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_BIT_BANG_EN_POS)) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga47929806455102fcfbef402aedc52497">  127</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS              3 </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga576d37ebad94e2b4cc4a026755890937">  128</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_MODE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gad75b13f8e459267b2736f0909a51f8af">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS            4 </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga1e7db49001ea5e3aec3dc1bf4b91867f">  131</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE                ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gad89a76d1ce26f7663e4361b4d2aa53b8">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS              5 </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga506bebe676845276cf9872da844d07d3">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_SINGLE_BIT_MODE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga38b6864f51c6e7f267d98cdc4dd617dc">  136</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_OVERDRIVE_POS                    6 </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gad15646450201faaba2706d148e0765bc">  137</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_OVERDRIVE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_OVERDRIVE_POS)) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga73386bd233df8b8ff1aba57dec4525fe">  139</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS            7 </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga8b2b1a95c7216667179f3b44e24eb40b">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE                ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__OWM__CLK__DIV__1US.html#gae8149d4a7d17a40cbee2f70906179edd">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS              0 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__OWM__CLK__DIV__1US.html#ga5c200c787d4032af90b29d4879c1bf85">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CLK_DIV_1US_DIVISOR                  ((uint32_t)(0xFFUL &lt;&lt; MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga5fd4b41d45f5a3d2ca44ab3eb2d85ad0">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS         0 </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gae6dc5cdf3326aaf03196410a6ed8ae0f">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_START_OW_RESET             ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga3a2e772f4762eb4de3637ba5ccc11a2f">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS               1 </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga4eaaac9dd2c205331a825a1a99f9e894">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_SRA_MODE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga6721079b1569ff556e5173abb70cba20">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS            2 </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga7caeac35773fafa345b5930af3f9895e">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE                ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gad882d1664973551aa3c37684267aa726">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS               3 </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga54ac9f97cc71177721c64f88629d80b8">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_OW_INPUT                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gaa119a70a79c535d765cc3fefbeaf2eb2">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS        7 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga6e189d6bb11a732fbfd527eecdf3d44d">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT            ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__OWM__DATA.html#ga6b5dc9370a90f2fb59b36cf3129fe3fc">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_DATA_TX_RX_POS                       0 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__OWM__DATA.html#gae8475760cb1980b9d7ee1d080061763f">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_DATA_TX_RX                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_OWM_DATA_TX_RX_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga8f5971fa6bd1f9ad7fec35c17640b399">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS              0 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#gabc4d9532e18f696a8578f0588195b5e1">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_OW_RESET_DONE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga7a07176cdacf5d4f82b0263194ee0700">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS              1 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#gaf6f95d9abcc56cd80cc3f9d016c0ee68">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_TX_DATA_EMPTY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga19b49f11fbe87f79e11aab494dbffee0">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_RX_DATA_READY_POS              2 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga250e3063528ccf841afb1fc49b208621">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_RX_DATA_READY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_RX_DATA_READY_POS)) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga1a885f5d95a9643fc528dd14b6d30d59">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_SHORT_POS                 3 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga1a11f7b6ae8badf066e65341830cfd33">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_SHORT                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_LINE_SHORT_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga01e95ef56fef45dcba079edb98050d95">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_LOW_POS                   4 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga1d306d0e4816f00c512aa9d9cb9b79f6">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_LOW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_LINE_LOW_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga7fd9366721af37a6d3b8fcf0a064040d">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS              0 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gad171658014cd0e033bd16b624186d49c">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_OW_RESET_DONE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga4b855ffb108f22f51b96c57330f1c5a1">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS              1 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gad7c2e4f724e967ef8694685b1dc47691">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_TX_DATA_EMPTY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gafbab5bb9c462334167b08c4acb5e570c">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_RX_DATA_READY_POS              2 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga1351d00d9ba49cf93b2b8c51474ab56f">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_RX_DATA_READY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_RX_DATA_READY_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga9814406ac5d6a4504cc77a122f09c20a">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_SHORT_POS                 3 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gaaa2d29e2b290e6c2352325431d54d50e">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_SHORT                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_LINE_SHORT_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gabd1dd16bb8536e6f279ef6823edb9495">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_LOW_POS                   4 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gabf466365e3e334494dc1e564566a2a30">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_LOW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_LINE_LOW_POS)) </span></div><div class="line"><a name="l00235"></a><span class="lineno">  235</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00236"></a><span class="lineno">  236</span>&#160;}</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;</div><div class="line"><a name="l00239"></a><span class="lineno">  239</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _OWM_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__owm__regs__t_html_a9060c026e1eaa09e3143d85334c903d4"><div class="ttname"><a href="structmxc__owm__regs__t.html#a9060c026e1eaa09e3143d85334c903d4">mxc_owm_regs_t::clk_div_1us</a></div><div class="ttdeci">__IO uint32_t clk_div_1us</div><div class="ttdoc">0x0004: OWM CLK_DIV_1US Register </div><div class="ttdef"><b>Definition:</b> owm_regs.h:90</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _OWM_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _OWM_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a46aff78e2a2038bc9c31b84d32c7162a">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a46aff78e2a2038bc9c31b84d32c7162a">cfg</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a9060c026e1eaa09e3143d85334c903d4">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a9060c026e1eaa09e3143d85334c903d4">clk_div_1us</a>;          </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#ae18c74e27313661f85be4399d304330e">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#ae18c74e27313661f85be4399d304330e">ctrl_stat</a>;            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#aec433ec13a578383425c8a27283591c3">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#aec433ec13a578383425c8a27283591c3">data</a>;                 </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a565df1f4a31f7a9fcfbc2e1c2ba6aec2">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a565df1f4a31f7a9fcfbc2e1c2ba6aec2">intfl</a>;                </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__owm__regs__t.html#a9863448b6682d87b14c91f3e37d57985">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__owm__regs__t.html#a9863448b6682d87b14c91f3e37d57985">inten</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;} <a class="code" href="structmxc__owm__regs__t.html">mxc_owm_regs_t</a>;</div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="comment">/* Register offsets for module OWM */</span></div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gaf71959160df0e6d962a85821f0ee1218">  104</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_CFG                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#ga03703f2e768a76a4760f36a8ce48aa64">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_CLK_DIV_1US              ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gabbdcfbc9d613854b6b9bc7b84e5637fb">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_CTRL_STAT                ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gae5e11768b15868be3f7c064c5a86634a">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_DATA                     ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#ga5901f76138b8307f5a688a7929627e80">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_INTFL                    ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__OWM__Register__Offsets.html#gaa8ae9ac3ecec8f29116fe2b5e63d9a63">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_OWM_INTEN                    ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga8ca7f597319b12e41bcc0170d7f3b66e">  118</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_LONG_LINE_MODE_POS               0 </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gacc9b7bc4b82abaf39332b1be8ca55c70">  119</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_LONG_LINE_MODE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_LONG_LINE_MODE_POS)) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gaf10b5f42e52735537752dfb438259c8b">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_FORCE_PRES_DET_POS               1 </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga6db90ad7761039738dde5ac3388a5efc">  122</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_FORCE_PRES_DET                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_FORCE_PRES_DET_POS)) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga9d8d48ce930629655269978225277d55">  124</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_BIT_BANG_EN_POS                  2 </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga1aa3076f3e26555096bf0316f633b2e7">  125</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_BIT_BANG_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_BIT_BANG_EN_POS)) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga47929806455102fcfbef402aedc52497">  127</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS              3 </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga576d37ebad94e2b4cc4a026755890937">  128</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_MODE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_EXT_PULLUP_MODE_POS)) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gad75b13f8e459267b2736f0909a51f8af">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS            4 </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga1e7db49001ea5e3aec3dc1bf4b91867f">  131</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_EXT_PULLUP_ENABLE                ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_EXT_PULLUP_ENABLE_POS)) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gad89a76d1ce26f7663e4361b4d2aa53b8">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS              5 </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga506bebe676845276cf9872da844d07d3">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_SINGLE_BIT_MODE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_SINGLE_BIT_MODE_POS)) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga38b6864f51c6e7f267d98cdc4dd617dc">  136</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_OVERDRIVE_POS                    6 </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#gad15646450201faaba2706d148e0765bc">  137</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_OVERDRIVE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_OVERDRIVE_POS)) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga73386bd233df8b8ff1aba57dec4525fe">  139</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS            7 </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__OWM__CFG.html#ga8b2b1a95c7216667179f3b44e24eb40b">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CFG_INT_PULLUP_ENABLE                ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CFG_INT_PULLUP_ENABLE_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__OWM__CLK__DIV__1US.html#gae8149d4a7d17a40cbee2f70906179edd">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS              0 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__OWM__CLK__DIV__1US.html#ga5c200c787d4032af90b29d4879c1bf85">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CLK_DIV_1US_DIVISOR                  ((uint32_t)(0xFFUL &lt;&lt; MXC_F_OWM_CLK_DIV_1US_DIVISOR_POS)) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga5fd4b41d45f5a3d2ca44ab3eb2d85ad0">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS         0 </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gae6dc5cdf3326aaf03196410a6ed8ae0f">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_START_OW_RESET             ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_START_OW_RESET_POS)) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga3a2e772f4762eb4de3637ba5ccc11a2f">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_SRA_MODE_POS               1 </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga4eaaac9dd2c205331a825a1a99f9e894">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_SRA_MODE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_SRA_MODE_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga6721079b1569ff556e5173abb70cba20">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS            2 </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga7caeac35773fafa345b5930af3f9895e">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_BIT_BANG_OE                ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_BIT_BANG_OE_POS)) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gad882d1664973551aa3c37684267aa726">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS               3 </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga54ac9f97cc71177721c64f88629d80b8">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_OW_INPUT                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gabe65c782f5b84f611654ee1bb62c9a64">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS           4 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga56c76f97651247ce58ac58825681ff39">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE               ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#gaa119a70a79c535d765cc3fefbeaf2eb2">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS        7 </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__OWM__CTRL__STAT.html#ga6e189d6bb11a732fbfd527eecdf3d44d">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT            ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__OWM__DATA.html#ga6b5dc9370a90f2fb59b36cf3129fe3fc">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_DATA_TX_RX_POS                       0 </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__OWM__DATA.html#gae8475760cb1980b9d7ee1d080061763f">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_DATA_TX_RX                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_OWM_DATA_TX_RX_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga8f5971fa6bd1f9ad7fec35c17640b399">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_OW_RESET_DONE_POS              0 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#gabc4d9532e18f696a8578f0588195b5e1">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_OW_RESET_DONE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_OW_RESET_DONE_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga7a07176cdacf5d4f82b0263194ee0700">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS              1 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#gaf6f95d9abcc56cd80cc3f9d016c0ee68">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_TX_DATA_EMPTY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_TX_DATA_EMPTY_POS)) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga19b49f11fbe87f79e11aab494dbffee0">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_RX_DATA_READY_POS              2 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga250e3063528ccf841afb1fc49b208621">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_RX_DATA_READY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_RX_DATA_READY_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga1a885f5d95a9643fc528dd14b6d30d59">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_SHORT_POS                 3 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga1a11f7b6ae8badf066e65341830cfd33">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_SHORT                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_LINE_SHORT_POS)) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga01e95ef56fef45dcba079edb98050d95">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_LOW_POS                   4 </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__OWM__INTFL.html#ga1d306d0e4816f00c512aa9d9cb9b79f6">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTFL_LINE_LOW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTFL_LINE_LOW_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga7fd9366721af37a6d3b8fcf0a064040d">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_OW_RESET_DONE_POS              0 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gad171658014cd0e033bd16b624186d49c">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_OW_RESET_DONE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_OW_RESET_DONE_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga4b855ffb108f22f51b96c57330f1c5a1">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS              1 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gad7c2e4f724e967ef8694685b1dc47691">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_TX_DATA_EMPTY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gafbab5bb9c462334167b08c4acb5e570c">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_RX_DATA_READY_POS              2 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga1351d00d9ba49cf93b2b8c51474ab56f">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_RX_DATA_READY                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_RX_DATA_READY_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#ga9814406ac5d6a4504cc77a122f09c20a">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_SHORT_POS                 3 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gaaa2d29e2b290e6c2352325431d54d50e">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_SHORT                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_LINE_SHORT_POS)) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gabd1dd16bb8536e6f279ef6823edb9495">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_LOW_POS                   4 </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__OWM__INTEN.html#gabf466365e3e334494dc1e564566a2a30">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_OWM_INTEN_LINE_LOW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_OWM_INTEN_LINE_LOW_POS)) </span></div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00239"></a><span class="lineno">  239</span>&#160;}</div><div class="line"><a name="l00240"></a><span class="lineno">  240</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00241"></a><span class="lineno">  241</span>&#160;</div><div class="line"><a name="l00242"></a><span class="lineno">  242</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _OWM_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__owm__regs__t_html_a9060c026e1eaa09e3143d85334c903d4"><div class="ttname"><a href="structmxc__owm__regs__t.html#a9060c026e1eaa09e3143d85334c903d4">mxc_owm_regs_t::clk_div_1us</a></div><div class="ttdeci">__IO uint32_t clk_div_1us</div><div class="ttdoc">0x0004: OWM CLK_DIV_1US Register </div><div class="ttdef"><b>Definition:</b> owm_regs.h:90</div></div>
 <div class="ttc" id="structmxc__owm__regs__t_html_a565df1f4a31f7a9fcfbc2e1c2ba6aec2"><div class="ttname"><a href="structmxc__owm__regs__t.html#a565df1f4a31f7a9fcfbc2e1c2ba6aec2">mxc_owm_regs_t::intfl</a></div><div class="ttdeci">__IO uint32_t intfl</div><div class="ttdoc">0x0010: OWM INTFL Register </div><div class="ttdef"><b>Definition:</b> owm_regs.h:93</div></div>
 <div class="ttc" id="structmxc__owm__regs__t_html_ae18c74e27313661f85be4399d304330e"><div class="ttname"><a href="structmxc__owm__regs__t.html#ae18c74e27313661f85be4399d304330e">mxc_owm_regs_t::ctrl_stat</a></div><div class="ttdeci">__IO uint32_t ctrl_stat</div><div class="ttdoc">0x0008: OWM CTRL_STAT Register </div><div class="ttdef"><b>Definition:</b> owm_regs.h:91</div></div>
 <div class="ttc" id="structmxc__owm__regs__t_html_a46aff78e2a2038bc9c31b84d32c7162a"><div class="ttname"><a href="structmxc__owm__regs__t.html#a46aff78e2a2038bc9c31b84d32c7162a">mxc_owm_regs_t::cfg</a></div><div class="ttdeci">__IO uint32_t cfg</div><div class="ttdoc">0x0000: OWM CFG Register </div><div class="ttdef"><b>Definition:</b> owm_regs.h:89</div></div>
diff --git a/lib/sdk/Documentation/html/pwrseq__regs_8h_source.html b/lib/sdk/Documentation/html/pwrseq__regs_8h_source.html
index eb4944b370a4a2d59cd1466bb99e75593fbb6234..9b53de5c8cd08ec91c231a1e7aa092fbef9f5da5 100644
--- a/lib/sdk/Documentation/html/pwrseq__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/pwrseq__regs_8h_source.html
@@ -71,24 +71,18 @@ $(document).ready(function(){initNavTree('pwrseq__regs_8h_source.html','');});
 <div class="title">pwrseq_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _PWRSEQ_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _PWRSEQ_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#acda7cefaab59b1351d543490c7de08fd">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#acda7cefaab59b1351d543490c7de08fd">lpcn</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">lpwkst0</a>;              </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#aea953e86a35e4980504849547ce92a6a">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#aea953e86a35e4980504849547ce92a6a">lpwken0</a>;              </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">lpwkst1</a>;              </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">lpwken1</a>;              </div><div class="line"><a name="l00094"></a><span class="lineno"><a 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href="structmxc__pwrseq__regs__t.html#a0c14230a8bd930a7d6fb6a20f9453711">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a0c14230a8bd930a7d6fb6a20f9453711">lpwken3</a>;              </div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;    __R  uint32_t rsv_0x24_0x2f[3];</div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a3b45e8fe1081cbbe7119e15a31607a59">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a3b45e8fe1081cbbe7119e15a31607a59">lppwst</a>;               </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a01e74384b07af3d4cc25d9df3119fdde">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a01e74384b07af3d4cc25d9df3119fdde">lppwen</a>;               </div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    __R  uint32_t rsv_0x38_0x3f[2];</div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">lpmemsd</a>;              </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a8061fe974b25823102de7c85f444ceb2">  103</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a8061fe974b25823102de7c85f444ceb2">lpvddpd</a>;              </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a5489a99b3c2604deceaa24eb3041955a">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a5489a99b3c2604deceaa24eb3041955a">gp0</a>;                  </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a22b51eadb62898ff2252e91f3f1d2e02">  105</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a22b51eadb62898ff2252e91f3f1d2e02">gp1</a>;                  </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#ad3f173b5c522262557112a4a871643ce">  106</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#ad3f173b5c522262557112a4a871643ce">lpmcstat</a>;             </div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a28f6161d913462e38ed382f10c8f38e6">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a28f6161d913462e38ed382f10c8f38e6">lpmcreq</a>;              </div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;} <a class="code" href="structmxc__pwrseq__regs__t.html">mxc_pwrseq_regs_t</a>;</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;<span class="comment">/* Register offsets for module PWRSEQ */</span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaf8c2b11606fbb27db53a94550588c114">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPCN                  ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga983fffe86f6bf2507240984507b0eedf">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKST0               ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga9d02050422bbde2399a294d16e379ecd">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKEN0               ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga6fd3ae151d4daab6523e20e240182b94">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKST1               ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaeab920c7ff9518b03f53fe72ef503782">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKEN1               ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga260d51b1e3f596da2dac0a2c03f6432f">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKST2               ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga5e9be1a8e80845fd6d67045939fe896a">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKEN2               ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga3ae3b73acb27371701ae7fd672b738d6">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKST3               ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga3719b942a8163670a049182b5c8bca84">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKEN3               ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga261f3bc5075aa2b742ad94e2b2a74528">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPPWST                ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaaf7833587e750d94ef8caa2f7608e1c6">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPPWEN                ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gab9037c3f57d36953a518da17d47f29f6">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gae3553e68300164d9e059aa72f72d7643">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPVDDPD               ((uint32_t)0x00000044UL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga14e99d4c86634a9609cb98d4940cf84c">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_GP0                   ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaa38ae45d494882073cf9218e44fb2af4">  131</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_GP1                   ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga19a1599cdc79f5c28b82ecec60c89565">  132</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPMCSTAT              ((uint32_t)0x00000050UL) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaac6bbd7cd8499c0326ac04e0c009236a">  133</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPMCREQ               ((uint32_t)0x00000054UL) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga3c3d1577d8578d6d68b76f0300ddb64e">  142</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_RAMRET_POS                   0 </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaca33471fa15c3428406d64d3ce47a421">  143</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_RAMRET                       ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga12528bfd2c077fc0353cf2d998d4fdc3">  144</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_DIS                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga811ef7a873711a33eddeba4d8128d97b">  145</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_DIS                   (MXC_V_PWRSEQ_LPCN_RAMRET_DIS &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaed1d0ac6c4d536f4036a1817b2bac77e">  146</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_EN1                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga66ecb773cefefc1c878762e1983f18d4">  147</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_EN1                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaab7eb051c1b7cea1ba2b39f5f603aa15">  148</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_EN2                   ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaadc00f2c77465b203150b142ffbaff2b">  149</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_EN2                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaa71c18567497dc26c94a422e06a06a45">  150</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_EN3                   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga3e61e0ce45ce806cb40284401b0c4e5c">  151</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_EN3                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga411c4daefb36a07ba8161c5665a6596b">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_OVR_POS                      4 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga361f0404d31a4d0ba9d81d9a76db401d">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_OVR                          ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPCN_OVR_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaf0661a8a4ab2d239da09fdef4bd53f2d">  155</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_OVR_0_9V                     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaca87c53fefb8cf5d93dc114639486405">  156</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_OVR_0_9V                     (MXC_V_PWRSEQ_LPCN_OVR_0_9V &lt;&lt; MXC_F_PWRSEQ_LPCN_OVR_POS) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga81c749a99d96dc02e459885332f34b79">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_OVR_1_0V                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga9a849614c9f2a0c4ae9fab206c460566">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_OVR_1_0V                     (MXC_V_PWRSEQ_LPCN_OVR_1_0V &lt;&lt; MXC_F_PWRSEQ_LPCN_OVR_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga33c838e203fc2d4acd53891143b9a9ae">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_OVR_1_1V                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gabb0f3426b25c64e590469d786cb5c9b0">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_OVR_1_1V                     (MXC_V_PWRSEQ_LPCN_OVR_1_1V &lt;&lt; MXC_F_PWRSEQ_LPCN_OVR_POS) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaf547756c4a853c0a43b27f048bae39cd">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BLKDET_POS                   6 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga0593f1fdc79b2d4eadc24da01caee225">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BLKDET                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_BLKDET_POS)) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gac0f52e6ed44b0179328e54d5369a1023">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_FVDDEN_POS                   7 </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaefa3f1dc939b4b0b5e5bd14898a7b6dd">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_FVDDEN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_FVDDEN_POS)) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gabc836b4d836e5df6e7fb4bfd3974a501">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_RREGEN_POS                   8 </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga37b3520f69b6cd27bf37a5912ae2d41a">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_RREGEN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_RREGEN_POS)) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga6d528e7dea9af6e84714e789b8ea8f13">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BCKGRND_POS                  9 </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gae0fd2c1fab8883b1e27189914936dcf5">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BCKGRND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gab5c258fed2adfac08320c698e2857b09">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_FWKM_POS                     10 </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaabdf2cec53a548c4a0b33823facad9cc">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_FWKM                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_FWKM_POS)) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga549513920ac8a481a5747dcea703e86e">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BGOFF_POS                    11 </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga9b00be7c27b216d54e8a341646bb2cf9">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BGOFF                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_BGOFF_POS)) </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gae4817c476e949a76adfcd7f631fddca0">  180</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDCMD_POS                   20 </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga8284ec2690f9491ea45d66b12c33daeb">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDCMD                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDCMD_POS)) </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga10e49b21e5f2aaff652a2a7a38d6f642">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VRTCMD_POS                   21 </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga33134602ac61b280e7d094ecb0a2f013">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VRTCMD                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VRTCMD_POS)) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga5910bfbadd1c937cac80aa73dec03007">  186</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDAMD_POS                   22 </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaefb789358c91c395a894b1f7aadbc961">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDAMD                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gada549e5a44da7dedf803c8cee9ff5d5f">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS                  23 </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga7fa1f965d46d8edb6379a377c824612e">  190</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOMD                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga6228bfa6e5ba7a9cff57bc231b2e4356">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS                 24 </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga7573f690db8251accbd6b1895b5256be">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOHMD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga442ea077e09d9246f138fd4e24116ecb">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS               25 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga4e4c0cd82f190c39684589ce283c51b6">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga73712db1e794c516ca595422623d6d00">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS              26 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga426e155ee65a4d402f04e23150fe9376">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga0a347b9cdb63bbf33536c22f0230789c">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDBMD_POS                   27 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga010c1595d047e92bcab7f22ce339053a">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDBMD                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKST0.html#ga58e9a7862dcd82b541359b4c84b0cedc">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS                0 </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKST0.html#gab8407322634f2b12d88123b3a93dfa8e">  214</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKST0_WAKEST                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKEN0.html#ga683e2434efe558a688605b7600369c65">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS                0 </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKEN0.html#ga8fa11fa07a7e63481935e2b5251ecc7a">  226</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN                    ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gabf8d0f24e4c5dbbb5dcb4f4eae48a124">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS              0 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga7229d10e5860b2c0805b68552bcc2fdf">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBLSWKST                  ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS)) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga00ea72b436d6bd8920dfab8cc8b6873b">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS            2 </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gade9b3591fec2237d30e6c955a475d8f3">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST                ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS)) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga864bddb08ba3102a71114cc4e1711bb9">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS               3 </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gacd2b9fa1c65425e376174eec57fb0f2d">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_SDMAWKST                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga4daff3bfee387e4c19b10dfb89bfe012">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS               16 </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga265bcf65921017a6d552182724768e7b">  246</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_BBMODEST                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#gae9803d372fbbdf493fc666ab3b23fe68">  256</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS              0 </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga6837c87d6fd0198b5d2585449ba889fd">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN                  ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS)) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga3ee22c70d22ce81a62b98aa18a52216d">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS            2 </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#gaee3102ee85cd6f169dcebb5b3c2fc5f1">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN                ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS)) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga703adc2738eadd76777396260c960b8d">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS               3 </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga41f9b241dd49a5a0dede2a628c680c58">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga5b0e971a88bdfafa427060dbffeb72a3">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS               0 </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac1476f813b4d9a41e01396eab4c72c07">  274</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac1b57b781df69f06b5841ebb7f4f101f">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS               1 </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaf4f3353f1b872fb02088af539c8b79dc">  277</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga5460943bd0edd6dcb24a4ea5bb7d6a61">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS               2 </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga93e76f4e691f6b0c58c3fa15f6ee0f11">  280</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaf24afc1a23c6632dee81067bba07b3da">  282</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS               3 </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga9fb4afe965840e49627fcd828f520fa2">  283</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6724874ba967d3e256bb90cc611da746">  285</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS               4 </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga4b2b0ab27c061954e9ef42e4e92ba14b">  286</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS)) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6c0005bd9957204108fb839915eca403">  288</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS               5 </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6eb62d9b453108166fc4398cb262bbc6">  289</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gade19b4798f36d70e9fd66172d0ac0cdf">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS               6 </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga239ce412c357eaa2d708069165c9a02c">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS)) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaa8765e2510eff852c4aed995dcf6485b">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS              7 </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga8a666504dc38fd7505b2ad0df741a742">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6a829671bd3ed8887eccf7462202b362">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS           8 </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga8a66bf492a3d46b6ca5c886c9b2fe923">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gae52fb973c2c357bb1cc810532471aeb9">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS              9 </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac735730480bf736185042f6c94e844e6">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SCACHESD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS)) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga12da57a5c1798b11eb52d6b727eea80e">  303</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS              10 </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga1b51cd5ee768ac2b4b5c6183b00bf687">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga0a5a21f75b160e89a78dfed75e7441c2">  306</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS             11 </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga675abb6e7ef535d4e8d3cdce0509d1bd">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gab68149d0317b2cbeee58bb5b92f8ee0c">  309</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS                 12 </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gae729502d7422f8eae9f773b154a7aaec">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROMSD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS)) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gabff350e2f1668ad7b3632a3ba6b22b31">  312</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS                13 </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaec8fb41043ae7275a866b367a15298c9">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS)) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga67dabdfba44dc70979ca5a46a2326ddf">  315</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS                 14 </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac5b7b6d873b261b155d83fe07f8df3fd">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_IC1SD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS)) </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga2cd9529af653c684a8d5989e9dbcf532">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS              0 </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga80779d4edf5e8649685bd07b4fea142e">  327</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS)) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#gaccbfdbcd79ba9a6cb2db24e55a17b6b8">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS              1 </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga60b491decd273323f00ccf067ba06d64">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga264b640648c3173ee7d6dead7c702111">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS                8 </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#gaaf136d6321cf24f012da49bfd9d024b8">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS)) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga6f571e0f1c16bcbae403da0abbecc2b8">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS                9 </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga220ff06972328bb819b00d8ddb168ce1">  336</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS)) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga118385431c823e3d01eedbec3ae10cc7">  338</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS                10 </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#gaa95e05af02e96f3eb747cdb4f7c1d7b6">  339</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS)) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga7253f786de8993a9e885f961dd88889b">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS                11 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga617a89d97c16d85649e5a1214ee451db">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS)) </span></div><div class="line"><a name="l00346"></a><span class="lineno">  346</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00347"></a><span class="lineno">  347</span>&#160;}</div><div class="line"><a name="l00348"></a><span class="lineno">  348</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00349"></a><span class="lineno">  349</span>&#160;</div><div class="line"><a name="l00350"></a><span class="lineno">  350</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _PWRSEQ_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__pwrseq__regs__t_html_a6e78094b2c983a37535445dd946d9e59"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a6e78094b2c983a37535445dd946d9e59">mxc_pwrseq_regs_t::lpwkst2</a></div><div class="ttdeci">__IO uint32_t lpwkst2</div><div class="ttdoc">0x14: PWRSEQ LPWKST2 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:94</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a8061fe974b25823102de7c85f444ceb2"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a8061fe974b25823102de7c85f444ceb2">mxc_pwrseq_regs_t::lpvddpd</a></div><div class="ttdeci">__IO uint32_t lpvddpd</div><div class="ttdoc">0x44: PWRSEQ LPVDDPD Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:103</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a04874b86ca61cac518d93937357222ea"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">mxc_pwrseq_regs_t::lpmemsd</a></div><div class="ttdeci">__IO uint32_t lpmemsd</div><div class="ttdoc">0x40: PWRSEQ LPMEMSD Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:102</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _PWRSEQ_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _PWRSEQ_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; 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   __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#acda7cefaab59b1351d543490c7de08fd">lpcn</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">lpwkst0</a>;              </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#aea953e86a35e4980504849547ce92a6a">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#aea953e86a35e4980504849547ce92a6a">lpwken0</a>;              </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">lpwkst1</a>;              </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">lpwken1</a>;              </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    __R  uint32_t rsv_0x14_0x2f[7];</div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a3b45e8fe1081cbbe7119e15a31607a59">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a3b45e8fe1081cbbe7119e15a31607a59">lppwst</a>;               </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a01e74384b07af3d4cc25d9df3119fdde">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a01e74384b07af3d4cc25d9df3119fdde">lppwen</a>;               </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    __R  uint32_t rsv_0x38_0x3f[2];</div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">lpmemsd</a>;              </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a8061fe974b25823102de7c85f444ceb2">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a8061fe974b25823102de7c85f444ceb2">lpvddpd</a>;              </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a275e49a4b3f5f23ec82436ac339972fe">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a275e49a4b3f5f23ec82436ac339972fe">buretvec</a>;             </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__pwrseq__regs__t.html#a2afa0f0e932e56ca6e98bd3dda5e7eaf">  101</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__pwrseq__regs__t.html#a2afa0f0e932e56ca6e98bd3dda5e7eaf">buaod</a>;                </div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;} <a class="code" href="structmxc__pwrseq__regs__t.html">mxc_pwrseq_regs_t</a>;</div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;</div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;<span class="comment">/* Register offsets for module PWRSEQ */</span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaf8c2b11606fbb27db53a94550588c114">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPCN                  ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga983fffe86f6bf2507240984507b0eedf">  112</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKST0               ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga9d02050422bbde2399a294d16e379ecd">  113</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKEN0               ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga6fd3ae151d4daab6523e20e240182b94">  114</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKST1               ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaeab920c7ff9518b03f53fe72ef503782">  115</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPWKEN1               ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga261f3bc5075aa2b742ad94e2b2a74528">  116</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPPWST                ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gaaf7833587e750d94ef8caa2f7608e1c6">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPPWEN                ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gab9037c3f57d36953a518da17d47f29f6">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPMEMSD               ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gae3553e68300164d9e059aa72f72d7643">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_LPVDDPD               ((uint32_t)0x00000044UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#ga0cba11b6c61c42fb64b29e1a56fb9d6c">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_BURETVEC              ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__PWRSEQ__Register__Offsets.html#gacadc8aa1a940e5c882afc80f05114eb3">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_PWRSEQ_BUAOD                 ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga3c3d1577d8578d6d68b76f0300ddb64e">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_RAMRET_POS                   0 </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaca33471fa15c3428406d64d3ce47a421">  131</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_RAMRET                       ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS)) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga12528bfd2c077fc0353cf2d998d4fdc3">  132</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_DIS                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga811ef7a873711a33eddeba4d8128d97b">  133</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_DIS                   (MXC_V_PWRSEQ_LPCN_RAMRET_DIS &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaed1d0ac6c4d536f4036a1817b2bac77e">  134</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_EN1                   ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga66ecb773cefefc1c878762e1983f18d4">  135</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_EN1                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaab7eb051c1b7cea1ba2b39f5f603aa15">  136</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_EN2                   ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaadc00f2c77465b203150b142ffbaff2b">  137</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_EN2                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaa71c18567497dc26c94a422e06a06a45">  138</a></span>&#160;<span class="preprocessor"> #define MXC_V_PWRSEQ_LPCN_RAMRET_EN3                   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga3e61e0ce45ce806cb40284401b0c4e5c">  139</a></span>&#160;<span class="preprocessor"> #define MXC_S_PWRSEQ_LPCN_RAMRET_EN3                   (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 &lt;&lt; MXC_F_PWRSEQ_LPCN_RAMRET_POS) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaf547756c4a853c0a43b27f048bae39cd">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BLKDET_POS                   6 </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga0593f1fdc79b2d4eadc24da01caee225">  142</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BLKDET                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_BLKDET_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga6d528e7dea9af6e84714e789b8ea8f13">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BCKGRND_POS                  9 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gae0fd2c1fab8883b1e27189914936dcf5">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BCKGRND                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gab5c258fed2adfac08320c698e2857b09">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_FWKM_POS                     10 </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaabdf2cec53a548c4a0b33823facad9cc">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_FWKM                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_FWKM_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga549513920ac8a481a5747dcea703e86e">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BGOFF_POS                    11 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga9b00be7c27b216d54e8a341646bb2cf9">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_BGOFF                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_BGOFF_POS)) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga4c10c6419e800d626982912542a70d63">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VCOREMD_POS                  20 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga8e4721e5ea519e50881082d219edbfca">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VCOREMD                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaf8b909d598274c6b1f750234cb366071">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VREGIMD_POS                  21 </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga0735cb716683bda8da97a5e1a9db367c">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VREGIMD                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VREGIMD_POS)) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga5910bfbadd1c937cac80aa73dec03007">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDAMD_POS                   22 </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaefb789358c91c395a894b1f7aadbc961">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDAMD                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gada549e5a44da7dedf803c8cee9ff5d5f">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS                  23 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga7fa1f965d46d8edb6379a377c824612e">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOMD                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga6228bfa6e5ba7a9cff57bc231b2e4356">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS                 24 </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga7573f690db8251accbd6b1895b5256be">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDIOHMD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga442ea077e09d9246f138fd4e24116ecb">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS               25 </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga4e4c0cd82f190c39684589ce283c51b6">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga73712db1e794c516ca595422623d6d00">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS              26 </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga426e155ee65a4d402f04e23150fe9376">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga0a347b9cdb63bbf33536c22f0230789c">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDBMD_POS                   27 </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga010c1595d047e92bcab7f22ce339053a">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VDDBMD                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga74bef05c987e44b1f08c91849d83472b">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS                 28 </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga145e0a9e21a29d4b64fc05d051aa4fe3">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VRXOUTMD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS)) </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga204ce9ceaa89526b817510fd21c668c6">  180</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS                 29 </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga10e983981dfd431b72d0aeeb02c6fff1">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_VTXOUTMD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS)) </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#ga1ddd068aa04a42652a52f7118fa4b4cf">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS               30 </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPCN.html#gaf0680d34bcd04607fd8ec78ca83ebf7a">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKST0.html#ga58e9a7862dcd82b541359b4c84b0cedc">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS                0 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKST0.html#gab8407322634f2b12d88123b3a93dfa8e">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKST0_WAKEST                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKEN0.html#ga683e2434efe558a688605b7600369c65">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS                0 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKEN0.html#ga8fa11fa07a7e63481935e2b5251ecc7a">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN                    ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKST1.html#gad18b6f40b1cf3519067d521f671ce904">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS                0 </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKST1.html#ga892e5b881f116b1dc635bc6cfec92f0d">  220</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKST1_WAKEST                    ((uint32_t)(0x3FFFFUL &lt;&lt; MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKEN1.html#ga61416acd550a69437cb40bb4c48b32ed">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS                0 </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPWKEN1.html#gab1631819e3a4f2e2e82f36c90ea1dd49">  232</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN                    ((uint32_t)(0x7FFFFFFFUL &lt;&lt; MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gabf8d0f24e4c5dbbb5dcb4f4eae48a124">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS              0 </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga7229d10e5860b2c0805b68552bcc2fdf">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBLSWKST                  ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS)) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga00ea72b436d6bd8920dfab8cc8b6873b">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS            2 </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gade9b3591fec2237d30e6c955a475d8f3">  246</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST                ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS)) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga864bddb08ba3102a71114cc4e1711bb9">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS               3 </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gacd2b9fa1c65425e376174eec57fb0f2d">  249</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_SDMAWKST                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gaab902ef4826bb180e0ec1c2fc9cfef6a">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS           4 </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gaeb84f8321de38264191e501d9d037085">  252</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS)) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gad7e266a3d29ca296af14050529d40f3c">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS           5 </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gaf2b348ad1edfec50c42b3000433efec4">  255</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS)) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga0fa055057f1eda6378ec85453545e2ad">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS           6 </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga62265771b9ee2e8eebfb45fe5fde0821">  258</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS)) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gac74b373d7451eb5a060771068fa41ad7">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS           7 </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga182106750f065d3f8415fd510db73c74">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS)) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga9258124c280f080ef32f979d4b22b45e">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS             8 </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga64634426ded9603ac914bda78acb4757">  264</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS)) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga0bfcd0a78fcc66c407d75499eb72d549">  266</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS             9 </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga2f52edbc3990b59cfeca642e5a348352">  267</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS)) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga2b49dd89bbd91b5fe3b12f287d01cb51">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS             10 </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga2f953a4efd514d9fc6e9e91256c18af7">  270</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS)) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga55e8f79fc521fc9ebdaa279d5cf85dab">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS             11 </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gaf0b7aabdbf6ea5bce083a43b144ef2be">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS)) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga4daff3bfee387e4c19b10dfb89bfe012">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS               16 </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga265bcf65921017a6d552182724768e7b">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_BBMODEST                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#gad10f933fd52e1f7b3f4b575342334a9f">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_RSTWKST_POS                17 </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWST.html#ga16c20f5cb3a9785640dba3ea0be83e81">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWST_RSTWKST                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWST_RSTWKST_POS)) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#gae9803d372fbbdf493fc666ab3b23fe68">  289</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS              0 </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga6837c87d6fd0198b5d2585449ba889fd">  290</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN                  ((uint32_t)(0x3UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS)) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga3ee22c70d22ce81a62b98aa18a52216d">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS            2 </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#gaee3102ee85cd6f169dcebb5b3c2fc5f1">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN                ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS)) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga703adc2738eadd76777396260c960b8d">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS               3 </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga41f9b241dd49a5a0dede2a628c680c58">  296</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga4e60730c6636457f94d88442944bc7fe">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS           4 </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga82c2e0b89c6c72f2c5ae4f99df2e42b4">  299</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS)) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga77e45fe3fe3713fa7f79ffddd5385dae">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS           5 </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga0a410750c4850fcbc700eaac8ea06ff3">  302</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS)) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#gae6222b68ca89ed3de252803366782134">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS           6 </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga48d7752da30f40f9fa3b998ea5c2a80a">  305</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS)) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga63a527fdaeb29c88c6a17cebdbd5e095">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS           7 </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPPWEN.html#ga840a927217ab02648ca076ecab511f21">  308</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS)) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga5b0e971a88bdfafa427060dbffeb72a3">  318</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS               0 </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac1476f813b4d9a41e01396eab4c72c07">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac1b57b781df69f06b5841ebb7f4f101f">  321</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS               1 </span></div><div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaf4f3353f1b872fb02088af539c8b79dc">  322</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) </span></div><div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga5460943bd0edd6dcb24a4ea5bb7d6a61">  324</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS               2 </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga93e76f4e691f6b0c58c3fa15f6ee0f11">  325</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaf24afc1a23c6632dee81067bba07b3da">  327</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS               3 </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga9fb4afe965840e49627fcd828f520fa2">  328</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6724874ba967d3e256bb90cc611da746">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS               4 </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga4b2b0ab27c061954e9ef42e4e92ba14b">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS)) </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6c0005bd9957204108fb839915eca403">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS               5 </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6eb62d9b453108166fc4398cb262bbc6">  334</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaa8765e2510eff852c4aed995dcf6485b">  336</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS              7 </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga8a666504dc38fd7505b2ad0df741a742">  337</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga6a829671bd3ed8887eccf7462202b362">  339</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS           8 </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga8a66bf492a3d46b6ca5c886c9b2fe923">  340</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD               ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga373224f4cf1f22cb51aff4e6f862a78a">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS                9 </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga8c08de18549d779f7d1062013c5845bc">  343</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS)) </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga12da57a5c1798b11eb52d6b727eea80e">  345</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS              10 </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga1b51cd5ee768ac2b4b5c6183b00bf687">  346</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) </span></div><div class="line"><a name="l00348"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga0a5a21f75b160e89a78dfed75e7441c2">  348</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS             11 </span></div><div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga675abb6e7ef535d4e8d3cdce0509d1bd">  349</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS)) </span></div><div class="line"><a name="l00351"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gab68149d0317b2cbeee58bb5b92f8ee0c">  351</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS                 12 </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gae729502d7422f8eae9f773b154a7aaec">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROMSD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS)) </span></div><div class="line"><a name="l00354"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gabff350e2f1668ad7b3632a3ba6b22b31">  354</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS                13 </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gaec8fb41043ae7275a866b367a15298c9">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS)) </span></div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#ga67dabdfba44dc70979ca5a46a2326ddf">  357</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS                 14 </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPMEMSD.html#gac5b7b6d873b261b155d83fe07f8df3fd">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPMEMSD_IC1SD                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS)) </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga2cd9529af653c684a8d5989e9dbcf532">  368</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS              0 </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga80779d4edf5e8649685bd07b4fea142e">  369</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS)) </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#gaccbfdbcd79ba9a6cb2db24e55a17b6b8">  371</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS              1 </span></div><div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga60b491decd273323f00ccf067ba06d64">  372</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS)) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga264b640648c3173ee7d6dead7c702111">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS                8 </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#gaaf136d6321cf24f012da49bfd9d024b8">  375</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS)) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga6f571e0f1c16bcbae403da0abbecc2b8">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS                9 </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga220ff06972328bb819b00d8ddb168ce1">  378</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS)) </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga118385431c823e3d01eedbec3ae10cc7">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS                10 </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#gaa95e05af02e96f3eb747cdb4f7c1d7b6">  381</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS)) </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga7253f786de8993a9e885f961dd88889b">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS                11 </span></div><div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="group__PWRSEQ__LPVDDPD.html#ga617a89d97c16d85649e5a1214ee451db">  384</a></span>&#160;<span class="preprocessor"> #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS)) </span></div><div class="line"><a name="l00388"></a><span class="lineno">  388</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00389"></a><span class="lineno">  389</span>&#160;}</div><div class="line"><a name="l00390"></a><span class="lineno">  390</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00391"></a><span class="lineno">  391</span>&#160;</div><div class="line"><a name="l00392"></a><span class="lineno">  392</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _PWRSEQ_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__pwrseq__regs__t_html_a8061fe974b25823102de7c85f444ceb2"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a8061fe974b25823102de7c85f444ceb2">mxc_pwrseq_regs_t::lpvddpd</a></div><div class="ttdeci">__IO uint32_t lpvddpd</div><div class="ttdoc">0x44: PWRSEQ LPVDDPD Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:99</div></div>
+<div class="ttc" id="structmxc__pwrseq__regs__t_html_a2afa0f0e932e56ca6e98bd3dda5e7eaf"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a2afa0f0e932e56ca6e98bd3dda5e7eaf">mxc_pwrseq_regs_t::buaod</a></div><div class="ttdeci">__IO uint32_t buaod</div><div class="ttdoc">0x4C: PWRSEQ BUAOD Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:101</div></div>
+<div class="ttc" id="structmxc__pwrseq__regs__t_html_a04874b86ca61cac518d93937357222ea"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a04874b86ca61cac518d93937357222ea">mxc_pwrseq_regs_t::lpmemsd</a></div><div class="ttdeci">__IO uint32_t lpmemsd</div><div class="ttdoc">0x40: PWRSEQ LPMEMSD Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:98</div></div>
+<div class="ttc" id="structmxc__pwrseq__regs__t_html_a275e49a4b3f5f23ec82436ac339972fe"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a275e49a4b3f5f23ec82436ac339972fe">mxc_pwrseq_regs_t::buretvec</a></div><div class="ttdeci">__IO uint32_t buretvec</div><div class="ttdoc">0x48: PWRSEQ BURETVEC Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:100</div></div>
 <div class="ttc" id="structmxc__pwrseq__regs__t_html_a537b6832bfc78f6b1a2fe2e08a2869f4"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a537b6832bfc78f6b1a2fe2e08a2869f4">mxc_pwrseq_regs_t::lpwken1</a></div><div class="ttdeci">__IO uint32_t lpwken1</div><div class="ttdoc">0x10: PWRSEQ LPWKEN1 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:93</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a28f6161d913462e38ed382f10c8f38e6"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a28f6161d913462e38ed382f10c8f38e6">mxc_pwrseq_regs_t::lpmcreq</a></div><div class="ttdeci">__IO uint32_t lpmcreq</div><div class="ttdoc">0x54: PWRSEQ LPMCREQ Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:107</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a01e74384b07af3d4cc25d9df3119fdde"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a01e74384b07af3d4cc25d9df3119fdde">mxc_pwrseq_regs_t::lppwen</a></div><div class="ttdeci">__IO uint32_t lppwen</div><div class="ttdoc">0x34: PWRSEQ LPPWEN Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:100</div></div>
+<div class="ttc" id="structmxc__pwrseq__regs__t_html_a01e74384b07af3d4cc25d9df3119fdde"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a01e74384b07af3d4cc25d9df3119fdde">mxc_pwrseq_regs_t::lppwen</a></div><div class="ttdeci">__IO uint32_t lppwen</div><div class="ttdoc">0x34: PWRSEQ LPPWEN Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:96</div></div>
 <div class="ttc" id="structmxc__pwrseq__regs__t_html_aea953e86a35e4980504849547ce92a6a"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#aea953e86a35e4980504849547ce92a6a">mxc_pwrseq_regs_t::lpwken0</a></div><div class="ttdeci">__IO uint32_t lpwken0</div><div class="ttdoc">0x08: PWRSEQ LPWKEN0 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:91</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a3b45e8fe1081cbbe7119e15a31607a59"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a3b45e8fe1081cbbe7119e15a31607a59">mxc_pwrseq_regs_t::lppwst</a></div><div class="ttdeci">__IO uint32_t lppwst</div><div class="ttdoc">0x30: PWRSEQ LPPWST Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:99</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a0c14230a8bd930a7d6fb6a20f9453711"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a0c14230a8bd930a7d6fb6a20f9453711">mxc_pwrseq_regs_t::lpwken3</a></div><div class="ttdeci">__IO uint32_t lpwken3</div><div class="ttdoc">0x20: PWRSEQ LPWKEN3 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:97</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a94c29a74efad6c3cebe1f55110b52e61"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a94c29a74efad6c3cebe1f55110b52e61">mxc_pwrseq_regs_t::lpwken2</a></div><div class="ttdeci">__IO uint32_t lpwken2</div><div class="ttdoc">0x18: PWRSEQ LPWKEN2 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:95</div></div>
+<div class="ttc" id="structmxc__pwrseq__regs__t_html_a3b45e8fe1081cbbe7119e15a31607a59"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a3b45e8fe1081cbbe7119e15a31607a59">mxc_pwrseq_regs_t::lppwst</a></div><div class="ttdeci">__IO uint32_t lppwst</div><div class="ttdoc">0x30: PWRSEQ LPPWST Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:95</div></div>
 <div class="ttc" id="structmxc__pwrseq__regs__t_html_a363b89a70bd871d3b80e0fa321ed770d"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a363b89a70bd871d3b80e0fa321ed770d">mxc_pwrseq_regs_t::lpwkst0</a></div><div class="ttdeci">__IO uint32_t lpwkst0</div><div class="ttdoc">0x04: PWRSEQ LPWKST0 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:90</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a5489a99b3c2604deceaa24eb3041955a"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a5489a99b3c2604deceaa24eb3041955a">mxc_pwrseq_regs_t::gp0</a></div><div class="ttdeci">__IO uint32_t gp0</div><div class="ttdoc">0x48: PWRSEQ GP0 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:104</div></div>
 <div class="ttc" id="structmxc__pwrseq__regs__t_html_acda7cefaab59b1351d543490c7de08fd"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#acda7cefaab59b1351d543490c7de08fd">mxc_pwrseq_regs_t::lpcn</a></div><div class="ttdeci">__IO uint32_t lpcn</div><div class="ttdoc">0x00: PWRSEQ LPCN Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:89</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a22b51eadb62898ff2252e91f3f1d2e02"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a22b51eadb62898ff2252e91f3f1d2e02">mxc_pwrseq_regs_t::gp1</a></div><div class="ttdeci">__IO uint32_t gp1</div><div class="ttdoc">0x4C: PWRSEQ GP1 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:105</div></div>
 <div class="ttc" id="structmxc__pwrseq__regs__t_html_af8c6160d69b43c2cb7e61167b83945cf"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#af8c6160d69b43c2cb7e61167b83945cf">mxc_pwrseq_regs_t::lpwkst1</a></div><div class="ttdeci">__IO uint32_t lpwkst1</div><div class="ttdoc">0x0C: PWRSEQ LPWKST1 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:92</div></div>
 <div class="ttc" id="structmxc__pwrseq__regs__t_html"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html">mxc_pwrseq_regs_t</a></div><div class="ttdoc">Structure type to access the PWRSEQ Registers. </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:88</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_ad3f173b5c522262557112a4a871643ce"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#ad3f173b5c522262557112a4a871643ce">mxc_pwrseq_regs_t::lpmcstat</a></div><div class="ttdeci">__IO uint32_t lpmcstat</div><div class="ttdoc">0x50: PWRSEQ LPMCSTAT Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:106</div></div>
-<div class="ttc" id="structmxc__pwrseq__regs__t_html_a846955a96142e1e7564aa77214f25a04"><div class="ttname"><a href="structmxc__pwrseq__regs__t.html#a846955a96142e1e7564aa77214f25a04">mxc_pwrseq_regs_t::lpwkst3</a></div><div class="ttdeci">__IO uint32_t lpwkst3</div><div class="ttdoc">0x1C: PWRSEQ LPWKST3 Register </div><div class="ttdef"><b>Definition:</b> pwrseq_regs.h:96</div></div>
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diff --git a/lib/sdk/Documentation/html/rpu_8h_source.html b/lib/sdk/Documentation/html/rpu_8h_source.html
index a128c727f1bb1b377dd6c49cc218bd2e1f7c7a6a..f6bf82106f0aa92f1badc1f8fc46a53d1dc17d64 100644
--- a/lib/sdk/Documentation/html/rpu_8h_source.html
+++ b/lib/sdk/Documentation/html/rpu_8h_source.html
@@ -71,63 +71,63 @@ $(document).ready(function(){initNavTree('rpu_8h_source.html','');});
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-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> * $Date: 2019-02-26 15:48:52 -0600 (Tue, 26 Feb 2019) $</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Revision: 41251 $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _RPU_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _RPU_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;rpu_regs.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;</div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="comment">// Bus Masters whose access to peripherals is controlled by the RPU</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160; 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   RPU_CRYPTO       = <a class="code" href="group__RPU__Register__Offsets.html#gae24964c3e6e7e54d4fd0b233f54f1c0e">MXC_R_RPU_CRYPTO</a>,</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;    RPU_WDT0         = <a class="code" href="group__RPU__Register__Offsets.html#ga4b9a63572672e8f54098314babb1cafe">MXC_R_RPU_WDT0</a>,</div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;    RPU_WDT1         = <a class="code" href="group__RPU__Register__Offsets.html#ga8178aa4e26199e56b5638f4303bbe746">MXC_R_RPU_WDT1</a>,</div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;    RPU_WDT2         = <a class="code" href="group__RPU__Register__Offsets.html#gadac918df083790b46d844d0a14e5a9db">MXC_R_RPU_WDT2</a>,</div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;    RPU_SMON         = <a class="code" href="group__RPU__Register__Offsets.html#ga6b246b4f9b96120df219e2bd17136c2b">MXC_R_RPU_SMON</a>,</div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160; 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   RPU_SDMA         = <a class="code" href="group__RPU__Register__Offsets.html#ga8a5327625d0202b91e35df282035fb15">MXC_R_RPU_SDMA</a>,</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    RPU_SPID         = <a class="code" href="group__RPU__Register__Offsets.html#gae16a302687610cb6cfaf2f06b92f3945">MXC_R_RPU_SPID</a>,</div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;    RPU_PT           = <a class="code" href="group__RPU__Register__Offsets.html#gac45db9f28336917b0ad4ec34e10fedb8">MXC_R_RPU_PT</a>,</div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    RPU_OWM          = <a class="code" href="group__RPU__Register__Offsets.html#ga2f9642cfb30ad9b3022f70b6866a7b66">MXC_R_RPU_OWM</a>,</div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    RPU_SEMA         = <a class="code" href="group__RPU__Register__Offsets.html#gacba86cb3b3d9b5e6fb6eaa0ea8c9f94d">MXC_R_RPU_SEMA</a>,</div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    RPU_UART0        = <a class="code" href="group__RPU__Register__Offsets.html#ga85374954f0649679ed9bb6c2285462a0">MXC_R_RPU_UART0</a>,</div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;    RPU_UART1        = <a class="code" href="group__RPU__Register__Offsets.html#gab8f74f1ffbabee67c6e99a7ec0db1ec1">MXC_R_RPU_UART1</a>,</div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    RPU_UART2        = <a class="code" href="group__RPU__Register__Offsets.html#gac516a6afad33b1224b22756bf1eb996c">MXC_R_RPU_UART2</a>,</div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;    RPU_QSPI1        = <a class="code" href="group__RPU__Register__Offsets.html#gae15f816006a79932498b5ecb7ca815be">MXC_R_RPU_QSPI1</a>,</div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    RPU_QSPI2        = <a class="code" href="group__RPU__Register__Offsets.html#gabeb20fbe45ae0c66dd64e810e63981ca">MXC_R_RPU_QSPI2</a>,</div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    RPU_AUDIO        = <a class="code" href="group__RPU__Register__Offsets.html#ga62858ee59d0413033e261d2fa6ac3260">MXC_R_RPU_AUDIO</a>,</div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    RPU_TRNG         = <a class="code" href="group__RPU__Register__Offsets.html#ga941d1c10cedf99ac6175ffe1fd13348c">MXC_R_RPU_TRNG</a>,</div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;    RPU_BTLE         = <a class="code" href="group__RPU__Register__Offsets.html#gaceec8d8b6f34220875c91ce9d95e4fdb">MXC_R_RPU_BTLE</a>,</div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    RPU_USBHS        = <a class="code" href="group__RPU__Register__Offsets.html#ga83f9fb182fac2146eeb38d7f4c2f48f1">MXC_R_RPU_USBHS</a>,</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;    RPU_SDIO         = <a class="code" href="group__RPU__Register__Offsets.html#ga875e2159d2590cb82bb0aaf08a896894">MXC_R_RPU_SDIO</a>,</div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    RPU_SPIXIPMFIFO  = <a class="code" href="group__RPU__Register__Offsets.html#ga8fc796061e0da47243c5094a440b24af">MXC_R_RPU_SPIXIPMFIFO</a>,</div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;    RPU_QSPI0        = <a class="code" href="group__RPU__Register__Offsets.html#gaf0edccb0dc771f958b394f1d43f1c724">MXC_R_RPU_QSPI0</a></div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;} rpu_device_t;</div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;</div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;<span class="comment">/* **** Function Prototypes **** */</span></div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rpu.html#ga11efbaa7edfce3dc888e04b4ba042a67">RPU_Allow</a>(rpu_device_t periph, uint32_t allow_mask);</div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;</div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rpu.html#gacd1d152f5e763d4dd8b062d3951f8e4d">RPU_Disallow</a>(rpu_device_t periph, uint32_t disallow_mask);</div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;</div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rpu.html#ga03bddd9598ed86c12629456c6c1b4719">RPU_IsAllowed</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;</div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;</div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;}</div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;</div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RPU_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__RPU__Register__Offsets_html_ga875e2159d2590cb82bb0aaf08a896894"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga875e2159d2590cb82bb0aaf08a896894">MXC_R_RPU_SDIO</a></div><div class="ttdeci">#define MXC_R_RPU_SDIO</div><div class="ttdoc">Offset from RPU Base Address:  0x0B60 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:267</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga7b36e48cb85c710ed58a1f5dc762d6f5"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga7b36e48cb85c710ed58a1f5dc762d6f5">MXC_R_RPU_BBCR</a></div><div class="ttdeci">#define MXC_R_RPU_BBCR</div><div class="ttdoc">Offset from RPU Base Address:  0x006C </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:227</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> * $Date: 2019-12-24 11:42:21 -0600 (Tue, 24 Dec 2019) $</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Revision: 50314 $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _RPU_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _RPU_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;rpu_regs.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;</div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="comment">// Bus Masters whose access to peripherals is controlled by the RPU</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;    RPU_DMA0_ALLOW  = 0x01,</div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;    RPU_DMA1_ALLOW  = 0x02,</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;    RPU_USB_ALLOW   = 0x04,</div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;    RPU_SYS0_ALLOW  = 0x08,</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;    RPU_SYS1_ALLOW  = 0x10,</div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;    RPU_SDMAD_ALLOW = 0x20,</div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;    RPU_SDMAI_ALLOW = 0x40,</div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;    RPU_CRYPTO_ALLOW = 0x80,</div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;    RPU_SDIO_ALLOW  = 0x100</div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;} rpu_allow_t;</div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">// Peripherals gated by the RPU</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;    RPU_GCR          = <a class="code" href="group__RPU__Register__Offsets.html#ga825b219b3f230d1b1e46121a81330e2b">MXC_R_RPU_GCR</a>,</div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;    RPU_FLC0         = <a class="code" href="group__RPU__Register__Offsets.html#gaa6b3f26966806128b9526fd5afe8fefd">MXC_R_RPU_FLC0</a>,</div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;    RPU_SDHCCTRL     = <a class="code" href="group__RPU__Register__Offsets.html#gac35bab8d18cc60bf5a2c26e6ac570fc8">MXC_R_RPU_SDHCCTRL</a>,</div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;    RPU_SIR          = <a class="code" href="group__RPU__Register__Offsets.html#ga08e5da34f084d5828f0b7d87de0e3934">MXC_R_RPU_SIR</a>,</div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;    RPU_FCR          = <a class="code" href="group__RPU__Register__Offsets.html#ga288078ece23c2fd5e462c487fef6b8cd">MXC_R_RPU_FCR</a>,</div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;    RPU_CRYPTO       = <a class="code" href="group__RPU__Register__Offsets.html#gae24964c3e6e7e54d4fd0b233f54f1c0e">MXC_R_RPU_CRYPTO</a>,</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;    RPU_WDT0         = <a class="code" href="group__RPU__Register__Offsets.html#ga4b9a63572672e8f54098314babb1cafe">MXC_R_RPU_WDT0</a>,</div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;    RPU_WDT1         = <a class="code" href="group__RPU__Register__Offsets.html#ga8178aa4e26199e56b5638f4303bbe746">MXC_R_RPU_WDT1</a>,</div><div class="line"><a name="l00085"></a><span class="lineno">   85</span>&#160;    RPU_WDT2         = <a class="code" href="group__RPU__Register__Offsets.html#gadac918df083790b46d844d0a14e5a9db">MXC_R_RPU_WDT2</a>,</div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;    RPU_SMON         = <a class="code" href="group__RPU__Register__Offsets.html#ga6b246b4f9b96120df219e2bd17136c2b">MXC_R_RPU_SMON</a>,</div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;    RPU_SIMO         = <a class="code" href="group__RPU__Register__Offsets.html#ga1d0f34cba28bac53dc792c9771bac914">MXC_R_RPU_SIMO</a>,</div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;    RPU_DVS          = <a class="code" href="group__RPU__Register__Offsets.html#ga60bf4b11fd8fc194e351b18143bb9fc3">MXC_R_RPU_DVS</a>,</div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;    RPU_BBSIR        = <a class="code" href="group__RPU__Register__Offsets.html#gac8c2dffbd2bd90af71b9bb402b88015a">MXC_R_RPU_BBSIR</a>,</div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;    RPU_RTC          = <a class="code" href="group__RPU__Register__Offsets.html#ga1ce634242a53c466a24d37c7d1f5b1db">MXC_R_RPU_RTC</a>,</div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;    RPU_WUT          = <a class="code" href="group__RPU__Register__Offsets.html#ga195ab65b469105cd3b9f94f39a9f2211">MXC_R_RPU_WUT</a>,</div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;    RPU_PWRSEQ       = <a class="code" href="group__RPU__Register__Offsets.html#ga3aa16487adf823d6da62ef102304513a">MXC_R_RPU_PWRSEQ</a>,</div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    RPU_MCR          = <a class="code" href="group__RPU__Register__Offsets.html#ga21b6c3af682ef64e5178e15e509588da">MXC_R_RPU_MCR</a>,</div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    RPU_GPIO0        = <a class="code" href="group__RPU__Register__Offsets.html#ga75ed135f829f917e0a5df435779b6cb9">MXC_R_RPU_GPIO0</a>,</div><div class="line"><a name="l00095"></a><span class="lineno">   95</span>&#160;    RPU_GPIO1        = <a class="code" href="group__RPU__Register__Offsets.html#ga6485a93c06828e0a150fed7a9f606416">MXC_R_RPU_GPIO1</a>,</div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;    RPU_TMR0         = <a class="code" href="group__RPU__Register__Offsets.html#gab2d78a4ac627079ab600e4d70f37f9d6">MXC_R_RPU_TMR0</a>,</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    RPU_TMR1         = <a class="code" href="group__RPU__Register__Offsets.html#ga54091642839ac8e783bc70518fce2b32">MXC_R_RPU_TMR1</a>,</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;    RPU_TMR2         = <a class="code" href="group__RPU__Register__Offsets.html#ga54b0a6e7c104e60ee4052bc26c2dc6bc">MXC_R_RPU_TMR2</a>,</div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;    RPU_TMR3         = <a class="code" href="group__RPU__Register__Offsets.html#gaf1f0e4cd8e917fb7623020ecc35db7b8">MXC_R_RPU_TMR3</a>,</div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;    RPU_TMR4         = <a class="code" href="group__RPU__Register__Offsets.html#gaccea9e5decdbbb8f69e6bb4c7f5f835b">MXC_R_RPU_TMR4</a>,</div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    RPU_TMR5         = <a class="code" href="group__RPU__Register__Offsets.html#gabd1887d752901b0228a696b5436f2adf">MXC_R_RPU_TMR5</a>,</div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;    RPU_HTIMER0      = <a class="code" href="group__RPU__Register__Offsets.html#ga01b922fb60ac3bd05effd03440ea8a52">MXC_R_RPU_HTIMER0</a>,</div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    RPU_HTIMER1      = <a class="code" href="group__RPU__Register__Offsets.html#gaa58379e2534bb94356a25513fcd63fb9">MXC_R_RPU_HTIMER1</a>,</div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;    RPU_I2C0_BUS0    = <a class="code" href="group__RPU__Register__Offsets.html#gaefb51f683d5b95a5eb7f8b96baa916e0">MXC_R_RPU_I2C0_BUS0</a>,</div><div class="line"><a name="l00105"></a><span class="lineno">  105</span>&#160;    RPU_I2C1_BUS0    = <a class="code" href="group__RPU__Register__Offsets.html#ga35491a688595e6a95011d50b045fa087">MXC_R_RPU_I2C1_BUS0</a>,</div><div class="line"><a name="l00106"></a><span class="lineno">  106</span>&#160;    RPU_I2C2_BUS0    = <a class="code" href="group__RPU__Register__Offsets.html#ga3c770e9f2dac8ddb3d8811ab78ed4ec5">MXC_R_RPU_I2C2_BUS0</a>,</div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;    RPU_SPIXFM       = <a class="code" href="group__RPU__Register__Offsets.html#gae1db0eeb2bf918bcd61de3eb74150a9d">MXC_R_RPU_SPIXFM</a>,</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    RPU_SPIXFC       = <a class="code" href="group__RPU__Register__Offsets.html#ga36ab22a27b914e37e8ac89738b311409">MXC_R_RPU_SPIXFC</a>,</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;    RPU_DMA0         = <a class="code" href="group__RPU__Register__Offsets.html#ga057a038e76a4e64b85b8ae1a1efea609">MXC_R_RPU_DMA0</a>,</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    RPU_FLC1         = <a class="code" href="group__RPU__Register__Offsets.html#ga0bc3cc9ea9796806169c81de21f64850">MXC_R_RPU_FLC1</a>,</div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;    RPU_ICC0         = <a class="code" href="group__RPU__Register__Offsets.html#ga25089af9382221427f076a0a744dcbc0">MXC_R_RPU_ICC0</a>,</div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    RPU_ICC1         = <a class="code" href="group__RPU__Register__Offsets.html#ga4b79d6a28a97c7e4672d87343f6e000a">MXC_R_RPU_ICC1</a>,</div><div class="line"><a name="l00113"></a><span class="lineno">  113</span>&#160;    RPU_SFCC         = <a class="code" href="group__RPU__Register__Offsets.html#gaa5c2e1662d3e38eeb649437d5ea7b732">MXC_R_RPU_SFCC</a>,</div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    RPU_SRCC         = <a class="code" href="group__RPU__Register__Offsets.html#ga5f1e62fc14fe4e1804029026aef6a31c">MXC_R_RPU_SRCC</a>,</div><div class="line"><a name="l00115"></a><span class="lineno">  115</span>&#160;    RPU_ADC          = <a class="code" href="group__RPU__Register__Offsets.html#ga5ddb3702ca58e824b39080fd943ad0e8">MXC_R_RPU_ADC</a>,</div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    RPU_DMA1         = <a class="code" href="group__RPU__Register__Offsets.html#gaae53b6ab781ae22de703e2eefe48cf8a">MXC_R_RPU_DMA1</a>,</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;    RPU_SDMA         = <a class="code" href="group__RPU__Register__Offsets.html#ga8a5327625d0202b91e35df282035fb15">MXC_R_RPU_SDMA</a>,</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    RPU_SPIXR        = <a class="code" href="group__RPU__Register__Offsets.html#ga81a72a43bdfa013b0483f14367077d90">MXC_R_RPU_SPIXR</a>,</div><div class="line"><a name="l00119"></a><span class="lineno">  119</span>&#160;    RPU_PTG_BUS0     = <a class="code" href="group__RPU__Register__Offsets.html#ga3d11b03929af18e7a7a25937b1c9b63c">MXC_R_RPU_PTG_BUS0</a>,</div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    RPU_OWM          = <a class="code" href="group__RPU__Register__Offsets.html#ga2f9642cfb30ad9b3022f70b6866a7b66">MXC_R_RPU_OWM</a>,</div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;    RPU_SEMA         = <a class="code" href="group__RPU__Register__Offsets.html#gacba86cb3b3d9b5e6fb6eaa0ea8c9f94d">MXC_R_RPU_SEMA</a>,</div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    RPU_UART0        = <a class="code" href="group__RPU__Register__Offsets.html#ga85374954f0649679ed9bb6c2285462a0">MXC_R_RPU_UART0</a>,</div><div class="line"><a name="l00123"></a><span class="lineno">  123</span>&#160;    RPU_UART1        = <a class="code" href="group__RPU__Register__Offsets.html#gab8f74f1ffbabee67c6e99a7ec0db1ec1">MXC_R_RPU_UART1</a>,</div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    RPU_UART2        = <a class="code" href="group__RPU__Register__Offsets.html#gac516a6afad33b1224b22756bf1eb996c">MXC_R_RPU_UART2</a>,</div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;    RPU_SPI1         = <a class="code" href="group__RPU__Register__Offsets.html#ga6e25854a9510774e7aa70a1cd10f79c9">MXC_R_RPU_SPI1</a>,</div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    RPU_SPI2         = <a class="code" href="group__RPU__Register__Offsets.html#ga50ac3cdb93d1c48ace45667fec075bfe">MXC_R_RPU_SPI2</a>,</div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;    RPU_AUDIO        = <a class="code" href="group__RPU__Register__Offsets.html#ga62858ee59d0413033e261d2fa6ac3260">MXC_R_RPU_AUDIO</a>,</div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    RPU_TRNG         = <a class="code" href="group__RPU__Register__Offsets.html#ga941d1c10cedf99ac6175ffe1fd13348c">MXC_R_RPU_TRNG</a>,</div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;    RPU_BTLE         = <a class="code" href="group__RPU__Register__Offsets.html#gaceec8d8b6f34220875c91ce9d95e4fdb">MXC_R_RPU_BTLE</a>,</div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    RPU_USBHS        = <a class="code" href="group__RPU__Register__Offsets.html#ga83f9fb182fac2146eeb38d7f4c2f48f1">MXC_R_RPU_USBHS</a>,</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;    RPU_SDIO         = <a class="code" href="group__RPU__Register__Offsets.html#ga875e2159d2590cb82bb0aaf08a896894">MXC_R_RPU_SDIO</a>,</div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    RPU_SPIXM_FIFO   = <a class="code" href="group__RPU__Register__Offsets.html#ga01858d55ade4d3d95e4b816b205a614c">MXC_R_RPU_SPIXM_FIFO</a>,</div><div class="line"><a name="l00133"></a><span class="lineno">  133</span>&#160;    RPU_SPI0         = <a class="code" href="group__RPU__Register__Offsets.html#gaaead5559747a6cf80244155c9a3fb00d">MXC_R_RPU_SPI0</a></div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;} rpu_device_t;</div><div class="line"><a name="l00135"></a><span class="lineno">  135</span>&#160;</div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;<span class="comment">/* **** Function Prototypes **** */</span></div><div class="line"><a name="l00144"></a><span class="lineno">  144</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rpu.html#ga11efbaa7edfce3dc888e04b4ba042a67">RPU_Allow</a>(rpu_device_t periph, uint32_t allow_mask);</div><div class="line"><a name="l00145"></a><span class="lineno">  145</span>&#160;</div><div class="line"><a name="l00153"></a><span class="lineno">  153</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rpu.html#gacd1d152f5e763d4dd8b062d3951f8e4d">RPU_Disallow</a>(rpu_device_t periph, uint32_t disallow_mask);</div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;</div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rpu.html#ga03bddd9598ed86c12629456c6c1b4719">RPU_IsAllowed</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00161"></a><span class="lineno">  161</span>&#160;</div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;</div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;}</div><div class="line"><a name="l00167"></a><span class="lineno">  167</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;</div><div class="line"><a name="l00169"></a><span class="lineno">  169</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RPU_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__RPU__Register__Offsets_html_ga875e2159d2590cb82bb0aaf08a896894"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga875e2159d2590cb82bb0aaf08a896894">MXC_R_RPU_SDIO</a></div><div class="ttdeci">#define MXC_R_RPU_SDIO</div><div class="ttdoc">Offset from RPU Base Address:  0x0B60 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:267</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gac35bab8d18cc60bf5a2c26e6ac570fc8"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gac35bab8d18cc60bf5a2c26e6ac570fc8">MXC_R_RPU_SDHCCTRL</a></div><div class="ttdeci">#define MXC_R_RPU_SDHCCTRL</div><div class="ttdoc">Offset from RPU Base Address:  0x0370 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:253</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gac8c2dffbd2bd90af71b9bb402b88015a"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gac8c2dffbd2bd90af71b9bb402b88015a">MXC_R_RPU_BBSIR</a></div><div class="ttdeci">#define MXC_R_RPU_BBSIR</div><div class="ttdoc">Offset from RPU Base Address:  0x0054 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:223</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_gaefb51f683d5b95a5eb7f8b96baa916e0"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaefb51f683d5b95a5eb7f8b96baa916e0">MXC_R_RPU_I2C0_BUS0</a></div><div class="ttdeci">#define MXC_R_RPU_I2C0_BUS0</div><div class="ttdoc">Offset from RPU Base Address:  0x01D0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:238</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga8178aa4e26199e56b5638f4303bbe746"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga8178aa4e26199e56b5638f4303bbe746">MXC_R_RPU_WDT1</a></div><div class="ttdeci">#define MXC_R_RPU_WDT1</div><div class="ttdoc">Offset from RPU Base Address:  0x0034 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:218</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gab2811596dad4ed289cf61ba37758efd3"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gab2811596dad4ed289cf61ba37758efd3">MXC_R_RPU_ICACHE1</a></div><div class="ttdeci">#define MXC_R_RPU_ICACHE1</div><div class="ttdoc">Offset from RPU Base Address:  0x02A4 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:247</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga43082d71a4f3f0d11685dc4d887776fc"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga43082d71a4f3f0d11685dc4d887776fc">MXC_R_RPU_I2C0</a></div><div class="ttdeci">#define MXC_R_RPU_I2C0</div><div class="ttdoc">Offset from RPU Base Address:  0x01D0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:238</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga3d11b03929af18e7a7a25937b1c9b63c"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga3d11b03929af18e7a7a25937b1c9b63c">MXC_R_RPU_PTG_BUS0</a></div><div class="ttdeci">#define MXC_R_RPU_PTG_BUS0</div><div class="ttdoc">Offset from RPU Base Address:  0x03C0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:255</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga54091642839ac8e783bc70518fce2b32"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga54091642839ac8e783bc70518fce2b32">MXC_R_RPU_TMR1</a></div><div class="ttdeci">#define MXC_R_RPU_TMR1</div><div class="ttdoc">Offset from RPU Base Address:  0x0110 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:231</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gabd1887d752901b0228a696b5436f2adf"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gabd1887d752901b0228a696b5436f2adf">MXC_R_RPU_TMR5</a></div><div class="ttdeci">#define MXC_R_RPU_TMR5</div><div class="ttdoc">Offset from RPU Base Address:  0x0150 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:235</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga0f1eb3de53098d80fc5fac38a33694df"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga0f1eb3de53098d80fc5fac38a33694df">MXC_R_RPU_I2C1</a></div><div class="ttdeci">#define MXC_R_RPU_I2C1</div><div class="ttdoc">Offset from RPU Base Address:  0x01E0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:239</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga36ab22a27b914e37e8ac89738b311409"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga36ab22a27b914e37e8ac89738b311409">MXC_R_RPU_SPIXFC</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXFC</div><div class="ttdoc">Offset from RPU Base Address:  0x0270 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:242</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga4b9a63572672e8f54098314babb1cafe"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga4b9a63572672e8f54098314babb1cafe">MXC_R_RPU_WDT0</a></div><div class="ttdeci">#define MXC_R_RPU_WDT0</div><div class="ttdoc">Offset from RPU Base Address:  0x0030 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:217</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga60bf4b11fd8fc194e351b18143bb9fc3"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga60bf4b11fd8fc194e351b18143bb9fc3">MXC_R_RPU_DVS</a></div><div class="ttdeci">#define MXC_R_RPU_DVS</div><div class="ttdoc">Offset from RPU Base Address:  0x0048 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:222</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga5d8f7ae5b0005a179405fc2b3eb803c3"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga5d8f7ae5b0005a179405fc2b3eb803c3">MXC_R_RPU_ICACHEXIP</a></div><div class="ttdeci">#define MXC_R_RPU_ICACHEXIP</div><div class="ttdoc">Offset from RPU Base Address:  0x02F0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:248</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga6485a93c06828e0a150fed7a9f606416"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga6485a93c06828e0a150fed7a9f606416">MXC_R_RPU_GPIO1</a></div><div class="ttdeci">#define MXC_R_RPU_GPIO1</div><div class="ttdoc">Offset from RPU Base Address:  0x0090 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:229</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga54b0a6e7c104e60ee4052bc26c2dc6bc"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga54b0a6e7c104e60ee4052bc26c2dc6bc">MXC_R_RPU_TMR2</a></div><div class="ttdeci">#define MXC_R_RPU_TMR2</div><div class="ttdoc">Offset from RPU Base Address:  0x0120 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:232</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gaed262a7e25af135fc96803ebf4857d2a"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaed262a7e25af135fc96803ebf4857d2a">MXC_R_RPU_DCACHE</a></div><div class="ttdeci">#define MXC_R_RPU_DCACHE</div><div class="ttdoc">Offset from RPU Base Address:  0x0330 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:249</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gaa6b3f26966806128b9526fd5afe8fefd"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaa6b3f26966806128b9526fd5afe8fefd">MXC_R_RPU_FLC0</a></div><div class="ttdeci">#define MXC_R_RPU_FLC0</div><div class="ttdoc">Offset from RPU Base Address:  0x0290 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:244</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga62858ee59d0413033e261d2fa6ac3260"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga62858ee59d0413033e261d2fa6ac3260">MXC_R_RPU_AUDIO</a></div><div class="ttdeci">#define MXC_R_RPU_AUDIO</div><div class="ttdoc">Offset from RPU Base Address:  0x04C0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:263</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_gaaead5559747a6cf80244155c9a3fb00d"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaaead5559747a6cf80244155c9a3fb00d">MXC_R_RPU_SPI0</a></div><div class="ttdeci">#define MXC_R_RPU_SPI0</div><div class="ttdoc">Offset from RPU Base Address:  0x0BE0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:269</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gadac918df083790b46d844d0a14e5a9db"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gadac918df083790b46d844d0a14e5a9db">MXC_R_RPU_WDT2</a></div><div class="ttdeci">#define MXC_R_RPU_WDT2</div><div class="ttdoc">Offset from RPU Base Address:  0x0038 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:219</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga3c770e9f2dac8ddb3d8811ab78ed4ec5"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga3c770e9f2dac8ddb3d8811ab78ed4ec5">MXC_R_RPU_I2C2_BUS0</a></div><div class="ttdeci">#define MXC_R_RPU_I2C2_BUS0</div><div class="ttdoc">Offset from RPU Base Address:  0x01F0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:240</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gacba86cb3b3d9b5e6fb6eaa0ea8c9f94d"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gacba86cb3b3d9b5e6fb6eaa0ea8c9f94d">MXC_R_RPU_SEMA</a></div><div class="ttdeci">#define MXC_R_RPU_SEMA</div><div class="ttdoc">Offset from RPU Base Address:  0x03E0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:257</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga5f1e62fc14fe4e1804029026aef6a31c"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga5f1e62fc14fe4e1804029026aef6a31c">MXC_R_RPU_SRCC</a></div><div class="ttdeci">#define MXC_R_RPU_SRCC</div><div class="ttdoc">Offset from RPU Base Address:  0x0330 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:249</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga288078ece23c2fd5e462c487fef6b8cd"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga288078ece23c2fd5e462c487fef6b8cd">MXC_R_RPU_FCR</a></div><div class="ttdeci">#define MXC_R_RPU_FCR</div><div class="ttdoc">Offset from RPU Base Address:  0x0008 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:215</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga1ce634242a53c466a24d37c7d1f5b1db"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga1ce634242a53c466a24d37c7d1f5b1db">MXC_R_RPU_RTC</a></div><div class="ttdeci">#define MXC_R_RPU_RTC</div><div class="ttdoc">Offset from RPU Base Address:  0x0060 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:224</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga3782ba8b5448573834be52c54d7b36a6"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga3782ba8b5448573834be52c54d7b36a6">MXC_R_RPU_I2C2</a></div><div class="ttdeci">#define MXC_R_RPU_I2C2</div><div class="ttdoc">Offset from RPU Base Address:  0x01F0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:240</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gac45db9f28336917b0ad4ec34e10fedb8"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gac45db9f28336917b0ad4ec34e10fedb8">MXC_R_RPU_PT</a></div><div class="ttdeci">#define MXC_R_RPU_PT</div><div class="ttdoc">Offset from RPU Base Address:  0x03C0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:255</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga25089af9382221427f076a0a744dcbc0"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga25089af9382221427f076a0a744dcbc0">MXC_R_RPU_ICC0</a></div><div class="ttdeci">#define MXC_R_RPU_ICC0</div><div class="ttdoc">Offset from RPU Base Address:  0x02A0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:246</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga81a72a43bdfa013b0483f14367077d90"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga81a72a43bdfa013b0483f14367077d90">MXC_R_RPU_SPIXR</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXR</div><div class="ttdoc">Offset from RPU Base Address:  0x03A0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:254</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga75ed135f829f917e0a5df435779b6cb9"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga75ed135f829f917e0a5df435779b6cb9">MXC_R_RPU_GPIO0</a></div><div class="ttdeci">#define MXC_R_RPU_GPIO0</div><div class="ttdoc">Offset from RPU Base Address:  0x0080 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:228</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga0bc3cc9ea9796806169c81de21f64850"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga0bc3cc9ea9796806169c81de21f64850">MXC_R_RPU_FLC1</a></div><div class="ttdeci">#define MXC_R_RPU_FLC1</div><div class="ttdoc">Offset from RPU Base Address:  0x0294 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:245</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gaceec8d8b6f34220875c91ce9d95e4fdb"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaceec8d8b6f34220875c91ce9d95e4fdb">MXC_R_RPU_BTLE</a></div><div class="ttdeci">#define MXC_R_RPU_BTLE</div><div class="ttdoc">Offset from RPU Base Address:  0x0500 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:265</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gaf0edccb0dc771f958b394f1d43f1c724"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaf0edccb0dc771f958b394f1d43f1c724">MXC_R_RPU_QSPI0</a></div><div class="ttdeci">#define MXC_R_RPU_QSPI0</div><div class="ttdoc">Offset from RPU Base Address:  0x0BE0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:269</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga6be2aeefa0e54c4269d488de15b342dc"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga6be2aeefa0e54c4269d488de15b342dc">MXC_R_RPU_SPIXIPM</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXIPM</div><div class="ttdoc">Offset from RPU Base Address:  0x0260 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:241</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga4b79d6a28a97c7e4672d87343f6e000a"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga4b79d6a28a97c7e4672d87343f6e000a">MXC_R_RPU_ICC1</a></div><div class="ttdeci">#define MXC_R_RPU_ICC1</div><div class="ttdoc">Offset from RPU Base Address:  0x02A4 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:247</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga35491a688595e6a95011d50b045fa087"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga35491a688595e6a95011d50b045fa087">MXC_R_RPU_I2C1_BUS0</a></div><div class="ttdeci">#define MXC_R_RPU_I2C1_BUS0</div><div class="ttdoc">Offset from RPU Base Address:  0x01E0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:239</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga01b922fb60ac3bd05effd03440ea8a52"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga01b922fb60ac3bd05effd03440ea8a52">MXC_R_RPU_HTIMER0</a></div><div class="ttdeci">#define MXC_R_RPU_HTIMER0</div><div class="ttdoc">Offset from RPU Base Address:  0x01B0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:236</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga1d0f34cba28bac53dc792c9771bac914"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga1d0f34cba28bac53dc792c9771bac914">MXC_R_RPU_SIMO</a></div><div class="ttdeci">#define MXC_R_RPU_SIMO</div><div class="ttdoc">Offset from RPU Base Address:  0x0044 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:221</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga50ac3cdb93d1c48ace45667fec075bfe"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga50ac3cdb93d1c48ace45667fec075bfe">MXC_R_RPU_SPI2</a></div><div class="ttdeci">#define MXC_R_RPU_SPI2</div><div class="ttdoc">Offset from RPU Base Address:  0x0480 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:262</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gaf1f0e4cd8e917fb7623020ecc35db7b8"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaf1f0e4cd8e917fb7623020ecc35db7b8">MXC_R_RPU_TMR3</a></div><div class="ttdeci">#define MXC_R_RPU_TMR3</div><div class="ttdoc">Offset from RPU Base Address:  0x0130 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:233</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga83f9fb182fac2146eeb38d7f4c2f48f1"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga83f9fb182fac2146eeb38d7f4c2f48f1">MXC_R_RPU_USBHS</a></div><div class="ttdeci">#define MXC_R_RPU_USBHS</div><div class="ttdoc">Offset from RPU Base Address:  0x0B10 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:266</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gaccea9e5decdbbb8f69e6bb4c7f5f835b"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaccea9e5decdbbb8f69e6bb4c7f5f835b">MXC_R_RPU_TMR4</a></div><div class="ttdeci">#define MXC_R_RPU_TMR4</div><div class="ttdoc">Offset from RPU Base Address:  0x0140 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:234</div></div>
 <div class="ttc" id="group__rpu_html_gacd1d152f5e763d4dd8b062d3951f8e4d"><div class="ttname"><a href="group__rpu.html#gacd1d152f5e763d4dd8b062d3951f8e4d">RPU_Disallow</a></div><div class="ttdeci">int RPU_Disallow(rpu_device_t periph, uint32_t disallow_mask)</div><div class="ttdoc">Disable access to peripherals restricted by the RPU This function must be called from handler (privil...</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga27265f4239201e692c712210d163545a"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga27265f4239201e692c712210d163545a">MXC_R_RPU_SPIXIPMC</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXIPMC</div><div class="ttdoc">Offset from RPU Base Address:  0x0270 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:242</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gac36de9b35c4c19ac0261ea7dbedf87fe"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gac36de9b35c4c19ac0261ea7dbedf87fe">MXC_R_RPU_ICACHE0</a></div><div class="ttdeci">#define MXC_R_RPU_ICACHE0</div><div class="ttdoc">Offset from RPU Base Address:  0x02A0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:246</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_gae1db0eeb2bf918bcd61de3eb74150a9d"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gae1db0eeb2bf918bcd61de3eb74150a9d">MXC_R_RPU_SPIXFM</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXFM</div><div class="ttdoc">Offset from RPU Base Address:  0x0260 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:241</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga3aa16487adf823d6da62ef102304513a"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga3aa16487adf823d6da62ef102304513a">MXC_R_RPU_PWRSEQ</a></div><div class="ttdeci">#define MXC_R_RPU_PWRSEQ</div><div class="ttdoc">Offset from RPU Base Address:  0x0068 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:226</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga8a5327625d0202b91e35df282035fb15"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga8a5327625d0202b91e35df282035fb15">MXC_R_RPU_SDMA</a></div><div class="ttdeci">#define MXC_R_RPU_SDMA</div><div class="ttdoc">Offset from RPU Base Address:  0x0360 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:252</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga2f9642cfb30ad9b3022f70b6866a7b66"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga2f9642cfb30ad9b3022f70b6866a7b66">MXC_R_RPU_OWM</a></div><div class="ttdeci">#define MXC_R_RPU_OWM</div><div class="ttdoc">Offset from RPU Base Address:  0x03D0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:256</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga825b219b3f230d1b1e46121a81330e2b"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga825b219b3f230d1b1e46121a81330e2b">MXC_R_RPU_GCR</a></div><div class="ttdeci">#define MXC_R_RPU_GCR</div><div class="ttdoc">Offset from RPU Base Address:  0x0000 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:213</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_gaa5c2e1662d3e38eeb649437d5ea7b732"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaa5c2e1662d3e38eeb649437d5ea7b732">MXC_R_RPU_SFCC</a></div><div class="ttdeci">#define MXC_R_RPU_SFCC</div><div class="ttdoc">Offset from RPU Base Address:  0x02F0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:248</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gae24964c3e6e7e54d4fd0b233f54f1c0e"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gae24964c3e6e7e54d4fd0b233f54f1c0e">MXC_R_RPU_CRYPTO</a></div><div class="ttdeci">#define MXC_R_RPU_CRYPTO</div><div class="ttdoc">Offset from RPU Base Address:  0x000C </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:216</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga6e25854a9510774e7aa70a1cd10f79c9"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga6e25854a9510774e7aa70a1cd10f79c9">MXC_R_RPU_SPI1</a></div><div class="ttdeci">#define MXC_R_RPU_SPI1</div><div class="ttdoc">Offset from RPU Base Address:  0x0460 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:261</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gac516a6afad33b1224b22756bf1eb996c"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gac516a6afad33b1224b22756bf1eb996c">MXC_R_RPU_UART2</a></div><div class="ttdeci">#define MXC_R_RPU_UART2</div><div class="ttdoc">Offset from RPU Base Address:  0x0440 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:260</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga01858d55ade4d3d95e4b816b205a614c"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga01858d55ade4d3d95e4b816b205a614c">MXC_R_RPU_SPIXM_FIFO</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXM_FIFO</div><div class="ttdoc">Offset from RPU Base Address:  0x0BC0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:268</div></div>
+<div class="ttc" id="group__RPU__Register__Offsets_html_ga21b6c3af682ef64e5178e15e509588da"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga21b6c3af682ef64e5178e15e509588da">MXC_R_RPU_MCR</a></div><div class="ttdeci">#define MXC_R_RPU_MCR</div><div class="ttdoc">Offset from RPU Base Address:  0x006C </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:227</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gab2d78a4ac627079ab600e4d70f37f9d6"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gab2d78a4ac627079ab600e4d70f37f9d6">MXC_R_RPU_TMR0</a></div><div class="ttdeci">#define MXC_R_RPU_TMR0</div><div class="ttdoc">Offset from RPU Base Address:  0x0100 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:230</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gaae53b6ab781ae22de703e2eefe48cf8a"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaae53b6ab781ae22de703e2eefe48cf8a">MXC_R_RPU_DMA1</a></div><div class="ttdeci">#define MXC_R_RPU_DMA1</div><div class="ttdoc">Offset from RPU Base Address:  0x0350 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:251</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga195ab65b469105cd3b9f94f39a9f2211"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga195ab65b469105cd3b9f94f39a9f2211">MXC_R_RPU_WUT</a></div><div class="ttdeci">#define MXC_R_RPU_WUT</div><div class="ttdoc">Offset from RPU Base Address:  0x0064 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:225</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga057a038e76a4e64b85b8ae1a1efea609"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga057a038e76a4e64b85b8ae1a1efea609">MXC_R_RPU_DMA0</a></div><div class="ttdeci">#define MXC_R_RPU_DMA0</div><div class="ttdoc">Offset from RPU Base Address:  0x0280 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:243</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga6b246b4f9b96120df219e2bd17136c2b"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga6b246b4f9b96120df219e2bd17136c2b">MXC_R_RPU_SMON</a></div><div class="ttdeci">#define MXC_R_RPU_SMON</div><div class="ttdoc">Offset from RPU Base Address:  0x0040 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:220</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_ga8fc796061e0da47243c5094a440b24af"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga8fc796061e0da47243c5094a440b24af">MXC_R_RPU_SPIXIPMFIFO</a></div><div class="ttdeci">#define MXC_R_RPU_SPIXIPMFIFO</div><div class="ttdoc">Offset from RPU Base Address:  0x0BC0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:268</div></div>
 <div class="ttc" id="group__rpu_html_ga11efbaa7edfce3dc888e04b4ba042a67"><div class="ttname"><a href="group__rpu.html#ga11efbaa7edfce3dc888e04b4ba042a67">RPU_Allow</a></div><div class="ttdeci">int RPU_Allow(rpu_device_t periph, uint32_t allow_mask)</div><div class="ttdoc">Enable access to peripherals restricted by the RPU This function must be called from handler (privile...</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gabeb20fbe45ae0c66dd64e810e63981ca"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gabeb20fbe45ae0c66dd64e810e63981ca">MXC_R_RPU_QSPI2</a></div><div class="ttdeci">#define MXC_R_RPU_QSPI2</div><div class="ttdoc">Offset from RPU Base Address:  0x0480 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:262</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gaa58379e2534bb94356a25513fcd63fb9"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gaa58379e2534bb94356a25513fcd63fb9">MXC_R_RPU_HTIMER1</a></div><div class="ttdeci">#define MXC_R_RPU_HTIMER1</div><div class="ttdoc">Offset from RPU Base Address:  0x01C0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:237</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_gab8f74f1ffbabee67c6e99a7ec0db1ec1"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gab8f74f1ffbabee67c6e99a7ec0db1ec1">MXC_R_RPU_UART1</a></div><div class="ttdeci">#define MXC_R_RPU_UART1</div><div class="ttdoc">Offset from RPU Base Address:  0x0430 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:259</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga941d1c10cedf99ac6175ffe1fd13348c"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga941d1c10cedf99ac6175ffe1fd13348c">MXC_R_RPU_TRNG</a></div><div class="ttdeci">#define MXC_R_RPU_TRNG</div><div class="ttdoc">Offset from RPU Base Address:  0x04D0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:264</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga08e5da34f084d5828f0b7d87de0e3934"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga08e5da34f084d5828f0b7d87de0e3934">MXC_R_RPU_SIR</a></div><div class="ttdeci">#define MXC_R_RPU_SIR</div><div class="ttdoc">Offset from RPU Base Address:  0x0004 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:214</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gae16a302687610cb6cfaf2f06b92f3945"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gae16a302687610cb6cfaf2f06b92f3945">MXC_R_RPU_SPID</a></div><div class="ttdeci">#define MXC_R_RPU_SPID</div><div class="ttdoc">Offset from RPU Base Address:  0x03A0 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:254</div></div>
-<div class="ttc" id="group__RPU__Register__Offsets_html_gae15f816006a79932498b5ecb7ca815be"><div class="ttname"><a href="group__RPU__Register__Offsets.html#gae15f816006a79932498b5ecb7ca815be">MXC_R_RPU_QSPI1</a></div><div class="ttdeci">#define MXC_R_RPU_QSPI1</div><div class="ttdoc">Offset from RPU Base Address:  0x0460 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:261</div></div>
 <div class="ttc" id="group__rpu_html_ga03bddd9598ed86c12629456c6c1b4719"><div class="ttname"><a href="group__rpu.html#ga03bddd9598ed86c12629456c6c1b4719">RPU_IsAllowed</a></div><div class="ttdeci">int RPU_IsAllowed(void)</div><div class="ttdoc">Check to see if this process is running in handler mode. </div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga5ddb3702ca58e824b39080fd943ad0e8"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga5ddb3702ca58e824b39080fd943ad0e8">MXC_R_RPU_ADC</a></div><div class="ttdeci">#define MXC_R_RPU_ADC</div><div class="ttdoc">Offset from RPU Base Address:  0x0340 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:250</div></div>
 <div class="ttc" id="group__RPU__Register__Offsets_html_ga85374954f0649679ed9bb6c2285462a0"><div class="ttname"><a href="group__RPU__Register__Offsets.html#ga85374954f0649679ed9bb6c2285462a0">MXC_R_RPU_UART0</a></div><div class="ttdeci">#define MXC_R_RPU_UART0</div><div class="ttdoc">Offset from RPU Base Address:  0x0420 </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:258</div></div>
diff --git a/lib/sdk/Documentation/html/rpu__regs_8h_source.html b/lib/sdk/Documentation/html/rpu__regs_8h_source.html
index 266deab7dc671652cad1e6d077be903bcc93e869..4b0f03fff98cae00b914ffa036983738334c2647 100644
--- a/lib/sdk/Documentation/html/rpu__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/rpu__regs_8h_source.html
@@ -71,49 +71,48 @@ $(document).ready(function(){initNavTree('rpu__regs_8h_source.html','');});
 <div class="title">rpu_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _RPU_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _RPU_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac64bf03f5a31181627b9d7bff229bbae">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac64bf03f5a31181627b9d7bff229bbae">gcr</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a5ae8ed804192af60d6d2ed665bc89de7">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a5ae8ed804192af60d6d2ed665bc89de7">sir</a>;                  </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a35801207272121e21d0a2a76430f1401">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a35801207272121e21d0a2a76430f1401">fcr</a>;                  </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a88a5580a133bfd53a7761f992ec2881b">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a88a5580a133bfd53a7761f992ec2881b">crypto</a>;               </div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    __R  uint32_t rsv_0x10_0x2f[8];</div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a7409b12c61b29a4fe257590a07c01ce4">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a7409b12c61b29a4fe257590a07c01ce4">wdt0</a>;                 </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a31e99638858f7d9a5d3e0c13467e50e9">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a31e99638858f7d9a5d3e0c13467e50e9">wdt1</a>;                 </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae0c2fff3d78c4cc13ea8ff6be0058747">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae0c2fff3d78c4cc13ea8ff6be0058747">wdt2</a>;                 </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    __R  uint32_t rsv_0x3c;</div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a83957039806dc91bd297c2e10e0cd031">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a83957039806dc91bd297c2e10e0cd031">smon</a>;                 </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a792a786a036390359f26f9be9c193850">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a792a786a036390359f26f9be9c193850">simo</a>;                 </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a087785341ce79484506cfd7287728e3d">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a087785341ce79484506cfd7287728e3d">dvs</a>;                  </div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    __R  uint32_t rsv_0x4c_0x53[2];</div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a509d073c9df3c06db1dc8a5fe779f377">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a509d073c9df3c06db1dc8a5fe779f377">bbsir</a>;                </div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    __R  uint32_t rsv_0x58_0x5f[2];</div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aab60df31ea3b2276598b3035cd9ba9c0">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aab60df31ea3b2276598b3035cd9ba9c0">rtc</a>;                  </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#af13a4525df9e31a7ac74da0fef71e39a">  105</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#af13a4525df9e31a7ac74da0fef71e39a">wut</a>;                  </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a50e2d7f83a0c9bf0f7e97ed0e3fd0057">  106</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a50e2d7f83a0c9bf0f7e97ed0e3fd0057">pwrseq</a>;               </div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a578dd37f6abddf3a8daea235ce614185">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a578dd37f6abddf3a8daea235ce614185">bbcr</a>;                 </div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    __R  uint32_t rsv_0x70_0x7f[4];</div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">  109</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">gpio0</a>;                </div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    __R  uint32_t rsv_0x84_0x8f[3];</div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#abe05f3718e793dfe14939c75bf94eca2">  111</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#abe05f3718e793dfe14939c75bf94eca2">gpio1</a>;                </div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    __R  uint32_t rsv_0x94_0xff[27];</div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a96b9adef08b7f6d1d545e28264275a4c">  113</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a96b9adef08b7f6d1d545e28264275a4c">tmr0</a>;                 </div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    __R  uint32_t rsv_0x104_0x10f[3];</div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a955e4f7e17b11917f743d0887530a356">  115</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a955e4f7e17b11917f743d0887530a356">tmr1</a>;                 </div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    __R  uint32_t rsv_0x114_0x11f[3];</div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a39c567882dcac38cc5717fee6cbf2d29">  117</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a39c567882dcac38cc5717fee6cbf2d29">tmr2</a>;                 </div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    __R  uint32_t rsv_0x124_0x12f[3];</div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a343226a105b94929065ea2caebe3313f">  119</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a343226a105b94929065ea2caebe3313f">tmr3</a>;                 </div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    __R  uint32_t rsv_0x134_0x13f[3];</div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a895fe2a194714f0392686a608d450b67">  121</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a895fe2a194714f0392686a608d450b67">tmr4</a>;                 </div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    __R  uint32_t rsv_0x144_0x14f[3];</div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab7c28ad4ea0a12610580d549a9e0a3e3">  123</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab7c28ad4ea0a12610580d549a9e0a3e3">tmr5</a>;                 </div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    __R  uint32_t rsv_0x154_0x1af[23];</div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a7ab74a3f9f055d17c3b1b426d8f1de0e">  125</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a7ab74a3f9f055d17c3b1b426d8f1de0e">htimer0</a>;              </div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    __R  uint32_t rsv_0x1b4_0x1bf[3];</div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a66a59e223df12aa7f8ddf8003bbbb4a7">  127</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a66a59e223df12aa7f8ddf8003bbbb4a7">htimer1</a>;              </div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    __R  uint32_t rsv_0x1c4_0x1cf[3];</div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a67f843cf68d636443ee57ce3133fbd12">  129</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a67f843cf68d636443ee57ce3133fbd12">i2c0</a>;                 </div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    __R  uint32_t rsv_0x1d4_0x1df[3];</div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a05e9a4140c71fdab6518205e023c6313">  131</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a05e9a4140c71fdab6518205e023c6313">i2c1</a>;                 </div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    __R  uint32_t rsv_0x1e4_0x1ef[3];</div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab2184b645146cece7001515e57b190ad">  133</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab2184b645146cece7001515e57b190ad">i2c2</a>;                 </div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;    __R  uint32_t rsv_0x1f4_0x25f[27];</div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#acd8b09dccd4281e8fa47a3f690e0c287">  135</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#acd8b09dccd4281e8fa47a3f690e0c287">spixipm</a>;              </div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;    __R  uint32_t rsv_0x264_0x26f[3];</div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a835774853a29501e6a1f750d5a57956c">  137</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a835774853a29501e6a1f750d5a57956c">spixipmc</a>;             </div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;    __R  uint32_t rsv_0x274_0x27f[3];</div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#af88deb799899cd4dd4690d67ae7ca8ec">  139</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#af88deb799899cd4dd4690d67ae7ca8ec">dma0</a>;                 </div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;    __R  uint32_t rsv_0x284_0x28f[3];</div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a3922d90aa5c3a901375d2f07585ddb8c">  141</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a3922d90aa5c3a901375d2f07585ddb8c">flc0</a>;                 </div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a5c48ec12eab4ffc70cd1edce57d6718c">  142</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a5c48ec12eab4ffc70cd1edce57d6718c">flc1</a>;                 </div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;    __R  uint32_t rsv_0x298_0x29f[2];</div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a3f3c752957bc9e467f5c9d2e831f555f">  144</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a3f3c752957bc9e467f5c9d2e831f555f">icache0</a>;              </div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a58cadc3c2770b44b7ebfa6c5f55635bd">  145</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a58cadc3c2770b44b7ebfa6c5f55635bd">icache1</a>;              </div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;    __R  uint32_t rsv_0x2a8_0x2ef[18];</div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a0214735f8b048f0386a35b3db6832bb1">  147</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a0214735f8b048f0386a35b3db6832bb1">icachexip</a>;            </div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;    __R  uint32_t rsv_0x2f4_0x32f[15];</div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a5fc2a3b485206573e4054868b11ca9eb">  149</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a5fc2a3b485206573e4054868b11ca9eb">dcache</a>;               </div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;    __R  uint32_t rsv_0x334_0x33f[3];</div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a2fc656d8a513ec404aaff8da6f011fa8">  151</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a2fc656d8a513ec404aaff8da6f011fa8">adc</a>;                  </div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;    __R  uint32_t rsv_0x344_0x34f[3];</div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae6ec9c9f9232226c77892d5226e94fd7">  153</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae6ec9c9f9232226c77892d5226e94fd7">dma1</a>;                 </div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;    __R  uint32_t rsv_0x354_0x35f[3];</div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac874de1a295a40dd380470c64ed28eb0">  155</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac874de1a295a40dd380470c64ed28eb0">sdma</a>;                 </div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;    __R  uint32_t rsv_0x364_0x36f[3];</div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a4aa815e028be017d2571b6c69a6c85aa">  157</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a4aa815e028be017d2571b6c69a6c85aa">sdhcctrl</a>;             </div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;    __R  uint32_t rsv_0x374_0x39f[11];</div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a107ce59e766452ddd16ba0c679c756c7">  159</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a107ce59e766452ddd16ba0c679c756c7">spid</a>;                 </div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;    __R  uint32_t rsv_0x3a4_0x3bf[7];</div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a8c9edc39d61f24c7df1c403a4a1b9e78">  161</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a8c9edc39d61f24c7df1c403a4a1b9e78">pt</a>;                   </div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;    __R  uint32_t rsv_0x3c4_0x3cf[3];</div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a35753561e0eecc1e5d1a5b15a78ab524">  163</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a35753561e0eecc1e5d1a5b15a78ab524">owm</a>;                  </div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;    __R  uint32_t rsv_0x3d4_0x3df[3];</div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a62bc3fca3b262224cf1b86be2d7608ff">  165</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a62bc3fca3b262224cf1b86be2d7608ff">sema</a>;                 </div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;    __R  uint32_t rsv_0x3e4_0x41f[15];</div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a2e1e85f1c673b9352d2afa16882f6b39">  167</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a2e1e85f1c673b9352d2afa16882f6b39">uart0</a>;                </div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;    __R  uint32_t rsv_0x424_0x42f[3];</div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab8395b7a2e0c8f984ec19d5b003d1aca">  169</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab8395b7a2e0c8f984ec19d5b003d1aca">uart1</a>;                </div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;    __R  uint32_t rsv_0x434_0x43f[3];</div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae0b16e375ee045fc432c2151f7ac2cc7">  171</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae0b16e375ee045fc432c2151f7ac2cc7">uart2</a>;                </div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;    __R  uint32_t rsv_0x444_0x45f[7];</div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a5877aea894835edc9344e9a0c9fab0d0">  173</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a5877aea894835edc9344e9a0c9fab0d0">qspi1</a>;                </div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;    __R  uint32_t rsv_0x464_0x47f[7];</div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aa9bf22e9a1dc0d8436bace1228c1cfd1">  175</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aa9bf22e9a1dc0d8436bace1228c1cfd1">qspi2</a>;                </div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;    __R  uint32_t rsv_0x484_0x4bf[15];</div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac6f45bdc77bf6cadfd61e0ae8e2fc3ec">  177</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac6f45bdc77bf6cadfd61e0ae8e2fc3ec">audio</a>;                </div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;    __R  uint32_t rsv_0x4c4_0x4cf[3];</div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a9feb124206f57e0aaee54f8cc32e0422">  179</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a9feb124206f57e0aaee54f8cc32e0422">trng</a>;                 </div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;    __R  uint32_t rsv_0x4d4_0x4ff[11];</div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">  181</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">btle</a>;                 </div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;    __R  uint32_t rsv_0x504_0xb0f[387];</div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aec838a3176ba946e9f886fbe6672df8a">  183</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aec838a3176ba946e9f886fbe6672df8a">usbhs</a>;                </div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;    __R  uint32_t rsv_0xb14_0xb5f[19];</div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a43c49ff6f60b9f78f587cf97befee4da">  185</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a43c49ff6f60b9f78f587cf97befee4da">sdio</a>;                 </div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;    __R  uint32_t rsv_0xb64_0xbbf[23];</div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab79390483fc759b36c1492da84c39142">  187</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab79390483fc759b36c1492da84c39142">spixipmfifo</a>;          </div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;    __R  uint32_t rsv_0xbc4_0xbdf[7];</div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aa2846a575112b79bd39dc16bf16b260d">  189</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aa2846a575112b79bd39dc16bf16b260d">qspi0</a>;                </div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;    __R  uint32_t rsv_0xbe4_0xeff[199];</div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a73401214b554adea90654ae4ee9e441a">  191</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a73401214b554adea90654ae4ee9e441a">sram0</a>;                </div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;    __R  uint32_t rsv_0xf04_0xf0f[3];</div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#af36206f67702f1598a065ceacb42ed76">  193</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#af36206f67702f1598a065ceacb42ed76">sram1</a>;                </div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;    __R  uint32_t rsv_0xf14_0xf1f[3];</div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae1d1de4f98df3b2171e9635b742376d1">  195</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae1d1de4f98df3b2171e9635b742376d1">sram2</a>;                </div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;    __R  uint32_t rsv_0xf24_0xf2f[3];</div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac31f8fe960e70e7f63a3e9b355204150">  197</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac31f8fe960e70e7f63a3e9b355204150">sram3</a>;                </div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;    __R  uint32_t rsv_0xf34_0xf3f[3];</div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#afce0eed072aa6ea690e311ea03098e96">  199</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#afce0eed072aa6ea690e311ea03098e96">sram4</a>;                </div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;    __R  uint32_t rsv_0xf44_0xf4f[3];</div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a7f226e3d43e02fcba1bbe3c75b8818dd">  201</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a7f226e3d43e02fcba1bbe3c75b8818dd">sram5</a>;                </div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;    __R  uint32_t rsv_0xf54_0xf5f[3];</div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a66156e610712dd5d497ea9cc69c82b7d">  203</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a66156e610712dd5d497ea9cc69c82b7d">sram6</a>;                </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;} <a class="code" href="structmxc__rpu__regs__t.html">mxc_rpu_regs_t</a>;</div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="comment">/* Register offsets for module RPU */</span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga825b219b3f230d1b1e46121a81330e2b">  213</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_GCR                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga08e5da34f084d5828f0b7d87de0e3934">  214</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SIR                      ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga288078ece23c2fd5e462c487fef6b8cd">  215</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_FCR                      ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gae24964c3e6e7e54d4fd0b233f54f1c0e">  216</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_CRYPTO                   ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga4b9a63572672e8f54098314babb1cafe">  217</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WDT0                     ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga8178aa4e26199e56b5638f4303bbe746">  218</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WDT1                     ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gadac918df083790b46d844d0a14e5a9db">  219</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WDT2                     ((uint32_t)0x00000038UL) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga6b246b4f9b96120df219e2bd17136c2b">  220</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SMON                     ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga1d0f34cba28bac53dc792c9771bac914">  221</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SIMO                     ((uint32_t)0x00000044UL) </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga60bf4b11fd8fc194e351b18143bb9fc3">  222</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DVS                      ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac8c2dffbd2bd90af71b9bb402b88015a">  223</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_BBSIR                    ((uint32_t)0x00000054UL) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga1ce634242a53c466a24d37c7d1f5b1db">  224</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_RTC                      ((uint32_t)0x00000060UL) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga195ab65b469105cd3b9f94f39a9f2211">  225</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WUT                      ((uint32_t)0x00000064UL) </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3aa16487adf823d6da62ef102304513a">  226</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_PWRSEQ                   ((uint32_t)0x00000068UL) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga7b36e48cb85c710ed58a1f5dc762d6f5">  227</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_BBCR                     ((uint32_t)0x0000006CUL) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga75ed135f829f917e0a5df435779b6cb9">  228</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_GPIO0                    ((uint32_t)0x00000080UL) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga6485a93c06828e0a150fed7a9f606416">  229</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_GPIO1                    ((uint32_t)0x00000090UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gab2d78a4ac627079ab600e4d70f37f9d6">  230</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR0                     ((uint32_t)0x00000100UL) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga54091642839ac8e783bc70518fce2b32">  231</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR1                     ((uint32_t)0x00000110UL) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga54b0a6e7c104e60ee4052bc26c2dc6bc">  232</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR2                     ((uint32_t)0x00000120UL) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaf1f0e4cd8e917fb7623020ecc35db7b8">  233</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR3                     ((uint32_t)0x00000130UL) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaccea9e5decdbbb8f69e6bb4c7f5f835b">  234</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR4                     ((uint32_t)0x00000140UL) </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gabd1887d752901b0228a696b5436f2adf">  235</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR5                     ((uint32_t)0x00000150UL) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga01b922fb60ac3bd05effd03440ea8a52">  236</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_HTIMER0                  ((uint32_t)0x000001B0UL) </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaa58379e2534bb94356a25513fcd63fb9">  237</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_HTIMER1                  ((uint32_t)0x000001C0UL) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga43082d71a4f3f0d11685dc4d887776fc">  238</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_I2C0                     ((uint32_t)0x000001D0UL) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga0f1eb3de53098d80fc5fac38a33694df">  239</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_I2C1                     ((uint32_t)0x000001E0UL) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3782ba8b5448573834be52c54d7b36a6">  240</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_I2C2                     ((uint32_t)0x000001F0UL) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga6be2aeefa0e54c4269d488de15b342dc">  241</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXIPM                  ((uint32_t)0x00000260UL) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga27265f4239201e692c712210d163545a">  242</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXIPMC                 ((uint32_t)0x00000270UL) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga057a038e76a4e64b85b8ae1a1efea609">  243</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DMA0                     ((uint32_t)0x00000280UL) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaa6b3f26966806128b9526fd5afe8fefd">  244</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_FLC0                     ((uint32_t)0x00000290UL) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga0bc3cc9ea9796806169c81de21f64850">  245</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_FLC1                     ((uint32_t)0x00000294UL) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac36de9b35c4c19ac0261ea7dbedf87fe">  246</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ICACHE0                  ((uint32_t)0x000002A0UL) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gab2811596dad4ed289cf61ba37758efd3">  247</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ICACHE1                  ((uint32_t)0x000002A4UL) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga5d8f7ae5b0005a179405fc2b3eb803c3">  248</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ICACHEXIP                ((uint32_t)0x000002F0UL) </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaed262a7e25af135fc96803ebf4857d2a">  249</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DCACHE                   ((uint32_t)0x00000330UL) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga5ddb3702ca58e824b39080fd943ad0e8">  250</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ADC                      ((uint32_t)0x00000340UL) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaae53b6ab781ae22de703e2eefe48cf8a">  251</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DMA1                     ((uint32_t)0x00000350UL) </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga8a5327625d0202b91e35df282035fb15">  252</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SDMA                     ((uint32_t)0x00000360UL) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac35bab8d18cc60bf5a2c26e6ac570fc8">  253</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SDHCCTRL                 ((uint32_t)0x00000370UL) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gae16a302687610cb6cfaf2f06b92f3945">  254</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPID                     ((uint32_t)0x000003A0UL) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac45db9f28336917b0ad4ec34e10fedb8">  255</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_PT                       ((uint32_t)0x000003C0UL) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga2f9642cfb30ad9b3022f70b6866a7b66">  256</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_OWM                      ((uint32_t)0x000003D0UL) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gacba86cb3b3d9b5e6fb6eaa0ea8c9f94d">  257</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SEMA                     ((uint32_t)0x000003E0UL) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga85374954f0649679ed9bb6c2285462a0">  258</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_UART0                    ((uint32_t)0x00000420UL) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gab8f74f1ffbabee67c6e99a7ec0db1ec1">  259</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_UART1                    ((uint32_t)0x00000430UL) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac516a6afad33b1224b22756bf1eb996c">  260</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_UART2                    ((uint32_t)0x00000440UL) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gae15f816006a79932498b5ecb7ca815be">  261</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_QSPI1                    ((uint32_t)0x00000460UL) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gabeb20fbe45ae0c66dd64e810e63981ca">  262</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_QSPI2                    ((uint32_t)0x00000480UL) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga62858ee59d0413033e261d2fa6ac3260">  263</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_AUDIO                    ((uint32_t)0x000004C0UL) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga941d1c10cedf99ac6175ffe1fd13348c">  264</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TRNG                     ((uint32_t)0x000004D0UL) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaceec8d8b6f34220875c91ce9d95e4fdb">  265</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_BTLE                     ((uint32_t)0x00000500UL) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga83f9fb182fac2146eeb38d7f4c2f48f1">  266</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_USBHS                    ((uint32_t)0x00000B10UL) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga875e2159d2590cb82bb0aaf08a896894">  267</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SDIO                     ((uint32_t)0x00000B60UL) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga8fc796061e0da47243c5094a440b24af">  268</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXIPMFIFO              ((uint32_t)0x00000BC0UL) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaf0edccb0dc771f958b394f1d43f1c724">  269</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_QSPI0                    ((uint32_t)0x00000BE0UL) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaa89e41fc29f41d205182c2b5c1562fb4">  270</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM0                    ((uint32_t)0x00000F00UL) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga54c9ab2b94411a5503096e37d3f52bdb">  271</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM1                    ((uint32_t)0x00000F10UL) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3b5b195ae20f2543636cdb103198c4f9">  272</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM2                    ((uint32_t)0x00000F20UL) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga60183c693f6bc997cdab1423eb47d886">  273</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM3                    ((uint32_t)0x00000F30UL) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaca7bdc52b13253bfa8800e60903753fb">  274</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM4                    ((uint32_t)0x00000F40UL) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga374830d66eddc8d17e811b9e022c1b80">  275</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM5                    ((uint32_t)0x00000F50UL) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga17c7ebc31497a1b176b5a43aeec56120">  276</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRAM6                    ((uint32_t)0x00000F60UL) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga45613b9968005275b68889d50eec47a6">  285</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga5c4dc6ae97d8ef03c53dc07083360302">  286</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gac13072c2eaa7feb9f76642c1eae6340e">  288</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gae0523df446484289b65fd18999d681fd">  289</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga0751e91f4e04aaa94edb33c9201cdb99">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_USBACN_POS                       2 </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga83b50d319cd027209654e1d3125cb313">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_USBACN_POS)) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gad913b8d101b22a509f02bf3ce3cf32aa">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gad49cf64928f9a49b460ae592da694fba">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga342014bc3993fc592232fbabb77c0db8">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga44b6cbf4a9f7464ea805a679c5e670f5">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga93ee2a8ea5ad72b06a4fbde4230ee316">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga0b1cbd0f8f1cd9ba70f9a1d486fcac1e">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SDMADACN_POS)) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gaf7de29d2dbda63e1459a752753640c42">  303</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gabd54d84db559f5c287e9d0d04d2deeaf">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga9a08743827a8e4a30e9319926061db3b">  306</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga25e9b054309a709031e1354aba0d9abf">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gacbcdb0df384ac66cc2b9bfeb5c2ae563">  309</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gad6c2401b5ceb55812d7e3975440d1e4c">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SDIOACN_POS)) </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga1a26134ce8516285c50f1a63f6cb54ba">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gaa391241f766ff2e106104d35559bb697">  321</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga24c4cd73a1cb3306d5c02a5fec15e47c">  323</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gab0727ac8b25d721dd18b628f7fb15747">  324</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga10d88182df7d61347bda9c90832e67a9">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_USBACN_POS                       2 </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga89a7d9ee44bea30b43caeb0d15667d0c">  327</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_USBACN_POS)) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga6cd1de18dce6e20e7250de7159c92b00">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga924211c21e8ed96ae45d1734acf1ad1d">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga82d963ded274a442328d60f2a7230355">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga4b7b342d16434d70104ae409af482d12">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gaaa96ece4586e613e760b17b5fc78363f">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga75e9029c865ba068cfa31c2123c915ce">  336</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SDMADACN_POS)) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga2357411312acef8509936a19f7b6704b">  338</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga3f418aa7c2a16ee4c4cdc363624cddc7">  339</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gaec06c636c711b6eb474053afb48d6973">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga72700c39efb95e77aa1e018f1dc64177">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga9ae9eed9410eb0ef5fdc4e3ad3925909">  344</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gab1c029b0c2e7e959572286845f478866">  345</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SDIOACN_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga0378376fb047fbffdb7b4b0677523c26">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga03546edf8870ea408f3954d4f012b98a">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaef3b176c7a3499ae10956f5168ef7d3b">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gad5cfc62e8dd5829cb71804884240d6ae">  359</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaaaadf8b1b7b9decfd76144285b3fe57b">  361</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_USBACN_POS                       2 </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaa0867a48c71c8033ad37c88d7b3a3ed0">  362</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_USBACN_POS)) </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga82255987f96912c64ee0650368826fe1">  364</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga58ae66fd6c42f28e22bfad1be1e6626d">  365</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga72463ffdaef1db595a1c68b9dd9ca866">  367</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga5de525c2839090dd2022ee57d6ef063f">  368</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga1233a376be569acae6f86ca4107e6c95">  370</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga7fea1008142cb6367adcb80d61828a56">  371</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SDMADACN_POS)) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaf41149cef409e805812a669a88912401">  373</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga32c81fef44b999d06b9701d62513a987">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gac87681fb0592d6b155a0145cf6a2dd60">  376</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga0f5317628021d59270b18de259779c2a">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga11ed4b139cd59f76c1280e762d4cd5c0">  379</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga22780296669cd1fb5538de57d239797f">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SDIOACN_POS)) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gaf1cb168f7684842a23ec23e6bcde8d8f">  390</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga2a15d1db227a176e99b1b06facf9954f">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_DMA0ACN_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gae116fd272064072cf84194fc1d1cdba8">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gacc62cd8cd0a28671ad6d91a4386d03ad">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_DMA1ACN_POS)) </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gadaa166446721e88609766178ec9cbc07">  396</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_USBACN_POS                    2 </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gacc3c86bf26850081c3cf90ac1bd7d0ed">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_USBACN_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gab1b95527f58b81bca669268eba3da0e8">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga954cea278dc3435df1c9cb9331d39858">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SYS0ACN_POS)) </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gaada98eb300dd9425eb07f68fc91900cf">  402</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga19bad648e1c6cdafdd004960803b2ac9">  403</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SYS1ACN_POS)) </span></div><div class="line"><a name="l00405"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga84a0b531b1a82d539e6382d5d1da2f09">  405</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMADACN_POS                  5 </span></div><div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga136cd9084235d106b89bdf6d3ec16058">  406</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SDMADACN_POS)) </span></div><div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gaa2d82149903a23a3c839cb6aab67f4d3">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga4c7a56f309c66a6a48af9fc06fae3610">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SDMAIACN_POS)) </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gae7b2a38d5d3e4f9cf987a9171f375817">  411</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga398d3262980a42e3c8c9a0fe76f25cdf">  412</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga6525daa158fe9c27149db057d25836ec">  414</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDIOACN_POS                   8 </span></div><div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga1997b64ab3906df7b937f7e8e60110ce">  415</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SDIOACN_POS)) </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga0161a348216d0a55018771e4790ca9e1">  425</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga36ed881c254b006455e6cad04e2377ca">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_DMA0ACN_POS)) </span></div><div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#gad0455723cf72c7b7a7769b1ecc6a38a0">  428</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#gad4031c067f4a2922ecddab9700c25c1c">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_DMA1ACN_POS)) </span></div><div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga5b39b74f0df22ccbbf8c60408fde720b">  431</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_USBACN_POS                      2 </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#gaffcea000411ce1f752fd26f6c108e858">  432</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_USBACN_POS)) </span></div><div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga0d4d89b7539218dfa2fbe6700e92c01d">  434</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga96717cf7f7e1c40f7fc142e8f93b5d93">  435</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SYS0ACN_POS)) </span></div><div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga270c9af57a0c7628c0c4933c245ca5e8">  437</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga81d49fb120cf28bd29f28bf969e9cbab">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SYS1ACN_POS)) </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga94d42ff69c6ad54c2c7fb58374c55226">  440</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga741a32e03fe4f22eb02a1c80247d395b">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SDMADACN_POS)) </span></div><div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga9be7a7022a5942a451fff212bd4a2089">  443</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00444"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga2a69d9d169483d31aa5dd92dc0180b90">  444</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SDMAIACN_POS)) </span></div><div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga7a73e40218782ab15dadfd1bdd81ca2a">  446</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00447"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga1c4491e929dacd01469759e287ea66cc">  447</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga14344f0c45f1c80a92d6114198e08929">  449</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga0b64dd8f913a9c66f420964d69be91f2">  450</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SDIOACN_POS)) </span></div><div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga4af0bfb0e7f41bbdcb85531de661ba3e">  460</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00461"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gad18d9cd8edca8f1f780dc668f75c5633">  461</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_DMA0ACN_POS)) </span></div><div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga2def22a877a576b40da4d22da5bb4691">  463</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga905fad7f884fa0a3e01ef72f03de44fe">  464</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_DMA1ACN_POS)) </span></div><div class="line"><a name="l00466"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gaf8708a7bac0ac6b0768291f1db43c196">  466</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_USBACN_POS                      2 </span></div><div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gae9c8d11b67b45af8b95647a683be2cee">  467</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_USBACN_POS)) </span></div><div class="line"><a name="l00469"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga713c8b04297d17366eecfd3693ac0b0f">  469</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga9c571b62864a9b6088d8052934fedd52">  470</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SYS0ACN_POS)) </span></div><div class="line"><a name="l00472"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga00a2b29e2b21e111b0f590ed39318e9b">  472</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gada399d456b3d95dfa2601c4942383f0a">  473</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SYS1ACN_POS)) </span></div><div class="line"><a name="l00475"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gaa132713969a8ea4a8f5ef24659254801">  475</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00476"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga8bd0720e419755087db2e9db09d875de">  476</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SDMADACN_POS)) </span></div><div class="line"><a name="l00478"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga37fff4a98c2952326545c4a7f0fe52ae">  478</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00479"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gafa8b0866be214105df635b3743a3e4d9">  479</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SDMAIACN_POS)) </span></div><div class="line"><a name="l00481"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga821a0b60a2a4b36d5155237c45db3e52">  481</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gadac7967813cba726b0819534acc4a491">  482</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga1e3debd7362cd25ce08b5fdefe48fd19">  484</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga897cdb1d2db02fdf1ee5b1e8f6d0dc4b">  485</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SDIOACN_POS)) </span></div><div class="line"><a name="l00495"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga5e7eb20629c3d0e09781ab9af183fd9d">  495</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gafc8c0520cc613b15a7122735377324b1">  496</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_DMA0ACN_POS)) </span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaab20167da063426114ff45630da2623e">  498</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gac0b1b4af4e9d2a40704156a7d2f46257">  499</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_DMA1ACN_POS)) </span></div><div class="line"><a name="l00501"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga5128f3571d65aae2954b3ef7340a3474">  501</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_USBACN_POS                      2 </span></div><div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gae084df8a411a255b748facc758221e44">  502</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_USBACN_POS)) </span></div><div class="line"><a name="l00504"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaf139c3f0f1a83bea067551de208ee685">  504</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga793f6e1668be932e0ff1fe6746dbca2b">  505</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SYS0ACN_POS)) </span></div><div class="line"><a name="l00507"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaff41aee468a958271e0dd5b7479a68bb">  507</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga61a25701d3739355c5614520c69af3f9">  508</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SYS1ACN_POS)) </span></div><div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gae96c8715134659f10db74afd82de30c2">  510</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga0478dc5626b063692071833ae24b81bf">  511</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SDMADACN_POS)) </span></div><div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gadc17f9b58217601b8a1e4c19dc1cc7a3">  513</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaeaeb76bef702892f4f775e39b03f0375">  514</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SDMAIACN_POS)) </span></div><div class="line"><a name="l00516"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga56ff40630b153c05c9faf5f5f9974746">  516</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga9eadf7cbb808589a0ecb62668f577144">  517</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00519"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga6c792c57af53c40f3a9ec5da97b3d468">  519</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00520"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga3dd5e2c9378ff9dcfc81a90d9e0abeee">  520</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SDIOACN_POS)) </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga0480f88c3b83b57c587b4be268fe1690">  530</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00531"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga97042edfd15e53f9f40c6ea4bc347ec7">  531</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_DMA0ACN_POS)) </span></div><div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga2b395fe594884c618ca07c62c113ef42">  533</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00534"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gad6431dc53d326f94bdf53659b03f9aeb">  534</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_DMA1ACN_POS)) </span></div><div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga73623a1b40b872b0ced6826009b1e4c9">  536</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_USBACN_POS                      2 </span></div><div class="line"><a name="l00537"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga014ba0eaf1ccc440ba943830231eca16">  537</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_USBACN_POS)) </span></div><div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gaf6f2207c85f2e54ca0f4e1842b27ed6e">  539</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga41f5e09a2ece0d7a2f6765e87edf53cc">  540</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SYS0ACN_POS)) </span></div><div class="line"><a name="l00542"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga232fa8c0ae664988e21305fb3fa7195b">  542</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00543"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga4aadb282f8bbae164344cfe9adbfb10e">  543</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SYS1ACN_POS)) </span></div><div class="line"><a name="l00545"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga0a80da072d8a063afd339394ad25a001">  545</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00546"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gab45774e3073076f3df60ef136f2e9734">  546</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SDMADACN_POS)) </span></div><div class="line"><a name="l00548"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga2d5f52ece6a322872d53d3a283e9664d">  548</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00549"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga8db3efb4c494ff1bcfe23feafc3689d9">  549</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SDMAIACN_POS)) </span></div><div class="line"><a name="l00551"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gaa09514fdbfa08bb0ab627342cfe999ef">  551</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00552"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga710a44268963b227f03ab31b77b47ce3">  552</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00554"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gafca18ea5ec9e35bbcc8f8283c2996c11">  554</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00555"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga09642da15b10ad10d5aee364bef5d03d">  555</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SDIOACN_POS)) </span></div><div class="line"><a name="l00565"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga640baa8fbf88180e6a4af79d1d1faec6">  565</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00566"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gaafe49e6b904846d7dc5c50592b84b515">  566</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_DMA0ACN_POS)) </span></div><div class="line"><a name="l00568"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga47677f66bc729446182f13c981326997">  568</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00569"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga4eea8dda1d9dd72e09d78a775e334568">  569</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_DMA1ACN_POS)) </span></div><div class="line"><a name="l00571"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga0e3085bf3063cb2a78ca87322038de56">  571</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_USBACN_POS                      2 </span></div><div class="line"><a name="l00572"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gaa6d149ad87332e9c634ced3b7597bb34">  572</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_USBACN_POS)) </span></div><div class="line"><a name="l00574"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gafc6b0283087f4c444932bd189901ced6">  574</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00575"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gad993f20f42328a538efe03312a9888a2">  575</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SYS0ACN_POS)) </span></div><div class="line"><a name="l00577"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga42bfec098a95915724be3e570288d1e2">  577</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00578"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga5e10a07c71672478197bb67a40d93dd9">  578</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SYS1ACN_POS)) </span></div><div class="line"><a name="l00580"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga685264395715903d0bea73510b62d061">  580</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00581"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga31843cee7a85dc5b2b1b0bed98e98d82">  581</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SDMADACN_POS)) </span></div><div class="line"><a name="l00583"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga586df4736de6f5307ed724f4b24853ef">  583</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00584"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gac49a2222255c0641fc0266f58c345390">  584</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SDMAIACN_POS)) </span></div><div class="line"><a name="l00586"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga3ac677d16ce8f935e890fc429b3fcbc4">  586</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00587"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga8e212c95246a66378e12f4c72dfd830c">  587</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00589"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga57cd0793831fc0648967bb32a212fed0">  589</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00590"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga45010ee3348702d76c9f3f424f63a446">  590</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SDIOACN_POS)) </span></div><div class="line"><a name="l00600"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gae6cae085e64781acc98e9b9d734e7e16">  600</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00601"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga31052610386eb955dfe1fcac834c9950">  601</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_DMA0ACN_POS)) </span></div><div class="line"><a name="l00603"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gadbac4dbd6ab31164ef5a0afdcd1d9d69">  603</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00604"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga0b4f7e10f28873d98999ad847ab85249">  604</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_DMA1ACN_POS)) </span></div><div class="line"><a name="l00606"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga2eb324ac04574cff4de9fbe851172b3a">  606</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_USBACN_POS                       2 </span></div><div class="line"><a name="l00607"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga7d94f9108fcbe9efe1db43c27bc6ac8d">  607</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_USBACN_POS)) </span></div><div class="line"><a name="l00609"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga41e1645ecd19b400d0297bb6090007a3">  609</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00610"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga3c4d4e1ff456447a54caad64aeb1598d">  610</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SYS0ACN_POS)) </span></div><div class="line"><a name="l00612"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga63b882b7652c8f687d9b84252199bac7">  612</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00613"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga290bd9599ab8748cd21e402bcb41a693">  613</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SYS1ACN_POS)) </span></div><div class="line"><a name="l00615"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gad63a9cb11d84ef4b7fc4d968e2da8ce3">  615</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00616"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga00d620785a9498472ada1e5364d8dfe0">  616</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SDMADACN_POS)) </span></div><div class="line"><a name="l00618"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga85db01639bb2aff7f97c1e48cd256056">  618</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00619"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga4410eee63366c45ad9229408fb0d6a56">  619</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SDMAIACN_POS)) </span></div><div class="line"><a name="l00621"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gacd1f7ca3857b76f8ee72e5fed712ef5c">  621</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00622"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga6aedf82ecdb4507f8ba01ff2546f7eb9">  622</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00624"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga4f3e212f046e0488ac3e58d6ca796c10">  624</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00625"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga5c6df9a2b032d2f925e941f7abb630df">  625</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SDIOACN_POS)) </span></div><div class="line"><a name="l00635"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga306856ae3f1a9f873cb972f28749f89d">  635</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l00636"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga9ba7ffe70b0703582bc7781ce06cc4ee">  636</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00638"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga70b7c9762d81ac34f32aff047a4bb079">  638</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l00639"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gafd6bb1a7703e3adf2085a92d9802255d">  639</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00641"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gadd51ce1f7f636e13e6e35326b314bc78">  641</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_USBACN_POS                     2 </span></div><div class="line"><a name="l00642"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gab6ad6ae34bc880690b3f6461c1d3992c">  642</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_USBACN                  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href="group__RPU__BBSIR.html#ga27694e5ce9de58b245e43947888131e5">  648</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00650"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga8625761ecc5d4ae1407c366838e8e97a">  650</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMADACN_POS                   5 </span></div><div class="line"><a name="l00651"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga0ae0f4110388ecef06a642d421a19d0f">  651</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SDMADACN_POS)) </span></div><div class="line"><a name="l00653"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gac962d318c7c39a5a8934f6948043f630">  653</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l00654"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gac23271538d6125c8d41961c3dcbaa931">  654</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00656"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga06e83d99b72c69a6a9c47453de9cbbe1">  656</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l00657"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga90b9a073eaf6b1fdcd27b7f2390be0fa">  657</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00659"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga8a308b593e34a3b837b16fcaff947105">  659</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDIOACN_POS                    8 </span></div><div class="line"><a name="l00660"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gaffdb6734194f08edca761b6244cd394b">  660</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SDIOACN_POS)) </span></div><div class="line"><a name="l00670"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gab1889912a28796ae5751828f6bebc1af">  670</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00671"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga874d9ea41b197289f2cdf09fe09dd41a">  671</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_DMA0ACN_POS)) </span></div><div class="line"><a name="l00673"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga7efd0476f78ce206132d2b8dbe73e7b1">  673</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00674"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga8a9dd12769dd9227c0785d2f1ecddbf8">  674</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_DMA1ACN_POS)) </span></div><div class="line"><a name="l00676"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga9bf538ecdcd70445c420fb899809fe70">  676</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_USBACN_POS                       2 </span></div><div class="line"><a name="l00677"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga6f816b6073f51900931a950684fecfdf">  677</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_USBACN_POS)) </span></div><div class="line"><a name="l00679"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gac71050ef92202cd68749064a12fdbbf8">  679</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00680"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga844a5290bff499358ef3de11b46b2745">  680</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SYS0ACN_POS)) </span></div><div class="line"><a name="l00682"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gaa93d642e4ceab65bab912a747bee0d41">  682</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00683"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gaa72ae31e82723ce6d52f6e2ebe0d3fe5">  683</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SYS1ACN_POS)) </span></div><div class="line"><a name="l00685"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga553ecb27dbbe6f08b22d70c7e319ca2c">  685</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00686"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gae6bd256f9848cfb97f1926418d0dcf70">  686</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SDMADACN_POS)) </span></div><div class="line"><a name="l00688"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga65c8bb0dda0ad6ef19e1b534f7fa621c">  688</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00689"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga6398416cb3807485439911c917724ce7">  689</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SDMAIACN_POS)) </span></div><div class="line"><a name="l00691"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga733ed8a37c8aebcb25253337a6fe2097">  691</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00692"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gac13aba84e71f18bdc5cc46481a357ef3">  692</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00694"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga6281ca27ca8ed7ca3af275d13ff0abcf">  694</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00695"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga4a955cc40006f11c70f843632024a309">  695</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SDIOACN_POS)) </span></div><div class="line"><a name="l00705"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gaf96c2c444706cbc834284abd3439f691">  705</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00706"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga592e011ffa599a62108579cf2954a51f">  706</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_DMA0ACN_POS)) </span></div><div class="line"><a name="l00708"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga46f292ecb6b674bb6433a3d8f22b96ca">  708</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00709"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga360babfc90435e773f8e42e048dbc6e9">  709</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_DMA1ACN_POS)) </span></div><div class="line"><a name="l00711"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga19a5be52be14e314f3884de82d40b7c9">  711</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_USBACN_POS                       2 </span></div><div class="line"><a name="l00712"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga56c0ff07452fd0d3db3e0dda55aa64ca">  712</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_USBACN_POS)) </span></div><div class="line"><a name="l00714"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gaaa6fa71d3de1c34c51217d6a62aeddee">  714</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00715"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga612e99b56b58c496578276e843d5cc8e">  715</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SYS0ACN_POS)) </span></div><div class="line"><a name="l00717"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gaef333d3fbe29ab4ba51855587b46c261">  717</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00718"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga51c3ce88248582b0b6cec5a8ed095720">  718</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SYS1ACN_POS)) </span></div><div class="line"><a name="l00720"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gae6e873bf156f3791439888f02f15f985">  720</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00721"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga9e90c20f4612796371094f0c39be0330">  721</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SDMADACN_POS)) </span></div><div class="line"><a name="l00723"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gafb8764c52fabe8378a1991b4b2f63ac0">  723</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00724"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga66eb595770a8e96fa0f4402156b32896">  724</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SDMAIACN_POS)) </span></div><div class="line"><a name="l00726"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga8bbfa55d92dc03b6885877bc32ad6dfc">  726</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00727"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gab01b31e652a552e1d9efbaaa2834d008">  727</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00729"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga45bf3ac9d768976caff451d52ffc79d4">  729</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00730"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga024cda5796bdff5e94fceb28937ca89f">  730</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SDIOACN_POS)) </span></div><div class="line"><a name="l00740"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga4569c447b8e038b577893a414058a713">  740</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l00741"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gae4020d6ea794759df54bd0f95f13e65a">  741</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_DMA0ACN_POS)) </span></div><div class="line"><a name="l00743"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gaeff0ec284c24a034cbc9664087a7851e">  743</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l00744"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga276389ca290bf8bbd56d2e3bae326533">  744</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_DMA1ACN_POS)) </span></div><div class="line"><a name="l00746"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gaa8db4dafcfb97031a72b4c69628d942e">  746</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_USBACN_POS                    2 </span></div><div class="line"><a name="l00747"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga7fbaaf8d966a849b32bee7be1fa6428e">  747</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_USBACN_POS)) </span></div><div class="line"><a name="l00749"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga5799f8d27c64ae5ef41f8aba10cd872d">  749</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l00750"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga2060cb2b62d5b0818111b9d937479a84">  750</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SYS0ACN_POS)) </span></div><div class="line"><a name="l00752"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga704376dd1d331af67cca3a5b80c78442">  752</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l00753"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga17f003bd99f2f5b1aa5fddeeeafc83df">  753</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SYS1ACN_POS)) </span></div><div class="line"><a name="l00755"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga8c3b4fb940e5450c57bb0871a462a2c5">  755</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMADACN_POS                  5 </span></div><div class="line"><a name="l00756"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gad427d6fcb4f0adbcf2bde34350cbcfeb">  756</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SDMADACN_POS)) </span></div><div class="line"><a name="l00758"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga1b975eb7882aae028ffda19cdcb1f009">  758</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l00759"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga8d429ef64d57742dfc27716a009d9dc4">  759</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SDMAIACN_POS)) </span></div><div class="line"><a name="l00761"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gaa857ae7041e4d97bf59420ab439c1069">  761</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l00762"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gae007d6889bc367574b2d322f415285ea">  762</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00764"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga819a48a505bc27a85345a26e9d44e0a2">  764</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDIOACN_POS                   8 </span></div><div class="line"><a name="l00765"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga58b4704b4b1f896ef9889247b3377cc8">  765</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SDIOACN_POS)) </span></div><div class="line"><a name="l00775"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga320491dd2aabd88189127e8174027e4f">  775</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00776"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#gaa18cca4f81bf4dc69c3b9202cf87c014">  776</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00778"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga8e125b1d1f23e1ecc6795445f500ad15">  778</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00779"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga10314a99486a6f6ca393686f36905585">  779</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00781"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga6886fba9b8fca27c480a747e89d4304b">  781</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_USBACN_POS                      2 </span></div><div class="line"><a name="l00782"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga1fd8b6a746433705e0d880089ea46bda">  782</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_USBACN_POS)) </span></div><div class="line"><a name="l00784"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga147da202cfc196a70c25238ff7c2c641">  784</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00785"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga2d4836c169f7f574591f21d5b9a7d109">  785</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00787"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#gaadd7263d07939acd5df3dd104999629a">  787</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00788"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga0b1a42535da32e6ba067781e2a297f3e">  788</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00790"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#gaf1f7436ac89840e192c53167e48fb399">  790</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00791"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga295f75f3fc0a754fa6e2a0a59a3dde92">  791</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_SDMADACN_POS)) </span></div><div class="line"><a name="l00793"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga1aa0ddd7911814d5b493b666710d78ff">  793</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00794"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga82e1b3f039b8a9579f328447a8d5bdbf">  794</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00796"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#gafbc9f809d67aa9423134d356cd607552">  796</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00797"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga2dab8bac9baa93d53f87f25b96435945">  797</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00799"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#gaa99a18581e1dfd84d2c9b091559ad14e">  799</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00800"></a><span class="lineno"><a class="line" href="group__RPU__BBCR.html#ga2009b2ec1555af40606de0169c7cdc63">  800</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBCR_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBCR_SDIOACN_POS)) </span></div><div class="line"><a name="l00810"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaa5db11c68cd9146653ae7b43d7071677">  810</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l00811"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gabf4ba9d4008a46800ec6c0eaeff9643e">  811</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_DMA0ACN_POS)) </span></div><div class="line"><a name="l00813"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga89452c5dd955595ccef0d23ca42c89fc">  813</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l00814"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaf2a9926d92bbb66a6d880bec749dcaef">  814</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_DMA1ACN_POS)) </span></div><div class="line"><a name="l00816"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga7cd7da8663b8f3f30d11d457d2286aab">  816</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_USBACN_POS                     2 </span></div><div class="line"><a name="l00817"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga2bfd3c80c2984ffd6405380844ee258f">  817</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_USBACN_POS)) </span></div><div class="line"><a name="l00819"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga02ad027850bf277117bf310a735a6649">  819</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l00820"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga9f7b81d3bb6c7b4915f5e66c534cf922">  820</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SYS0ACN_POS)) </span></div><div class="line"><a name="l00822"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaec025e5ecc2018849cf37e521cad640c">  822</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l00823"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaba943f5c4d690a551a4a382fdb77f945">  823</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SYS1ACN_POS)) </span></div><div class="line"><a name="l00825"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga66e93317c6a8f4f7abaca5138062ea7e">  825</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMADACN_POS                   5 </span></div><div class="line"><a name="l00826"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga1e58664648f84a140a4c58ecbcfc49fb">  826</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SDMADACN_POS)) </span></div><div class="line"><a name="l00828"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga42cde52fedadd87901a22452305ad8a3">  828</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l00829"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gac2eb97cb354b828785586873a2baf5b8">  829</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SDMAIACN_POS)) </span></div><div class="line"><a name="l00831"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga04306edd58942ea79f1fe1566b39e890">  831</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l00832"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gae7b85eaced4f94933d9f22f03e1f4782">  832</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00834"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gae14ef4dd0f971ee49a1492b4834be50c">  834</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDIOACN_POS                    8 </span></div><div class="line"><a name="l00835"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga37fa4ab1a0cd2c3788b3ba0acdea4525">  835</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SDIOACN_POS)) </span></div><div class="line"><a name="l00845"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga088272ce8ba3953078f66d1e9661af76">  845</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l00846"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gab4ea8ced74717eb642ba72f36c870c93">  846</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_DMA0ACN_POS)) </span></div><div class="line"><a name="l00848"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gae6bfae1113d3a441d057097e2c8e04da">  848</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l00849"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gad1bd8d4477d50440551530f95e6457cb">  849</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_DMA1ACN_POS)) </span></div><div class="line"><a name="l00851"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gacfb5ee544f717addd39e0a1547d060d4">  851</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_USBACN_POS                     2 </span></div><div class="line"><a name="l00852"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga2adc2f01e0ba73160432c0ab78044b56">  852</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_USBACN_POS)) </span></div><div class="line"><a name="l00854"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga166af524c718661b0a29fb3e5726b0b4">  854</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l00855"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gab2e6892352a801eec823c71b381ebae2">  855</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SYS0ACN_POS)) </span></div><div class="line"><a name="l00857"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gaf72b2324de9b1710a57d6ca0d598759d">  857</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l00858"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga1a6ad2a78dcd99067cd811c7e61ca6dc">  858</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SYS1ACN_POS)) </span></div><div class="line"><a name="l00860"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga66d7ada7d67bd388208201532416e6b9">  860</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMADACN_POS                   5 </span></div><div class="line"><a name="l00861"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga0ed93f9429b2d5a72c24748963bbc627">  861</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SDMADACN_POS)) </span></div><div class="line"><a name="l00863"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga5d1697a8c3ea0ebf45639cf137ef4fcc">  863</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l00864"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga42a79a214db07b860ceb6e1ace9795a2">  864</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SDMAIACN_POS)) </span></div><div class="line"><a name="l00866"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga8a7a6c2b1ae5cb8cf9b71947d674fe23">  866</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l00867"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga7306cb77f9b5a638e184fa670ec661f4">  867</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00869"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gae171adb61de8bb5a7e0292a59e28c290">  869</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDIOACN_POS                    8 </span></div><div class="line"><a name="l00870"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga3dd207b61fd8822f8dc7519f6210a95d">  870</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SDIOACN_POS)) </span></div><div class="line"><a name="l00880"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga75c5b18d3d516ea2e073526ef016f95a">  880</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00881"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga495990e1cfb6b5614487068e0d1eaa68">  881</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_DMA0ACN_POS)) </span></div><div class="line"><a name="l00883"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga04b8f00a8494383456fcd7ccbdb2488d">  883</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00884"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gad9a19c812b731b927231974dc42dc102">  884</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_DMA1ACN_POS)) </span></div><div class="line"><a name="l00886"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga91d39beecfaf3f63ea1fa3cb3c03d9be">  886</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_USBACN_POS                      2 </span></div><div class="line"><a name="l00887"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga976e43193815750835fd12857608448c">  887</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_USBACN_POS)) </span></div><div class="line"><a name="l00889"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gae77fb312fd94eecbea83c4db59138064">  889</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00890"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga917b7396a66a57eb612aaf9f85c2186f">  890</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SYS0ACN_POS)) </span></div><div class="line"><a name="l00892"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga9eba409bfb929629c59a7e6f4ad8da11">  892</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00893"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga71443f7155b8ebb4f13104b76736ff63">  893</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SYS1ACN_POS)) </span></div><div class="line"><a name="l00895"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gafcd86ff62eb147654a97bdda98c50636">  895</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00896"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga9874f61c22f156bf7bede48d1a735efa">  896</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SDMADACN_POS)) </span></div><div class="line"><a name="l00898"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gaf45e63135227c4b86b3b28aab723c816">  898</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00899"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga344a749028ae763c52ea20119256244c">  899</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SDMAIACN_POS)) </span></div><div class="line"><a name="l00901"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga60358ed27753203bd73f89bdd1787ebd">  901</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00902"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga4d24c4cd8eda801dcc58491f679ae07d">  902</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00904"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gadedf7fdd53e9eb5daf19669f8282246d">  904</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00905"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gabd06ffd71ca62141aa1b9db626ac28d2">  905</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SDIOACN_POS)) </span></div><div class="line"><a name="l00915"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaa6f500345830f001fa029625107f69d2">  915</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00916"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaeac74ccd431a7087ad181c4d24e35755">  916</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_DMA0ACN_POS)) </span></div><div class="line"><a name="l00918"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga74e622c219ddd38b66a1276a50aad1aa">  918</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00919"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga7617c1fd6bba4f98f05bb4c33057e3a4">  919</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_DMA1ACN_POS)) </span></div><div class="line"><a name="l00921"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga04b730f1e82d7d8064167a6ed55c73af">  921</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_USBACN_POS                      2 </span></div><div class="line"><a name="l00922"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gac11aab58cac19300317710fc49129a0b">  922</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_USBACN_POS)) </span></div><div class="line"><a name="l00924"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga053cc5c3ab6776140f6dea0459eadd3c">  924</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00925"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga81e3bb7cd914b0dd170fae63b4683a53">  925</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SYS0ACN_POS)) </span></div><div class="line"><a name="l00927"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga9a52441c46bd5aa03dc1a2f896a9857e">  927</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00928"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga1472c8016e328c84398f9b62d399f7ef">  928</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SYS1ACN_POS)) </span></div><div class="line"><a name="l00930"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga06970102e8f282edcbff65caad668d0f">  930</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00931"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga3d5d6f72437839eaf8de31cd065e0bb4">  931</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SDMADACN_POS)) </span></div><div class="line"><a name="l00933"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga7ec625606000798375c78a490f793768">  933</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00934"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaa13dc7b24030e970232dca4aaf2dbc86">  934</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SDMAIACN_POS)) </span></div><div class="line"><a name="l00936"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaf21f920df39a53a467e4bcf2515138d5">  936</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00937"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga71140b8e5f1a99865042c0a5b7d05f06">  937</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00939"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga29ff72973e75c7aabe9d344afe3e91ac">  939</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00940"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga87ad75c32395013bbef606daca934c83">  940</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SDIOACN_POS)) </span></div><div class="line"><a name="l00950"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga6523751950e08dfd19759f1ac0a1a2cb">  950</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00951"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga5ce7b1d44b33ef931ef8e3c5818e1923">  951</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_DMA0ACN_POS)) </span></div><div class="line"><a name="l00953"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gab55aec1a61a30b1ed255f271b58b6bf4">  953</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00954"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gad691aab7341d4d63fb3e7f8905d65d28">  954</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_DMA1ACN_POS)) </span></div><div class="line"><a name="l00956"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga5a2bbbf45e4516a639dacfe897ffac4f">  956</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_USBACN_POS                      2 </span></div><div class="line"><a name="l00957"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gaf714b341f57e916de5ecfc605e6c59cf">  957</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_USBACN_POS)) </span></div><div class="line"><a name="l00959"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gabc388d52471cc160057c6d3da6c67360">  959</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00960"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gad62239bcc1029609561b1a2bf591f7d6">  960</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SYS0ACN_POS)) </span></div><div class="line"><a name="l00962"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga27c4a9417e5a6b00ea55672258081c38">  962</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00963"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gaf76084ca046aeb3aaf040976ff19f75c">  963</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SYS1ACN_POS)) </span></div><div class="line"><a name="l00965"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga96a4cb8f05319f7e1622966cb4440af8">  965</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00966"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga710b570f416d03d930c3ddb2a35d5977">  966</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SDMADACN_POS)) </span></div><div class="line"><a name="l00968"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga140dfabb3cb3c4349f40a0f372275648">  968</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00969"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga4157bdd559f60528cfffd11526cac265">  969</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SDMAIACN_POS)) </span></div><div class="line"><a name="l00971"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga651362f87566b4f21c5a3fd1b396ba4b">  971</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00972"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga2147ddf1013d8c4842b1d4c6d5be2115">  972</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00974"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gac562af7b8fdc9a3254cfcf1eba84b8bf">  974</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00975"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gaa9ca145006666d86a1bbf2cd9524fd14">  975</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SDIOACN_POS)) </span></div><div class="line"><a name="l00985"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga658c7874f29667f2f9cb4e6496e80362">  985</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00986"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gab612e51e4b7b076b879c49a7f79f6862">  986</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_DMA0ACN_POS)) </span></div><div class="line"><a name="l00988"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga3038c15864b7d70124b9056beeae8ee4">  988</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00989"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gad5d0b836b24dcdb64a278be7073a35d8">  989</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_DMA1ACN_POS)) </span></div><div class="line"><a name="l00991"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga402a6248e73ba85acb7d0758392b3cbc">  991</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_USBACN_POS                      2 </span></div><div class="line"><a name="l00992"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga3236b23726ba291911c014e62aff49cc">  992</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_USBACN_POS)) </span></div><div class="line"><a name="l00994"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga7aa669b71664bdd996fd7f6756bdcbb0">  994</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00995"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gae7a91abf9c98b38245dee7f0ec307c14">  995</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SYS0ACN_POS)) </span></div><div class="line"><a name="l00997"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga358b69c2787fb2db842678478a815f27">  997</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00998"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga8e45430a51d5e8a3e2fe2a9e128e8c55">  998</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SYS1ACN_POS)) </span></div><div class="line"><a name="l01000"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga3fcb85878a64537cf6bfd4b8eff8c834"> 1000</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01001"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gabfb2b89c5e56aa72e74e6fbfedcb7785"> 1001</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SDMADACN_POS)) </span></div><div class="line"><a name="l01003"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga61731340a4bf472442e55e53d96e5da0"> 1003</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01004"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga995c38f588b835ded6e6c9d3ca5f16f0"> 1004</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SDMAIACN_POS)) </span></div><div class="line"><a name="l01006"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga9a59d91acf515c319a245558d7ce1060"> 1006</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01007"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gafd9a39012ba2191737f3a0fd258412b7"> 1007</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01009"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga241d684c17acd033a6729f4b21fd9b51"> 1009</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01010"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga61d966afc5a06129454bc468ea7fdff3"> 1010</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SDIOACN_POS)) </span></div><div class="line"><a name="l01020"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga97dd2ba6090fe4c0d5c9cd245b559634"> 1020</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01021"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga22ce57afb3ee9d27c5a214ce30da0a45"> 1021</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_DMA0ACN_POS)) </span></div><div class="line"><a name="l01023"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gac4bf886fc5460896b7fc31f947a1b456"> 1023</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01024"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga6465d1ec95d5befb79d323ee5991a807"> 1024</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_DMA1ACN_POS)) </span></div><div class="line"><a name="l01026"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gaae70f4c4be16ada5c15992bb66fc8fa1"> 1026</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_USBACN_POS                      2 </span></div><div class="line"><a name="l01027"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga402b0b923a8e2df219e4b5d0d8ac153d"> 1027</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_USBACN_POS)) </span></div><div class="line"><a name="l01029"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga736c6b086fad7ad97fe48e82cb9dcaf0"> 1029</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01030"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga276367b0bcdbbf19830932e177d828cf"> 1030</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SYS0ACN_POS)) </span></div><div class="line"><a name="l01032"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gad79f0203dd52486c2340a18d2f541f21"> 1032</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01033"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gac2d6d71328a3a03e8215e49e38af5676"> 1033</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SYS1ACN_POS)) </span></div><div class="line"><a name="l01035"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gac31631c580fc1aeafb8e7935dfa4364b"> 1035</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01036"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga3a4fd39c8a8cb03126a150b761f3d7b7"> 1036</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SDMADACN_POS)) </span></div><div class="line"><a name="l01038"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga09cd1a79d0095d26bd9337dc841c85b2"> 1038</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01039"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga4732ca4fc3ece240022e33f3a1dd4c21"> 1039</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SDMAIACN_POS)) </span></div><div class="line"><a name="l01041"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga4a79c7d05ddedf62d280e31790420377"> 1041</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01042"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga00bf66fa1cf5593cbb2cb0d02ee3a79b"> 1042</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01044"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gaf6efdd2cd0fc4b2f0ec590c500ed2467"> 1044</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01045"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gae729f462eeb7009ce14f2e35b95e59fc"> 1045</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SDIOACN_POS)) </span></div><div class="line"><a name="l01055"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga913b8077be50daf219dbf00b6993019e"> 1055</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01056"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gadfc93ecbce80607d50a94e34a66b207e"> 1056</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_DMA0ACN_POS)) </span></div><div class="line"><a name="l01058"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga370d8ca6299329dd30889dbb57d64307"> 1058</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01059"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gac83ddf7b0fbb1127f042ba42e604bfff"> 1059</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_DMA1ACN_POS)) </span></div><div class="line"><a name="l01061"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga21c8419e92f4b0612236756e29079436"> 1061</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_USBACN_POS                      2 </span></div><div class="line"><a name="l01062"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga6389e580e5a961986a9f013df15b9fba"> 1062</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_USBACN_POS)) </span></div><div class="line"><a name="l01064"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gaeddbad3147e874323035af3ee4017b05"> 1064</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01065"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga4727421768ceb44aaaa8d9050719b957"> 1065</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SYS0ACN_POS)) </span></div><div class="line"><a name="l01067"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga17ce4263420feb84a56447e3ef01f286"> 1067</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01068"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga09aeed1ab101765303b9e0903a990dd6"> 1068</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SYS1ACN_POS)) </span></div><div class="line"><a name="l01070"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga6bcc47a18c7d07f0bcd6c2109622f292"> 1070</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01071"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga523a3c5e3c9df1dbf5691598b5cec131"> 1071</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SDMADACN_POS)) </span></div><div class="line"><a name="l01073"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gafdcbd467868fe7a43886a45eb05ddc1f"> 1073</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01074"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga82143ecc83be5fe8c3deddebe0f58bf4"> 1074</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SDMAIACN_POS)) </span></div><div class="line"><a name="l01076"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gabd4fbf6bf2ecfd1c248415c3d4b50104"> 1076</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01077"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gacd03ef43d92df594d556c605b541e4a2"> 1077</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01079"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga637d4ca9bc28f36b566bb9eb38f7cd35"> 1079</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01080"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga3fa9563c39f4f8cfcf2115f3c1880f5a"> 1080</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SDIOACN_POS)) </span></div><div class="line"><a name="l01090"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga5d04bd438fba5d51efaf253b0214ae8a"> 1090</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01091"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gadd9f591a0fda5ef13f9d5741b5d16274"> 1091</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01093"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga327c2175ff397a7846708dca6ca18166"> 1093</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01094"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga886b3b98f35b34f2dbe200777e2ef673"> 1094</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01096"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga9d2d1211238e3ab97a341ffd014d5e3b"> 1096</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_USBACN_POS                   2 </span></div><div class="line"><a name="l01097"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gab624337a92db4d1ba7b2005f0e3f1ad5"> 1097</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_USBACN_POS)) </span></div><div class="line"><a name="l01099"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga7c3ad9652ddf06a9c4d5aa60d26e11a4"> 1099</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01100"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gad7191b3a72ab400b85231beaf5bac6fa"> 1100</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01102"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga3c46bf5a1694451f7ae991db5b0089b3"> 1102</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01103"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gaf7ad2c3ba7834099c11c9de833cafc13"> 1103</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01105"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga51b5b1457b91fdf9dcf6a8fa99d013ac"> 1105</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01106"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga4db2bef15e456c7c8835a1e5a1b7095b"> 1106</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SDMADACN_POS)) </span></div><div class="line"><a name="l01108"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga41e4ee76ebf0330a92ef331c33e03570"> 1108</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01109"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga1b63069ec866d33f50bc05524a677a51"> 1109</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01111"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga7ba3cacfbce92112efbb07049b30f583"> 1111</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01112"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga4430f4643568c2586fff2fdb9eb4855b"> 1112</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01114"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gaba8af080229a589be7f740cc40dbc834"> 1114</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01115"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga37ef8530632a8ee39fe933657597ab5d"> 1115</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SDIOACN_POS)) </span></div><div class="line"><a name="l01125"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga124cd2f28d464d3227e532aa644e4959"> 1125</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01126"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga9b86479d5b894501bafc5d2a7a8a3997"> 1126</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01128"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gaa491f9b0b42bfb9e18c50533727da293"> 1128</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01129"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gab32729a01924593862023c711be13454"> 1129</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01131"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gae5147ec732997ee88a37ce67faefbf1e"> 1131</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_USBACN_POS                   2 </span></div><div class="line"><a name="l01132"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga139acf6899875b2160ae7d3ad169aa45"> 1132</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_USBACN_POS)) </span></div><div class="line"><a name="l01134"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga6ca8351efd86fd40a492ab7ae3d4afa0"> 1134</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01135"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gae9ffe24f562d646fb727c238831e00bb"> 1135</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01137"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gaff53d7b98a8cc36874391e9a0ee92296"> 1137</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01138"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga99890fe9ebf3334f9cd334c8bb6fa636"> 1138</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01140"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga4a8e45a3a9069e8dd63b8c243d0bf2f7"> 1140</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01141"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga0d90df4402a0e0071f72e405a1f4da32"> 1141</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SDMADACN_POS)) </span></div><div class="line"><a name="l01143"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gaba5c8ad2cd144026b773b0a0a83aea9c"> 1143</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01144"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga20041e0ac4b00734efc4ae8f814a8003"> 1144</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01146"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga3eb3360cbbb829e3eab8e3beb200eac6"> 1146</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01147"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga6ec6840e7f69453784aaccca2fcd3a2d"> 1147</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01149"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gab4857b5322ea1426eec70479ccc5b02e"> 1149</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01150"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gafa1dbcaa12cca9cdc355e69221f58553"> 1150</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SDIOACN_POS)) </span></div><div class="line"><a name="l01160"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#gab5a6d13046a52ee33a1e9c9638f987e6"> 1160</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01161"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga852bb274fbfc05d53e6a8d24592efe80"> 1161</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01163"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#gaf60368e9b89cf3e677ff9192568dc155"> 1163</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01164"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga097338fb9fb5e9c0c298148203e0114e"> 1164</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01166"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#gac1bc7785e792c0e4b60053991860b9e9"> 1166</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_USBACN_POS                      2 </span></div><div class="line"><a name="l01167"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#gab345d58aa970e335f2e28ff3b2dba920"> 1167</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_USBACN_POS)) </span></div><div class="line"><a name="l01169"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga488e402127afb60947f24b883607777c"> 1169</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01170"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#gad8f3f43b24b1b47aa0b60cc173e4ea62"> 1170</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01172"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga79e0530b49d372b10e9436276600d4b2"> 1172</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01173"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#gaff4a0ef445bdca6ff928c88af4ed7549"> 1173</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01175"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga936e94e8e6ed8fcf5f89f008f64b169b"> 1175</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01176"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga7993da3d9d058006a72c67313b230ca9"> 1176</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_SDMADACN_POS)) </span></div><div class="line"><a name="l01178"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga64ef7666bd6e419bd331eaad5d15ee9f"> 1178</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01179"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga513dbc62fabc4f35c7f14eec407daaef"> 1179</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01181"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga31fa9994c0b5b14ff8dadb40de3d8d4c"> 1181</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01182"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga0b6eeb3de01f63e773aa375a48a8eb83"> 1182</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01184"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga024c8da321305595600767c37cf0fbe6"> 1184</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01185"></a><span class="lineno"><a class="line" href="group__RPU__I2C0.html#ga8fd71bbc95ebf87b1f1069fb7a0ae08f"> 1185</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_SDIOACN_POS)) </span></div><div class="line"><a name="l01195"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga954c698c5e400056f605861513ac4417"> 1195</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01196"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga90ccf969351ed8b00b19eef2a607c744"> 1196</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01198"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga6c5ca9741ad64dfcba3a4d4378ae1573"> 1198</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01199"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#gac2ca54961298f0dda89a8a9b94e08650"> 1199</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01201"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga763151a1cec7fba8a7d4bea36103ca8e"> 1201</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_USBACN_POS                      2 </span></div><div class="line"><a name="l01202"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga51b5f2aec47f5e7acb42a0a2b73b9def"> 1202</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_USBACN_POS)) </span></div><div class="line"><a name="l01204"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga11720988b172db42743a6e69e396c6fe"> 1204</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01205"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga190d179703d3224969124f9e1a0a3eff"> 1205</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01207"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga2525904ba19cba6934b9e1d6110dcf97"> 1207</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01208"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga7000ba802bdacf8b27399064e3bb6320"> 1208</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01210"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#gaf07b0b2d43f85754aaf6a00353e5895a"> 1210</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01211"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga38a60eca96ded1a13588c49c3e2d7e46"> 1211</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_SDMADACN_POS)) </span></div><div class="line"><a name="l01213"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga969b7169a93a3f338519b9a87cb35427"> 1213</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01214"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#gabe9d889fbffcd5e6b81e321e093eaa69"> 1214</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01216"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga7960f0081cdcf42ffe960fc178319724"> 1216</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01217"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga024a00f0dfb9ced7620c7f1d2cb60840"> 1217</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01219"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga7ae97b7082f39e463b9ef25f0a3637fb"> 1219</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01220"></a><span class="lineno"><a class="line" href="group__RPU__I2C1.html#ga492ca14cd7517248592918f8f383e585"> 1220</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_SDIOACN_POS)) </span></div><div class="line"><a name="l01230"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga186ab7ed870fa54b8c7b43c531099bb1"> 1230</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01231"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga7ab1aec29666da4c4bde43e01b69111e"> 1231</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_DMA0ACN_POS)) </span></div><div class="line"><a name="l01233"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#gaffb8b5e66e59c0890d83b5a6d9568319"> 1233</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01234"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga31f27bf3e68614f5256aa3368aa7826d"> 1234</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_DMA1ACN_POS)) </span></div><div class="line"><a name="l01236"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#gaf95deed6bf79b569c50a6663619941d4"> 1236</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_USBACN_POS                      2 </span></div><div class="line"><a name="l01237"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga8004d393be46f7c03b156fb8a500deee"> 1237</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_USBACN_POS)) </span></div><div class="line"><a name="l01239"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga3f3fa4c1ddcd5e74761d8355488b2523"> 1239</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01240"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#gad9d9848be64adf7b07f53a6d11ce3710"> 1240</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_SYS0ACN_POS)) </span></div><div class="line"><a name="l01242"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga2f6b655e23df9e76a634cf8b2c25611a"> 1242</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01243"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga3279ae5d810fd3b8bb8b29708bf92cf1"> 1243</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_SYS1ACN_POS)) </span></div><div class="line"><a name="l01245"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#gae0e22cacb1f8187478b41cb8f3cbcaf0"> 1245</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01246"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga40fcd6ecb8d6e697d21d40f657ca9851"> 1246</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_SDMADACN_POS)) </span></div><div class="line"><a name="l01248"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga1cea10c46dc79ba986d70aa74bade320"> 1248</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01249"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#gafea52d1a321a4c6cca475766b9a8c9d1"> 1249</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_SDMAIACN_POS)) </span></div><div class="line"><a name="l01251"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga8c3f68d0e0d8021d6af3043f35f08562"> 1251</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01252"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga9b598092254bb4287f123fc878879dcc"> 1252</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01254"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#gaa9c02fa0735a998dcdcf89d824689e5e"> 1254</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01255"></a><span class="lineno"><a class="line" href="group__RPU__I2C2.html#ga36f610e4b6698657571271a48b5f3f35"> 1255</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_SDIOACN_POS)) </span></div><div class="line"><a name="l01265"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#gac656495ce64ea58e4f7dd215d9ae7855"> 1265</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01266"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga259882da134d52d512447e3d34fdb92c"> 1266</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_DMA0ACN_POS)) </span></div><div class="line"><a name="l01268"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga7e7bead4f6061f87e906a25961f60c76"> 1268</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01269"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga15bfeabddc6eafebe90929a7989d0c24"> 1269</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_DMA1ACN_POS)) </span></div><div class="line"><a name="l01271"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga014a76b9162e044631ae65e2eb00b692"> 1271</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_USBACN_POS                   2 </span></div><div class="line"><a name="l01272"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga37f4b4bf6ff9b80cd8d534742a650cea"> 1272</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_USBACN_POS)) </span></div><div class="line"><a name="l01274"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga5319959709abb4475e96b9751d8ad65b"> 1274</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01275"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#gabd53ec58d6b5cf144ea5e338896e0ed6"> 1275</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_SYS0ACN_POS)) </span></div><div class="line"><a name="l01277"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#gacfdbd7505b34a0c20bb54e95144fb9f9"> 1277</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01278"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga946404a738ea456c4fcac3f481966b5a"> 1278</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_SYS1ACN_POS)) </span></div><div class="line"><a name="l01280"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga418bfa764405ab27e92262466f2fd208"> 1280</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01281"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga671a9468948fe46e4a2e74f13421b257"> 1281</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_SDMADACN_POS)) </span></div><div class="line"><a name="l01283"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga9ed542e26ca9540dbb982f9bd796d6e6"> 1283</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01284"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga96816f7a363d170317e2924c862500d8"> 1284</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_SDMAIACN_POS)) </span></div><div class="line"><a name="l01286"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#gac55a05a509762f5ad20d871bda730d1b"> 1286</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01287"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga80adca710beba66bcdd2ce45027d25a4"> 1287</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01289"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#ga7442c4c58bc461d0ea280f3b286bec06"> 1289</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01290"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPM.html#gad40d67b1326f84f2bda212a8f2c70c71"> 1290</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPM_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPM_SDIOACN_POS)) </span></div><div class="line"><a name="l01300"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga5ce2b6ddbaf7e59b39a2b44f862e7655"> 1300</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_DMA0ACN_POS                 0 </span></div><div class="line"><a name="l01301"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga3b5950f60a389df10fdb1ca150c87e3f"> 1301</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_DMA0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_DMA0ACN_POS)) </span></div><div class="line"><a name="l01303"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga816cd413caf31d69bc2b14db4a5b1387"> 1303</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_DMA1ACN_POS                 1 </span></div><div class="line"><a name="l01304"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gaedc1fc10fc1cfc1c92770c1b3575d496"> 1304</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_DMA1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_DMA1ACN_POS)) </span></div><div class="line"><a name="l01306"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga4b7a5013315f2e809aaa3097f36e1126"> 1306</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_USBACN_POS                  2 </span></div><div class="line"><a name="l01307"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gaa1a76dec2f9e5d65d60a193f4ab38be7"> 1307</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_USBACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_USBACN_POS)) </span></div><div class="line"><a name="l01309"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gaf8d9485347d095a426bdd280ebdc0d90"> 1309</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SYS0ACN_POS                 3 </span></div><div class="line"><a name="l01310"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga8a4912d1832a6c5d4b878117fb0232ea"> 1310</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SYS0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_SYS0ACN_POS)) </span></div><div class="line"><a name="l01312"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga660b2ef8c8ad8677786daa3b45fcdbad"> 1312</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SYS1ACN_POS                 4 </span></div><div class="line"><a name="l01313"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gaad3480699ff964c6b8618c8e90e4d2e0"> 1313</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SYS1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_SYS1ACN_POS)) </span></div><div class="line"><a name="l01315"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga72620f426935c7a907c78ea3a9852fca"> 1315</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SDMADACN_POS                5 </span></div><div class="line"><a name="l01316"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gab763d50705bebda205c6f1dbb9dc3ee3"> 1316</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SDMADACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_SDMADACN_POS)) </span></div><div class="line"><a name="l01318"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gaaffe93903f1f7bfcf80b17aa961fd0f7"> 1318</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SDMAIACN_POS                6 </span></div><div class="line"><a name="l01319"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gafd77d31cf7b7aaf53a5af3ec63123585"> 1319</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SDMAIACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_SDMAIACN_POS)) </span></div><div class="line"><a name="l01321"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gab6e444e8f97aa164ce6d6e1e9061b49e"> 1321</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS               7 </span></div><div class="line"><a name="l01322"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga44a11431a568f92dc74c87e76aa4eff5"> 1322</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_CRYPTOACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01324"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#gaddf7e9d7a4036f05855ac692e6f5a244"> 1324</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SDIOACN_POS                 8 </span></div><div class="line"><a name="l01325"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMC.html#ga5f27f60cde647cf697e129f77688fc8e"> 1325</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMC_SDIOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMC_SDIOACN_POS)) </span></div><div class="line"><a name="l01335"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaaac30a92418dc6b8a994a0b4e4cbd1e0"> 1335</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01336"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaa072bec83f56706b4024cda91e6c8cc0"> 1336</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01338"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gacff6b95c9815e786960623252d9b9071"> 1338</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01339"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga39714c9edf98bb6562368dfdec4b1a16"> 1339</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01341"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga4cc8a106385ce0bd2ded879af432216a"> 1341</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_USBACN_POS                      2 </span></div><div class="line"><a name="l01342"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga6257eab00fd2c882f129a9913847ca86"> 1342</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_USBACN_POS)) </span></div><div class="line"><a name="l01344"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga44be5d94765c607470bc69558159bf84"> 1344</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01345"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gab3eb118a820424bf722bbe0c6d069c7a"> 1345</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01347"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaf0aa86ee311f767b60eb1eeefc76dd04"> 1347</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01348"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga6cb40140bb0bbef7f5c3618305a83cc7"> 1348</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01350"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga3b32064707683b554534ec2f5e515c31"> 1350</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01351"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga7f44a7929a23fc2e2bc80cf1abd89da9"> 1351</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SDMADACN_POS)) </span></div><div class="line"><a name="l01353"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga8dd41e25f4cfd14ed40259c62752dd13"> 1353</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01354"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga8cfa5b0fdbed7f5c96a9a303a384a47e"> 1354</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01356"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaaae657c5e6d1520064298045dfa5311d"> 1356</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01357"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaef76eea2e0e85c6750ecc24478097f35"> 1357</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01359"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaff2b33395677f6e2281d5cf65c3aa4b7"> 1359</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01360"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaf2ff1a705aa4a4dd9e7b7ef4c2bbd8ff"> 1360</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SDIOACN_POS)) </span></div><div class="line"><a name="l01370"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga0d250b554193a0d57f0e62d63be440dd"> 1370</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01371"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga1e49c14ffcaba30bc1a14176213cac75"> 1371</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01373"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga4d9d6df5ca77135cbc7943a6c8cc5f39"> 1373</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01374"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#gad338eb72bdafb8ce48cf37c81ab553a1"> 1374</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01376"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga38982917eb333ef90000d735dea48ead"> 1376</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_USBACN_POS                      2 </span></div><div class="line"><a name="l01377"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga3ea22a69095779bdd25d389004e33743"> 1377</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_USBACN_POS)) </span></div><div class="line"><a name="l01379"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga9cb71197ed95733ddc5a73b22e1bb5d9"> 1379</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01380"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#gab2555af18790432df380966e668d235a"> 1380</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01382"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga8c4efafca2aa49e4f50b482a8b6dc4b5"> 1382</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01383"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga9e0a8bafccf0ecc3112b1f4e12f77a34"> 1383</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01385"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga90a92f715126046d8466ec783a978e06"> 1385</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01386"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga2b2ab5335365fa64f291e864af2baefc"> 1386</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SDMADACN_POS)) </span></div><div class="line"><a name="l01388"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga0fe9606419f294f7e10b684e1772399a"> 1388</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01389"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga4a2798163095e8eb618b9f7943ec6199"> 1389</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01391"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga1774245cfdc9097cdf293d1a146a9ee1"> 1391</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01392"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga62be6a54525bc94528bb38afc1da8993"> 1392</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01394"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga0b19160276cddb01fc5cb1351f845193"> 1394</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01395"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#gaba940b1bf7c68cd22710ff453874a9f6"> 1395</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SDIOACN_POS)) </span></div><div class="line"><a name="l01405"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga9e71d13c36a918630ea5513a4eaf7b67"> 1405</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01406"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga4da14dac3bbd913f7817fa4465cc3feb"> 1406</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01408"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga6cb43ab8a3a65bee299dde641f81bb33"> 1408</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01409"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga2158e80541f33bc29a78e183f05be3e4"> 1409</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01411"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gaf4a3aa53bbe8f54be86eed324a1f5f06"> 1411</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_USBACN_POS                      2 </span></div><div class="line"><a name="l01412"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga63f3535ec4b7c0df9637fc0c7a9bc5f7"> 1412</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_USBACN_POS)) </span></div><div class="line"><a name="l01414"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga93610f5e8de8f84db7ec15d61c8d0e94"> 1414</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01415"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga928c96df4296255ed9112be9e2e4844a"> 1415</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01417"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga167b22530aca9c15261bd709a4b1bc8c"> 1417</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01418"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gaa990eab68b110b8dc7a479c167ba7bae"> 1418</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01420"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga00aca77c11c7f2b9e9cfef0cb6c07cf5"> 1420</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01421"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gaf10a0446e0e869266d0897ccdc220655"> 1421</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SDMADACN_POS)) </span></div><div class="line"><a name="l01423"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga7d68d92ff0bad4cc72c6fcfdc493998f"> 1423</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01424"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga6b07f10878bc57e3697a3d88b84f35a7"> 1424</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01426"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga8eed358f70642c60964178435b5098ab"> 1426</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01427"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gac5f1220fb91df2ddab070e4ded809daa"> 1427</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01429"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga4b4ed47f882b81512ec0e9b9107a9ca4"> 1429</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01430"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga55befb13e027b35f4b50860a4c50200e"> 1430</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SDIOACN_POS)) </span></div><div class="line"><a name="l01440"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#gaa92d59993107cf31c3b19b2b1bbf1978"> 1440</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01441"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga38ca7fdc6bfe68ce4bf3bfb16923b7e1"> 1441</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01443"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga2d7c037f32526c65fedb2888aa513cd6"> 1443</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01444"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga1b9b09e5b86a06dc69e29af635eaaad6"> 1444</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01446"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga1386886891900deffe66d0ab6151a902"> 1446</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_USBACN_POS                   2 </span></div><div class="line"><a name="l01447"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#gabb2687e9524b32ff78614fab066897fa"> 1447</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_USBACN_POS)) </span></div><div class="line"><a name="l01449"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#gae613f2f59bd4391abaf889bd3c318788"> 1449</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01450"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#gac98cd90a6c5c7f4a5516e0e98d336780"> 1450</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01452"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga459ccc4007818918aca5ee0d0d3d029d"> 1452</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01453"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga9364ad6d94c58aa67969edf4554e6170"> 1453</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01455"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#gac6df480322a5cc646694494cace8b30c"> 1455</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01456"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga52927b05eef9ac9b0f37ed177f252c3e"> 1456</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_SDMADACN_POS)) </span></div><div class="line"><a name="l01458"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga81bb69bcb7a4988b54600606a1b131b1"> 1458</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01459"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga8ef2a31a0b4212cc165a651f70fe0992"> 1459</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01461"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga8e62e909516dce35767aa1349b324097"> 1461</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01462"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga7b9c751a701253c58ec0e36edbf45648"> 1462</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01464"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga53a8127bd074b26c73668d1f60bfd9ec"> 1464</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01465"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE0.html#ga726a13c55ff80792a6f52b9aa48dc3cb"> 1465</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE0_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE0_SDIOACN_POS)) </span></div><div class="line"><a name="l01475"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga74c63e4931ca09f6211c7655c611b602"> 1475</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01476"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga5d847ca04ea992f47101b1cb0d52dc23"> 1476</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01478"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#gaac2b600efc62a447933f1c7ecfd045c3"> 1478</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01479"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga0b6e3523f7e744ef80b13cd68e45c80b"> 1479</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01481"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga71bf98a2c8825d2c03455eb89e64a1d4"> 1481</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_USBACN_POS                   2 </span></div><div class="line"><a name="l01482"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga7e02a158d9d35b731dc48c6258bfb860"> 1482</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_USBACN_POS)) </span></div><div class="line"><a name="l01484"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga6bc385ed7a2450b15834c3078205836b"> 1484</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01485"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga6cca64135be6b271d6f635ca7b5a2059"> 1485</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01487"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga3967f95b1369ff05c46e8f3cb2dedfd6"> 1487</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01488"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga340cbcc482594dddfe9d9cd525837c21"> 1488</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01490"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga0025616975e3c3a65915513efd26d9d1"> 1490</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01491"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga61afdb22d4b055f239f2fbace1e6d22c"> 1491</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_SDMADACN_POS)) </span></div><div class="line"><a name="l01493"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga330f67c17007f3e13540db3c65024479"> 1493</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01494"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga97928a1a45ef4b63c31ce7ee87ef3dfb"> 1494</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01496"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#gab1197429155c8c950f42e88ca20a2cd1"> 1496</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01497"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#gac9e81e93057c29108e770d56df921805"> 1497</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01499"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#gab6381c8577268dd507b6c8262995afac"> 1499</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01500"></a><span class="lineno"><a class="line" href="group__RPU__ICACHE1.html#ga40e512743b23dad5bd83b2f9073ed351"> 1500</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHE1_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHE1_SDIOACN_POS)) </span></div><div class="line"><a name="l01510"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga63b081bb2bd8ca37b5a4ce1af6bca391"> 1510</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_DMA0ACN_POS                0 </span></div><div class="line"><a name="l01511"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga32af0e4462490e993d8e23122fdf924a"> 1511</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_DMA0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_DMA0ACN_POS)) </span></div><div class="line"><a name="l01513"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#gacb87886c3d3d0810b2c3112a9f8196c1"> 1513</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_DMA1ACN_POS                1 </span></div><div class="line"><a name="l01514"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#gac218ec1e7754ceef3c89565ea8cc9fc8"> 1514</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_DMA1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_DMA1ACN_POS)) </span></div><div class="line"><a name="l01516"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga72e7c668c676c91fe795d48602f8cb31"> 1516</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_USBACN_POS                 2 </span></div><div class="line"><a name="l01517"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga918aa6604d8ce89d50b2dcd12c8069ba"> 1517</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_USBACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_USBACN_POS)) </span></div><div class="line"><a name="l01519"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga713484e82f3412f58f32b122a2fc8a86"> 1519</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SYS0ACN_POS                3 </span></div><div class="line"><a name="l01520"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#gaf5de65efb3a391f10aa202944cefa35e"> 1520</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SYS0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_SYS0ACN_POS)) </span></div><div class="line"><a name="l01522"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga9a5b199a7b993c05c032150b4e8351e6"> 1522</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SYS1ACN_POS                4 </span></div><div class="line"><a name="l01523"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga38cdd9640993d2fb0a9e9ec31927cacd"> 1523</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SYS1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_SYS1ACN_POS)) </span></div><div class="line"><a name="l01525"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga9954b25d9bb787174bf85d8c14458534"> 1525</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SDMADACN_POS               5 </span></div><div class="line"><a name="l01526"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga7847c3cf8a95ce954f6404b59c88b3f4"> 1526</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SDMADACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_SDMADACN_POS)) </span></div><div class="line"><a name="l01528"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga6e26613c7d163090ebe03a01c8eee91e"> 1528</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SDMAIACN_POS               6 </span></div><div class="line"><a name="l01529"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#gaf9bc9a760e2df4b201035b348c00dd46"> 1529</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SDMAIACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_SDMAIACN_POS)) </span></div><div class="line"><a name="l01531"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#gade9091403f1e445cacbc2e833406aaeb"> 1531</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_CRYPTOACN_POS              7 </span></div><div class="line"><a name="l01532"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga92735a9a5e720248b651b0960388de74"> 1532</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_CRYPTOACN                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01534"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#gac631b4805c026c4339eb954582e4c8ab"> 1534</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SDIOACN_POS                8 </span></div><div class="line"><a name="l01535"></a><span class="lineno"><a class="line" href="group__RPU__ICACHEXIP.html#ga4011d5a25801216922fff79d8667faae"> 1535</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICACHEXIP_SDIOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICACHEXIP_SDIOACN_POS)) </span></div><div class="line"><a name="l01545"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga72aa1a3eec5aafd8cd4f82bae1ccc375"> 1545</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l01546"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga41db0481c4b4d6a9d5d70df71f10b5b9"> 1546</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_DMA0ACN_POS)) </span></div><div class="line"><a name="l01548"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga6d981ff306d156180ad6c41520de7af2"> 1548</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l01549"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#gacb5d6c8c08eaec587a6f7130f365515d"> 1549</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_DMA1ACN_POS)) </span></div><div class="line"><a name="l01551"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga4fba081d2b6c63ee584a0218a5f29353"> 1551</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_USBACN_POS                    2 </span></div><div class="line"><a name="l01552"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga421e693f10224640811b952836bb4749"> 1552</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_USBACN_POS)) </span></div><div class="line"><a name="l01554"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga70e2b2636899c7ad23bdf008cd1248f3"> 1554</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l01555"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga5f02e6466b9350b28276bbf080ab97a3"> 1555</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_SYS0ACN_POS)) </span></div><div class="line"><a name="l01557"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga31982cfd4dfade34b02a9fbf43cc2731"> 1557</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l01558"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga6e9f64c66689aa5b26ee7a3082194d57"> 1558</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_SYS1ACN_POS)) </span></div><div class="line"><a name="l01560"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#gaa7610bc1d95e34d08ffb5160c9085f30"> 1560</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SDMADACN_POS                  5 </span></div><div class="line"><a name="l01561"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#gaf068a1b3fe49d0f86f818f49a4734982"> 1561</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_SDMADACN_POS)) </span></div><div class="line"><a name="l01563"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga23e455a84dc9dc6a4dede4012824a77c"> 1563</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l01564"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga72b638aa89b4db89db85d7922ba942b4"> 1564</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_SDMAIACN_POS)) </span></div><div class="line"><a name="l01566"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga13ec1be8d188f8fa0e78c6997106e1e3"> 1566</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l01567"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga60bae9746872bb773fbb8e94e8e3bc91"> 1567</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01569"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga6c81081f516f5b8d1670166fa10b079e"> 1569</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SDIOACN_POS                   8 </span></div><div class="line"><a name="l01570"></a><span class="lineno"><a class="line" href="group__RPU__DCACHE.html#ga63e90849add29d1adfc75ba70567d07a"> 1570</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DCACHE_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DCACHE_SDIOACN_POS)) </span></div><div class="line"><a name="l01580"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga4a63de0cff3c784eca45c1aebd9b218a"> 1580</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l01581"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1c74857d1228d21abc8a820bb72b875c"> 1581</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_DMA0ACN_POS)) </span></div><div class="line"><a name="l01583"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaeb7eb1d76872a891f625c0c796fc8d8c"> 1583</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l01584"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga4090ebff75b5910127269d8f99ee8abc"> 1584</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_DMA1ACN_POS)) </span></div><div class="line"><a name="l01586"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga969d966cc08321e8b45449d2f4a15213"> 1586</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_USBACN_POS                       2 </span></div><div class="line"><a name="l01587"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1b73be95926164f95a7e8a302ce498b0"> 1587</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_USBACN_POS)) </span></div><div class="line"><a name="l01589"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga3c864f51da69c7101cb1b60c5b3932ec"> 1589</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l01590"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1be8a306010797f8a84db0cead233579"> 1590</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SYS0ACN_POS)) </span></div><div class="line"><a name="l01592"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga86d628f98f5bdf7960252e111ceb9f1e"> 1592</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l01593"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1dd91386eed8ff271a3833162ff6940a"> 1593</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SYS1ACN_POS)) </span></div><div class="line"><a name="l01595"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga7c2fce49a79e8a05cde2c3af74b719ec"> 1595</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMADACN_POS                     5 </span></div><div class="line"><a name="l01596"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaa898066d1a710d726bd6b36f7bad086f"> 1596</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SDMADACN_POS)) </span></div><div class="line"><a name="l01598"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gadb2d4ff8f4aaa8411648507a200bb1f0"> 1598</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l01599"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaaf041858322fbe68e25ca2bab52d95a5"> 1599</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SDMAIACN_POS)) </span></div><div class="line"><a name="l01601"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gabaecc29d86cf20f18ffef4ae57b9d567"> 1601</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l01602"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaa04688c6dc467e91da34070ef2e8af82"> 1602</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01604"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaec9307fa1ebca5f4a4819729d7cf85f0"> 1604</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDIOACN_POS                      8 </span></div><div class="line"><a name="l01605"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga8dc0742fda2d083bde7d76d4c9d6525f"> 1605</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SDIOACN_POS)) </span></div><div class="line"><a name="l01615"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga596be1b3796470725e1f1a936bd15220"> 1615</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01616"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga5d787c96810f5feb7fb96a75e88cb47d"> 1616</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01618"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga39c93098920ebd3fb49fd1dd6d0e05c6"> 1618</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01619"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga918f9277b1b0e7d1ba8ba93100d5378d"> 1619</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01621"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga89b7e89b990f15b9e5871fe97fc513f0"> 1621</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_USBACN_POS                      2 </span></div><div class="line"><a name="l01622"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gad6c1e07a30266ad07a8cba19fb0d8b3b"> 1622</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_USBACN_POS)) </span></div><div class="line"><a name="l01624"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga7601eaec0ee69e089266fbc4155536bb"> 1624</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01625"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gaa048f632a320996be790247075f4357c"> 1625</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01627"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gac02a9fc8e5b1d5b0801ed13d50d4bcee"> 1627</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01628"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gafc33c6f25d48b485fb62bd66e684c041"> 1628</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01630"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga7de7ba09798b9dc13f785e6634442cc3"> 1630</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01631"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga259735da1778d9e7822169eda5606340"> 1631</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SDMADACN_POS)) </span></div><div class="line"><a name="l01633"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga35f418023bde9dddeb36729157f4fefb"> 1633</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01634"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga879b8aa5d57bc9e0ecd6dd9acb3ff530"> 1634</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01636"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gaba5a75511874477669f2d57e0cc927b6"> 1636</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01637"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga450a3dea8838b14c0f59daa4501d812a"> 1637</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01639"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga83aeaa9a9a86234526a5c05345558b28"> 1639</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01640"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gaf296c345707b1da22d834b49db286645"> 1640</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SDIOACN_POS)) </span></div><div class="line"><a name="l01650"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga9e4db568a0ee380e49f2cd42dbe4645c"> 1650</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01651"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga9d0c8fdbd4aa9d8784ab3fd44dab2361"> 1651</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_DMA0ACN_POS)) </span></div><div class="line"><a name="l01653"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga2686f683f00112d193d9a539b3b62c70"> 1653</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01654"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gab9e870affb0a8e99b945390af4d52f18"> 1654</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_DMA1ACN_POS)) </span></div><div class="line"><a name="l01656"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga98f55aee810176d44cceef96193464a2"> 1656</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_USBACN_POS                      2 </span></div><div class="line"><a name="l01657"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7a7b0af8cf6ed9741b22825497b03745"> 1657</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_USBACN_POS)) </span></div><div class="line"><a name="l01659"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga50c25de38da8d036f87d774be7a6005c"> 1659</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01660"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gada1ce0639775ab7c5e6d2faa83cf6bb4"> 1660</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SYS0ACN_POS)) </span></div><div class="line"><a name="l01662"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gaf5240aa575d4585be1adad3e00336c5c"> 1662</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01663"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7047287dc06f86e50b028dfffbbaa2f6"> 1663</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SYS1ACN_POS)) </span></div><div class="line"><a name="l01665"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga032c8f95c4c24e892e1ff5bd970cda51"> 1665</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01666"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gadbd2b6b5523eae1f7b5de6deb396c4b6"> 1666</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SDMADACN_POS)) </span></div><div class="line"><a name="l01668"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gad8532f6b6a4e1b1c1b629396c9e08a75"> 1668</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01669"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga262290f224eb130208e998f4f176e2bb"> 1669</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SDMAIACN_POS)) </span></div><div class="line"><a name="l01671"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gac5c52f44acd1161733be694da9850e45"> 1671</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01672"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gaab7f883f4ddcbce67d884b61fce5ed73"> 1672</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01674"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7b1e32fca99bc9642f3f67a7a67abc33"> 1674</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01675"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7c3b62d4736acb88a62d1f7bbba171f1"> 1675</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SDIOACN_POS)) </span></div><div class="line"><a name="l01685"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gad5de5c91ea21a84582aa2e59ac0b34f2"> 1685</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA0ACN_POS                 0 </span></div><div class="line"><a name="l01686"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga05e6d8504501cc9a55df6dd9df054d51"> 1686</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_DMA0ACN_POS)) </span></div><div class="line"><a name="l01688"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaa3d10ad11f2c3c3364ef3b7928be2e02"> 1688</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA1ACN_POS                 1 </span></div><div class="line"><a name="l01689"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga6e1c77b14e6db5cfa2bccc470c45ae94"> 1689</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_DMA1ACN_POS)) </span></div><div class="line"><a name="l01691"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gab8f97a51c5c270e7805285c4f96b60b9"> 1691</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_USBACN_POS                  2 </span></div><div class="line"><a name="l01692"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga95b2c653a5d0fa7d35a3ac034c154cd1"> 1692</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_USBACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_USBACN_POS)) </span></div><div class="line"><a name="l01694"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gac4e7196e88e5186873681c870694ecd6"> 1694</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS0ACN_POS                 3 </span></div><div class="line"><a name="l01695"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaafa07d905c0c318cdfad51c63d4cddbb"> 1695</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SYS0ACN_POS)) </span></div><div class="line"><a name="l01697"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga28df6903b92f1d5239d93b570f27ddef"> 1697</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS1ACN_POS                 4 </span></div><div class="line"><a name="l01698"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga68b43247d6dca24ccacdbaa9453fd3a8"> 1698</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SYS1ACN_POS)) </span></div><div class="line"><a name="l01700"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gab9ddfbe2ae13a16829a041808c0f1b50"> 1700</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMADACN_POS                5 </span></div><div class="line"><a name="l01701"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga55961a126882b20e699f927184806180"> 1701</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMADACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SDMADACN_POS)) </span></div><div class="line"><a name="l01703"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gad6f86438c38cab6fe23aaa6d16a73aa6"> 1703</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMAIACN_POS                6 </span></div><div class="line"><a name="l01704"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaa0609e9ead17b162e0bde52c3fbea3c1"> 1704</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMAIACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SDMAIACN_POS)) </span></div><div class="line"><a name="l01706"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gad776c64b800b8d752ee3fe748a876088"> 1706</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_CRYPTOACN_POS               7 </span></div><div class="line"><a name="l01707"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga8533b460a44986e2f1fc3ec4bd2a13a0"> 1707</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_CRYPTOACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01709"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga122038524b3351fb39588b2e83219f02"> 1709</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDIOACN_POS                 8 </span></div><div class="line"><a name="l01710"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaad9e9b1cbe2bad1ece794af25d1bcfab"> 1710</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDIOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SDIOACN_POS)) </span></div><div class="line"><a name="l01720"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gaf8b4ab45d27dd8b6261b46bddd76131a"> 1720</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01721"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga474da9fddaa9444e5fb287f6319e071f"> 1721</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_DMA0ACN_POS)) </span></div><div class="line"><a name="l01723"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gaa361f4cfeb13de1a81bfb4ebfba817c9"> 1723</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01724"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga5054fad82ea8e0951df2bd689c8cb151"> 1724</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_DMA1ACN_POS)) </span></div><div class="line"><a name="l01726"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga5fd34d2d8f2446197c53483117a4b9f9"> 1726</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_USBACN_POS                      2 </span></div><div class="line"><a name="l01727"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gad1e6302b62fe949b42fc6c3858064670"> 1727</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_USBACN_POS)) </span></div><div class="line"><a name="l01729"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga800364abb3b4c0b78a41dd88034166e6"> 1729</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01730"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga2f8c37b9f3d0de8cca48bdb83003eb8d"> 1730</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_SYS0ACN_POS)) </span></div><div class="line"><a name="l01732"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga9bab949dbef4399c8889a164a64829b8"> 1732</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01733"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga146fd4c32b041fd032fd19bbd0f2172e"> 1733</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_SYS1ACN_POS)) </span></div><div class="line"><a name="l01735"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga8cc36d8f4198fcad444185967ada4b07"> 1735</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01736"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gac9c638c37015978c0fd8ff312638742e"> 1736</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_SDMADACN_POS)) </span></div><div class="line"><a name="l01738"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gab366310e5992f7a33fe449d61a0859a8"> 1738</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01739"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga8c5e6ed89c0cb336cdd17644870613f1"> 1739</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_SDMAIACN_POS)) </span></div><div class="line"><a name="l01741"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gac3304e366b54804f6e8fc7710126d90a"> 1741</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01742"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gaaebfcfbc5235d3af6ce8ae38c2d43d3c"> 1742</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01744"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#gaf2846ef557cc8d069cf00008d1a1dfee"> 1744</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01745"></a><span class="lineno"><a class="line" href="group__RPU__SPID.html#ga3ad1f31615319f265330d3c94e601107"> 1745</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPID_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPID_SDIOACN_POS)) </span></div><div class="line"><a name="l01755"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga39c67da002391d27403a02cb9102873a"> 1755</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_DMA0ACN_POS                       0 </span></div><div class="line"><a name="l01756"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga78e5859b58b92e2ef1865d6cea237a2e"> 1756</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_DMA0ACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_DMA0ACN_POS)) </span></div><div class="line"><a name="l01758"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga7e5a482f8a4a9e175edd397cc2906f39"> 1758</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_DMA1ACN_POS                       1 </span></div><div class="line"><a name="l01759"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga7ff0633a2bcc9dc3c985543d2818ae2a"> 1759</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_DMA1ACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_DMA1ACN_POS)) </span></div><div class="line"><a name="l01761"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga4058e49edb0f5fa7751fa10aa2a5e71b"> 1761</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_USBACN_POS                        2 </span></div><div class="line"><a name="l01762"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga9adca29f3d2b6ecdb8a1ac6b250100c4"> 1762</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_USBACN                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_USBACN_POS)) </span></div><div class="line"><a name="l01764"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#gab5d1f8607b8c892e6baf32350793ffce"> 1764</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SYS0ACN_POS                       3 </span></div><div class="line"><a name="l01765"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga869e5f812b4e663d024ade976c21928a"> 1765</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SYS0ACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_SYS0ACN_POS)) </span></div><div class="line"><a name="l01767"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#gaf55df2e4671e06d52b51dbd06b0df49b"> 1767</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SYS1ACN_POS                       4 </span></div><div class="line"><a name="l01768"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#gad4d5c7d785b0066aa19199475052e55e"> 1768</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SYS1ACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_SYS1ACN_POS)) </span></div><div class="line"><a name="l01770"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga23434b7e6c78eaf6c01e12ecf4db46eb"> 1770</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SDMADACN_POS                      5 </span></div><div class="line"><a name="l01771"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga77134fac74af3b1fc14fc30bdb14f6d1"> 1771</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SDMADACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_SDMADACN_POS)) </span></div><div class="line"><a name="l01773"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga6cffed9196d9707555b146616695149d"> 1773</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SDMAIACN_POS                      6 </span></div><div class="line"><a name="l01774"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#gaa5f29dcfc40d3aa8d338f0be908cdfdc"> 1774</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SDMAIACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_SDMAIACN_POS)) </span></div><div class="line"><a name="l01776"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga94212f31d531388571125c3df2ba1e40"> 1776</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_CRYPTOACN_POS                     7 </span></div><div class="line"><a name="l01777"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#gacb6a8f803f052391741afaf3813db7fc"> 1777</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_CRYPTOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01779"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga3750ed16ac17f680c0f76512b1be623d"> 1779</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SDIOACN_POS                       8 </span></div><div class="line"><a name="l01780"></a><span class="lineno"><a class="line" href="group__RPU__PT.html#ga8c759f97ec5e239ef2354cee63d756b7"> 1780</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PT_SDIOACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PT_SDIOACN_POS)) </span></div><div class="line"><a name="l01790"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#gacf0ffa1f074dfb058db0f5c7303b2ffc"> 1790</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l01791"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga3b82b473679baa026cb6e52ef0b44e59"> 1791</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_DMA0ACN_POS)) </span></div><div class="line"><a name="l01793"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga8ebf386f7d4eea8632060874e64d07c8"> 1793</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l01794"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga169c5a108c7b8469b39f28c1137ef1e1"> 1794</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_DMA1ACN_POS)) </span></div><div class="line"><a name="l01796"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga562a29e3664558c4f642253c0c0ad9af"> 1796</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_USBACN_POS                       2 </span></div><div class="line"><a name="l01797"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga6654b679741d53197bf672c4b5ac0e9c"> 1797</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_USBACN_POS)) </span></div><div class="line"><a name="l01799"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga5adc4da10831d4bb624387b2f893b281"> 1799</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l01800"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga354d50fa0c2386f3911fa191f7f15cb9"> 1800</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SYS0ACN_POS)) </span></div><div class="line"><a name="l01802"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga8ad9ed4b7fd5f844e75ffe8231424584"> 1802</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l01803"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga40d3122d9fbf1dc215f6b14859331d7a"> 1803</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SYS1ACN_POS)) </span></div><div class="line"><a name="l01805"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#gaf4a9226601db132059c4b4dd87a38ca1"> 1805</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMADACN_POS                     5 </span></div><div class="line"><a name="l01806"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga987a2cb401253f19339a1e46ffcfe850"> 1806</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SDMADACN_POS)) </span></div><div class="line"><a name="l01808"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga485ebafd212ca01976ef0d681939e220"> 1808</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l01809"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#gac0d9d8abf26182776fd42bd105fba49c"> 1809</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SDMAIACN_POS)) </span></div><div class="line"><a name="l01811"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga7245d8df0d9fcda03c38506268cd9cf7"> 1811</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l01812"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga94c0561f48ada11ae54021149b325b2e"> 1812</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01814"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga12393078f2ecdcd023eb9de651d23682"> 1814</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDIOACN_POS                      8 </span></div><div class="line"><a name="l01815"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga210735e35fe23579f0c5d93d3c0285f3"> 1815</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SDIOACN_POS)) </span></div><div class="line"><a name="l01825"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gad839e6656bcfa864acb5b923bf86e597"> 1825</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01826"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gadc225d8fb33d684120fbcfd1dcf0a0cf"> 1826</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_DMA0ACN_POS)) </span></div><div class="line"><a name="l01828"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga3601eb8bf270d822166ed7c3e5aba13c"> 1828</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01829"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga40be1fa2a460bbe958a98808bfc64c85"> 1829</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_DMA1ACN_POS)) </span></div><div class="line"><a name="l01831"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gacd2a5d6215fb39441524822cd37a1570"> 1831</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_USBACN_POS                      2 </span></div><div class="line"><a name="l01832"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga2dfcf705a51f8da27c3fb26af521c001"> 1832</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_USBACN_POS)) </span></div><div class="line"><a name="l01834"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga587a0885cf30ebddc88af549a911330b"> 1834</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01835"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga48d7f36747f0c548673aec48d8dbbfe3"> 1835</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SYS0ACN_POS)) </span></div><div class="line"><a name="l01837"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gaf5e849609b45fac19f0591625723f9bd"> 1837</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01838"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gaf553f80ed0e2a02388a4a28d054e90ec"> 1838</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SYS1ACN_POS)) </span></div><div class="line"><a name="l01840"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga18422e3e08ab661c93c766f207dd0eca"> 1840</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01841"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga33b90180db00a2f3eae25528ec57fa1d"> 1841</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SDMADACN_POS)) </span></div><div class="line"><a name="l01843"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga68b32a99ebc64348211fbdb7cd4425d6"> 1843</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01844"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga63fb375b59c7dad6ec6f4a70de0cc67f"> 1844</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SDMAIACN_POS)) </span></div><div class="line"><a name="l01846"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga151bbc937135ddecb0fb701e3fe6259a"> 1846</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01847"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga127aec806999623d2bdc624e5c35aada"> 1847</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01849"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga460ae167213cffb2623ed99de41498b3"> 1849</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01850"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga06e711476fadb3e483d85b04121aacb8"> 1850</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SDIOACN_POS)) </span></div><div class="line"><a name="l01860"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gac91a10f54ce8ca670dd985e70c792f60"> 1860</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01861"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga259231c9fdc4ee5742ca4790663aef98"> 1861</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01863"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga5f4898e494ac7114e1fe37b9770c49c5"> 1863</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01864"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gac573088d6bc80992f2954adfc3c1fd06"> 1864</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01866"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga4ef2dab23320eb30070b8aae40e118fc"> 1866</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_USBACN_POS                     2 </span></div><div class="line"><a name="l01867"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga58606600b22c9a8af7b0c3a30f6a9270"> 1867</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_USBACN_POS)) </span></div><div class="line"><a name="l01869"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gabc70702897811f9fed5c7c720c39d7a1"> 1869</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01870"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga3244c065baba0c2c4f2266fede5a6394"> 1870</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01872"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gae893b5d1213e1e94a24c9b56ed26a39b"> 1872</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01873"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gab2d75648fcc1b1054b59cab44adf5bff"> 1873</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01875"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gac66a3f1fdcf74768933c415610bc1aea"> 1875</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01876"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga58132e72fcf3d6524e2eeb6221a2e133"> 1876</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SDMADACN_POS)) </span></div><div class="line"><a name="l01878"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gae3a485e9b25a902296acb37735b3919b"> 1878</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01879"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga96283394db993675cd0554c5f2aba21e"> 1879</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01881"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga1d03a9fb644e7d0a4773cb7b43e05db8"> 1881</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01882"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga420a8893e5c8e66ff47d7c42e6dc6711"> 1882</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01884"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gaa343cea179696abf1cd95405567fa7d9"> 1884</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01885"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga5a0bf04464ab4a155810e9f73cd14441"> 1885</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SDIOACN_POS)) </span></div><div class="line"><a name="l01895"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gaaf7f45ffaf6b32bcf63756fa7e9ca029"> 1895</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01896"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gab8f6dee986f45d564e532a8ad9ff46ea"> 1896</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01898"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga983d82baec14eb71ec044517f48bf48a"> 1898</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01899"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga5510d182bd23dd06c379b9c1a6faed0b"> 1899</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01901"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga8e0305f6bf9d0965a62ac8ca6a5d867e"> 1901</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_USBACN_POS                     2 </span></div><div class="line"><a name="l01902"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gae89423f07dd7ab2e234a0e9470d9a954"> 1902</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_USBACN_POS)) </span></div><div class="line"><a name="l01904"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gaa9dbf33fea2ff661315ee1c18aead88b"> 1904</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01905"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga4ec63d315e71cd78e5725034cd60e506"> 1905</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01907"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga7d87b9929add9b3b823962040cbfc463"> 1907</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01908"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gab29c0859582767a4ce4d5e2a21b53be8"> 1908</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01910"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga7d1cd1000b3c7a558b2c438126b14d35"> 1910</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01911"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gaa40054936c85ab383e16c553ac69b671"> 1911</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SDMADACN_POS)) </span></div><div class="line"><a name="l01913"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga534270a51f1c683816e22b9c9b8550c3"> 1913</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01914"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gae31eb68280ae161f9b3d359ed1d6c958"> 1914</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01916"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gabcd0d9555a00bc1eeacd730158d63ed6"> 1916</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01917"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga44cdff4aaf5d09f8eba112d65fad5f82"> 1917</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01919"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga34cf0f514b57fb2eca440ce077c62c24"> 1919</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01920"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga95c875794d87305bea54368f6e97dbb7"> 1920</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SDIOACN_POS)) </span></div><div class="line"><a name="l01930"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga8142275d8923cc8858bebd48a4abeb1e"> 1930</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01931"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gaebda61867d08ba453ba449bb28401a9e"> 1931</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_DMA0ACN_POS)) </span></div><div class="line"><a name="l01933"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gab53b20c172a2731a3bb81e7b7507925d"> 1933</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01934"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga1bd1026e132f773fdc248f7691d01ec2"> 1934</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_DMA1ACN_POS)) </span></div><div class="line"><a name="l01936"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gabea2137f01df4a2fff71f682cb1d8689"> 1936</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_USBACN_POS                     2 </span></div><div class="line"><a name="l01937"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga87facbf169acf917cfb13b2c77ec1e68"> 1937</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_USBACN_POS)) </span></div><div class="line"><a name="l01939"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga3fec2db09d3b7132f7285af4d693b537"> 1939</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01940"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gae83ad07cc6f7cab5e0119aa180d87574"> 1940</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SYS0ACN_POS)) </span></div><div class="line"><a name="l01942"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gad9ed21fb99b367306f594f29043feda0"> 1942</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01943"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gae1c3f065c46655962ef4a57666b49777"> 1943</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SYS1ACN_POS)) </span></div><div class="line"><a name="l01945"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga1be38ceb7b14c9512742346af543aee0"> 1945</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01946"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga7eea78f38b68f384c46208fd4b4decf3"> 1946</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SDMADACN_POS)) </span></div><div class="line"><a name="l01948"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gadbbcd1774979946a01b94099c780d5fb"> 1948</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01949"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga8cfcc7a4839db9ba2ee9e12bd8b8f597"> 1949</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SDMAIACN_POS)) </span></div><div class="line"><a name="l01951"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga70eb9c22e47f37292c9d8afb72f113eb"> 1951</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01952"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gab7d657010c7500f49d9ab93ff0d28049"> 1952</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01954"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gaa359bf4bdf8df1ae690bc06d5e53dd2e"> 1954</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01955"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gae9b66870dd58ecf76bd49eaeee641b51"> 1955</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SDIOACN_POS)) </span></div><div class="line"><a name="l01965"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#gaeae39524ad21880dbdc06452dbc2f235"> 1965</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01966"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#gaa8ef5e0877f409f20dcd3f0770da3074"> 1966</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01968"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#gabaa7733506654780887c941c39e85f50"> 1968</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01969"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga0f852957adfb92df03017e82694fd656"> 1969</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01971"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga2fe5b3fcc13d00dee7c1823d72e82b06"> 1971</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_USBACN_POS                     2 </span></div><div class="line"><a name="l01972"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga9554f20ad91fc33c33ccc344499ec2fe"> 1972</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_USBACN_POS)) </span></div><div class="line"><a name="l01974"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga2898185f43001fea194e4e8b1ab6c905"> 1974</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01975"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga424f9e19787cb278841375617fe97ced"> 1975</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01977"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga605939cc576441a2235f22670869d32b"> 1977</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01978"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga2e50ede9ab76b11a235e291e10198cf5"> 1978</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01980"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga797ed1339fa6cfd4ca690a9520e413f8"> 1980</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01981"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga301b668ceb08c7286fd8e78760a93d69"> 1981</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_SDMADACN_POS)) </span></div><div class="line"><a name="l01983"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga01ef3a48fac9e1e7ed5a5f37edd38262"> 1983</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01984"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga33a16893f7bac08f38555decc49b4898"> 1984</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01986"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#gab1f4ebfd2888f6751386f8026f737dde"> 1986</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01987"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#ga860a3d8e16803d1db4c9b03ef9608393"> 1987</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01989"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#gacc2f14c20075c810892f2f8d7628c6dc"> 1989</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01990"></a><span class="lineno"><a class="line" href="group__RPU__QSPI1.html#gacc349eeddb992e461175772604565c0b"> 1990</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI1_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI1_SDIOACN_POS)) </span></div><div class="line"><a name="l02000"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#gaafa8facbee73fa9279aa67f804015caa"> 2000</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l02001"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#gafef255c9d917bca9401a0281917f2777"> 2001</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_DMA0ACN_POS)) </span></div><div class="line"><a name="l02003"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga25422615b330b8d11ea72496d2073d05"> 2003</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l02004"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga98e59480ba83b96a698e9f72d1825c56"> 2004</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_DMA1ACN_POS)) </span></div><div class="line"><a name="l02006"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#gafed847ba9e310f0548b92250c70d9572"> 2006</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_USBACN_POS                     2 </span></div><div class="line"><a name="l02007"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga698dfd03a03f3a74a33946fd5558609f"> 2007</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_USBACN_POS)) </span></div><div class="line"><a name="l02009"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga9d9e62b2d539a44fa22405e253806e88"> 2009</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l02010"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga5ee537f58a536dd48fde911025356adc"> 2010</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_SYS0ACN_POS)) </span></div><div class="line"><a name="l02012"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga15d16916382beac1ce3882f7ad284bee"> 2012</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l02013"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#gac2f40ec426f2c72a5be19f33720dd553"> 2013</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_SYS1ACN_POS)) </span></div><div class="line"><a name="l02015"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga22a3a9a04bfe669175d93d2658238922"> 2015</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SDMADACN_POS                   5 </span></div><div class="line"><a name="l02016"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga12b5d16cc312a4831ebcbcf745865063"> 2016</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_SDMADACN_POS)) </span></div><div class="line"><a name="l02018"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga5c29e3e221263f48a355bf7853a4355c"> 2018</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l02019"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga5c521b22f936549378e445943b33e11f"> 2019</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_SDMAIACN_POS)) </span></div><div class="line"><a name="l02021"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#gada852d3c026d3ca432e70a02717f0df0"> 2021</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l02022"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga7be2fb77525238e579ef74e5972ccd2e"> 2022</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02024"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#ga9d9901d960e390dcaa5d38b10998c8e1"> 2024</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SDIOACN_POS                    8 </span></div><div class="line"><a name="l02025"></a><span class="lineno"><a class="line" href="group__RPU__QSPI2.html#gae32dc606cd552b8afc2adfe4c0d07946"> 2025</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI2_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI2_SDIOACN_POS)) </span></div><div class="line"><a name="l02035"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaee8e89ece9fa2f2d943634d11fe29902"> 2035</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l02036"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga3685264e241376b152460548d7d73702"> 2036</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_DMA0ACN_POS)) </span></div><div class="line"><a name="l02038"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaea8a90bd33cc2bc7f67da13854bc7d4b"> 2038</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l02039"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga228649976a7406dcae395229ef6c7214"> 2039</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_DMA1ACN_POS)) </span></div><div class="line"><a name="l02041"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gafe9e7429f5e6e2b50f3b0b69f51f172f"> 2041</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_USBACN_POS                     2 </span></div><div class="line"><a name="l02042"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga390f291494a115dc03a41f3490f727ef"> 2042</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_USBACN_POS)) </span></div><div class="line"><a name="l02044"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga2d69a17086b1d71e3fb0ae9112af9657"> 2044</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l02045"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaa34730052edba6ce24f897a90794d16d"> 2045</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SYS0ACN_POS)) </span></div><div class="line"><a name="l02047"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gab0b54413e43a9f5dc06f35c75bd1f295"> 2047</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l02048"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga175107d6c2e8715736eef724ba0decb6"> 2048</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SYS1ACN_POS)) </span></div><div class="line"><a name="l02050"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga800cac5ddf6303662cf8e553159e772d"> 2050</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMADACN_POS                   5 </span></div><div class="line"><a name="l02051"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga583a3f12607bd223195237d3f523211d"> 2051</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SDMADACN_POS)) </span></div><div class="line"><a name="l02053"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaa319f042c382cebb2468d08d9cb33331"> 2053</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l02054"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga8629187b36c026890d31daedbe04b091"> 2054</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SDMAIACN_POS)) </span></div><div class="line"><a name="l02056"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga4ac3da3d7afb79fdbddfd5dde8a78c88"> 2056</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l02057"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaae60bf5f1a71f4d5deeba73a72f719cd"> 2057</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02059"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga0bdb627a2ab9a939d24ea0f66b4f26ef"> 2059</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDIOACN_POS                    8 </span></div><div class="line"><a name="l02060"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga1e37c86c7f5e17cfdc0c350a58187a2d"> 2060</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SDIOACN_POS)) </span></div><div class="line"><a name="l02070"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gad801b09c8e1233918f76c2cbe884fc78"> 2070</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l02071"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga6814dc8776d8d7f8ccad572bcda587cc"> 2071</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_DMA0ACN_POS)) </span></div><div class="line"><a name="l02073"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gadbd2f10999e4aa3901cd3230aff888d0"> 2073</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l02074"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga487da76645221c9d68f42f6b9526af46"> 2074</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_DMA1ACN_POS)) </span></div><div class="line"><a name="l02076"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gaff8ea21c34d572148b206ee0fab6552e"> 2076</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_USBACN_POS                      2 </span></div><div class="line"><a name="l02077"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga432f37df792593d95da5dbc00872f2ca"> 2077</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_USBACN_POS)) </span></div><div class="line"><a name="l02079"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga95324901d39b0ad6baca4c8fdb737979"> 2079</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l02080"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gacf7d1b9ca36d5dcd628c79f0df775dcb"> 2080</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SYS0ACN_POS)) </span></div><div class="line"><a name="l02082"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga88ca992464198d232e6c874e228bc99a"> 2082</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l02083"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga89b6cfa1d6971fa27c3b094e35472328"> 2083</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SYS1ACN_POS)) </span></div><div class="line"><a name="l02085"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga3fa704a4ec82280641b41e6b729d4b1a"> 2085</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMADACN_POS                    5 </span></div><div class="line"><a name="l02086"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga75afa7f4a67c9579f26bd0362b930f51"> 2086</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SDMADACN_POS)) </span></div><div class="line"><a name="l02088"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga58b337d71807fa24029e1f48299e2a3e"> 2088</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l02089"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gabd0075bbe63b1479dd8b7a69f42922fd"> 2089</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SDMAIACN_POS)) </span></div><div class="line"><a name="l02091"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gae239aa16530c24b2ae5098310578e571"> 2091</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l02092"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga1327ebbda918052df18a24e8e4d4e545"> 2092</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02094"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga3c48b0db3b6a1fef2197d27527046270"> 2094</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDIOACN_POS                     8 </span></div><div class="line"><a name="l02095"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gad72208b646d8f7fc0ab242710e49f587"> 2095</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SDIOACN_POS)) </span></div><div class="line"><a name="l02105"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaaffbf0e4e966f68adc0682af47c6fd08"> 2105</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l02106"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga1f98a9f87ed66d5af5823d0b0bece68f"> 2106</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_DMA0ACN_POS)) </span></div><div class="line"><a name="l02108"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gac6efc94a581a14782449c82a28bac4a6"> 2108</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l02109"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga0da2b6b392c9ab0a2dbb6ae07577658e"> 2109</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_DMA1ACN_POS)) </span></div><div class="line"><a name="l02111"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga02ed3d2ec1fc9ba327ac0c95ff33b05e"> 2111</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_USBACN_POS                      2 </span></div><div class="line"><a name="l02112"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga823829fed82b88104599d41247fb1046"> 2112</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_USBACN_POS)) </span></div><div class="line"><a name="l02114"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaf28d0357fccf0f69ffda83f945ec1b4a"> 2114</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l02115"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga766f5d0e26e5a1a48ee20c67ba6cd238"> 2115</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SYS0ACN_POS)) </span></div><div class="line"><a name="l02117"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga9c21b4166f44d4ae4bfdc7e44190a6dd"> 2117</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l02118"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaef81a0b726c6deb72fb9834484462f6d"> 2118</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SYS1ACN_POS)) </span></div><div class="line"><a name="l02120"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaaac8c4fb50ea1c44b348180c2c4a2fd6"> 2120</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMADACN_POS                    5 </span></div><div class="line"><a name="l02121"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaf8809af5a801a452a3d162bb08557df3"> 2121</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SDMADACN_POS)) </span></div><div class="line"><a name="l02123"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga34535ec593fc175eb786d0f7479ef5b5"> 2123</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l02124"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gadfacd8e713e3516b6257c279cb033f3c"> 2124</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SDMAIACN_POS)) </span></div><div class="line"><a name="l02126"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga2a5051e61c8d2fb58aeac34d2f2279c2"> 2126</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l02127"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga2437f6bae874ea0407dba1b6138b3561"> 2127</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02129"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga92531949144558194dae649a7706ae9b"> 2129</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDIOACN_POS                     8 </span></div><div class="line"><a name="l02130"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga2892aaa8578641018524ebf1436643df"> 2130</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SDIOACN_POS)) </span></div><div class="line"><a name="l02140"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga66f26c810609b94ba95a0ea64af08197"> 2140</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02141"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga9ff21274af674228ebb7704a066024cc"> 2141</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02143"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga1388f71eac0bb93e3200a4118a6148b8"> 2143</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02144"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gac9259f9a36e566dc0d90d6c42b18151a"> 2144</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02146"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga9196372a613a9e144ee84656e13c153e"> 2146</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02147"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga946a114d7c88900abac14d474a6ee324"> 2147</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02149"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga37b877774cbfb438b9fb7e8b79e0e84f"> 2149</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02150"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga648e5b819bd9734a91471feca586ff39"> 2150</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02152"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga5b580f056625fec5f9b099dee788a059"> 2152</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNR_POS                    4 </span></div><div class="line"><a name="l02153"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga0d4b76280ad6ffe89a0183c10abed63f"> 2153</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_USBACNR_POS)) </span></div><div class="line"><a name="l02155"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga121bb6872b3b271af2b2b670909caece"> 2155</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNW_POS                    5 </span></div><div class="line"><a name="l02156"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaa6f8173695c50589b62f4d02fbeba485"> 2156</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_USBACNW_POS)) </span></div><div class="line"><a name="l02158"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga6ad4446805d3726c276432b74c2caabd"> 2158</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02159"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaf48195d123b0ef5d912768768bf335d5"> 2159</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02161"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaa9f86282f0feed3d99ba0d1c51884e14"> 2161</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02162"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gabb5f0ea4eadcf7237921a4cd8b541c37"> 2162</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02164"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaab09a7f84e5487dae0e44150b52faad0"> 2164</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02165"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga43104e07ac771e333ee8ecad69cb7658"> 2165</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02167"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga42d8e254401450bbf5d91b2b8b6a8477"> 2167</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02168"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaf3d2f6fb0e20892bb9a7092b9f26d3f7"> 2168</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02170"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga407c8e22b0ad8271a2cb0c21cfd90ed0"> 2170</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02171"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga04ccc5722bc872635e46bf10e8bfbb96"> 2171</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMADACNR_POS)) </span></div><div class="line"><a name="l02173"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga67ea0aea0d66682b4858eb092cdccdd1"> 2173</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02174"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gae1ac812caecd99c42a24873fcac556a8"> 2174</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMADACNW_POS)) </span></div><div class="line"><a name="l02176"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gabdf9f3d6efc5692a3d166a49637a8ebc"> 2176</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02177"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga777bca5a8f1965584d7337f97ae47b82"> 2177</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02179"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga1f4f4e4f760628f2e1c8ae0ba8d82acf"> 2179</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02180"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga3d4e27a89e5bbefc17836661f6a44c7f"> 2180</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02182"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga293972c9b34a24851abbfec26f0c137f"> 2182</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02183"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga0583982ec0ea9ed48ee8cb61709a4665"> 2183</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02185"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga600a278679e91e8fe5221b80ab25e958"> 2185</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02186"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gac02e30eecfefceda1932f1267e7f873c"> 2186</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02188"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga6b043fc5f011d1fd0b4baeb9765778d5"> 2188</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02189"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gacf682440db2559287571168ef88c6ea8"> 2189</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDIOACNR_POS)) </span></div><div class="line"><a name="l02191"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga079ba77fcba9935f864e8cd25d491f76"> 2191</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02192"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga4a736402394a3c68d0433cf30e4495d0"> 2192</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDIOACNW_POS)) </span></div><div class="line"><a name="l02202"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga94d8deb0bf8dc303e908b2e7b2a67314"> 2202</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNR_POS                    0 </span></div><div class="line"><a name="l02203"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga59d14bbcff780fb5465905fd3ad59313"> 2203</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02205"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga3f300995e258eb710874c8feb47aff6e"> 2205</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNW_POS                    1 </span></div><div class="line"><a name="l02206"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gabc9dd5ebf621efcbc776204eee9df79e"> 2206</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02208"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga10d9832e39fc7b555f65d7509ea1a57d"> 2208</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNR_POS                    2 </span></div><div class="line"><a name="l02209"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga3f0e14f512f52c7fe08e3a0d96dcd481"> 2209</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02211"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gae852b6ac0b0ff839de339ba0304a57c1"> 2211</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNW_POS                    3 </span></div><div class="line"><a name="l02212"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga8f0c799d3b7f22319a52ebe85b22e862"> 2212</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02214"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaa1f67d7fdbfd2d8d9fb471f463fab360"> 2214</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNR_POS                     4 </span></div><div class="line"><a name="l02215"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaffa9c53c103bfa70a773e21027cd23fa"> 2215</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_USBACNR_POS)) </span></div><div class="line"><a name="l02217"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga21b00204c774d080a23601e426af28b8"> 2217</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNW_POS                     5 </span></div><div class="line"><a name="l02218"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gacd1f501b99750f6255d199ecbdf159aa"> 2218</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNW                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_USBACNW_POS)) </span></div><div class="line"><a name="l02220"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga5d3637710dfb0a292c28fa73fad2c693"> 2220</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNR_POS                    6 </span></div><div class="line"><a name="l02221"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gae31ca158724e85ae243f3a035c2a1e66"> 2221</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02223"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gacc3093f985523b0eeef66bd6b29841f8"> 2223</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNW_POS                    7 </span></div><div class="line"><a name="l02224"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaceaa0b96755a7414e32065c0332febf1"> 2224</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02226"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga088dbabc114e3fee456b14d0096afe53"> 2226</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNR_POS                    8 </span></div><div class="line"><a name="l02227"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga0367ac1403d8a6bc81846b52fcb4ed88"> 2227</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02229"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gacc0e9ed3f51d1c2ae18bf41cbf36fe31"> 2229</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNW_POS                    9 </span></div><div class="line"><a name="l02230"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gad1de49c9909752dee127f0d5196ed3a9"> 2230</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02232"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga4456f3809dc151953b1e582825941a1a"> 2232</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNR_POS                   10 </span></div><div class="line"><a name="l02233"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gac7e03323b968833afd0ac74e19b0af70"> 2233</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMADACNR_POS)) </span></div><div class="line"><a name="l02235"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga73a5dd35ea498fbad5aaafae54d8f947"> 2235</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNW_POS                   11 </span></div><div class="line"><a name="l02236"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaa2cb8c868551234f1da3cdc1bf5693f9"> 2236</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMADACNW_POS)) </span></div><div class="line"><a name="l02238"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaaedb58ec264486ebd8ac9df8928602c6"> 2238</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNR_POS                   12 </span></div><div class="line"><a name="l02239"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gab939b362781f566802f3a3ec696220f7"> 2239</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02241"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga68c6b67ad5b3d9defb8aab187bee195f"> 2241</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNW_POS                   13 </span></div><div class="line"><a name="l02242"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga88c4178a46e9639ce9f995157f421372"> 2242</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02244"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga9c29c73c83704c6f56257b71f6655e9d"> 2244</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNR_POS                  14 </span></div><div class="line"><a name="l02245"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gab0c6adff08f51c10c9e32337fd7175bd"> 2245</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02247"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaeb221f5948b3f71296cfac2637514418"> 2247</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNW_POS                  15 </span></div><div class="line"><a name="l02248"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga4a09b3d09f094075695cd5493851f828"> 2248</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02250"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga9e1147d8a3330dacb2c063f57b1731a6"> 2250</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNR_POS                    16 </span></div><div class="line"><a name="l02251"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga0bd09f3a9afb32fddc0a2c1fd0d788af"> 2251</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDIOACNR_POS)) </span></div><div class="line"><a name="l02253"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gab422f60dbef7d0c9ee659a469fe28f6a"> 2253</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNW_POS                    17 </span></div><div class="line"><a name="l02254"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga3b02473b8065b4e455ff4d0dd2094ecc"> 2254</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDIOACNW_POS)) </span></div><div class="line"><a name="l02264"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga5f3f4079b37476344694ded4a5054676"> 2264</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNR_POS             0 </span></div><div class="line"><a name="l02265"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga7370f1a25b391b7337b71d0ce57ca1a9"> 2265</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02267"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga8b08ccce1d399ed4656edc375df2b4d5"> 2267</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNW_POS             1 </span></div><div class="line"><a name="l02268"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gaf35e17a986d3f7e1f3809858b63a20a3"> 2268</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02270"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga37dffdc835e7d8fe1a5ec975a76d9fdd"> 2270</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNR_POS             2 </span></div><div class="line"><a name="l02271"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gaf13d0b29a62848ba22789f1e204eac52"> 2271</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02273"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga5a66680d28157854440d1979dd1f368c"> 2273</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNW_POS             3 </span></div><div class="line"><a name="l02274"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga1f8f3de2e6ebf90c6b688bd28407959b"> 2274</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02276"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga8d74700670d64aad77e74eff5e900337"> 2276</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_USBACNR_POS              4 </span></div><div class="line"><a name="l02277"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gab7d63b6bcf71dbe0822cfef892e76fd9"> 2277</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_USBACNR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_USBACNR_POS)) </span></div><div class="line"><a name="l02279"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga90050840056412a7eda6e40c63c3897b"> 2279</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_USBACNW_POS              5 </span></div><div class="line"><a name="l02280"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gae9eb62d5b55192f0cc5952d59f85a537"> 2280</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_USBACNW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_USBACNW_POS)) </span></div><div class="line"><a name="l02282"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga2356eb407f7c8cbf0b53e6165890eb65"> 2282</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNR_POS             6 </span></div><div class="line"><a name="l02283"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga8e26c7f7c4212b004d4be8429ea7f8aa"> 2283</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02285"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga589aa85880674f90bf641c000e0ab84c"> 2285</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNW_POS             7 </span></div><div class="line"><a name="l02286"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga5d57fccc91ed6542695367ee01a4d1a4"> 2286</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02288"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga96dd82d6365c81c01d11af543ee4da01"> 2288</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNR_POS             8 </span></div><div class="line"><a name="l02289"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga4d066c9f83c2dac6e934d3030d177c33"> 2289</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02291"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga5a40386282e172d1f2c46b61f47be033"> 2291</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNW_POS             9 </span></div><div class="line"><a name="l02292"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga5f409c9a58abbab4d4e18ab135d86600"> 2292</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02294"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga475b9682ed4fc8b3967bda5e4aa488cb"> 2294</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNR_POS            10 </span></div><div class="line"><a name="l02295"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gab7bc7737a38d9543ba2e1007d65f753f"> 2295</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SDMADACNR_POS)) </span></div><div class="line"><a name="l02297"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga3b21b001effb0af98220a4cdd872f68e"> 2297</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNW_POS            11 </span></div><div class="line"><a name="l02298"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gad6e8dba0294cd0b14f0cca24b8cc370f"> 2298</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNW                ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SDMADACNW_POS)) </span></div><div class="line"><a name="l02300"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gac1b05cf2e7a36eea25c41d764d2751c0"> 2300</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNR_POS            12 </span></div><div class="line"><a name="l02301"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga2a570cf819930643bdf348f534776d09"> 2301</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02303"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga0987b2fe495601593f6680ea69f725d1"> 2303</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNW_POS            13 </span></div><div class="line"><a name="l02304"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga00f7da1f59dcfdc31933f875fc0334b1"> 2304</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNW                ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02306"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga24937f80cb0acc8418db6ad6a26a8725"> 2306</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNR_POS           14 </span></div><div class="line"><a name="l02307"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gadfcc8ba576cc4ebca0a6af3dbadd5c56"> 2307</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02309"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga55345d94fa249ba854b4dedce4268773"> 2309</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNW_POS           15 </span></div><div class="line"><a name="l02310"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gabdf9861c19971f96eee8be03a86a3942"> 2310</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNW               ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02312"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga63d412ebb5335516e12ffa62b6003c88"> 2312</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNR_POS             16 </span></div><div class="line"><a name="l02313"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga5f4967182f77485b3b2cb6dbed109292"> 2313</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SDIOACNR_POS)) </span></div><div class="line"><a name="l02315"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#ga26f1290d687d0c6e89606e0712f9433d"> 2315</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNW_POS             17 </span></div><div class="line"><a name="l02316"></a><span class="lineno"><a class="line" href="group__RPU__SPIXIPMFIFO.html#gaf36bcfff4c96e3d3a190941e960c42d5"> 2316</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXIPMFIFO_SDIOACNW_POS)) </span></div><div class="line"><a name="l02326"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga6ab4672a8403b00e37f13d3ed1c14591"> 2326</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02327"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga6b24d1f709b871a848573edc35559907"> 2327</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02329"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gafa2ab4e8142111e8f99b8592dc11fad2"> 2329</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02330"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gad2a5a467131861af62178c0f5a01bace"> 2330</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02332"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gac2c8aed19fbbb0f827b4ab731ef2f13f"> 2332</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02333"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga4a9d9b07e4dc5a52f25dea730c486734"> 2333</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02335"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga6e31b0077af9976abc1fcdd53fcc9a4d"> 2335</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02336"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga12f4d423d05257da24a6ac6af529f77c"> 2336</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02338"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gab8db7316ff62eefe94b73bad3e05e16e"> 2338</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_USBACNR_POS                    4 </span></div><div class="line"><a name="l02339"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga88425e260324c897d27e322cd2c936ac"> 2339</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_USBACNR_POS)) </span></div><div class="line"><a name="l02341"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga4e2b5fcefd623bece02e1968d3de4242"> 2341</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_USBACNW_POS                    5 </span></div><div class="line"><a name="l02342"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gad3b4b71ac38f101f8d8e28a885a67b50"> 2342</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_USBACNW_POS)) </span></div><div class="line"><a name="l02344"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga13763f4dd778b64a30f201c1a4ee8ea2"> 2344</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02345"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gabb02da7df5b2b5dbd9b71695aae5f8c8"> 2345</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02347"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga8d00a3307a4d30d854584d21451084ed"> 2347</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02348"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga24507e449fe63debd4179a0d994642a2"> 2348</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02350"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga902b566ee3d7ccf3769f5e7f9c4dbdaf"> 2350</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02351"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gac22d0a106c4df5700248af6cd37bf905"> 2351</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02353"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gab85a76c26cb80a7dab648fd99a0cfed0"> 2353</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02354"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga853d82c101ee916a7a5c7120e12b2fd1"> 2354</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02356"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga89c028f65db691a3742b240f3785d615"> 2356</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02357"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga86a80158f6a38548377cec3f5c5f065a"> 2357</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SDMADACNR_POS)) </span></div><div class="line"><a name="l02359"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga5aa373559662eddeb7a9cadc4e71f29f"> 2359</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02360"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga2f44ec815c09a00b60fdb0bacadf26ec"> 2360</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SDMADACNW_POS)) </span></div><div class="line"><a name="l02362"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga3aae06afea17b6bc3cd9fad0f61c51b2"> 2362</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02363"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gad2c8e219589a4a5491f0c0a3362ab7c7"> 2363</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02365"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga20a5da6ca294de3effd13a599846f023"> 2365</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02366"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga98473635448a7e51fce0c31e550824a9"> 2366</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02368"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gabffd331e6cc0f9f55d4eab2fdaf738f6"> 2368</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02369"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga0653e4470025c008e0f87da856c70c14"> 2369</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02371"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gaec9d4ab5d8a8d11c06a5b54d5d03e323"> 2371</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02372"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gafb7c5d9d6c96afb096c1463542dc0176"> 2372</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02374"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga632db0be0be390bcc9bfeb352fcdab4c"> 2374</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02375"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gaa0d17ffa99b3033b314724e6fc90d13e"> 2375</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SDIOACNR_POS)) </span></div><div class="line"><a name="l02377"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#gae493307663d2e000b92ecdc4b3612057"> 2377</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02378"></a><span class="lineno"><a class="line" href="group__RPU__QSPI0.html#ga54734eba4ad6bd03da3f7642da40bff0"> 2378</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_QSPI0_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_QSPI0_SDIOACNW_POS)) </span></div><div class="line"><a name="l02388"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gada6dddeba4bf9db86b81d93f095acb77"> 2388</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02389"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga4ce5f7c9f1b6848f96fd6b8758d6c837"> 2389</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02391"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga260a38958a0f8ba82979949f03574afa"> 2391</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02392"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga273117211920213b84f8830944bae101"> 2392</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02394"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga8c633621af1b971a7c0c21bc0910ff7e"> 2394</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02395"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga4bb5fbcafa9b1270d60202ef6dcad485"> 2395</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02397"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga1242d05fb38b9d9bb288efd94c45c3d0"> 2397</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02398"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga02041806a4cba27ce94b6dafeb54844f"> 2398</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02400"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga10598ce2ee4ec99be771c26c8452a05f"> 2400</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_USBACNR_POS                    4 </span></div><div class="line"><a name="l02401"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga831f7f59fd014e02d1cb1af297da2c22"> 2401</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_USBACNR_POS)) </span></div><div class="line"><a name="l02403"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gac68eff5bdf0d111ffd464c90e51247a7"> 2403</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_USBACNW_POS                    5 </span></div><div class="line"><a name="l02404"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaf9d71f18ea5768d2bc82a59daacba03c"> 2404</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_USBACNW_POS)) </span></div><div class="line"><a name="l02406"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaceb29cf42df26f8eb4e1cde63c42e5ad"> 2406</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02407"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gae29da3f3bcdd9a2e3558b35a0f748eba"> 2407</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02409"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaae21f969cb9a2026ae38488b7ecac2fa"> 2409</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02410"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga810384b38779b4387250e3ec6bbb445d"> 2410</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02412"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaab376a96d446340d45cfc93c34294726"> 2412</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02413"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaa301c8897c790bad708fa8a4fd4a7009"> 2413</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02415"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga98504ba0a816d005ee93327d29b17902"> 2415</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02416"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaa5123ef60bf9f8fdb4ae1505b5ef4d40"> 2416</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02418"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga2906abfb38cc8794b1d6f08c34c64368"> 2418</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02419"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga7ea4640c0171fd39533a4331435e78ad"> 2419</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SDMADACNR_POS)) </span></div><div class="line"><a name="l02421"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga034a7d9d9026699ccc2c930a7e286bc1"> 2421</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02422"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga5e39a9bbc77709bbe27725670f987bcc"> 2422</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SDMADACNW_POS)) </span></div><div class="line"><a name="l02424"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gabb7171721e6476226c1dd9079714b782"> 2424</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02425"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gac9606a2be5a035cade5095413f48fb02"> 2425</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02427"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gad2bcf3ac1ea2a1470d246cf5f4da1f82"> 2427</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02428"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga2924955864a40420c5dc9c5ed3a0d05c"> 2428</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02430"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga29fd64ce638401ab7d3601c1ea202618"> 2430</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02431"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga499056aaebe0e13d53a3d2df716286b7"> 2431</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02433"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga8825104673f0764552b7128fafdf1fab"> 2433</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02434"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#ga71c6f431b6cc27a5298e9e199ee5fc72"> 2434</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02436"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaf6622fe1099ace1cc2d9df41528c99c7"> 2436</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02437"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaa243e4ceda285a2145cc48921c8b9223"> 2437</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SDIOACNR_POS)) </span></div><div class="line"><a name="l02439"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gab011f03d0cfc613a4313babdcfdf4a90"> 2439</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02440"></a><span class="lineno"><a class="line" href="group__RPU__SRAM0.html#gaf43394d52a54fa7c5fce39bcaac11003"> 2440</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM0_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM0_SDIOACNW_POS)) </span></div><div class="line"><a name="l02450"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gadf81e20742de9235b39067e2e3a1c8b4"> 2450</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02451"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga7b150335f124858ed732fd38655e774b"> 2451</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02453"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga404fb1630796efbe3a13b9ab2788cd8a"> 2453</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02454"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga4d37a6eafb598c04d462a88e41376b68"> 2454</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02456"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gaa9b796df01995d61bf4730974dec4ebc"> 2456</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02457"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga5500958d33d70a33073c31bf1fca1997"> 2457</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02459"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga832a54b38bb9756be15bef9aebf6ea94"> 2459</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02460"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga9e7297aafc9f5bae38a3b0cc865e04aa"> 2460</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02462"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gab710611c6de7d7f36cedea27c755cf55"> 2462</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_USBACNR_POS                    4 </span></div><div class="line"><a name="l02463"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga8cef99e444f985ce6da17ea54f86679f"> 2463</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_USBACNR_POS)) </span></div><div class="line"><a name="l02465"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gae89480bf94c1752660d1a99bfe46f1ae"> 2465</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_USBACNW_POS                    5 </span></div><div class="line"><a name="l02466"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga1921f5e60c3fb6e2037ab56c77ba9555"> 2466</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_USBACNW_POS)) </span></div><div class="line"><a name="l02468"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga00063ac30eb855e4e81cbe02cf246252"> 2468</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02469"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gaa22a890d128a8f15a261b4a5c8b5d535"> 2469</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02471"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga4c9ed0b4258390a4837716894ea73769"> 2471</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02472"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga02046edb8a2bcf9e5fc0bf1c70ec94fb"> 2472</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02474"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gad9ae40206252d9a5703a01c9486fe385"> 2474</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02475"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gacf06af0a33195691695548c8a52ed539"> 2475</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02477"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga7fbebe8f078cfb6cc790789a27097f8c"> 2477</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02478"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gab75cae7aef9df14a257c3b9be2c09bdf"> 2478</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02480"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga3e002cbce0b08775a4e8c99129892b20"> 2480</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02481"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga0b735b96eab87dd60fa900e73010f957"> 2481</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SDMADACNR_POS)) </span></div><div class="line"><a name="l02483"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gacfbc7314abba6e91b3aec2ece48052dd"> 2483</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02484"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gaf7a13156427445181606187639520fca"> 2484</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SDMADACNW_POS)) </span></div><div class="line"><a name="l02486"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gad77c04d6e67114b1eaee48d28ac24a21"> 2486</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02487"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga899872a598d3bff3aaa42d8b9c200a45"> 2487</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02489"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga59e57c87242050c22d6b0f79f3422037"> 2489</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02490"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga48095f9491cca441de9f52dd457b34ac"> 2490</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02492"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga09080b174116b451b7ecf0a74894b516"> 2492</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02493"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga822c9711a1fb4cc3fd565b845ba154ba"> 2493</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02495"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga0304adbfe577aba1e27c40b6c1a8422c"> 2495</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02496"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gaf22aebb7a56a82fce0aca69ebdb5927d"> 2496</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02498"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gab0c15bc27aa4827285700075cc20e7ce"> 2498</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02499"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#gabd7047a832585fd5870dee832746c055"> 2499</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SDIOACNR_POS)) </span></div><div class="line"><a name="l02501"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga32d5d9ebc95ecaff57208f9520b36ca5"> 2501</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02502"></a><span class="lineno"><a class="line" href="group__RPU__SRAM1.html#ga117520396585a250e1963f75dc2c1719"> 2502</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM1_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM1_SDIOACNW_POS)) </span></div><div class="line"><a name="l02512"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gabd69fcf38f6b63818b41b2fc7659c68f"> 2512</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02513"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga93cb6294dd1b41e54413a8ac59063db9"> 2513</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02515"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaadc7bc6800abea11477b198207c049eb"> 2515</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02516"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga07817517ccf731d152b266bccbedeabc"> 2516</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02518"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga09f6ada95f335e72b590a7191ffc8005"> 2518</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02519"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga7911cbf3e7c31071f2cedf1c12db188d"> 2519</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02521"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaf3fb81911c4d9ef3cce57f3009bfe780"> 2521</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02522"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga840ac9d70816b2a631d432b1f037fb0b"> 2522</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02524"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga7016271a8083fec905b7108664f0f132"> 2524</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_USBACNR_POS                    4 </span></div><div class="line"><a name="l02525"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga96219151b5daeef8f041b7d0c17e4b7b"> 2525</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_USBACNR_POS)) </span></div><div class="line"><a name="l02527"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga1199f9632ebde800d65b6e07135351fe"> 2527</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_USBACNW_POS                    5 </span></div><div class="line"><a name="l02528"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaa49261f93c3a8a6d4c760b136f8c9b71"> 2528</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_USBACNW_POS)) </span></div><div class="line"><a name="l02530"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga1a9322896112929e509128b9d78a372f"> 2530</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02531"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gab8ebaf6c5bf72dc083c4aea770131b1d"> 2531</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02533"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gab2efcbf165203a6e7b07d5e91a7ee0bf"> 2533</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02534"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga938d71225251c62e07d9c5c03036982f"> 2534</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02536"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga285be547952f3856f940ad7a0c616f9c"> 2536</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02537"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gadfddceeeaf244d09b1cf151ad6211dd8"> 2537</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02539"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga7667fabf2ad070e645c4ae8c7c80f9e1"> 2539</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02540"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga1e6a1b6af6f63b5475dd356d45d5a4c3"> 2540</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02542"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga721dc87c798d5a1797d1aca3c7116791"> 2542</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02543"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaf8f40e781059fb644952fd6356413e78"> 2543</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SDMADACNR_POS)) </span></div><div class="line"><a name="l02545"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga10c2464527870e5b133f1c81af20dd2f"> 2545</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02546"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga60e4d4a9a6d20fab039ba198ec0c431e"> 2546</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SDMADACNW_POS)) </span></div><div class="line"><a name="l02548"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaec34ceb89a10917c25b525019726f83c"> 2548</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02549"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga995dd755c9bede76412b0592e5cf1b6a"> 2549</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02551"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga7024e137893698c2e84ea53b7e7331e5"> 2551</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02552"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga06eda8fd7f678c7e0b6d258713eedce1"> 2552</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02554"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga48ae5999fe5eb858a7077e7218155a86"> 2554</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02555"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga7419efff37b238838dec81b72f34079d"> 2555</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02557"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaba16059cb64f61d9f59dce5715632ac0"> 2557</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02558"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga3cbfec4bb2d3ee47bf8332ef2d37644c"> 2558</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02560"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga0bd8dd695732a57b1a1318991d3cac25"> 2560</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02561"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gaf693feb40b9408a9bb476fabd33f44d6"> 2561</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SDIOACNR_POS)) </span></div><div class="line"><a name="l02563"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#ga2c3f297a1861e5f18635945b9bab4765"> 2563</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02564"></a><span class="lineno"><a class="line" href="group__RPU__SRAM2.html#gac3b2ae46c1269037fea73a0dd86d615a"> 2564</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM2_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM2_SDIOACNW_POS)) </span></div><div class="line"><a name="l02574"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga2b31996214ab00f7f1c6b9e989561b1b"> 2574</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02575"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga1fb1b5fceec07e87cfe19e36e7950b0e"> 2575</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02577"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gacb7636b7baebcb55d6401faade7952f1"> 2577</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02578"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga953f572d0304586510453d4014f517d2"> 2578</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02580"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga4577b0253f7b38e749523ffbab5eccfa"> 2580</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02581"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga10bca2a52a5fea4ff60ed14f18412771"> 2581</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02583"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga5dbfb2b24004dad61af37b2b7993cc15"> 2583</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02584"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga17cb993a9f69033be3827a74b336460b"> 2584</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02586"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaedc9bce3f20af26f79df90a969f67efb"> 2586</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_USBACNR_POS                    4 </span></div><div class="line"><a name="l02587"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga8270bbd637a796d36e129553833f049d"> 2587</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_USBACNR_POS)) </span></div><div class="line"><a name="l02589"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga9229a5382b60ab27f4edfb72192fda41"> 2589</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_USBACNW_POS                    5 </span></div><div class="line"><a name="l02590"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaf3e8014c0b1711f97d3b53f84b98bcaa"> 2590</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_USBACNW_POS)) </span></div><div class="line"><a name="l02592"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga889b0b4577f88e7a9d2f81e9ec87df21"> 2592</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02593"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gac1ff633c9b413a8327cee4ae633c77b7"> 2593</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02595"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga478402b67def4987a37b18f48e91d762"> 2595</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02596"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga9b3d858e20c3ca119204131231796d14"> 2596</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02598"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaffdf115cbb6e19f5e5c37561df1a2f14"> 2598</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02599"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga12d657598562da783fac81e00b6c6d5d"> 2599</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02601"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaf056a3fa52935330a3743805d86f32db"> 2601</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02602"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga8a3f71e55e5469550360769a10e4ac96"> 2602</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02604"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gae7fcbb58612e5a9c5e35d3e3de69508d"> 2604</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02605"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga4a8c28f417874edef1a4815f8e1357db"> 2605</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SDMADACNR_POS)) </span></div><div class="line"><a name="l02607"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga58324785c0750e9bff58f1e27fce2c1c"> 2607</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02608"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga87050413f1bed13bcbb4fd8c935631dd"> 2608</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SDMADACNW_POS)) </span></div><div class="line"><a name="l02610"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga209fd29358fc3a22a0c87f7f98839175"> 2610</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02611"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaacb653f62c6156fe3ca7235527e4a3f0"> 2611</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02613"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaf7f7b9d3673632c2cbfe20c6a1bb3626"> 2613</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02614"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gacc788517df5739516c339df8b4259d01"> 2614</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02616"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga5e40eceb19cce4b2cc7ce754747e4126"> 2616</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02617"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga9c8ffa8077d3baca9e9af875d6c5c24f"> 2617</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02619"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaccb4faee6739c681224b6c684c5825df"> 2619</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02620"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga80a1af42a9876c9f672e0087dfb03ad3"> 2620</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02622"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga7707454fc9479c5cc59089145a078d4e"> 2622</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02623"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gaebdc82ca4413e2a0a3b175c537f6b3c8"> 2623</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SDIOACNR_POS)) </span></div><div class="line"><a name="l02625"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#ga5215742af16028bfba54a8751abdd03b"> 2625</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02626"></a><span class="lineno"><a class="line" href="group__RPU__SRAM3.html#gacf5ec187adc88e4c802e82516687b200"> 2626</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM3_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM3_SDIOACNW_POS)) </span></div><div class="line"><a name="l02636"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga57102ecb5e48eff78129093f3c4f9841"> 2636</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02637"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga4e2684bddad9a86549a2172038f967cf"> 2637</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02639"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gad072d335211ddf42fa5c67b000cd3b38"> 2639</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02640"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gafd0c8668843ed53a7517adec2c5d7ed3"> 2640</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02642"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gaf7c51d09d692beccad00afe8e0523cad"> 2642</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02643"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga162e078460b4285e057e30ff7fc21a41"> 2643</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02645"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga9e7ab8742c94d3d7a7ee330778df9ff0"> 2645</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02646"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga5bf119031734a819dbea8d8f87a9f867"> 2646</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02648"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga3cd6fd55571f1628a7ff0f55f1697a93"> 2648</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_USBACNR_POS                    4 </span></div><div class="line"><a name="l02649"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gad72bcdb03854e65395e8f226407a0a28"> 2649</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_USBACNR_POS)) </span></div><div class="line"><a name="l02651"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga992590a4e1d5084cf01721fec7c6f754"> 2651</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_USBACNW_POS                    5 </span></div><div class="line"><a name="l02652"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gaf66938f21658782e804b51b079c2c8e4"> 2652</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_USBACNW_POS)) </span></div><div class="line"><a name="l02654"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gac580b477546f465a6e683651c1612f7b"> 2654</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02655"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga5afac43dd6d47e5532a2b238e71e698d"> 2655</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02657"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga867c4b587ee6ebca460ba0cb4573cbbb"> 2657</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02658"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga6b3f187d30bf20ed49cbbbf213a12635"> 2658</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02660"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga0cbcfcd9434d26fe96e8a7a897c61824"> 2660</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02661"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga6b1f1a61cee253762824e43548b30fb2"> 2661</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02663"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gaa4242512a90ad8de5054243e3803d3f7"> 2663</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02664"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga889aefc2c0ebfeb77ba1389a66694e1b"> 2664</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02666"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gafe4c9aa1fea595a06b1876d6a5807b58"> 2666</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02667"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga23796749a899a5c31f6c30a6e0f7cdab"> 2667</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SDMADACNR_POS)) </span></div><div class="line"><a name="l02669"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gaff0c265769e7b95cebe6572e5b7bc824"> 2669</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02670"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga2252adde1dbd5bc181d138aa10aea785"> 2670</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SDMADACNW_POS)) </span></div><div class="line"><a name="l02672"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga5a4c924437e4e8c05a95a4465ef8a8ea"> 2672</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02673"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga26d0c39634cc33dc5cfd590357bc3a59"> 2673</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02675"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga8206869c6782354146c60089ff99a8ec"> 2675</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02676"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga247bb27e01e212fa142c925a77331127"> 2676</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02678"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gad61c4d0553dd19c7dc11149fbe9f9591"> 2678</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02679"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga580d245b0c8409cb00b41032b2510c19"> 2679</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02681"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga098171b3be6b996ddf9195552f6088c0"> 2681</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02682"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga4769bf1be92cc34e3f586b71c8ecaebf"> 2682</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02684"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#gad75d46d54369aec2b21a827f80ce94ce"> 2684</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02685"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga8752d7b7f7bff9fa241f7ab55b23bb7a"> 2685</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SDIOACNR_POS)) </span></div><div class="line"><a name="l02687"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga6a8a2e5fa3082817247e5a58f73feab8"> 2687</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02688"></a><span class="lineno"><a class="line" href="group__RPU__SRAM4.html#ga8c6abe5e822b26819d96ca3461b17e4c"> 2688</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM4_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM4_SDIOACNW_POS)) </span></div><div class="line"><a name="l02698"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga20446b13a2fad3490e634f3c52e67a52"> 2698</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02699"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaa37519d589638696237ab14d4e240c6f"> 2699</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02701"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaa6cc51ac34666ea4c1bb2739a6858570"> 2701</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02702"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga710a2d344dcb9963dbd59e699f44f5e1"> 2702</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02704"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga19274328b5b59cfd54cfe63f390793f5"> 2704</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02705"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga29ab5a59d428c62a874e7f544cef8d91"> 2705</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02707"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga69b7dd2bb42251a817ee446badf082e3"> 2707</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02708"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga1090ee625d08d0d584ef1d39b900b719"> 2708</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02710"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga59fc03b85712166155a3ec902573cc5e"> 2710</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_USBACNR_POS                    4 </span></div><div class="line"><a name="l02711"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga9544bbd4b9ca22c1be305fad496373af"> 2711</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_USBACNR_POS)) </span></div><div class="line"><a name="l02713"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga621bffab259edf59dfb0157b5eaac17b"> 2713</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_USBACNW_POS                    5 </span></div><div class="line"><a name="l02714"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga3efcaf90dc8be3e1dd5e6b423bf855bd"> 2714</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_USBACNW_POS)) </span></div><div class="line"><a name="l02716"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaa9b3153048fa1f8381a05e268ead1056"> 2716</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02717"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga772f1392db8e08a1618108ade5e0cba9"> 2717</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02719"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga5fedf34db7386ce3fe86b4901fefc48d"> 2719</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02720"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaca9d4c6571db249897743e56ff252a3e"> 2720</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02722"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gad5c01e9686faa3caeb77e42846087a67"> 2722</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02723"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga0eb3d0e4e4a7e5ff2fdd1321fd8f358f"> 2723</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02725"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gabb4abffa6c9ced5b03102614f981f213"> 2725</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02726"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gac47a4f71109927dca257f9c7936edb4e"> 2726</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02728"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga94f438194471e0a2cd557e14ade0b9bb"> 2728</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02729"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga38e1bff96a0f770c82fb7d14cafc2e24"> 2729</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SDMADACNR_POS)) </span></div><div class="line"><a name="l02731"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga01bd2807c442f487ca9a62e7f54056b5"> 2731</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02732"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gad07972bac217d97c026818302b2b3379"> 2732</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SDMADACNW_POS)) </span></div><div class="line"><a name="l02734"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga8f4e3ec42b5c76f80651a440a607e566"> 2734</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02735"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gab99edc2a88a621f73a83f16782de6700"> 2735</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02737"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga112b54f1ffd46dc4e84c3f5d261f3b87"> 2737</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02738"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gab5646d6e1765c54b75de58e5542a9f7d"> 2738</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02740"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga0c55afc028d457646e350152131f320a"> 2740</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02741"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaa7b7b8a4c8332bff39b25aa89a0a6317"> 2741</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02743"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gafddda01f9aedb4b8a42225ae13ba795a"> 2743</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02744"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaa06c26f926b319110cfaa1fac694b6ff"> 2744</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02746"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#gaa67c0fb9343ace1a3526e064e1aa4a48"> 2746</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02747"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga239f8f05b3e17864fbdf70bae26d67ee"> 2747</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SDIOACNR_POS)) </span></div><div class="line"><a name="l02749"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga84ecd51bcf33a841e0ea3fa629efc7ab"> 2749</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02750"></a><span class="lineno"><a class="line" href="group__RPU__SRAM5.html#ga45ac40f72f148afc0f7e77fe4d60b031"> 2750</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM5_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM5_SDIOACNW_POS)) </span></div><div class="line"><a name="l02760"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gafc35d5bf2035d85daca972b30a31d0f9"> 2760</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02761"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gafb484b0de185afdf9fa083274836da66"> 2761</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02763"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga31dae9081bcf90f2d485d42b8133392d"> 2763</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02764"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga8ffccff262398578f8550f65720ad356"> 2764</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02766"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gafe87091cdebed90f1857996340ecb7bd"> 2766</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02767"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga8255512ad253032e1b71d5dae2ef5ddb"> 2767</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02769"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gada5035f5e9b3dd1a7a3887532eab5ad7"> 2769</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02770"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga73b91fcae0cc31df49a8fe0ec6a7c6cf"> 2770</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02772"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga71a2fc34f1b30d90eab82a8fecd80310"> 2772</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_USBACNR_POS                    4 </span></div><div class="line"><a name="l02773"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga43496f0d1ba9ff411980bf71768809e7"> 2773</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_USBACNR_POS)) </span></div><div class="line"><a name="l02775"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gab632ccd51bdd3dbf6065a4470f55e55b"> 2775</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_USBACNW_POS                    5 </span></div><div class="line"><a name="l02776"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gace3e4624b200a462f24dbd646f3a2681"> 2776</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_USBACNW_POS)) </span></div><div class="line"><a name="l02778"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga02c577d1014e3d344941db91bf8bc180"> 2778</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02779"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga632e9c5b77fffada49480643d04e653d"> 2779</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02781"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga0bdc6c9a8095b15647aa3e096b47ed9f"> 2781</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02782"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga393fe7cc5e6ed26504a81bd994cdf0ef"> 2782</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02784"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga7c8ae6cdd655f82454f059f6ea5e69d7"> 2784</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02785"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gad42795a7d8d6cbf8be66da2941ef9281"> 2785</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02787"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga0fdc4bd52260831f645fd5d89b683ccf"> 2787</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02788"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga7b3c6fac8729a54821620f9f667fb5b8"> 2788</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02790"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga3598508c6c7dba2755afe63d31514cc0"> 2790</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02791"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga0eaa00ce3974f5c637e46d4eaa50bc6f"> 2791</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SDMADACNR_POS)) </span></div><div class="line"><a name="l02793"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga51baa0c4ad57a71f71fb3d7ebc95104a"> 2793</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02794"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga24903780928b611031e07c85997c964b"> 2794</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SDMADACNW_POS)) </span></div><div class="line"><a name="l02796"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga84f15ca8a2cbff4a475ecd7d8dea1183"> 2796</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02797"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga49f0542872f3afc6ec3f33246e26428a"> 2797</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02799"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga40b17abcbecc63144c0aeed7666e3916"> 2799</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02800"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gad5f6959f72e1e925f7f23ef5362f1720"> 2800</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02802"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga0f3ebd01b4df3e9e87b051c30489c1c7"> 2802</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02803"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga121841a56990d5379f27c4add1c4156f"> 2803</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02805"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga87934ee0f9afdf084fdb177a40ade18d"> 2805</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02806"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#gafaf425b2cbb9d634c2eaffd8e90fb0e0"> 2806</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02808"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga460ec25b722bc88343f03bcaba9c0cf6"> 2808</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02809"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga2e493938dca05bed4d666e4abdb3848a"> 2809</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SDIOACNR_POS)) </span></div><div class="line"><a name="l02811"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga590add6f136066d407878cee343b2d4b"> 2811</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02812"></a><span class="lineno"><a class="line" href="group__RPU__SRAM6.html#ga8a9a827878d3d4e9a3417eec1761dc22"> 2812</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRAM6_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRAM6_SDIOACNW_POS)) </span></div><div class="line"><a name="l02816"></a><span class="lineno"> 2816</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l02817"></a><span class="lineno"> 2817</span>&#160;}</div><div class="line"><a name="l02818"></a><span class="lineno"> 2818</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l02819"></a><span class="lineno"> 2819</span>&#160;</div><div class="line"><a name="l02820"></a><span class="lineno"> 2820</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RPU_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__rpu__regs__t_html_a66156e610712dd5d497ea9cc69c82b7d"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a66156e610712dd5d497ea9cc69c82b7d">mxc_rpu_regs_t::sram6</a></div><div class="ttdeci">__IO uint32_t sram6</div><div class="ttdoc">0x0F60: RPU SRAM6 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:203</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _RPU_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _RPU_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac64bf03f5a31181627b9d7bff229bbae">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac64bf03f5a31181627b9d7bff229bbae">gcr</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a5ae8ed804192af60d6d2ed665bc89de7">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a5ae8ed804192af60d6d2ed665bc89de7">sir</a>;                  </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a35801207272121e21d0a2a76430f1401">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a35801207272121e21d0a2a76430f1401">fcr</a>;                  </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a88a5580a133bfd53a7761f992ec2881b">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a88a5580a133bfd53a7761f992ec2881b">crypto</a>;               </div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;    __R  uint32_t rsv_0x10_0x2f[8];</div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a7409b12c61b29a4fe257590a07c01ce4">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a7409b12c61b29a4fe257590a07c01ce4">wdt0</a>;                 </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a31e99638858f7d9a5d3e0c13467e50e9">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a31e99638858f7d9a5d3e0c13467e50e9">wdt1</a>;                 </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae0c2fff3d78c4cc13ea8ff6be0058747">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae0c2fff3d78c4cc13ea8ff6be0058747">wdt2</a>;                 </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;    __R  uint32_t rsv_0x3c;</div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a83957039806dc91bd297c2e10e0cd031">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a83957039806dc91bd297c2e10e0cd031">smon</a>;                 </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a792a786a036390359f26f9be9c193850">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a792a786a036390359f26f9be9c193850">simo</a>;                 </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a087785341ce79484506cfd7287728e3d">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a087785341ce79484506cfd7287728e3d">dvs</a>;                  </div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;    __R  uint32_t rsv_0x4c_0x53[2];</div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a509d073c9df3c06db1dc8a5fe779f377">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a509d073c9df3c06db1dc8a5fe779f377">bbsir</a>;                </div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;    __R  uint32_t rsv_0x58_0x5f[2];</div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aab60df31ea3b2276598b3035cd9ba9c0">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aab60df31ea3b2276598b3035cd9ba9c0">rtc</a>;                  </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#af13a4525df9e31a7ac74da0fef71e39a">  105</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#af13a4525df9e31a7ac74da0fef71e39a">wut</a>;                  </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a50e2d7f83a0c9bf0f7e97ed0e3fd0057">  106</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a50e2d7f83a0c9bf0f7e97ed0e3fd0057">pwrseq</a>;               </div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a171cf0c62b66f6b04ee8ff99ee230ba1">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a171cf0c62b66f6b04ee8ff99ee230ba1">mcr</a>;                  </div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;    __R  uint32_t rsv_0x70_0x7f[4];</div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">  109</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">gpio0</a>;                </div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;    __R  uint32_t rsv_0x84_0x8f[3];</div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#abe05f3718e793dfe14939c75bf94eca2">  111</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#abe05f3718e793dfe14939c75bf94eca2">gpio1</a>;                </div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;    __R  uint32_t rsv_0x94_0xff[27];</div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a96b9adef08b7f6d1d545e28264275a4c">  113</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a96b9adef08b7f6d1d545e28264275a4c">tmr0</a>;                 </div><div class="line"><a name="l00114"></a><span class="lineno">  114</span>&#160;    __R  uint32_t rsv_0x104_0x10f[3];</div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a955e4f7e17b11917f743d0887530a356">  115</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a955e4f7e17b11917f743d0887530a356">tmr1</a>;                 </div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;    __R  uint32_t rsv_0x114_0x11f[3];</div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a39c567882dcac38cc5717fee6cbf2d29">  117</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a39c567882dcac38cc5717fee6cbf2d29">tmr2</a>;                 </div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;    __R  uint32_t rsv_0x124_0x12f[3];</div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a343226a105b94929065ea2caebe3313f">  119</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a343226a105b94929065ea2caebe3313f">tmr3</a>;                 </div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;    __R  uint32_t rsv_0x134_0x13f[3];</div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a895fe2a194714f0392686a608d450b67">  121</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a895fe2a194714f0392686a608d450b67">tmr4</a>;                 </div><div class="line"><a name="l00122"></a><span class="lineno">  122</span>&#160;    __R  uint32_t rsv_0x144_0x14f[3];</div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab7c28ad4ea0a12610580d549a9e0a3e3">  123</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab7c28ad4ea0a12610580d549a9e0a3e3">tmr5</a>;                 </div><div class="line"><a name="l00124"></a><span class="lineno">  124</span>&#160;    __R  uint32_t rsv_0x154_0x1af[23];</div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a7ab74a3f9f055d17c3b1b426d8f1de0e">  125</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a7ab74a3f9f055d17c3b1b426d8f1de0e">htimer0</a>;              </div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;    __R  uint32_t rsv_0x1b4_0x1bf[3];</div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a66a59e223df12aa7f8ddf8003bbbb4a7">  127</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a66a59e223df12aa7f8ddf8003bbbb4a7">htimer1</a>;              </div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;    __R  uint32_t rsv_0x1c4_0x1cf[3];</div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aee54ba2b716b8ec8eb511d6d7dee57a1">  129</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aee54ba2b716b8ec8eb511d6d7dee57a1">i2c0_bus0</a>;            </div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;    __R  uint32_t rsv_0x1d4_0x1df[3];</div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae1f643fe22f713dc8f1345ac2582a628">  131</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae1f643fe22f713dc8f1345ac2582a628">i2c1_bus0</a>;            </div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;    __R  uint32_t rsv_0x1e4_0x1ef[3];</div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a46f94aa32bf20f1306dd0b30bad69ec6">  133</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a46f94aa32bf20f1306dd0b30bad69ec6">i2c2_bus0</a>;            </div><div class="line"><a name="l00134"></a><span class="lineno">  134</span>&#160;    __R  uint32_t rsv_0x1f4_0x25f[27];</div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a0fa6182dc552923bce9dcbf52de361a3">  135</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a0fa6182dc552923bce9dcbf52de361a3">spixfm</a>;               </div><div class="line"><a name="l00136"></a><span class="lineno">  136</span>&#160;    __R  uint32_t rsv_0x264_0x26f[3];</div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a938e8c511fe710606bb950a76477b9a2">  137</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a938e8c511fe710606bb950a76477b9a2">spixfc</a>;               </div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;    __R  uint32_t rsv_0x274_0x27f[3];</div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#af88deb799899cd4dd4690d67ae7ca8ec">  139</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#af88deb799899cd4dd4690d67ae7ca8ec">dma0</a>;                 </div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;    __R  uint32_t rsv_0x284_0x28f[3];</div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a3922d90aa5c3a901375d2f07585ddb8c">  141</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a3922d90aa5c3a901375d2f07585ddb8c">flc0</a>;                 </div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a5c48ec12eab4ffc70cd1edce57d6718c">  142</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a5c48ec12eab4ffc70cd1edce57d6718c">flc1</a>;                 </div><div class="line"><a name="l00143"></a><span class="lineno">  143</span>&#160;    __R  uint32_t rsv_0x298_0x29f[2];</div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a4f719bdddec9869dc1226debe906860d">  144</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a4f719bdddec9869dc1226debe906860d">icc0</a>;                 </div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aafa4124620f7faaef5a033b4309be329">  145</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aafa4124620f7faaef5a033b4309be329">icc1</a>;                 </div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;    __R  uint32_t rsv_0x2a8_0x2ef[18];</div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a8080c2b6a8f3a34c04a83d4255e96b61">  147</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a8080c2b6a8f3a34c04a83d4255e96b61">sfcc</a>;                 </div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;    __R  uint32_t rsv_0x2f4_0x32f[15];</div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ace3ea78cbad80bfeca273e59f9f7b9c1">  149</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ace3ea78cbad80bfeca273e59f9f7b9c1">srcc</a>;                 </div><div class="line"><a name="l00150"></a><span class="lineno">  150</span>&#160;    __R  uint32_t rsv_0x334_0x33f[3];</div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a2fc656d8a513ec404aaff8da6f011fa8">  151</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a2fc656d8a513ec404aaff8da6f011fa8">adc</a>;                  </div><div class="line"><a name="l00152"></a><span class="lineno">  152</span>&#160;    __R  uint32_t rsv_0x344_0x34f[3];</div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae6ec9c9f9232226c77892d5226e94fd7">  153</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae6ec9c9f9232226c77892d5226e94fd7">dma1</a>;                 </div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;    __R  uint32_t rsv_0x354_0x35f[3];</div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac874de1a295a40dd380470c64ed28eb0">  155</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac874de1a295a40dd380470c64ed28eb0">sdma</a>;                 </div><div class="line"><a name="l00156"></a><span class="lineno">  156</span>&#160;    __R  uint32_t rsv_0x364_0x36f[3];</div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a4aa815e028be017d2571b6c69a6c85aa">  157</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a4aa815e028be017d2571b6c69a6c85aa">sdhcctrl</a>;             </div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;    __R  uint32_t rsv_0x374_0x39f[11];</div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a493a625cf6437fc4ea51aeb6433d377b">  159</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a493a625cf6437fc4ea51aeb6433d377b">spixr</a>;                </div><div class="line"><a name="l00160"></a><span class="lineno">  160</span>&#160;    __R  uint32_t rsv_0x3a4_0x3bf[7];</div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a7cf24cf377876560e35ce321484cf3a4">  161</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a7cf24cf377876560e35ce321484cf3a4">ptg_bus0</a>;             </div><div class="line"><a name="l00162"></a><span class="lineno">  162</span>&#160;    __R  uint32_t rsv_0x3c4_0x3cf[3];</div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a35753561e0eecc1e5d1a5b15a78ab524">  163</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a35753561e0eecc1e5d1a5b15a78ab524">owm</a>;                  </div><div class="line"><a name="l00164"></a><span class="lineno">  164</span>&#160;    __R  uint32_t rsv_0x3d4_0x3df[3];</div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a62bc3fca3b262224cf1b86be2d7608ff">  165</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a62bc3fca3b262224cf1b86be2d7608ff">sema</a>;                 </div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;    __R  uint32_t rsv_0x3e4_0x41f[15];</div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a2e1e85f1c673b9352d2afa16882f6b39">  167</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a2e1e85f1c673b9352d2afa16882f6b39">uart0</a>;                </div><div class="line"><a name="l00168"></a><span class="lineno">  168</span>&#160;    __R  uint32_t rsv_0x424_0x42f[3];</div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab8395b7a2e0c8f984ec19d5b003d1aca">  169</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab8395b7a2e0c8f984ec19d5b003d1aca">uart1</a>;                </div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;    __R  uint32_t rsv_0x434_0x43f[3];</div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ae0b16e375ee045fc432c2151f7ac2cc7">  171</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ae0b16e375ee045fc432c2151f7ac2cc7">uart2</a>;                </div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;    __R  uint32_t rsv_0x444_0x45f[7];</div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a6a8f3593c33e8e2a2c07ed8389670108">  173</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a6a8f3593c33e8e2a2c07ed8389670108">spi1</a>;                 </div><div class="line"><a name="l00174"></a><span class="lineno">  174</span>&#160;    __R  uint32_t rsv_0x464_0x47f[7];</div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aa617d084516acc758d283a33deed9a38">  175</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aa617d084516acc758d283a33deed9a38">spi2</a>;                 </div><div class="line"><a name="l00176"></a><span class="lineno">  176</span>&#160;    __R  uint32_t rsv_0x484_0x4bf[15];</div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ac6f45bdc77bf6cadfd61e0ae8e2fc3ec">  177</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ac6f45bdc77bf6cadfd61e0ae8e2fc3ec">audio</a>;                </div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;    __R  uint32_t rsv_0x4c4_0x4cf[3];</div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a9feb124206f57e0aaee54f8cc32e0422">  179</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a9feb124206f57e0aaee54f8cc32e0422">trng</a>;                 </div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;    __R  uint32_t rsv_0x4d4_0x4ff[11];</div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">  181</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">btle</a>;                 </div><div class="line"><a name="l00182"></a><span class="lineno">  182</span>&#160;    __R  uint32_t rsv_0x504_0xb0f[387];</div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aec838a3176ba946e9f886fbe6672df8a">  183</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aec838a3176ba946e9f886fbe6672df8a">usbhs</a>;                </div><div class="line"><a name="l00184"></a><span class="lineno">  184</span>&#160;    __R  uint32_t rsv_0xb14_0xb5f[19];</div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a43c49ff6f60b9f78f587cf97befee4da">  185</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a43c49ff6f60b9f78f587cf97befee4da">sdio</a>;                 </div><div class="line"><a name="l00186"></a><span class="lineno">  186</span>&#160;    __R  uint32_t rsv_0xb64_0xbbf[23];</div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#aa66553c7c4c2ff2a65e176af948e6399">  187</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#aa66553c7c4c2ff2a65e176af948e6399">spixm_fifo</a>;           </div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;    __R  uint32_t rsv_0xbc4_0xbdf[7];</div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#ab3363e181a7630bc3d3201eb3b879dfa">  189</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#ab3363e181a7630bc3d3201eb3b879dfa">spi0</a>;                 </div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;    __R  uint32_t rsv_0xbe4_0xeff[199];</div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a326ba0b5ed008b242db40e9ab75500bc">  191</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a326ba0b5ed008b242db40e9ab75500bc">sysram0</a>;              </div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;    __R  uint32_t rsv_0xf04_0xf0f[3];</div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#acf032f7d78b6532dd6ad36ba8443a121">  193</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#acf032f7d78b6532dd6ad36ba8443a121">sysram1</a>;              </div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;    __R  uint32_t rsv_0xf14_0xf1f[3];</div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a3d15538d060546e2f115288d3a9ab709">  195</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a3d15538d060546e2f115288d3a9ab709">sysram2</a>;              </div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;    __R  uint32_t rsv_0xf24_0xf2f[3];</div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a33efdc41a5dab826941aff9e4ee47d0d">  197</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a33efdc41a5dab826941aff9e4ee47d0d">sysram3</a>;              </div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;    __R  uint32_t rsv_0xf34_0xf3f[3];</div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a70722dd45c3732d6e3d827e46e722c39">  199</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a70722dd45c3732d6e3d827e46e722c39">sysram4</a>;              </div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;    __R  uint32_t rsv_0xf44_0xf4f[3];</div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a26e3639950f8bd188d066afec39d2bfe">  201</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a26e3639950f8bd188d066afec39d2bfe">sysram5</a>;              </div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;    __R  uint32_t rsv_0xf54_0xf5f[3];</div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="structmxc__rpu__regs__t.html#a086921af8001fdf0d9af8935b068f865">  203</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rpu__regs__t.html#a086921af8001fdf0d9af8935b068f865">sysram6</a>;              </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;} <a class="code" href="structmxc__rpu__regs__t.html">mxc_rpu_regs_t</a>;</div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="comment">/* Register offsets for module RPU */</span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga825b219b3f230d1b1e46121a81330e2b">  213</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_GCR                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga08e5da34f084d5828f0b7d87de0e3934">  214</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SIR                      ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga288078ece23c2fd5e462c487fef6b8cd">  215</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_FCR                      ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gae24964c3e6e7e54d4fd0b233f54f1c0e">  216</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_CRYPTO                   ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga4b9a63572672e8f54098314babb1cafe">  217</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WDT0                     ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga8178aa4e26199e56b5638f4303bbe746">  218</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WDT1                     ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gadac918df083790b46d844d0a14e5a9db">  219</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WDT2                     ((uint32_t)0x00000038UL) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga6b246b4f9b96120df219e2bd17136c2b">  220</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SMON                     ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga1d0f34cba28bac53dc792c9771bac914">  221</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SIMO                     ((uint32_t)0x00000044UL) </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga60bf4b11fd8fc194e351b18143bb9fc3">  222</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DVS                      ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac8c2dffbd2bd90af71b9bb402b88015a">  223</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_BBSIR                    ((uint32_t)0x00000054UL) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga1ce634242a53c466a24d37c7d1f5b1db">  224</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_RTC                      ((uint32_t)0x00000060UL) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga195ab65b469105cd3b9f94f39a9f2211">  225</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_WUT                      ((uint32_t)0x00000064UL) </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3aa16487adf823d6da62ef102304513a">  226</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_PWRSEQ                   ((uint32_t)0x00000068UL) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga21b6c3af682ef64e5178e15e509588da">  227</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_MCR                      ((uint32_t)0x0000006CUL) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga75ed135f829f917e0a5df435779b6cb9">  228</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_GPIO0                    ((uint32_t)0x00000080UL) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga6485a93c06828e0a150fed7a9f606416">  229</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_GPIO1                    ((uint32_t)0x00000090UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gab2d78a4ac627079ab600e4d70f37f9d6">  230</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR0                     ((uint32_t)0x00000100UL) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga54091642839ac8e783bc70518fce2b32">  231</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR1                     ((uint32_t)0x00000110UL) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga54b0a6e7c104e60ee4052bc26c2dc6bc">  232</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR2                     ((uint32_t)0x00000120UL) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaf1f0e4cd8e917fb7623020ecc35db7b8">  233</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR3                     ((uint32_t)0x00000130UL) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaccea9e5decdbbb8f69e6bb4c7f5f835b">  234</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR4                     ((uint32_t)0x00000140UL) </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gabd1887d752901b0228a696b5436f2adf">  235</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TMR5                     ((uint32_t)0x00000150UL) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga01b922fb60ac3bd05effd03440ea8a52">  236</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_HTIMER0                  ((uint32_t)0x000001B0UL) </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaa58379e2534bb94356a25513fcd63fb9">  237</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_HTIMER1                  ((uint32_t)0x000001C0UL) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaefb51f683d5b95a5eb7f8b96baa916e0">  238</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_I2C0_BUS0                ((uint32_t)0x000001D0UL) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga35491a688595e6a95011d50b045fa087">  239</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_I2C1_BUS0                ((uint32_t)0x000001E0UL) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3c770e9f2dac8ddb3d8811ab78ed4ec5">  240</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_I2C2_BUS0                ((uint32_t)0x000001F0UL) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gae1db0eeb2bf918bcd61de3eb74150a9d">  241</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXFM                   ((uint32_t)0x00000260UL) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga36ab22a27b914e37e8ac89738b311409">  242</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXFC                   ((uint32_t)0x00000270UL) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga057a038e76a4e64b85b8ae1a1efea609">  243</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DMA0                     ((uint32_t)0x00000280UL) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaa6b3f26966806128b9526fd5afe8fefd">  244</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_FLC0                     ((uint32_t)0x00000290UL) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga0bc3cc9ea9796806169c81de21f64850">  245</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_FLC1                     ((uint32_t)0x00000294UL) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga25089af9382221427f076a0a744dcbc0">  246</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ICC0                     ((uint32_t)0x000002A0UL) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga4b79d6a28a97c7e4672d87343f6e000a">  247</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ICC1                     ((uint32_t)0x000002A4UL) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaa5c2e1662d3e38eeb649437d5ea7b732">  248</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SFCC                     ((uint32_t)0x000002F0UL) </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga5f1e62fc14fe4e1804029026aef6a31c">  249</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SRCC                     ((uint32_t)0x00000330UL) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga5ddb3702ca58e824b39080fd943ad0e8">  250</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_ADC                      ((uint32_t)0x00000340UL) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaae53b6ab781ae22de703e2eefe48cf8a">  251</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_DMA1                     ((uint32_t)0x00000350UL) </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga8a5327625d0202b91e35df282035fb15">  252</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SDMA                     ((uint32_t)0x00000360UL) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac35bab8d18cc60bf5a2c26e6ac570fc8">  253</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SDHCCTRL                 ((uint32_t)0x00000370UL) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga81a72a43bdfa013b0483f14367077d90">  254</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXR                    ((uint32_t)0x000003A0UL) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3d11b03929af18e7a7a25937b1c9b63c">  255</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_PTG_BUS0                 ((uint32_t)0x000003C0UL) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga2f9642cfb30ad9b3022f70b6866a7b66">  256</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_OWM                      ((uint32_t)0x000003D0UL) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gacba86cb3b3d9b5e6fb6eaa0ea8c9f94d">  257</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SEMA                     ((uint32_t)0x000003E0UL) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga85374954f0649679ed9bb6c2285462a0">  258</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_UART0                    ((uint32_t)0x00000420UL) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gab8f74f1ffbabee67c6e99a7ec0db1ec1">  259</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_UART1                    ((uint32_t)0x00000430UL) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gac516a6afad33b1224b22756bf1eb996c">  260</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_UART2                    ((uint32_t)0x00000440UL) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga6e25854a9510774e7aa70a1cd10f79c9">  261</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPI1                     ((uint32_t)0x00000460UL) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga50ac3cdb93d1c48ace45667fec075bfe">  262</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPI2                     ((uint32_t)0x00000480UL) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga62858ee59d0413033e261d2fa6ac3260">  263</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_AUDIO                    ((uint32_t)0x000004C0UL) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga941d1c10cedf99ac6175ffe1fd13348c">  264</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_TRNG                     ((uint32_t)0x000004D0UL) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaceec8d8b6f34220875c91ce9d95e4fdb">  265</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_BTLE                     ((uint32_t)0x00000500UL) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga83f9fb182fac2146eeb38d7f4c2f48f1">  266</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_USBHS                    ((uint32_t)0x00000B10UL) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga875e2159d2590cb82bb0aaf08a896894">  267</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SDIO                     ((uint32_t)0x00000B60UL) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga01858d55ade4d3d95e4b816b205a614c">  268</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPIXM_FIFO               ((uint32_t)0x00000BC0UL) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaaead5559747a6cf80244155c9a3fb00d">  269</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SPI0                     ((uint32_t)0x00000BE0UL) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga9adb439090f1e123ea26b27419b78e0d">  270</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM0                  ((uint32_t)0x00000F00UL) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3b02a3527d90fe72a9370275c10e0a7f">  271</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM1                  ((uint32_t)0x00000F10UL) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaad0aea08157e57d140a785373293a87c">  272</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM2                  ((uint32_t)0x00000F20UL) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gaf535375ba256f6704127e211319dcd1b">  273</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM3                  ((uint32_t)0x00000F30UL) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga646bc7e0120b60ddb0f1685e73a730e2">  274</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM4                  ((uint32_t)0x00000F40UL) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#gab62de04717839368cc2d2f4069ce5b00">  275</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM5                  ((uint32_t)0x00000F50UL) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__RPU__Register__Offsets.html#ga3d076f2b8bc705e27a68c4aab0d79113">  276</a></span>&#160;<span class="preprocessor"> #define MXC_R_RPU_SYSRAM6                  ((uint32_t)0x00000F60UL) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga45613b9968005275b68889d50eec47a6">  285</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga5c4dc6ae97d8ef03c53dc07083360302">  286</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gac13072c2eaa7feb9f76642c1eae6340e">  288</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gae0523df446484289b65fd18999d681fd">  289</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga0751e91f4e04aaa94edb33c9201cdb99">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_USBACN_POS                       2 </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga83b50d319cd027209654e1d3125cb313">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_USBACN_POS)) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gad913b8d101b22a509f02bf3ce3cf32aa">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gad49cf64928f9a49b460ae592da694fba">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga342014bc3993fc592232fbabb77c0db8">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga44b6cbf4a9f7464ea805a679c5e670f5">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga93ee2a8ea5ad72b06a4fbde4230ee316">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga0b1cbd0f8f1cd9ba70f9a1d486fcac1e">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SDMADACN_POS)) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gaf7de29d2dbda63e1459a752753640c42">  303</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gabd54d84db559f5c287e9d0d04d2deeaf">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga9a08743827a8e4a30e9319926061db3b">  306</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#ga25e9b054309a709031e1354aba0d9abf">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gacbcdb0df384ac66cc2b9bfeb5c2ae563">  309</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__RPU__GCR.html#gad6c2401b5ceb55812d7e3975440d1e4c">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GCR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GCR_SDIOACN_POS)) </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga1a26134ce8516285c50f1a63f6cb54ba">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gaa391241f766ff2e106104d35559bb697">  321</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00323"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga24c4cd73a1cb3306d5c02a5fec15e47c">  323</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gab0727ac8b25d721dd18b628f7fb15747">  324</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00326"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga10d88182df7d61347bda9c90832e67a9">  326</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_USBACN_POS                       2 </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga89a7d9ee44bea30b43caeb0d15667d0c">  327</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_USBACN_POS)) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga6cd1de18dce6e20e7250de7159c92b00">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga924211c21e8ed96ae45d1734acf1ad1d">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga82d963ded274a442328d60f2a7230355">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga4b7b342d16434d70104ae409af482d12">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gaaa96ece4586e613e760b17b5fc78363f">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga75e9029c865ba068cfa31c2123c915ce">  336</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SDMADACN_POS)) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga2357411312acef8509936a19f7b6704b">  338</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga3f418aa7c2a16ee4c4cdc363624cddc7">  339</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gaec06c636c711b6eb474053afb48d6973">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga72700c39efb95e77aa1e018f1dc64177">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#ga9ae9eed9410eb0ef5fdc4e3ad3925909">  344</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__RPU__SIR.html#gab1c029b0c2e7e959572286845f478866">  345</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIR_SDIOACN_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga0378376fb047fbffdb7b4b0677523c26">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga03546edf8870ea408f3954d4f012b98a">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaef3b176c7a3499ae10956f5168ef7d3b">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gad5cfc62e8dd5829cb71804884240d6ae">  359</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaaaadf8b1b7b9decfd76144285b3fe57b">  361</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_USBACN_POS                       2 </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaa0867a48c71c8033ad37c88d7b3a3ed0">  362</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_USBACN_POS)) </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga82255987f96912c64ee0650368826fe1">  364</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga58ae66fd6c42f28e22bfad1be1e6626d">  365</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga72463ffdaef1db595a1c68b9dd9ca866">  367</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga5de525c2839090dd2022ee57d6ef063f">  368</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga1233a376be569acae6f86ca4107e6c95">  370</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga7fea1008142cb6367adcb80d61828a56">  371</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SDMADACN_POS)) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gaf41149cef409e805812a669a88912401">  373</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga32c81fef44b999d06b9701d62513a987">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#gac87681fb0592d6b155a0145cf6a2dd60">  376</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga0f5317628021d59270b18de259779c2a">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga11ed4b139cd59f76c1280e762d4cd5c0">  379</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__RPU__FCR.html#ga22780296669cd1fb5538de57d239797f">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FCR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FCR_SDIOACN_POS)) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gaf1cb168f7684842a23ec23e6bcde8d8f">  390</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga2a15d1db227a176e99b1b06facf9954f">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_DMA0ACN_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gae116fd272064072cf84194fc1d1cdba8">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gacc62cd8cd0a28671ad6d91a4386d03ad">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_DMA1ACN_POS)) </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gadaa166446721e88609766178ec9cbc07">  396</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_USBACN_POS                    2 </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gacc3c86bf26850081c3cf90ac1bd7d0ed">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_USBACN_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gab1b95527f58b81bca669268eba3da0e8">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga954cea278dc3435df1c9cb9331d39858">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SYS0ACN_POS)) </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gaada98eb300dd9425eb07f68fc91900cf">  402</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga19bad648e1c6cdafdd004960803b2ac9">  403</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SYS1ACN_POS)) </span></div><div class="line"><a name="l00405"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga84a0b531b1a82d539e6382d5d1da2f09">  405</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMADACN_POS                  5 </span></div><div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga136cd9084235d106b89bdf6d3ec16058">  406</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SDMADACN_POS)) </span></div><div class="line"><a name="l00408"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gaa2d82149903a23a3c839cb6aab67f4d3">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga4c7a56f309c66a6a48af9fc06fae3610">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SDMAIACN_POS)) </span></div><div class="line"><a name="l00411"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#gae7b2a38d5d3e4f9cf987a9171f375817">  411</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l00412"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga398d3262980a42e3c8c9a0fe76f25cdf">  412</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga6525daa158fe9c27149db057d25836ec">  414</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDIOACN_POS                   8 </span></div><div class="line"><a name="l00415"></a><span class="lineno"><a class="line" href="group__RPU__CRYPTO.html#ga1997b64ab3906df7b937f7e8e60110ce">  415</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_CRYPTO_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_CRYPTO_SDIOACN_POS)) </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga0161a348216d0a55018771e4790ca9e1">  425</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga36ed881c254b006455e6cad04e2377ca">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_DMA0ACN_POS)) </span></div><div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#gad0455723cf72c7b7a7769b1ecc6a38a0">  428</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#gad4031c067f4a2922ecddab9700c25c1c">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_DMA1ACN_POS)) </span></div><div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga5b39b74f0df22ccbbf8c60408fde720b">  431</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_USBACN_POS                      2 </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#gaffcea000411ce1f752fd26f6c108e858">  432</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_USBACN_POS)) </span></div><div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga0d4d89b7539218dfa2fbe6700e92c01d">  434</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga96717cf7f7e1c40f7fc142e8f93b5d93">  435</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SYS0ACN_POS)) </span></div><div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga270c9af57a0c7628c0c4933c245ca5e8">  437</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga81d49fb120cf28bd29f28bf969e9cbab">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SYS1ACN_POS)) </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga94d42ff69c6ad54c2c7fb58374c55226">  440</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga741a32e03fe4f22eb02a1c80247d395b">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SDMADACN_POS)) </span></div><div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga9be7a7022a5942a451fff212bd4a2089">  443</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00444"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga2a69d9d169483d31aa5dd92dc0180b90">  444</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SDMAIACN_POS)) </span></div><div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga7a73e40218782ab15dadfd1bdd81ca2a">  446</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00447"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga1c4491e929dacd01469759e287ea66cc">  447</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga14344f0c45f1c80a92d6114198e08929">  449</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="group__RPU__WDT0.html#ga0b64dd8f913a9c66f420964d69be91f2">  450</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT0_SDIOACN_POS)) </span></div><div class="line"><a name="l00460"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga4af0bfb0e7f41bbdcb85531de661ba3e">  460</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00461"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gad18d9cd8edca8f1f780dc668f75c5633">  461</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_DMA0ACN_POS)) </span></div><div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga2def22a877a576b40da4d22da5bb4691">  463</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga905fad7f884fa0a3e01ef72f03de44fe">  464</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_DMA1ACN_POS)) </span></div><div class="line"><a name="l00466"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gaf8708a7bac0ac6b0768291f1db43c196">  466</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_USBACN_POS                      2 </span></div><div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gae9c8d11b67b45af8b95647a683be2cee">  467</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_USBACN_POS)) </span></div><div class="line"><a name="l00469"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga713c8b04297d17366eecfd3693ac0b0f">  469</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga9c571b62864a9b6088d8052934fedd52">  470</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SYS0ACN_POS)) </span></div><div class="line"><a name="l00472"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga00a2b29e2b21e111b0f590ed39318e9b">  472</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gada399d456b3d95dfa2601c4942383f0a">  473</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SYS1ACN_POS)) </span></div><div class="line"><a name="l00475"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gaa132713969a8ea4a8f5ef24659254801">  475</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00476"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga8bd0720e419755087db2e9db09d875de">  476</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SDMADACN_POS)) </span></div><div class="line"><a name="l00478"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga37fff4a98c2952326545c4a7f0fe52ae">  478</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00479"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gafa8b0866be214105df635b3743a3e4d9">  479</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SDMAIACN_POS)) </span></div><div class="line"><a name="l00481"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga821a0b60a2a4b36d5155237c45db3e52">  481</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00482"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#gadac7967813cba726b0819534acc4a491">  482</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga1e3debd7362cd25ce08b5fdefe48fd19">  484</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__RPU__WDT1.html#ga897cdb1d2db02fdf1ee5b1e8f6d0dc4b">  485</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT1_SDIOACN_POS)) </span></div><div class="line"><a name="l00495"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga5e7eb20629c3d0e09781ab9af183fd9d">  495</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gafc8c0520cc613b15a7122735377324b1">  496</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_DMA0ACN_POS)) </span></div><div class="line"><a name="l00498"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaab20167da063426114ff45630da2623e">  498</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gac0b1b4af4e9d2a40704156a7d2f46257">  499</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_DMA1ACN_POS)) </span></div><div class="line"><a name="l00501"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga5128f3571d65aae2954b3ef7340a3474">  501</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_USBACN_POS                      2 </span></div><div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gae084df8a411a255b748facc758221e44">  502</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_USBACN_POS)) </span></div><div class="line"><a name="l00504"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaf139c3f0f1a83bea067551de208ee685">  504</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga793f6e1668be932e0ff1fe6746dbca2b">  505</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SYS0ACN_POS)) </span></div><div class="line"><a name="l00507"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaff41aee468a958271e0dd5b7479a68bb">  507</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga61a25701d3739355c5614520c69af3f9">  508</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SYS1ACN_POS)) </span></div><div class="line"><a name="l00510"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gae96c8715134659f10db74afd82de30c2">  510</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga0478dc5626b063692071833ae24b81bf">  511</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SDMADACN_POS)) </span></div><div class="line"><a name="l00513"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gadc17f9b58217601b8a1e4c19dc1cc7a3">  513</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#gaeaeb76bef702892f4f775e39b03f0375">  514</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SDMAIACN_POS)) </span></div><div class="line"><a name="l00516"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga56ff40630b153c05c9faf5f5f9974746">  516</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga9eadf7cbb808589a0ecb62668f577144">  517</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00519"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga6c792c57af53c40f3a9ec5da97b3d468">  519</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00520"></a><span class="lineno"><a class="line" href="group__RPU__WDT2.html#ga3dd5e2c9378ff9dcfc81a90d9e0abeee">  520</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WDT2_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WDT2_SDIOACN_POS)) </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga0480f88c3b83b57c587b4be268fe1690">  530</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00531"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga97042edfd15e53f9f40c6ea4bc347ec7">  531</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_DMA0ACN_POS)) </span></div><div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga2b395fe594884c618ca07c62c113ef42">  533</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00534"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gad6431dc53d326f94bdf53659b03f9aeb">  534</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_DMA1ACN_POS)) </span></div><div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga73623a1b40b872b0ced6826009b1e4c9">  536</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_USBACN_POS                      2 </span></div><div class="line"><a name="l00537"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga014ba0eaf1ccc440ba943830231eca16">  537</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_USBACN_POS)) </span></div><div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gaf6f2207c85f2e54ca0f4e1842b27ed6e">  539</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga41f5e09a2ece0d7a2f6765e87edf53cc">  540</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SYS0ACN_POS)) </span></div><div class="line"><a name="l00542"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga232fa8c0ae664988e21305fb3fa7195b">  542</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00543"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga4aadb282f8bbae164344cfe9adbfb10e">  543</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SYS1ACN_POS)) </span></div><div class="line"><a name="l00545"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga0a80da072d8a063afd339394ad25a001">  545</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00546"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gab45774e3073076f3df60ef136f2e9734">  546</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SDMADACN_POS)) </span></div><div class="line"><a name="l00548"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga2d5f52ece6a322872d53d3a283e9664d">  548</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00549"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga8db3efb4c494ff1bcfe23feafc3689d9">  549</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SDMAIACN_POS)) </span></div><div class="line"><a name="l00551"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gaa09514fdbfa08bb0ab627342cfe999ef">  551</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00552"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga710a44268963b227f03ab31b77b47ce3">  552</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00554"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#gafca18ea5ec9e35bbcc8f8283c2996c11">  554</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00555"></a><span class="lineno"><a class="line" href="group__RPU__SMON.html#ga09642da15b10ad10d5aee364bef5d03d">  555</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SMON_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SMON_SDIOACN_POS)) </span></div><div class="line"><a name="l00565"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga640baa8fbf88180e6a4af79d1d1faec6">  565</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00566"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gaafe49e6b904846d7dc5c50592b84b515">  566</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_DMA0ACN_POS)) </span></div><div class="line"><a name="l00568"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga47677f66bc729446182f13c981326997">  568</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00569"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga4eea8dda1d9dd72e09d78a775e334568">  569</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_DMA1ACN_POS)) </span></div><div class="line"><a name="l00571"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga0e3085bf3063cb2a78ca87322038de56">  571</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_USBACN_POS                      2 </span></div><div class="line"><a name="l00572"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gaa6d149ad87332e9c634ced3b7597bb34">  572</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_USBACN_POS)) </span></div><div class="line"><a name="l00574"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gafc6b0283087f4c444932bd189901ced6">  574</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00575"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gad993f20f42328a538efe03312a9888a2">  575</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SYS0ACN_POS)) </span></div><div class="line"><a name="l00577"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga42bfec098a95915724be3e570288d1e2">  577</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00578"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga5e10a07c71672478197bb67a40d93dd9">  578</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SYS1ACN_POS)) </span></div><div class="line"><a name="l00580"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga685264395715903d0bea73510b62d061">  580</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00581"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga31843cee7a85dc5b2b1b0bed98e98d82">  581</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SDMADACN_POS)) </span></div><div class="line"><a name="l00583"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga586df4736de6f5307ed724f4b24853ef">  583</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00584"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#gac49a2222255c0641fc0266f58c345390">  584</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SDMAIACN_POS)) </span></div><div class="line"><a name="l00586"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga3ac677d16ce8f935e890fc429b3fcbc4">  586</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00587"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga8e212c95246a66378e12f4c72dfd830c">  587</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00589"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga57cd0793831fc0648967bb32a212fed0">  589</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00590"></a><span class="lineno"><a class="line" href="group__RPU__SIMO.html#ga45010ee3348702d76c9f3f424f63a446">  590</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SIMO_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SIMO_SDIOACN_POS)) </span></div><div class="line"><a name="l00600"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gae6cae085e64781acc98e9b9d734e7e16">  600</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00601"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga31052610386eb955dfe1fcac834c9950">  601</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_DMA0ACN_POS)) </span></div><div class="line"><a name="l00603"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gadbac4dbd6ab31164ef5a0afdcd1d9d69">  603</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00604"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga0b4f7e10f28873d98999ad847ab85249">  604</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_DMA1ACN_POS)) </span></div><div class="line"><a name="l00606"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga2eb324ac04574cff4de9fbe851172b3a">  606</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_USBACN_POS                       2 </span></div><div class="line"><a name="l00607"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga7d94f9108fcbe9efe1db43c27bc6ac8d">  607</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_USBACN_POS)) </span></div><div class="line"><a name="l00609"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga41e1645ecd19b400d0297bb6090007a3">  609</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00610"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga3c4d4e1ff456447a54caad64aeb1598d">  610</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SYS0ACN_POS)) </span></div><div class="line"><a name="l00612"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga63b882b7652c8f687d9b84252199bac7">  612</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00613"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga290bd9599ab8748cd21e402bcb41a693">  613</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SYS1ACN_POS)) </span></div><div class="line"><a name="l00615"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gad63a9cb11d84ef4b7fc4d968e2da8ce3">  615</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00616"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga00d620785a9498472ada1e5364d8dfe0">  616</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SDMADACN_POS)) </span></div><div class="line"><a name="l00618"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga85db01639bb2aff7f97c1e48cd256056">  618</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00619"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga4410eee63366c45ad9229408fb0d6a56">  619</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SDMAIACN_POS)) </span></div><div class="line"><a name="l00621"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#gacd1f7ca3857b76f8ee72e5fed712ef5c">  621</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00622"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga6aedf82ecdb4507f8ba01ff2546f7eb9">  622</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00624"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga4f3e212f046e0488ac3e58d6ca796c10">  624</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00625"></a><span class="lineno"><a class="line" href="group__RPU__DVS.html#ga5c6df9a2b032d2f925e941f7abb630df">  625</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DVS_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DVS_SDIOACN_POS)) </span></div><div class="line"><a name="l00635"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga306856ae3f1a9f873cb972f28749f89d">  635</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l00636"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga9ba7ffe70b0703582bc7781ce06cc4ee">  636</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00638"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga70b7c9762d81ac34f32aff047a4bb079">  638</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l00639"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gafd6bb1a7703e3adf2085a92d9802255d">  639</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00641"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gadd51ce1f7f636e13e6e35326b314bc78">  641</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_USBACN_POS                     2 </span></div><div class="line"><a name="l00642"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gab6ad6ae34bc880690b3f6461c1d3992c">  642</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_USBACN                  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href="group__RPU__BBSIR.html#ga27694e5ce9de58b245e43947888131e5">  648</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00650"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga8625761ecc5d4ae1407c366838e8e97a">  650</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMADACN_POS                   5 </span></div><div class="line"><a name="l00651"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga0ae0f4110388ecef06a642d421a19d0f">  651</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SDMADACN_POS)) </span></div><div class="line"><a name="l00653"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gac962d318c7c39a5a8934f6948043f630">  653</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l00654"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gac23271538d6125c8d41961c3dcbaa931">  654</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00656"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga06e83d99b72c69a6a9c47453de9cbbe1">  656</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l00657"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga90b9a073eaf6b1fdcd27b7f2390be0fa">  657</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00659"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#ga8a308b593e34a3b837b16fcaff947105">  659</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDIOACN_POS                    8 </span></div><div class="line"><a name="l00660"></a><span class="lineno"><a class="line" href="group__RPU__BBSIR.html#gaffdb6734194f08edca761b6244cd394b">  660</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BBSIR_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BBSIR_SDIOACN_POS)) </span></div><div class="line"><a name="l00670"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gab1889912a28796ae5751828f6bebc1af">  670</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00671"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga874d9ea41b197289f2cdf09fe09dd41a">  671</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_DMA0ACN_POS)) </span></div><div class="line"><a name="l00673"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga7efd0476f78ce206132d2b8dbe73e7b1">  673</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00674"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga8a9dd12769dd9227c0785d2f1ecddbf8">  674</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_DMA1ACN_POS)) </span></div><div class="line"><a name="l00676"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga9bf538ecdcd70445c420fb899809fe70">  676</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_USBACN_POS                       2 </span></div><div class="line"><a name="l00677"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga6f816b6073f51900931a950684fecfdf">  677</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_USBACN_POS)) </span></div><div class="line"><a name="l00679"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gac71050ef92202cd68749064a12fdbbf8">  679</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00680"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga844a5290bff499358ef3de11b46b2745">  680</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SYS0ACN_POS)) </span></div><div class="line"><a name="l00682"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gaa93d642e4ceab65bab912a747bee0d41">  682</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00683"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gaa72ae31e82723ce6d52f6e2ebe0d3fe5">  683</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SYS1ACN_POS)) </span></div><div class="line"><a name="l00685"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga553ecb27dbbe6f08b22d70c7e319ca2c">  685</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00686"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gae6bd256f9848cfb97f1926418d0dcf70">  686</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SDMADACN_POS)) </span></div><div class="line"><a name="l00688"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga65c8bb0dda0ad6ef19e1b534f7fa621c">  688</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00689"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga6398416cb3807485439911c917724ce7">  689</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SDMAIACN_POS)) </span></div><div class="line"><a name="l00691"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga733ed8a37c8aebcb25253337a6fe2097">  691</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00692"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#gac13aba84e71f18bdc5cc46481a357ef3">  692</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00694"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga6281ca27ca8ed7ca3af275d13ff0abcf">  694</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00695"></a><span class="lineno"><a class="line" href="group__RPU__RTC.html#ga4a955cc40006f11c70f843632024a309">  695</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_RTC_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_RTC_SDIOACN_POS)) </span></div><div class="line"><a name="l00705"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gaf96c2c444706cbc834284abd3439f691">  705</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00706"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga592e011ffa599a62108579cf2954a51f">  706</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_DMA0ACN_POS)) </span></div><div class="line"><a name="l00708"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga46f292ecb6b674bb6433a3d8f22b96ca">  708</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00709"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga360babfc90435e773f8e42e048dbc6e9">  709</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_DMA1ACN_POS)) </span></div><div class="line"><a name="l00711"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga19a5be52be14e314f3884de82d40b7c9">  711</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_USBACN_POS                       2 </span></div><div class="line"><a name="l00712"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga56c0ff07452fd0d3db3e0dda55aa64ca">  712</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_USBACN_POS)) </span></div><div class="line"><a name="l00714"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gaaa6fa71d3de1c34c51217d6a62aeddee">  714</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00715"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga612e99b56b58c496578276e843d5cc8e">  715</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SYS0ACN_POS)) </span></div><div class="line"><a name="l00717"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gaef333d3fbe29ab4ba51855587b46c261">  717</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00718"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga51c3ce88248582b0b6cec5a8ed095720">  718</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SYS1ACN_POS)) </span></div><div class="line"><a name="l00720"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gae6e873bf156f3791439888f02f15f985">  720</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00721"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga9e90c20f4612796371094f0c39be0330">  721</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SDMADACN_POS)) </span></div><div class="line"><a name="l00723"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gafb8764c52fabe8378a1991b4b2f63ac0">  723</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00724"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga66eb595770a8e96fa0f4402156b32896">  724</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SDMAIACN_POS)) </span></div><div class="line"><a name="l00726"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga8bbfa55d92dc03b6885877bc32ad6dfc">  726</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00727"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#gab01b31e652a552e1d9efbaaa2834d008">  727</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00729"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga45bf3ac9d768976caff451d52ffc79d4">  729</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00730"></a><span class="lineno"><a class="line" href="group__RPU__WUT.html#ga024cda5796bdff5e94fceb28937ca89f">  730</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_WUT_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_WUT_SDIOACN_POS)) </span></div><div class="line"><a name="l00740"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga4569c447b8e038b577893a414058a713">  740</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l00741"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gae4020d6ea794759df54bd0f95f13e65a">  741</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_DMA0ACN_POS)) </span></div><div class="line"><a name="l00743"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gaeff0ec284c24a034cbc9664087a7851e">  743</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l00744"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga276389ca290bf8bbd56d2e3bae326533">  744</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_DMA1ACN_POS)) </span></div><div class="line"><a name="l00746"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gaa8db4dafcfb97031a72b4c69628d942e">  746</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_USBACN_POS                    2 </span></div><div class="line"><a name="l00747"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga7fbaaf8d966a849b32bee7be1fa6428e">  747</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_USBACN_POS)) </span></div><div class="line"><a name="l00749"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga5799f8d27c64ae5ef41f8aba10cd872d">  749</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l00750"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga2060cb2b62d5b0818111b9d937479a84">  750</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SYS0ACN_POS)) </span></div><div class="line"><a name="l00752"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga704376dd1d331af67cca3a5b80c78442">  752</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l00753"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga17f003bd99f2f5b1aa5fddeeeafc83df">  753</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SYS1ACN_POS)) </span></div><div class="line"><a name="l00755"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga8c3b4fb940e5450c57bb0871a462a2c5">  755</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMADACN_POS                  5 </span></div><div class="line"><a name="l00756"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gad427d6fcb4f0adbcf2bde34350cbcfeb">  756</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SDMADACN_POS)) </span></div><div class="line"><a name="l00758"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga1b975eb7882aae028ffda19cdcb1f009">  758</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l00759"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga8d429ef64d57742dfc27716a009d9dc4">  759</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SDMAIACN_POS)) </span></div><div class="line"><a name="l00761"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gaa857ae7041e4d97bf59420ab439c1069">  761</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l00762"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#gae007d6889bc367574b2d322f415285ea">  762</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00764"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga819a48a505bc27a85345a26e9d44e0a2">  764</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDIOACN_POS                   8 </span></div><div class="line"><a name="l00765"></a><span class="lineno"><a class="line" href="group__RPU__PWRSEQ.html#ga58b4704b4b1f896ef9889247b3377cc8">  765</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PWRSEQ_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PWRSEQ_SDIOACN_POS)) </span></div><div class="line"><a name="l00775"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga9a71318b6999b9402899f22134bf209d">  775</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l00776"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#gae4b29f8b86dc13824a0942f68645ab53">  776</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_DMA0ACN_POS)) </span></div><div class="line"><a name="l00778"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga2b8ccc62390b1252bd4bd4aed02e3804">  778</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l00779"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga61ddf6188d3c6a895218e8a6a23682e7">  779</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_DMA1ACN_POS)) </span></div><div class="line"><a name="l00781"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#gabfce98057e217dd9569519616fe55ef3">  781</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_USBACN_POS                       2 </span></div><div class="line"><a name="l00782"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga72549fc850c4154265b5f93b5d479a22">  782</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_USBACN_POS)) </span></div><div class="line"><a name="l00784"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga2a96f1907060f54ceb3d87993f870a1f">  784</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l00785"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga870b2713f65719a0d0afa0b8b206f988">  785</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_SYS0ACN_POS)) </span></div><div class="line"><a name="l00787"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#gac0571ab3af3ba2a28f71021540ba12bc">  787</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l00788"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga04288881fb2586cf4406096c09425339">  788</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_SYS1ACN_POS)) </span></div><div class="line"><a name="l00790"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#gab672c31846d4124bceeb0802ceefb466">  790</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SDMADACN_POS                     5 </span></div><div class="line"><a name="l00791"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga160487f4408a251efd7cf362fa3dea18">  791</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_SDMADACN_POS)) </span></div><div class="line"><a name="l00793"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga9ae8cc21cf42a7c52c9f283878883fae">  793</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l00794"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga4fae63b45b2bd88878fca231afb7b21f">  794</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_SDMAIACN_POS)) </span></div><div class="line"><a name="l00796"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga36d85d76dfea568ac873204db317ec2a">  796</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l00797"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga907430c6844334d7e873eb4280c70fd9">  797</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00799"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga856768c00451818b44f593030a16e03b">  799</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SDIOACN_POS                      8 </span></div><div class="line"><a name="l00800"></a><span class="lineno"><a class="line" href="group__RPU__MCR.html#ga1c55d03d4de2cda7fea87e244f4258f2">  800</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_MCR_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_MCR_SDIOACN_POS)) </span></div><div class="line"><a name="l00810"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaa5db11c68cd9146653ae7b43d7071677">  810</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l00811"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gabf4ba9d4008a46800ec6c0eaeff9643e">  811</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_DMA0ACN_POS)) </span></div><div class="line"><a name="l00813"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga89452c5dd955595ccef0d23ca42c89fc">  813</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l00814"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaf2a9926d92bbb66a6d880bec749dcaef">  814</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_DMA1ACN_POS)) </span></div><div class="line"><a name="l00816"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga7cd7da8663b8f3f30d11d457d2286aab">  816</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_USBACN_POS                     2 </span></div><div class="line"><a name="l00817"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga2bfd3c80c2984ffd6405380844ee258f">  817</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_USBACN_POS)) </span></div><div class="line"><a name="l00819"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga02ad027850bf277117bf310a735a6649">  819</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l00820"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga9f7b81d3bb6c7b4915f5e66c534cf922">  820</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SYS0ACN_POS)) </span></div><div class="line"><a name="l00822"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaec025e5ecc2018849cf37e521cad640c">  822</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l00823"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gaba943f5c4d690a551a4a382fdb77f945">  823</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SYS1ACN_POS)) </span></div><div class="line"><a name="l00825"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga66e93317c6a8f4f7abaca5138062ea7e">  825</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMADACN_POS                   5 </span></div><div class="line"><a name="l00826"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga1e58664648f84a140a4c58ecbcfc49fb">  826</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SDMADACN_POS)) </span></div><div class="line"><a name="l00828"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga42cde52fedadd87901a22452305ad8a3">  828</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l00829"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gac2eb97cb354b828785586873a2baf5b8">  829</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SDMAIACN_POS)) </span></div><div class="line"><a name="l00831"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga04306edd58942ea79f1fe1566b39e890">  831</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l00832"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gae7b85eaced4f94933d9f22f03e1f4782">  832</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00834"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#gae14ef4dd0f971ee49a1492b4834be50c">  834</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDIOACN_POS                    8 </span></div><div class="line"><a name="l00835"></a><span class="lineno"><a class="line" href="group__RPU__GPIO0.html#ga37fa4ab1a0cd2c3788b3ba0acdea4525">  835</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO0_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO0_SDIOACN_POS)) </span></div><div class="line"><a name="l00845"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga088272ce8ba3953078f66d1e9661af76">  845</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l00846"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gab4ea8ced74717eb642ba72f36c870c93">  846</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_DMA0ACN_POS)) </span></div><div class="line"><a name="l00848"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gae6bfae1113d3a441d057097e2c8e04da">  848</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l00849"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gad1bd8d4477d50440551530f95e6457cb">  849</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_DMA1ACN_POS)) </span></div><div class="line"><a name="l00851"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gacfb5ee544f717addd39e0a1547d060d4">  851</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_USBACN_POS                     2 </span></div><div class="line"><a name="l00852"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga2adc2f01e0ba73160432c0ab78044b56">  852</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_USBACN_POS)) </span></div><div class="line"><a name="l00854"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga166af524c718661b0a29fb3e5726b0b4">  854</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l00855"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gab2e6892352a801eec823c71b381ebae2">  855</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SYS0ACN_POS)) </span></div><div class="line"><a name="l00857"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gaf72b2324de9b1710a57d6ca0d598759d">  857</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l00858"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga1a6ad2a78dcd99067cd811c7e61ca6dc">  858</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SYS1ACN_POS)) </span></div><div class="line"><a name="l00860"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga66d7ada7d67bd388208201532416e6b9">  860</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMADACN_POS                   5 </span></div><div class="line"><a name="l00861"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga0ed93f9429b2d5a72c24748963bbc627">  861</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SDMADACN_POS)) </span></div><div class="line"><a name="l00863"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga5d1697a8c3ea0ebf45639cf137ef4fcc">  863</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l00864"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga42a79a214db07b860ceb6e1ace9795a2">  864</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SDMAIACN_POS)) </span></div><div class="line"><a name="l00866"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga8a7a6c2b1ae5cb8cf9b71947d674fe23">  866</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l00867"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga7306cb77f9b5a638e184fa670ec661f4">  867</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00869"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#gae171adb61de8bb5a7e0292a59e28c290">  869</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDIOACN_POS                    8 </span></div><div class="line"><a name="l00870"></a><span class="lineno"><a class="line" href="group__RPU__GPIO1.html#ga3dd207b61fd8822f8dc7519f6210a95d">  870</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_GPIO1_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_GPIO1_SDIOACN_POS)) </span></div><div class="line"><a name="l00880"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga75c5b18d3d516ea2e073526ef016f95a">  880</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00881"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga495990e1cfb6b5614487068e0d1eaa68">  881</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_DMA0ACN_POS)) </span></div><div class="line"><a name="l00883"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga04b8f00a8494383456fcd7ccbdb2488d">  883</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00884"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gad9a19c812b731b927231974dc42dc102">  884</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_DMA1ACN_POS)) </span></div><div class="line"><a name="l00886"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga91d39beecfaf3f63ea1fa3cb3c03d9be">  886</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_USBACN_POS                      2 </span></div><div class="line"><a name="l00887"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga976e43193815750835fd12857608448c">  887</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_USBACN_POS)) </span></div><div class="line"><a name="l00889"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gae77fb312fd94eecbea83c4db59138064">  889</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00890"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga917b7396a66a57eb612aaf9f85c2186f">  890</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SYS0ACN_POS)) </span></div><div class="line"><a name="l00892"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga9eba409bfb929629c59a7e6f4ad8da11">  892</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00893"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga71443f7155b8ebb4f13104b76736ff63">  893</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SYS1ACN_POS)) </span></div><div class="line"><a name="l00895"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gafcd86ff62eb147654a97bdda98c50636">  895</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00896"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga9874f61c22f156bf7bede48d1a735efa">  896</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SDMADACN_POS)) </span></div><div class="line"><a name="l00898"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gaf45e63135227c4b86b3b28aab723c816">  898</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00899"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga344a749028ae763c52ea20119256244c">  899</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SDMAIACN_POS)) </span></div><div class="line"><a name="l00901"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga60358ed27753203bd73f89bdd1787ebd">  901</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00902"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#ga4d24c4cd8eda801dcc58491f679ae07d">  902</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00904"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gadedf7fdd53e9eb5daf19669f8282246d">  904</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00905"></a><span class="lineno"><a class="line" href="group__RPU__TMR0.html#gabd06ffd71ca62141aa1b9db626ac28d2">  905</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR0_SDIOACN_POS)) </span></div><div class="line"><a name="l00915"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaa6f500345830f001fa029625107f69d2">  915</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00916"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaeac74ccd431a7087ad181c4d24e35755">  916</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_DMA0ACN_POS)) </span></div><div class="line"><a name="l00918"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga74e622c219ddd38b66a1276a50aad1aa">  918</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00919"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga7617c1fd6bba4f98f05bb4c33057e3a4">  919</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_DMA1ACN_POS)) </span></div><div class="line"><a name="l00921"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga04b730f1e82d7d8064167a6ed55c73af">  921</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_USBACN_POS                      2 </span></div><div class="line"><a name="l00922"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gac11aab58cac19300317710fc49129a0b">  922</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_USBACN_POS)) </span></div><div class="line"><a name="l00924"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga053cc5c3ab6776140f6dea0459eadd3c">  924</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00925"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga81e3bb7cd914b0dd170fae63b4683a53">  925</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SYS0ACN_POS)) </span></div><div class="line"><a name="l00927"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga9a52441c46bd5aa03dc1a2f896a9857e">  927</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00928"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga1472c8016e328c84398f9b62d399f7ef">  928</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SYS1ACN_POS)) </span></div><div class="line"><a name="l00930"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga06970102e8f282edcbff65caad668d0f">  930</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00931"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga3d5d6f72437839eaf8de31cd065e0bb4">  931</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SDMADACN_POS)) </span></div><div class="line"><a name="l00933"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga7ec625606000798375c78a490f793768">  933</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00934"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaa13dc7b24030e970232dca4aaf2dbc86">  934</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SDMAIACN_POS)) </span></div><div class="line"><a name="l00936"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#gaf21f920df39a53a467e4bcf2515138d5">  936</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00937"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga71140b8e5f1a99865042c0a5b7d05f06">  937</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00939"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga29ff72973e75c7aabe9d344afe3e91ac">  939</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00940"></a><span class="lineno"><a class="line" href="group__RPU__TMR1.html#ga87ad75c32395013bbef606daca934c83">  940</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR1_SDIOACN_POS)) </span></div><div class="line"><a name="l00950"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga6523751950e08dfd19759f1ac0a1a2cb">  950</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00951"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga5ce7b1d44b33ef931ef8e3c5818e1923">  951</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_DMA0ACN_POS)) </span></div><div class="line"><a name="l00953"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gab55aec1a61a30b1ed255f271b58b6bf4">  953</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00954"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gad691aab7341d4d63fb3e7f8905d65d28">  954</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_DMA1ACN_POS)) </span></div><div class="line"><a name="l00956"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga5a2bbbf45e4516a639dacfe897ffac4f">  956</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_USBACN_POS                      2 </span></div><div class="line"><a name="l00957"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gaf714b341f57e916de5ecfc605e6c59cf">  957</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_USBACN_POS)) </span></div><div class="line"><a name="l00959"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gabc388d52471cc160057c6d3da6c67360">  959</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00960"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gad62239bcc1029609561b1a2bf591f7d6">  960</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SYS0ACN_POS)) </span></div><div class="line"><a name="l00962"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga27c4a9417e5a6b00ea55672258081c38">  962</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00963"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gaf76084ca046aeb3aaf040976ff19f75c">  963</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SYS1ACN_POS)) </span></div><div class="line"><a name="l00965"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga96a4cb8f05319f7e1622966cb4440af8">  965</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMADACN_POS                    5 </span></div><div class="line"><a name="l00966"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga710b570f416d03d930c3ddb2a35d5977">  966</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SDMADACN_POS)) </span></div><div class="line"><a name="l00968"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga140dfabb3cb3c4349f40a0f372275648">  968</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l00969"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga4157bdd559f60528cfffd11526cac265">  969</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SDMAIACN_POS)) </span></div><div class="line"><a name="l00971"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga651362f87566b4f21c5a3fd1b396ba4b">  971</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l00972"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#ga2147ddf1013d8c4842b1d4c6d5be2115">  972</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l00974"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gac562af7b8fdc9a3254cfcf1eba84b8bf">  974</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDIOACN_POS                     8 </span></div><div class="line"><a name="l00975"></a><span class="lineno"><a class="line" href="group__RPU__TMR2.html#gaa9ca145006666d86a1bbf2cd9524fd14">  975</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR2_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR2_SDIOACN_POS)) </span></div><div class="line"><a name="l00985"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga658c7874f29667f2f9cb4e6496e80362">  985</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l00986"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gab612e51e4b7b076b879c49a7f79f6862">  986</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_DMA0ACN_POS)) </span></div><div class="line"><a name="l00988"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga3038c15864b7d70124b9056beeae8ee4">  988</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l00989"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gad5d0b836b24dcdb64a278be7073a35d8">  989</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_DMA1ACN_POS)) </span></div><div class="line"><a name="l00991"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga402a6248e73ba85acb7d0758392b3cbc">  991</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_USBACN_POS                      2 </span></div><div class="line"><a name="l00992"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga3236b23726ba291911c014e62aff49cc">  992</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_USBACN_POS)) </span></div><div class="line"><a name="l00994"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga7aa669b71664bdd996fd7f6756bdcbb0">  994</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l00995"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gae7a91abf9c98b38245dee7f0ec307c14">  995</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SYS0ACN_POS)) </span></div><div class="line"><a name="l00997"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga358b69c2787fb2db842678478a815f27">  997</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l00998"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga8e45430a51d5e8a3e2fe2a9e128e8c55">  998</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SYS1ACN_POS)) </span></div><div class="line"><a name="l01000"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga3fcb85878a64537cf6bfd4b8eff8c834"> 1000</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01001"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gabfb2b89c5e56aa72e74e6fbfedcb7785"> 1001</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SDMADACN_POS)) </span></div><div class="line"><a name="l01003"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga61731340a4bf472442e55e53d96e5da0"> 1003</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01004"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga995c38f588b835ded6e6c9d3ca5f16f0"> 1004</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SDMAIACN_POS)) </span></div><div class="line"><a name="l01006"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga9a59d91acf515c319a245558d7ce1060"> 1006</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01007"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#gafd9a39012ba2191737f3a0fd258412b7"> 1007</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01009"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga241d684c17acd033a6729f4b21fd9b51"> 1009</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01010"></a><span class="lineno"><a class="line" href="group__RPU__TMR3.html#ga61d966afc5a06129454bc468ea7fdff3"> 1010</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR3_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR3_SDIOACN_POS)) </span></div><div class="line"><a name="l01020"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga97dd2ba6090fe4c0d5c9cd245b559634"> 1020</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01021"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga22ce57afb3ee9d27c5a214ce30da0a45"> 1021</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_DMA0ACN_POS)) </span></div><div class="line"><a name="l01023"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gac4bf886fc5460896b7fc31f947a1b456"> 1023</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01024"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga6465d1ec95d5befb79d323ee5991a807"> 1024</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_DMA1ACN_POS)) </span></div><div class="line"><a name="l01026"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gaae70f4c4be16ada5c15992bb66fc8fa1"> 1026</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_USBACN_POS                      2 </span></div><div class="line"><a name="l01027"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga402b0b923a8e2df219e4b5d0d8ac153d"> 1027</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_USBACN_POS)) </span></div><div class="line"><a name="l01029"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga736c6b086fad7ad97fe48e82cb9dcaf0"> 1029</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01030"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga276367b0bcdbbf19830932e177d828cf"> 1030</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SYS0ACN_POS)) </span></div><div class="line"><a name="l01032"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gad79f0203dd52486c2340a18d2f541f21"> 1032</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01033"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gac2d6d71328a3a03e8215e49e38af5676"> 1033</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SYS1ACN_POS)) </span></div><div class="line"><a name="l01035"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gac31631c580fc1aeafb8e7935dfa4364b"> 1035</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01036"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga3a4fd39c8a8cb03126a150b761f3d7b7"> 1036</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SDMADACN_POS)) </span></div><div class="line"><a name="l01038"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga09cd1a79d0095d26bd9337dc841c85b2"> 1038</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01039"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga4732ca4fc3ece240022e33f3a1dd4c21"> 1039</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SDMAIACN_POS)) </span></div><div class="line"><a name="l01041"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga4a79c7d05ddedf62d280e31790420377"> 1041</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01042"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#ga00bf66fa1cf5593cbb2cb0d02ee3a79b"> 1042</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01044"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gaf6efdd2cd0fc4b2f0ec590c500ed2467"> 1044</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01045"></a><span class="lineno"><a class="line" href="group__RPU__TMR4.html#gae729f462eeb7009ce14f2e35b95e59fc"> 1045</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR4_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR4_SDIOACN_POS)) </span></div><div class="line"><a name="l01055"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga913b8077be50daf219dbf00b6993019e"> 1055</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01056"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gadfc93ecbce80607d50a94e34a66b207e"> 1056</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_DMA0ACN_POS)) </span></div><div class="line"><a name="l01058"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga370d8ca6299329dd30889dbb57d64307"> 1058</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01059"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gac83ddf7b0fbb1127f042ba42e604bfff"> 1059</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_DMA1ACN_POS)) </span></div><div class="line"><a name="l01061"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga21c8419e92f4b0612236756e29079436"> 1061</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_USBACN_POS                      2 </span></div><div class="line"><a name="l01062"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga6389e580e5a961986a9f013df15b9fba"> 1062</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_USBACN_POS)) </span></div><div class="line"><a name="l01064"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gaeddbad3147e874323035af3ee4017b05"> 1064</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01065"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga4727421768ceb44aaaa8d9050719b957"> 1065</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SYS0ACN_POS)) </span></div><div class="line"><a name="l01067"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga17ce4263420feb84a56447e3ef01f286"> 1067</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01068"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga09aeed1ab101765303b9e0903a990dd6"> 1068</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SYS1ACN_POS)) </span></div><div class="line"><a name="l01070"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga6bcc47a18c7d07f0bcd6c2109622f292"> 1070</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01071"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga523a3c5e3c9df1dbf5691598b5cec131"> 1071</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SDMADACN_POS)) </span></div><div class="line"><a name="l01073"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gafdcbd467868fe7a43886a45eb05ddc1f"> 1073</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01074"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga82143ecc83be5fe8c3deddebe0f58bf4"> 1074</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SDMAIACN_POS)) </span></div><div class="line"><a name="l01076"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gabd4fbf6bf2ecfd1c248415c3d4b50104"> 1076</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01077"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#gacd03ef43d92df594d556c605b541e4a2"> 1077</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01079"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga637d4ca9bc28f36b566bb9eb38f7cd35"> 1079</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01080"></a><span class="lineno"><a class="line" href="group__RPU__TMR5.html#ga3fa9563c39f4f8cfcf2115f3c1880f5a"> 1080</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TMR5_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TMR5_SDIOACN_POS)) </span></div><div class="line"><a name="l01090"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga5d04bd438fba5d51efaf253b0214ae8a"> 1090</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01091"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gadd9f591a0fda5ef13f9d5741b5d16274"> 1091</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01093"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga327c2175ff397a7846708dca6ca18166"> 1093</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01094"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga886b3b98f35b34f2dbe200777e2ef673"> 1094</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01096"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga9d2d1211238e3ab97a341ffd014d5e3b"> 1096</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_USBACN_POS                   2 </span></div><div class="line"><a name="l01097"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gab624337a92db4d1ba7b2005f0e3f1ad5"> 1097</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_USBACN_POS)) </span></div><div class="line"><a name="l01099"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga7c3ad9652ddf06a9c4d5aa60d26e11a4"> 1099</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01100"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gad7191b3a72ab400b85231beaf5bac6fa"> 1100</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01102"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga3c46bf5a1694451f7ae991db5b0089b3"> 1102</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01103"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gaf7ad2c3ba7834099c11c9de833cafc13"> 1103</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01105"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga51b5b1457b91fdf9dcf6a8fa99d013ac"> 1105</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01106"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga4db2bef15e456c7c8835a1e5a1b7095b"> 1106</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SDMADACN_POS)) </span></div><div class="line"><a name="l01108"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga41e4ee76ebf0330a92ef331c33e03570"> 1108</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01109"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga1b63069ec866d33f50bc05524a677a51"> 1109</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01111"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga7ba3cacfbce92112efbb07049b30f583"> 1111</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01112"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga4430f4643568c2586fff2fdb9eb4855b"> 1112</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01114"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#gaba8af080229a589be7f740cc40dbc834"> 1114</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01115"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER0.html#ga37ef8530632a8ee39fe933657597ab5d"> 1115</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER0_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER0_SDIOACN_POS)) </span></div><div class="line"><a name="l01125"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga124cd2f28d464d3227e532aa644e4959"> 1125</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA0ACN_POS                  0 </span></div><div class="line"><a name="l01126"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga9b86479d5b894501bafc5d2a7a8a3997"> 1126</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01128"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gaa491f9b0b42bfb9e18c50533727da293"> 1128</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA1ACN_POS                  1 </span></div><div class="line"><a name="l01129"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gab32729a01924593862023c711be13454"> 1129</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_DMA1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01131"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gae5147ec732997ee88a37ce67faefbf1e"> 1131</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_USBACN_POS                   2 </span></div><div class="line"><a name="l01132"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga139acf6899875b2160ae7d3ad169aa45"> 1132</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_USBACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_USBACN_POS)) </span></div><div class="line"><a name="l01134"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga6ca8351efd86fd40a492ab7ae3d4afa0"> 1134</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS0ACN_POS                  3 </span></div><div class="line"><a name="l01135"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gae9ffe24f562d646fb727c238831e00bb"> 1135</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS0ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01137"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gaff53d7b98a8cc36874391e9a0ee92296"> 1137</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS1ACN_POS                  4 </span></div><div class="line"><a name="l01138"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga99890fe9ebf3334f9cd334c8bb6fa636"> 1138</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SYS1ACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01140"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga4a8e45a3a9069e8dd63b8c243d0bf2f7"> 1140</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMADACN_POS                 5 </span></div><div class="line"><a name="l01141"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga0d90df4402a0e0071f72e405a1f4da32"> 1141</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMADACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SDMADACN_POS)) </span></div><div class="line"><a name="l01143"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gaba5c8ad2cd144026b773b0a0a83aea9c"> 1143</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMAIACN_POS                 6 </span></div><div class="line"><a name="l01144"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga20041e0ac4b00734efc4ae8f814a8003"> 1144</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDMAIACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01146"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga3eb3360cbbb829e3eab8e3beb200eac6"> 1146</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_CRYPTOACN_POS                7 </span></div><div class="line"><a name="l01147"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#ga6ec6840e7f69453784aaccca2fcd3a2d"> 1147</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_CRYPTOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01149"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gab4857b5322ea1426eec70479ccc5b02e"> 1149</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDIOACN_POS                  8 </span></div><div class="line"><a name="l01150"></a><span class="lineno"><a class="line" href="group__RPU__HTIMER1.html#gafa1dbcaa12cca9cdc355e69221f58553"> 1150</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_HTIMER1_SDIOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_HTIMER1_SDIOACN_POS)) </span></div><div class="line"><a name="l01160"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#gab56db33fcf241afaa1ffea83cc6100c4"> 1160</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_DMA0ACN_POS                0 </span></div><div class="line"><a name="l01161"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#gae083cf140f5de8522e4ea26c58f10c10"> 1161</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_DMA0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01163"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#gae6acf2bfa0c6f983094c9b12c27fc4ed"> 1163</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_DMA1ACN_POS                1 </span></div><div class="line"><a name="l01164"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga0c3b58973dcd8f3410ccc16434cde604"> 1164</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_DMA1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01166"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga08f07e172966cfbb13580a830a210f09"> 1166</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_USBACN_POS                 2 </span></div><div class="line"><a name="l01167"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#gaaea9cdf66f2c40a47387cf7042397cde"> 1167</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_USBACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_USBACN_POS)) </span></div><div class="line"><a name="l01169"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga99147d5bc622fa6def33161adbdf0912"> 1169</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SYS0ACN_POS                3 </span></div><div class="line"><a name="l01170"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#gabf6b59a692b03a12210fc28da453c716"> 1170</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SYS0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01172"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#gac3ae51620d20416cbfb231cf91622032"> 1172</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SYS1ACN_POS                4 </span></div><div class="line"><a name="l01173"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga923e63a0f2e6ed8d38eaac876a171f8a"> 1173</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SYS1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01175"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga710b89a22ce72085e5b1918c14c2d165"> 1175</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SDMADACN_POS               5 </span></div><div class="line"><a name="l01176"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga31d76d0980d8c4bd3e1e06e31b65bef4"> 1176</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SDMADACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_SDMADACN_POS)) </span></div><div class="line"><a name="l01178"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga87b805a9cbcea3a7f2e5b27a564a3810"> 1178</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SDMAIACN_POS               6 </span></div><div class="line"><a name="l01179"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga476d14e0df3eefec150d6b9b4ca6bdb0"> 1179</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SDMAIACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01181"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga9928b661fb126430c0e5e9ce1a40f64e"> 1181</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_CRYPTOACN_POS              7 </span></div><div class="line"><a name="l01182"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga878aedaf6a561bdd439ef363f3c8d68e"> 1182</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_CRYPTOACN                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01184"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga5e10db27acb9dfd6050148ff959995f9"> 1184</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SDIOACN_POS                8 </span></div><div class="line"><a name="l01185"></a><span class="lineno"><a class="line" href="group__RPU__I2C0__BUS0.html#ga086ce781f47ab49b2f46a3638e1c8e9e"> 1185</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C0_BUS0_SDIOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C0_BUS0_SDIOACN_POS)) </span></div><div class="line"><a name="l01195"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga73341c8b9c2df2ec97b29070ff5eca71"> 1195</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_DMA0ACN_POS                0 </span></div><div class="line"><a name="l01196"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gaa898547baf3aa757396a382f4ec0b26d"> 1196</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_DMA0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01198"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gaadbfb287f51de08b0befedcd3c8a07b8"> 1198</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_DMA1ACN_POS                1 </span></div><div class="line"><a name="l01199"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga6057dcc8f71ec341a9e62a46d450b015"> 1199</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_DMA1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01201"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga32fc9a13c2c4e332fe20052e2240824b"> 1201</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_USBACN_POS                 2 </span></div><div class="line"><a name="l01202"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gabbbf104ba0a91d8dc6d080ea51db3d3b"> 1202</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_USBACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_USBACN_POS)) </span></div><div class="line"><a name="l01204"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga5aa44eeaa2fb60f7ebf5567da47f42ee"> 1204</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SYS0ACN_POS                3 </span></div><div class="line"><a name="l01205"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gaff161f249c87e06b74adf9b620b1239f"> 1205</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SYS0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01207"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gaf8c95e328418d771d03f1d284b7267b9"> 1207</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SYS1ACN_POS                4 </span></div><div class="line"><a name="l01208"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga30f9aaf2a65fbacd5bf2898f10bc9bad"> 1208</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SYS1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01210"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gae72470cc8d3963616cf1a0d7f37574f2"> 1210</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SDMADACN_POS               5 </span></div><div class="line"><a name="l01211"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gadaf4f3feed4083751ceec33edcea638d"> 1211</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SDMADACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_SDMADACN_POS)) </span></div><div class="line"><a name="l01213"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga4ee98d30bf9a0e21dd13633031751e3e"> 1213</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SDMAIACN_POS               6 </span></div><div class="line"><a name="l01214"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga6009177328c59eda7ec50f752b7814f3"> 1214</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SDMAIACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01216"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#gab86045356fab74e4c40623e2a22aa4fa"> 1216</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_CRYPTOACN_POS              7 </span></div><div class="line"><a name="l01217"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga43523052f57733a45f0a0604e0c9918b"> 1217</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_CRYPTOACN                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01219"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga57eb9d8a442419a699f450d08dfaa266"> 1219</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SDIOACN_POS                8 </span></div><div class="line"><a name="l01220"></a><span class="lineno"><a class="line" href="group__RPU__I2C1__BUS0.html#ga61646cfb590222485af1a64e996b8edf"> 1220</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C1_BUS0_SDIOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C1_BUS0_SDIOACN_POS)) </span></div><div class="line"><a name="l01230"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga15bb6da03053d2898f97f343921e4aa0"> 1230</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_DMA0ACN_POS                0 </span></div><div class="line"><a name="l01231"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gaeb02206d8cb15c02f36c5975e62e1b8a"> 1231</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_DMA0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01233"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga207b3bb834dda0bd4a13770c2d74f72e"> 1233</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_DMA1ACN_POS                1 </span></div><div class="line"><a name="l01234"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gaa982806b5789ddb4e8456c55b6e9daca"> 1234</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_DMA1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01236"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gad3de1508e7bf4c029b9785a2dcad6d87"> 1236</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_USBACN_POS                 2 </span></div><div class="line"><a name="l01237"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga136dfa37289959ec353b3ccaa9e7e539"> 1237</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_USBACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_USBACN_POS)) </span></div><div class="line"><a name="l01239"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga06fae5524cfc8879236f983115a74983"> 1239</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SYS0ACN_POS                3 </span></div><div class="line"><a name="l01240"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gad4809e16d919d97268eb9d6cc7c6513f"> 1240</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SYS0ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01242"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga4432ae0cd4d8193ac2c7efc725b83252"> 1242</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SYS1ACN_POS                4 </span></div><div class="line"><a name="l01243"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga50cd626295e094864ba810f73695d59b"> 1243</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SYS1ACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01245"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gafdb654693cc642a99959e76647dc1e05"> 1245</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SDMADACN_POS               5 </span></div><div class="line"><a name="l01246"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gacb3ef570d578077a2277864570ffd662"> 1246</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SDMADACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_SDMADACN_POS)) </span></div><div class="line"><a name="l01248"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga3d1d7ba602770334602cc21c5c70c538"> 1248</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SDMAIACN_POS               6 </span></div><div class="line"><a name="l01249"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga6e6f78b8c3b8fa6183891327c45d2cc6"> 1249</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SDMAIACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01251"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga99927cb1e769df4a4f06b0a9c3edfa55"> 1251</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_CRYPTOACN_POS              7 </span></div><div class="line"><a name="l01252"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga8742bd146a8ff75f0a40cb738acfa3c4"> 1252</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_CRYPTOACN                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01254"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#gad9db0e57768871d8378df9ed8d062e5a"> 1254</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SDIOACN_POS                8 </span></div><div class="line"><a name="l01255"></a><span class="lineno"><a class="line" href="group__RPU__I2C2__BUS0.html#ga73f3547588984e15449de5a804350b95"> 1255</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_I2C2_BUS0_SDIOACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_I2C2_BUS0_SDIOACN_POS)) </span></div><div class="line"><a name="l01265"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#gaeac4673814cd7ac943bb65ea973cb143"> 1265</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l01266"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga0be60fc17e7a70afd6721300d9bba4fc"> 1266</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_DMA0ACN_POS)) </span></div><div class="line"><a name="l01268"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga39ddb4d39410855ce9d70d3617a6c783"> 1268</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l01269"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#gace8bc746e53d402bf6ec7e7144e75e23"> 1269</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_DMA1ACN_POS)) </span></div><div class="line"><a name="l01271"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga5ae6321447226a8af12d7e3789905f73"> 1271</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_USBACN_POS                    2 </span></div><div class="line"><a name="l01272"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga6ad8555263df5b93594ea87aba51b587"> 1272</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_USBACN_POS)) </span></div><div class="line"><a name="l01274"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga5056fef3a07b57f6619480438e9a5b08"> 1274</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l01275"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#gaf562dd145c4eb0f17284c74be02b9897"> 1275</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_SYS0ACN_POS)) </span></div><div class="line"><a name="l01277"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga67485271573f58ed887e6ac38a5eed9e"> 1277</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l01278"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga3474481d7218a2c961880e7a2ca53820"> 1278</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_SYS1ACN_POS)) </span></div><div class="line"><a name="l01280"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#gac2b9f4545a3cb5548705b38255e75e8e"> 1280</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SDMADACN_POS                  5 </span></div><div class="line"><a name="l01281"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#gad7e81fa2503138a43eaed0a56dec0384"> 1281</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_SDMADACN_POS)) </span></div><div class="line"><a name="l01283"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga9f4c614412a382ad29d87ba32de247e4"> 1283</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l01284"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga992c71a9184c0f473bd8f00140c297a2"> 1284</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_SDMAIACN_POS)) </span></div><div class="line"><a name="l01286"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga05417c33b9865f6a615d959a1da496bd"> 1286</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l01287"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga2b8bdec18aba9c5345f48926e5900542"> 1287</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01289"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#ga92a829ec21c6769a1da90cb124eb16d7"> 1289</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SDIOACN_POS                   8 </span></div><div class="line"><a name="l01290"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFM.html#gae04c2c134a6e369d14e8edacc0b28c8e"> 1290</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFM_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFM_SDIOACN_POS)) </span></div><div class="line"><a name="l01300"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gaad3590f193b6e540af3755deaf902aea"> 1300</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_DMA0ACN_POS                   0 </span></div><div class="line"><a name="l01301"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gacd1486a1d036da55f438e950e5069eac"> 1301</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_DMA0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_DMA0ACN_POS)) </span></div><div class="line"><a name="l01303"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gabbe5f0dac75788a07f791675b70c7c21"> 1303</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_DMA1ACN_POS                   1 </span></div><div class="line"><a name="l01304"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga911b4a2d9665b193e4b7aef92eb1e1b6"> 1304</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_DMA1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_DMA1ACN_POS)) </span></div><div class="line"><a name="l01306"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga20687d2684d69f967ba3eb04069c2100"> 1306</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_USBACN_POS                    2 </span></div><div class="line"><a name="l01307"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga607cec1a54144b03f89e8d7039d9ce0f"> 1307</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_USBACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_USBACN_POS)) </span></div><div class="line"><a name="l01309"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga617b6ffc6a85bbd79902a5a19b13c31c"> 1309</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SYS0ACN_POS                   3 </span></div><div class="line"><a name="l01310"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gaed38f596f8e4c685b08a0c357cf2023a"> 1310</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SYS0ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_SYS0ACN_POS)) </span></div><div class="line"><a name="l01312"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga56d28979875ef8a098213cd8e7b7101c"> 1312</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SYS1ACN_POS                   4 </span></div><div class="line"><a name="l01313"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gabc27d836a6f88c6e0a24fabba090af31"> 1313</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SYS1ACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_SYS1ACN_POS)) </span></div><div class="line"><a name="l01315"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gaad08cabd24850ee44f3d4be39aac6b8a"> 1315</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SDMADACN_POS                  5 </span></div><div class="line"><a name="l01316"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga8c68f269da1c0973099bab100cc49735"> 1316</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SDMADACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_SDMADACN_POS)) </span></div><div class="line"><a name="l01318"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga618fec52dafc363b5d80fc1469eec522"> 1318</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SDMAIACN_POS                  6 </span></div><div class="line"><a name="l01319"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga0c54d7d92d9834426da9bcc01e1c4055"> 1319</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SDMAIACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_SDMAIACN_POS)) </span></div><div class="line"><a name="l01321"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga78f84fe5a70182da18c78e2dd80d47d9"> 1321</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_CRYPTOACN_POS                 7 </span></div><div class="line"><a name="l01322"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gaf3075cb47dce0339a19a3fa48b6cff1c"> 1322</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_CRYPTOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01324"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#gabe219c300a03dc5fae9828d3c20fa2cc"> 1324</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SDIOACN_POS                   8 </span></div><div class="line"><a name="l01325"></a><span class="lineno"><a class="line" href="group__RPU__SPIXFC.html#ga0b41778c5276eb4c295a446cd1e6e439"> 1325</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXFC_SDIOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXFC_SDIOACN_POS)) </span></div><div class="line"><a name="l01335"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaaac30a92418dc6b8a994a0b4e4cbd1e0"> 1335</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01336"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaa072bec83f56706b4024cda91e6c8cc0"> 1336</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01338"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gacff6b95c9815e786960623252d9b9071"> 1338</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01339"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga39714c9edf98bb6562368dfdec4b1a16"> 1339</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01341"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga4cc8a106385ce0bd2ded879af432216a"> 1341</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_USBACN_POS                      2 </span></div><div class="line"><a name="l01342"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga6257eab00fd2c882f129a9913847ca86"> 1342</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_USBACN_POS)) </span></div><div class="line"><a name="l01344"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga44be5d94765c607470bc69558159bf84"> 1344</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01345"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gab3eb118a820424bf722bbe0c6d069c7a"> 1345</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01347"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaf0aa86ee311f767b60eb1eeefc76dd04"> 1347</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01348"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga6cb40140bb0bbef7f5c3618305a83cc7"> 1348</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01350"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga3b32064707683b554534ec2f5e515c31"> 1350</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01351"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga7f44a7929a23fc2e2bc80cf1abd89da9"> 1351</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SDMADACN_POS)) </span></div><div class="line"><a name="l01353"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga8dd41e25f4cfd14ed40259c62752dd13"> 1353</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01354"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#ga8cfa5b0fdbed7f5c96a9a303a384a47e"> 1354</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01356"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaaae657c5e6d1520064298045dfa5311d"> 1356</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01357"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaef76eea2e0e85c6750ecc24478097f35"> 1357</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01359"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaff2b33395677f6e2281d5cf65c3aa4b7"> 1359</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01360"></a><span class="lineno"><a class="line" href="group__RPU__DMA0.html#gaf2ff1a705aa4a4dd9e7b7ef4c2bbd8ff"> 1360</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA0_SDIOACN_POS)) </span></div><div class="line"><a name="l01370"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga0d250b554193a0d57f0e62d63be440dd"> 1370</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01371"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga1e49c14ffcaba30bc1a14176213cac75"> 1371</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01373"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga4d9d6df5ca77135cbc7943a6c8cc5f39"> 1373</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01374"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#gad338eb72bdafb8ce48cf37c81ab553a1"> 1374</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01376"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga38982917eb333ef90000d735dea48ead"> 1376</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_USBACN_POS                      2 </span></div><div class="line"><a name="l01377"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga3ea22a69095779bdd25d389004e33743"> 1377</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_USBACN_POS)) </span></div><div class="line"><a name="l01379"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga9cb71197ed95733ddc5a73b22e1bb5d9"> 1379</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01380"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#gab2555af18790432df380966e668d235a"> 1380</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01382"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga8c4efafca2aa49e4f50b482a8b6dc4b5"> 1382</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01383"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga9e0a8bafccf0ecc3112b1f4e12f77a34"> 1383</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01385"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga90a92f715126046d8466ec783a978e06"> 1385</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01386"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga2b2ab5335365fa64f291e864af2baefc"> 1386</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SDMADACN_POS)) </span></div><div class="line"><a name="l01388"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga0fe9606419f294f7e10b684e1772399a"> 1388</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01389"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga4a2798163095e8eb618b9f7943ec6199"> 1389</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01391"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga1774245cfdc9097cdf293d1a146a9ee1"> 1391</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01392"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga62be6a54525bc94528bb38afc1da8993"> 1392</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01394"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#ga0b19160276cddb01fc5cb1351f845193"> 1394</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01395"></a><span class="lineno"><a class="line" href="group__RPU__FLC0.html#gaba940b1bf7c68cd22710ff453874a9f6"> 1395</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC0_SDIOACN_POS)) </span></div><div class="line"><a name="l01405"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga9e71d13c36a918630ea5513a4eaf7b67"> 1405</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01406"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga4da14dac3bbd913f7817fa4465cc3feb"> 1406</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01408"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga6cb43ab8a3a65bee299dde641f81bb33"> 1408</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01409"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga2158e80541f33bc29a78e183f05be3e4"> 1409</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01411"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gaf4a3aa53bbe8f54be86eed324a1f5f06"> 1411</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_USBACN_POS                      2 </span></div><div class="line"><a name="l01412"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga63f3535ec4b7c0df9637fc0c7a9bc5f7"> 1412</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_USBACN_POS)) </span></div><div class="line"><a name="l01414"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga93610f5e8de8f84db7ec15d61c8d0e94"> 1414</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01415"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga928c96df4296255ed9112be9e2e4844a"> 1415</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01417"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga167b22530aca9c15261bd709a4b1bc8c"> 1417</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01418"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gaa990eab68b110b8dc7a479c167ba7bae"> 1418</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01420"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga00aca77c11c7f2b9e9cfef0cb6c07cf5"> 1420</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01421"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gaf10a0446e0e869266d0897ccdc220655"> 1421</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SDMADACN_POS)) </span></div><div class="line"><a name="l01423"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga7d68d92ff0bad4cc72c6fcfdc493998f"> 1423</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01424"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga6b07f10878bc57e3697a3d88b84f35a7"> 1424</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01426"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga8eed358f70642c60964178435b5098ab"> 1426</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01427"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#gac5f1220fb91df2ddab070e4ded809daa"> 1427</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01429"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga4b4ed47f882b81512ec0e9b9107a9ca4"> 1429</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01430"></a><span class="lineno"><a class="line" href="group__RPU__FLC1.html#ga55befb13e027b35f4b50860a4c50200e"> 1430</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_FLC1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_FLC1_SDIOACN_POS)) </span></div><div class="line"><a name="l01440"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga78c5fa6d56d8f3943e1c048e55405ab8"> 1440</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01441"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga6b0e688ccaaff1b302ac65f45938f2c0"> 1441</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01443"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga5f0b13bb5c9a1cba55e09e468db9856c"> 1443</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01444"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#gaada05de5c78bea35986dcf48404cf89e"> 1444</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01446"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#gab559859eb6cdf4ee2c0b2eea61e50708"> 1446</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_USBACN_POS                      2 </span></div><div class="line"><a name="l01447"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga3fa139f746abd8be5feb73c4374d25e6"> 1447</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_USBACN_POS)) </span></div><div class="line"><a name="l01449"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga5b5d8ecae248913283c2b00772e0697b"> 1449</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01450"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga51df876ab31d007437bd79c55a16c9ef"> 1450</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01452"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga3a2bd8f54d2a1e714f0eb6ee5f7df3d0"> 1452</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01453"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga92961ef458c2c2c7b5ec85e709c90b82"> 1453</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01455"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga10a3ffb2f8671c73ff30b5f26f8afbca"> 1455</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01456"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga7f8c1a9fb6dff5e888df669311ca5a67"> 1456</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_SDMADACN_POS)) </span></div><div class="line"><a name="l01458"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#gae6ed75ec17b51f36312118dae98c2817"> 1458</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01459"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga83723a9d5012578b9b2dbd9a26eb6fb1"> 1459</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01461"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga7615136806e79b7c23fb7fb38013e00a"> 1461</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01462"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga976521a3acd7c87dc3e7b881dfaaf023"> 1462</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01464"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#ga6ed37d0e7cb1fd6a7146340f2b0b4238"> 1464</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01465"></a><span class="lineno"><a class="line" href="group__RPU__ICC0.html#gad8c862406038a17a1d361d2dac12668a"> 1465</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC0_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC0_SDIOACN_POS)) </span></div><div class="line"><a name="l01475"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga1cd7ede13811daa8de5fd1082e9eef91"> 1475</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01476"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gafa0ca2046cf0d822da20e3caedb5dc7a"> 1476</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01478"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gab5a33683cfbc86acfc0824487b1ffa3f"> 1478</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01479"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gafad8fef0d41361b0d4396018c49185aa"> 1479</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01481"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gaf8cb67c13bb93e9dfd013d847095d714"> 1481</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_USBACN_POS                      2 </span></div><div class="line"><a name="l01482"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gad5caa54679631fc424c2bdd49253ac39"> 1482</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_USBACN_POS)) </span></div><div class="line"><a name="l01484"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga27f8f56f10a5a3583dd39bd8d97b64bb"> 1484</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01485"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gaac44a9d69288b935d0b090c44624853a"> 1485</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01487"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga672e18eb27eb3b6fd4baa75675f3b83d"> 1487</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01488"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga4ec9d72e49726fc5d629bd0339c3ad0d"> 1488</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01490"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga04893041a5b832c4728a75f33df7e198"> 1490</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01491"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gac03a3bfd7abb3d2e040f7795430c7019"> 1491</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_SDMADACN_POS)) </span></div><div class="line"><a name="l01493"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga35fb004e18b31b71db377845c0739676"> 1493</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01494"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga7e3c35d601361b00d76f5b45862f9c67"> 1494</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01496"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga63af9f2c949ec0b1d19137105be66a45"> 1496</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01497"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#gaa3407cc27796cd871552173b77bc1293"> 1497</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01499"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga736522da18feb979141d0d1a04acc994"> 1499</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01500"></a><span class="lineno"><a class="line" href="group__RPU__ICC1.html#ga2096275d1633379a58f4fce61e967042"> 1500</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ICC1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ICC1_SDIOACN_POS)) </span></div><div class="line"><a name="l01510"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#gacad29d26f5b37eaed5921083d38c5738"> 1510</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01511"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga8d3b248dc0f85e5f5b7619a7fc95e6ee"> 1511</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_DMA0ACN_POS)) </span></div><div class="line"><a name="l01513"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga4f4a4d1f1553efc440ffafd891c1e082"> 1513</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01514"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga730e7862df54ce688f024d9f5bf48dd9"> 1514</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_DMA1ACN_POS)) </span></div><div class="line"><a name="l01516"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga06ba83f0cdf686fa77e463616f045ebd"> 1516</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_USBACN_POS                      2 </span></div><div class="line"><a name="l01517"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga80b29c451ce28fe5f17ecd8e54e9a31a"> 1517</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_USBACN_POS)) </span></div><div class="line"><a name="l01519"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#gaf9a1c76fa2586a6e8f8c7696e316f82c"> 1519</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01520"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga680548f12d0eb1f7a221e14b09f99474"> 1520</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_SYS0ACN_POS)) </span></div><div class="line"><a name="l01522"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga8f91f9dc65291d1fe434641c97fe07a4"> 1522</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01523"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga0eb6a39d25bf873055892e862ca3c42d"> 1523</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_SYS1ACN_POS)) </span></div><div class="line"><a name="l01525"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga2076040e8818bb924048192cde352962"> 1525</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01526"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga8fe54427783138936cb075ec339c7c08"> 1526</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_SDMADACN_POS)) </span></div><div class="line"><a name="l01528"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga0570bfc9b1e2b00d3f20ea4275a53025"> 1528</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01529"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga27fd25000f3df90f36fd136289e56370"> 1529</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_SDMAIACN_POS)) </span></div><div class="line"><a name="l01531"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#gae6a9ac1cf69e84f28cf4523f7ac6d81d"> 1531</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01532"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga984bb3347b32bc8c986341e588657ceb"> 1532</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01534"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#gaed5ef6e59481c59c81dff9fd92984c40"> 1534</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01535"></a><span class="lineno"><a class="line" href="group__RPU__SFCC.html#ga01aa6f0f57201416def85a43b499c853"> 1535</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SFCC_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SFCC_SDIOACN_POS)) </span></div><div class="line"><a name="l01545"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gac7155ac7c2e1357ec0be71f1952777c9"> 1545</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01546"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gada58af7c8cd2dabd99de522baa3c940e"> 1546</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_DMA0ACN_POS)) </span></div><div class="line"><a name="l01548"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga4eb29f34163cf00a894c3d751b3ce189"> 1548</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01549"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga5aed4d9c9b88b0dca6d6164a6e7f784f"> 1549</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_DMA1ACN_POS)) </span></div><div class="line"><a name="l01551"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga851b998cba8acc3f136fb72873b7100b"> 1551</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_USBACN_POS                      2 </span></div><div class="line"><a name="l01552"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga47feef03ef3c31a3bb666534de928a5c"> 1552</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_USBACN_POS)) </span></div><div class="line"><a name="l01554"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gaee4bcfbb2d45d684184f978414aac1bc"> 1554</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01555"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gaf67d5d2688d9b8969986a9189a004af3"> 1555</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_SYS0ACN_POS)) </span></div><div class="line"><a name="l01557"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga1b4cdddd046b2b9cd749dcccedbdee20"> 1557</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01558"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gaf06d05e784f71b0c4eafd790babff6f0"> 1558</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_SYS1ACN_POS)) </span></div><div class="line"><a name="l01560"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga94f54a8b3646b1fda8831c1b43ca56f2"> 1560</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01561"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gaec596668570ced5c69271f47180e6790"> 1561</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_SDMADACN_POS)) </span></div><div class="line"><a name="l01563"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga3c46cea865414c8e60223947f7335029"> 1563</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01564"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga5f5a1588cce93237b0e811c46909596d"> 1564</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_SDMAIACN_POS)) </span></div><div class="line"><a name="l01566"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga8edbfc30eacace048abbb40cd09a584c"> 1566</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01567"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#gad3022f0939c58a7a5f7c08d902e538de"> 1567</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01569"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga6739f44c605c0cf1fbdac735c2412f60"> 1569</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01570"></a><span class="lineno"><a class="line" href="group__RPU__SRCC.html#ga68283ab42283d6b77d57bda695ccbac3"> 1570</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SRCC_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SRCC_SDIOACN_POS)) </span></div><div class="line"><a name="l01580"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga4a63de0cff3c784eca45c1aebd9b218a"> 1580</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l01581"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1c74857d1228d21abc8a820bb72b875c"> 1581</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_DMA0ACN_POS)) </span></div><div class="line"><a name="l01583"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaeb7eb1d76872a891f625c0c796fc8d8c"> 1583</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l01584"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga4090ebff75b5910127269d8f99ee8abc"> 1584</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_DMA1ACN_POS)) </span></div><div class="line"><a name="l01586"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga969d966cc08321e8b45449d2f4a15213"> 1586</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_USBACN_POS                       2 </span></div><div class="line"><a name="l01587"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1b73be95926164f95a7e8a302ce498b0"> 1587</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_USBACN_POS)) </span></div><div class="line"><a name="l01589"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga3c864f51da69c7101cb1b60c5b3932ec"> 1589</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l01590"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1be8a306010797f8a84db0cead233579"> 1590</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SYS0ACN_POS)) </span></div><div class="line"><a name="l01592"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga86d628f98f5bdf7960252e111ceb9f1e"> 1592</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l01593"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga1dd91386eed8ff271a3833162ff6940a"> 1593</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SYS1ACN_POS)) </span></div><div class="line"><a name="l01595"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga7c2fce49a79e8a05cde2c3af74b719ec"> 1595</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMADACN_POS                     5 </span></div><div class="line"><a name="l01596"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaa898066d1a710d726bd6b36f7bad086f"> 1596</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SDMADACN_POS)) </span></div><div class="line"><a name="l01598"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gadb2d4ff8f4aaa8411648507a200bb1f0"> 1598</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l01599"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaaf041858322fbe68e25ca2bab52d95a5"> 1599</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SDMAIACN_POS)) </span></div><div class="line"><a name="l01601"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gabaecc29d86cf20f18ffef4ae57b9d567"> 1601</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l01602"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaa04688c6dc467e91da34070ef2e8af82"> 1602</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01604"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#gaec9307fa1ebca5f4a4819729d7cf85f0"> 1604</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDIOACN_POS                      8 </span></div><div class="line"><a name="l01605"></a><span class="lineno"><a class="line" href="group__RPU__ADC.html#ga8dc0742fda2d083bde7d76d4c9d6525f"> 1605</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_ADC_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_ADC_SDIOACN_POS)) </span></div><div class="line"><a name="l01615"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga596be1b3796470725e1f1a936bd15220"> 1615</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01616"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga5d787c96810f5feb7fb96a75e88cb47d"> 1616</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01618"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga39c93098920ebd3fb49fd1dd6d0e05c6"> 1618</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01619"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga918f9277b1b0e7d1ba8ba93100d5378d"> 1619</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01621"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga89b7e89b990f15b9e5871fe97fc513f0"> 1621</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_USBACN_POS                      2 </span></div><div class="line"><a name="l01622"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gad6c1e07a30266ad07a8cba19fb0d8b3b"> 1622</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_USBACN_POS)) </span></div><div class="line"><a name="l01624"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga7601eaec0ee69e089266fbc4155536bb"> 1624</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01625"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gaa048f632a320996be790247075f4357c"> 1625</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01627"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gac02a9fc8e5b1d5b0801ed13d50d4bcee"> 1627</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01628"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gafc33c6f25d48b485fb62bd66e684c041"> 1628</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01630"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga7de7ba09798b9dc13f785e6634442cc3"> 1630</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01631"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga259735da1778d9e7822169eda5606340"> 1631</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SDMADACN_POS)) </span></div><div class="line"><a name="l01633"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga35f418023bde9dddeb36729157f4fefb"> 1633</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01634"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga879b8aa5d57bc9e0ecd6dd9acb3ff530"> 1634</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01636"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gaba5a75511874477669f2d57e0cc927b6"> 1636</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01637"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga450a3dea8838b14c0f59daa4501d812a"> 1637</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01639"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#ga83aeaa9a9a86234526a5c05345558b28"> 1639</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01640"></a><span class="lineno"><a class="line" href="group__RPU__DMA1.html#gaf296c345707b1da22d834b49db286645"> 1640</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_DMA1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_DMA1_SDIOACN_POS)) </span></div><div class="line"><a name="l01650"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga9e4db568a0ee380e49f2cd42dbe4645c"> 1650</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01651"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga9d0c8fdbd4aa9d8784ab3fd44dab2361"> 1651</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_DMA0ACN_POS)) </span></div><div class="line"><a name="l01653"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga2686f683f00112d193d9a539b3b62c70"> 1653</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01654"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gab9e870affb0a8e99b945390af4d52f18"> 1654</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_DMA1ACN_POS)) </span></div><div class="line"><a name="l01656"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga98f55aee810176d44cceef96193464a2"> 1656</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_USBACN_POS                      2 </span></div><div class="line"><a name="l01657"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7a7b0af8cf6ed9741b22825497b03745"> 1657</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_USBACN_POS)) </span></div><div class="line"><a name="l01659"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga50c25de38da8d036f87d774be7a6005c"> 1659</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01660"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gada1ce0639775ab7c5e6d2faa83cf6bb4"> 1660</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SYS0ACN_POS)) </span></div><div class="line"><a name="l01662"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gaf5240aa575d4585be1adad3e00336c5c"> 1662</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01663"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7047287dc06f86e50b028dfffbbaa2f6"> 1663</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SYS1ACN_POS)) </span></div><div class="line"><a name="l01665"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga032c8f95c4c24e892e1ff5bd970cda51"> 1665</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01666"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gadbd2b6b5523eae1f7b5de6deb396c4b6"> 1666</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SDMADACN_POS)) </span></div><div class="line"><a name="l01668"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gad8532f6b6a4e1b1c1b629396c9e08a75"> 1668</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01669"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga262290f224eb130208e998f4f176e2bb"> 1669</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SDMAIACN_POS)) </span></div><div class="line"><a name="l01671"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gac5c52f44acd1161733be694da9850e45"> 1671</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01672"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#gaab7f883f4ddcbce67d884b61fce5ed73"> 1672</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01674"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7b1e32fca99bc9642f3f67a7a67abc33"> 1674</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01675"></a><span class="lineno"><a class="line" href="group__RPU__SDMA.html#ga7c3b62d4736acb88a62d1f7bbba171f1"> 1675</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDMA_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDMA_SDIOACN_POS)) </span></div><div class="line"><a name="l01685"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gad5de5c91ea21a84582aa2e59ac0b34f2"> 1685</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA0ACN_POS                 0 </span></div><div class="line"><a name="l01686"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga05e6d8504501cc9a55df6dd9df054d51"> 1686</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_DMA0ACN_POS)) </span></div><div class="line"><a name="l01688"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaa3d10ad11f2c3c3364ef3b7928be2e02"> 1688</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA1ACN_POS                 1 </span></div><div class="line"><a name="l01689"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga6e1c77b14e6db5cfa2bccc470c45ae94"> 1689</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_DMA1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_DMA1ACN_POS)) </span></div><div class="line"><a name="l01691"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gab8f97a51c5c270e7805285c4f96b60b9"> 1691</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_USBACN_POS                  2 </span></div><div class="line"><a name="l01692"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga95b2c653a5d0fa7d35a3ac034c154cd1"> 1692</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_USBACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_USBACN_POS)) </span></div><div class="line"><a name="l01694"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gac4e7196e88e5186873681c870694ecd6"> 1694</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS0ACN_POS                 3 </span></div><div class="line"><a name="l01695"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaafa07d905c0c318cdfad51c63d4cddbb"> 1695</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SYS0ACN_POS)) </span></div><div class="line"><a name="l01697"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga28df6903b92f1d5239d93b570f27ddef"> 1697</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS1ACN_POS                 4 </span></div><div class="line"><a name="l01698"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga68b43247d6dca24ccacdbaa9453fd3a8"> 1698</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SYS1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SYS1ACN_POS)) </span></div><div class="line"><a name="l01700"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gab9ddfbe2ae13a16829a041808c0f1b50"> 1700</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMADACN_POS                5 </span></div><div class="line"><a name="l01701"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga55961a126882b20e699f927184806180"> 1701</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMADACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SDMADACN_POS)) </span></div><div class="line"><a name="l01703"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gad6f86438c38cab6fe23aaa6d16a73aa6"> 1703</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMAIACN_POS                6 </span></div><div class="line"><a name="l01704"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaa0609e9ead17b162e0bde52c3fbea3c1"> 1704</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDMAIACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SDMAIACN_POS)) </span></div><div class="line"><a name="l01706"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gad776c64b800b8d752ee3fe748a876088"> 1706</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_CRYPTOACN_POS               7 </span></div><div class="line"><a name="l01707"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga8533b460a44986e2f1fc3ec4bd2a13a0"> 1707</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_CRYPTOACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01709"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#ga122038524b3351fb39588b2e83219f02"> 1709</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDIOACN_POS                 8 </span></div><div class="line"><a name="l01710"></a><span class="lineno"><a class="line" href="group__RPU__SDHCCTRL.html#gaad9e9b1cbe2bad1ece794af25d1bcfab"> 1710</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDHCCTRL_SDIOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDHCCTRL_SDIOACN_POS)) </span></div><div class="line"><a name="l01720"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gae530a9d2c6bc6c335192088970b2c739"> 1720</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01721"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga0dd5ec9057d8816d777eae17481bf168"> 1721</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_DMA0ACN_POS)) </span></div><div class="line"><a name="l01723"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gaeb58c24e428362debfffcf001f190f85"> 1723</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01724"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga53b3880fafc88af82cb845decc37e558"> 1724</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_DMA1ACN_POS)) </span></div><div class="line"><a name="l01726"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga8a0c4edee2bb88cb0ebf4c757ca6fec8"> 1726</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_USBACN_POS                     2 </span></div><div class="line"><a name="l01727"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga385389b29eb71d8546f183aee74e13ab"> 1727</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_USBACN_POS)) </span></div><div class="line"><a name="l01729"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga47ba639eade3778abb1cb030414bacbb"> 1729</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01730"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga0a834fb5719894bf020b835228aeac3e"> 1730</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_SYS0ACN_POS)) </span></div><div class="line"><a name="l01732"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gac76478a9bc542fc65a46ad082a129959"> 1732</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01733"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga58b212a3ca5cf5d5f7f87860df2ecdf7"> 1733</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_SYS1ACN_POS)) </span></div><div class="line"><a name="l01735"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gaadf3743337d6c4df541537600185a8ab"> 1735</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01736"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga11a2c1e0e447ee1ea5a5010cc8fd4a22"> 1736</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_SDMADACN_POS)) </span></div><div class="line"><a name="l01738"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga85530bc19004771dd32f4e32ab3e6a20"> 1738</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01739"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gaf680abbc13ef604c0f80791fee7722fd"> 1739</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_SDMAIACN_POS)) </span></div><div class="line"><a name="l01741"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gaa861e2a52c3ca5d7c39224179d44be16"> 1741</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01742"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#gadf6b38a782f8acc890b2a3f5f9dba315"> 1742</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01744"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga159032df3d2c6968d42ff0ca0fe16661"> 1744</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01745"></a><span class="lineno"><a class="line" href="group__RPU__SPIXR.html#ga2b779ba0f2fb3fc36bb7326f70d29fdc"> 1745</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXR_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXR_SDIOACN_POS)) </span></div><div class="line"><a name="l01755"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#gae4cc810f5b673d7b7598393cc3d6afcd"> 1755</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_DMA0ACN_POS                 0 </span></div><div class="line"><a name="l01756"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga98c67d4f1384e2917a2be3867f919021"> 1756</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_DMA0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01758"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga2201327d23e5de7e44387bdbca36a6fb"> 1758</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_DMA1ACN_POS                 1 </span></div><div class="line"><a name="l01759"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#gade5f0e0ad2054208f351bf886c3bc343"> 1759</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_DMA1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01761"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga2e13e520b38d803bc5a5393a696b43e1"> 1761</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_USBACN_POS                  2 </span></div><div class="line"><a name="l01762"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#gaebe032b4061021cd0afcd1781559a878"> 1762</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_USBACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_USBACN_POS)) </span></div><div class="line"><a name="l01764"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga8dc2bc55a8c39ed2ea5507f53e896cc5"> 1764</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SYS0ACN_POS                 3 </span></div><div class="line"><a name="l01765"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga4505a9a805cf94539f49a9b970cf69d3"> 1765</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SYS0ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01767"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga099c4d3fd1bc4c7bbe700bd3aea83260"> 1767</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SYS1ACN_POS                 4 </span></div><div class="line"><a name="l01768"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga5ddd4938860b9900a29a18f63b7740ab"> 1768</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SYS1ACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01770"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga1198bd6462072ad4e07ab8946de4ff8a"> 1770</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SDMADACN_POS                5 </span></div><div class="line"><a name="l01771"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga0e7f7fe593f13340953d8deb2ea14d30"> 1771</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SDMADACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_SDMADACN_POS)) </span></div><div class="line"><a name="l01773"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga9d0ee81745a5e4463dfdee2724e54258"> 1773</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SDMAIACN_POS                6 </span></div><div class="line"><a name="l01774"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga41ca5f70090e4f15fef126af16e82fd6"> 1774</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SDMAIACN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01776"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga9ebd7fa118317badf5af0282455f79ba"> 1776</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_CRYPTOACN_POS               7 </span></div><div class="line"><a name="l01777"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga2b7b228653a8d74d0dc64e5cdf16dded"> 1777</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_CRYPTOACN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01779"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#gaf549f7e8bc510e4aa385f7eb0c189880"> 1779</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SDIOACN_POS                 8 </span></div><div class="line"><a name="l01780"></a><span class="lineno"><a class="line" href="group__RPU__PTG__BUS0.html#ga045d6319cbf95ba62b42789984045fbe"> 1780</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_PTG_BUS0_SDIOACN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_PTG_BUS0_SDIOACN_POS)) </span></div><div class="line"><a name="l01790"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#gacf0ffa1f074dfb058db0f5c7303b2ffc"> 1790</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA0ACN_POS                      0 </span></div><div class="line"><a name="l01791"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga3b82b473679baa026cb6e52ef0b44e59"> 1791</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_DMA0ACN_POS)) </span></div><div class="line"><a name="l01793"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga8ebf386f7d4eea8632060874e64d07c8"> 1793</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA1ACN_POS                      1 </span></div><div class="line"><a name="l01794"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga169c5a108c7b8469b39f28c1137ef1e1"> 1794</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_DMA1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_DMA1ACN_POS)) </span></div><div class="line"><a name="l01796"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga562a29e3664558c4f642253c0c0ad9af"> 1796</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_USBACN_POS                       2 </span></div><div class="line"><a name="l01797"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga6654b679741d53197bf672c4b5ac0e9c"> 1797</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_USBACN                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_USBACN_POS)) </span></div><div class="line"><a name="l01799"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga5adc4da10831d4bb624387b2f893b281"> 1799</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS0ACN_POS                      3 </span></div><div class="line"><a name="l01800"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga354d50fa0c2386f3911fa191f7f15cb9"> 1800</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS0ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SYS0ACN_POS)) </span></div><div class="line"><a name="l01802"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga8ad9ed4b7fd5f844e75ffe8231424584"> 1802</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS1ACN_POS                      4 </span></div><div class="line"><a name="l01803"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga40d3122d9fbf1dc215f6b14859331d7a"> 1803</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SYS1ACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SYS1ACN_POS)) </span></div><div class="line"><a name="l01805"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#gaf4a9226601db132059c4b4dd87a38ca1"> 1805</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMADACN_POS                     5 </span></div><div class="line"><a name="l01806"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga987a2cb401253f19339a1e46ffcfe850"> 1806</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMADACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SDMADACN_POS)) </span></div><div class="line"><a name="l01808"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga485ebafd212ca01976ef0d681939e220"> 1808</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMAIACN_POS                     6 </span></div><div class="line"><a name="l01809"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#gac0d9d8abf26182776fd42bd105fba49c"> 1809</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDMAIACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SDMAIACN_POS)) </span></div><div class="line"><a name="l01811"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga7245d8df0d9fcda03c38506268cd9cf7"> 1811</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_CRYPTOACN_POS                    7 </span></div><div class="line"><a name="l01812"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga94c0561f48ada11ae54021149b325b2e"> 1812</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_CRYPTOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01814"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga12393078f2ecdcd023eb9de651d23682"> 1814</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDIOACN_POS                      8 </span></div><div class="line"><a name="l01815"></a><span class="lineno"><a class="line" href="group__RPU__OWM.html#ga210735e35fe23579f0c5d93d3c0285f3"> 1815</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_OWM_SDIOACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_OWM_SDIOACN_POS)) </span></div><div class="line"><a name="l01825"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gad839e6656bcfa864acb5b923bf86e597"> 1825</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01826"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gadc225d8fb33d684120fbcfd1dcf0a0cf"> 1826</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_DMA0ACN_POS)) </span></div><div class="line"><a name="l01828"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga3601eb8bf270d822166ed7c3e5aba13c"> 1828</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01829"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga40be1fa2a460bbe958a98808bfc64c85"> 1829</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_DMA1ACN_POS)) </span></div><div class="line"><a name="l01831"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gacd2a5d6215fb39441524822cd37a1570"> 1831</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_USBACN_POS                      2 </span></div><div class="line"><a name="l01832"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga2dfcf705a51f8da27c3fb26af521c001"> 1832</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_USBACN_POS)) </span></div><div class="line"><a name="l01834"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga587a0885cf30ebddc88af549a911330b"> 1834</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01835"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga48d7f36747f0c548673aec48d8dbbfe3"> 1835</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SYS0ACN_POS)) </span></div><div class="line"><a name="l01837"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gaf5e849609b45fac19f0591625723f9bd"> 1837</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01838"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#gaf553f80ed0e2a02388a4a28d054e90ec"> 1838</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SYS1ACN_POS)) </span></div><div class="line"><a name="l01840"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga18422e3e08ab661c93c766f207dd0eca"> 1840</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01841"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga33b90180db00a2f3eae25528ec57fa1d"> 1841</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SDMADACN_POS)) </span></div><div class="line"><a name="l01843"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga68b32a99ebc64348211fbdb7cd4425d6"> 1843</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01844"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga63fb375b59c7dad6ec6f4a70de0cc67f"> 1844</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SDMAIACN_POS)) </span></div><div class="line"><a name="l01846"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga151bbc937135ddecb0fb701e3fe6259a"> 1846</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01847"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga127aec806999623d2bdc624e5c35aada"> 1847</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01849"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga460ae167213cffb2623ed99de41498b3"> 1849</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01850"></a><span class="lineno"><a class="line" href="group__RPU__SEMA.html#ga06e711476fadb3e483d85b04121aacb8"> 1850</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SEMA_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SEMA_SDIOACN_POS)) </span></div><div class="line"><a name="l01860"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gac91a10f54ce8ca670dd985e70c792f60"> 1860</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01861"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga259231c9fdc4ee5742ca4790663aef98"> 1861</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_DMA0ACN_POS)) </span></div><div class="line"><a name="l01863"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga5f4898e494ac7114e1fe37b9770c49c5"> 1863</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01864"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gac573088d6bc80992f2954adfc3c1fd06"> 1864</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_DMA1ACN_POS)) </span></div><div class="line"><a name="l01866"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga4ef2dab23320eb30070b8aae40e118fc"> 1866</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_USBACN_POS                     2 </span></div><div class="line"><a name="l01867"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga58606600b22c9a8af7b0c3a30f6a9270"> 1867</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_USBACN_POS)) </span></div><div class="line"><a name="l01869"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gabc70702897811f9fed5c7c720c39d7a1"> 1869</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01870"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga3244c065baba0c2c4f2266fede5a6394"> 1870</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SYS0ACN_POS)) </span></div><div class="line"><a name="l01872"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gae893b5d1213e1e94a24c9b56ed26a39b"> 1872</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01873"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gab2d75648fcc1b1054b59cab44adf5bff"> 1873</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SYS1ACN_POS)) </span></div><div class="line"><a name="l01875"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gac66a3f1fdcf74768933c415610bc1aea"> 1875</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01876"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga58132e72fcf3d6524e2eeb6221a2e133"> 1876</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SDMADACN_POS)) </span></div><div class="line"><a name="l01878"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gae3a485e9b25a902296acb37735b3919b"> 1878</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01879"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga96283394db993675cd0554c5f2aba21e"> 1879</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SDMAIACN_POS)) </span></div><div class="line"><a name="l01881"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga1d03a9fb644e7d0a4773cb7b43e05db8"> 1881</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01882"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga420a8893e5c8e66ff47d7c42e6dc6711"> 1882</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01884"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#gaa343cea179696abf1cd95405567fa7d9"> 1884</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01885"></a><span class="lineno"><a class="line" href="group__RPU__UART0.html#ga5a0bf04464ab4a155810e9f73cd14441"> 1885</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART0_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART0_SDIOACN_POS)) </span></div><div class="line"><a name="l01895"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gaaf7f45ffaf6b32bcf63756fa7e9ca029"> 1895</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01896"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gab8f6dee986f45d564e532a8ad9ff46ea"> 1896</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01898"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga983d82baec14eb71ec044517f48bf48a"> 1898</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01899"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga5510d182bd23dd06c379b9c1a6faed0b"> 1899</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01901"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga8e0305f6bf9d0965a62ac8ca6a5d867e"> 1901</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_USBACN_POS                     2 </span></div><div class="line"><a name="l01902"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gae89423f07dd7ab2e234a0e9470d9a954"> 1902</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_USBACN_POS)) </span></div><div class="line"><a name="l01904"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gaa9dbf33fea2ff661315ee1c18aead88b"> 1904</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01905"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga4ec63d315e71cd78e5725034cd60e506"> 1905</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01907"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga7d87b9929add9b3b823962040cbfc463"> 1907</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01908"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gab29c0859582767a4ce4d5e2a21b53be8"> 1908</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01910"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga7d1cd1000b3c7a558b2c438126b14d35"> 1910</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01911"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gaa40054936c85ab383e16c553ac69b671"> 1911</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SDMADACN_POS)) </span></div><div class="line"><a name="l01913"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga534270a51f1c683816e22b9c9b8550c3"> 1913</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01914"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gae31eb68280ae161f9b3d359ed1d6c958"> 1914</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01916"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#gabcd0d9555a00bc1eeacd730158d63ed6"> 1916</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01917"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga44cdff4aaf5d09f8eba112d65fad5f82"> 1917</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01919"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga34cf0f514b57fb2eca440ce077c62c24"> 1919</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01920"></a><span class="lineno"><a class="line" href="group__RPU__UART1.html#ga95c875794d87305bea54368f6e97dbb7"> 1920</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART1_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART1_SDIOACN_POS)) </span></div><div class="line"><a name="l01930"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga8142275d8923cc8858bebd48a4abeb1e"> 1930</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l01931"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gaebda61867d08ba453ba449bb28401a9e"> 1931</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_DMA0ACN_POS)) </span></div><div class="line"><a name="l01933"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gab53b20c172a2731a3bb81e7b7507925d"> 1933</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l01934"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga1bd1026e132f773fdc248f7691d01ec2"> 1934</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_DMA1ACN_POS)) </span></div><div class="line"><a name="l01936"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gabea2137f01df4a2fff71f682cb1d8689"> 1936</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_USBACN_POS                     2 </span></div><div class="line"><a name="l01937"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga87facbf169acf917cfb13b2c77ec1e68"> 1937</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_USBACN_POS)) </span></div><div class="line"><a name="l01939"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga3fec2db09d3b7132f7285af4d693b537"> 1939</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l01940"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gae83ad07cc6f7cab5e0119aa180d87574"> 1940</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SYS0ACN_POS)) </span></div><div class="line"><a name="l01942"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gad9ed21fb99b367306f594f29043feda0"> 1942</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l01943"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gae1c3f065c46655962ef4a57666b49777"> 1943</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SYS1ACN_POS)) </span></div><div class="line"><a name="l01945"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga1be38ceb7b14c9512742346af543aee0"> 1945</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMADACN_POS                   5 </span></div><div class="line"><a name="l01946"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga7eea78f38b68f384c46208fd4b4decf3"> 1946</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SDMADACN_POS)) </span></div><div class="line"><a name="l01948"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gadbbcd1774979946a01b94099c780d5fb"> 1948</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l01949"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga8cfcc7a4839db9ba2ee9e12bd8b8f597"> 1949</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SDMAIACN_POS)) </span></div><div class="line"><a name="l01951"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#ga70eb9c22e47f37292c9d8afb72f113eb"> 1951</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l01952"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gab7d657010c7500f49d9ab93ff0d28049"> 1952</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01954"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gaa359bf4bdf8df1ae690bc06d5e53dd2e"> 1954</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDIOACN_POS                    8 </span></div><div class="line"><a name="l01955"></a><span class="lineno"><a class="line" href="group__RPU__UART2.html#gae9b66870dd58ecf76bd49eaeee641b51"> 1955</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_UART2_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_UART2_SDIOACN_POS)) </span></div><div class="line"><a name="l01965"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#gab9596fbb50fadecfefe82e73cf9a0750"> 1965</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l01966"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#gaad36bcd99f67bac98c99c291c076c018"> 1966</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_DMA0ACN_POS)) </span></div><div class="line"><a name="l01968"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga5a2b0d8cb1b8df842812720706b2319b"> 1968</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l01969"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga7eadd7192ea430fa666bc3ff058e0033"> 1969</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_DMA1ACN_POS)) </span></div><div class="line"><a name="l01971"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#gad7c87e4f071e0c9116c27e995f83234b"> 1971</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_USBACN_POS                      2 </span></div><div class="line"><a name="l01972"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga38a89d938bab3c82e71c23a2c524f5ce"> 1972</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_USBACN_POS)) </span></div><div class="line"><a name="l01974"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga5f3beb3da8c0a4263e4c4f45d9d35724"> 1974</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l01975"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga81ca1f9894eb4035e5f4eb299d3f0718"> 1975</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_SYS0ACN_POS)) </span></div><div class="line"><a name="l01977"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga038eb1c7ffcc1f6dca622ae609f0aba8"> 1977</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l01978"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga1324b694da2da7680964ab2c520310d3"> 1978</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_SYS1ACN_POS)) </span></div><div class="line"><a name="l01980"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#gaf87ea99237bf3bbb53c5a27202568325"> 1980</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SDMADACN_POS                    5 </span></div><div class="line"><a name="l01981"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#gab70ba4a1c867fd7a4acd96a778572a00"> 1981</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_SDMADACN_POS)) </span></div><div class="line"><a name="l01983"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga8ed9719734c7bedf7056332983bd8100"> 1983</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l01984"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#gac5db6cc84e1082e3e4135e39809f9e89"> 1984</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_SDMAIACN_POS)) </span></div><div class="line"><a name="l01986"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga54e2fd39ea2dbea74853699c7c17fc89"> 1986</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l01987"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga7e976867ad5c75c1d3c97e3d68b5defa"> 1987</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_CRYPTOACN_POS)) </span></div><div class="line"><a name="l01989"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga0af7df04c6bf5a3b1bdd4af39a6abdc6"> 1989</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SDIOACN_POS                     8 </span></div><div class="line"><a name="l01990"></a><span class="lineno"><a class="line" href="group__RPU__SPI1.html#ga15909461b416ca3a5fc906f7f82a3d4e"> 1990</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI1_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI1_SDIOACN_POS)) </span></div><div class="line"><a name="l02000"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga4ea090b5de1e03c18a4d5022646d1d32"> 2000</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l02001"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gaf8380c91b9d6ff9c7899fa33a5f43250"> 2001</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_DMA0ACN_POS)) </span></div><div class="line"><a name="l02003"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gae6a05a92dcb523a6398f5f9cbeeed501"> 2003</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l02004"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga11a0722d4f151cd10a379955046161fc"> 2004</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_DMA1ACN_POS)) </span></div><div class="line"><a name="l02006"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga4fc1382254c20a253140cb4f14158fb9"> 2006</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_USBACN_POS                      2 </span></div><div class="line"><a name="l02007"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gaab1bd14dc84246355b2633d672f0821c"> 2007</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_USBACN_POS)) </span></div><div class="line"><a name="l02009"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gaa03def6b53fb10877f921e884ed0ce70"> 2009</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l02010"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gab07f01f368bdd164e0a2b291690a7d13"> 2010</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_SYS0ACN_POS)) </span></div><div class="line"><a name="l02012"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga7a48f2ac53fbcb68851645df972bc8aa"> 2012</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l02013"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gaaa67c823eadcd2d3654be063d448a64e"> 2013</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_SYS1ACN_POS)) </span></div><div class="line"><a name="l02015"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga7453cba92fb226cb82682a0d34a440b9"> 2015</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SDMADACN_POS                    5 </span></div><div class="line"><a name="l02016"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gaf42251ca73c1295eaeaafd690af71914"> 2016</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_SDMADACN_POS)) </span></div><div class="line"><a name="l02018"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gac03df3ff798c7fdb15601f051adb3fb0"> 2018</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l02019"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#gab82d1cae9bcbbfca2d4876664b387ebb"> 2019</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_SDMAIACN_POS)) </span></div><div class="line"><a name="l02021"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga03e5ece28999d18b6e1ed31c138d8f33"> 2021</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l02022"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga1c6d44e82c0f9bafd59417bba8148796"> 2022</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02024"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga1880a4168c0d3e73fbd70e30191953fe"> 2024</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SDIOACN_POS                     8 </span></div><div class="line"><a name="l02025"></a><span class="lineno"><a class="line" href="group__RPU__SPI2.html#ga237a55528cf67eaa4354cfbe13eccc49"> 2025</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI2_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI2_SDIOACN_POS)) </span></div><div class="line"><a name="l02035"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaee8e89ece9fa2f2d943634d11fe29902"> 2035</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA0ACN_POS                    0 </span></div><div class="line"><a name="l02036"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga3685264e241376b152460548d7d73702"> 2036</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_DMA0ACN_POS)) </span></div><div class="line"><a name="l02038"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaea8a90bd33cc2bc7f67da13854bc7d4b"> 2038</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA1ACN_POS                    1 </span></div><div class="line"><a name="l02039"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga228649976a7406dcae395229ef6c7214"> 2039</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_DMA1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_DMA1ACN_POS)) </span></div><div class="line"><a name="l02041"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gafe9e7429f5e6e2b50f3b0b69f51f172f"> 2041</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_USBACN_POS                     2 </span></div><div class="line"><a name="l02042"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga390f291494a115dc03a41f3490f727ef"> 2042</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_USBACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_USBACN_POS)) </span></div><div class="line"><a name="l02044"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga2d69a17086b1d71e3fb0ae9112af9657"> 2044</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS0ACN_POS                    3 </span></div><div class="line"><a name="l02045"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaa34730052edba6ce24f897a90794d16d"> 2045</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS0ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SYS0ACN_POS)) </span></div><div class="line"><a name="l02047"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gab0b54413e43a9f5dc06f35c75bd1f295"> 2047</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS1ACN_POS                    4 </span></div><div class="line"><a name="l02048"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga175107d6c2e8715736eef724ba0decb6"> 2048</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SYS1ACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SYS1ACN_POS)) </span></div><div class="line"><a name="l02050"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga800cac5ddf6303662cf8e553159e772d"> 2050</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMADACN_POS                   5 </span></div><div class="line"><a name="l02051"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga583a3f12607bd223195237d3f523211d"> 2051</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMADACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SDMADACN_POS)) </span></div><div class="line"><a name="l02053"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaa319f042c382cebb2468d08d9cb33331"> 2053</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMAIACN_POS                   6 </span></div><div class="line"><a name="l02054"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga8629187b36c026890d31daedbe04b091"> 2054</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDMAIACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SDMAIACN_POS)) </span></div><div class="line"><a name="l02056"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga4ac3da3d7afb79fdbddfd5dde8a78c88"> 2056</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_CRYPTOACN_POS                  7 </span></div><div class="line"><a name="l02057"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#gaae60bf5f1a71f4d5deeba73a72f719cd"> 2057</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_CRYPTOACN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02059"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga0bdb627a2ab9a939d24ea0f66b4f26ef"> 2059</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDIOACN_POS                    8 </span></div><div class="line"><a name="l02060"></a><span class="lineno"><a class="line" href="group__RPU__AUDIO.html#ga1e37c86c7f5e17cfdc0c350a58187a2d"> 2060</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_AUDIO_SDIOACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_AUDIO_SDIOACN_POS)) </span></div><div class="line"><a name="l02070"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gad801b09c8e1233918f76c2cbe884fc78"> 2070</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l02071"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga6814dc8776d8d7f8ccad572bcda587cc"> 2071</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_DMA0ACN_POS)) </span></div><div class="line"><a name="l02073"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gadbd2f10999e4aa3901cd3230aff888d0"> 2073</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l02074"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga487da76645221c9d68f42f6b9526af46"> 2074</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_DMA1ACN_POS)) </span></div><div class="line"><a name="l02076"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gaff8ea21c34d572148b206ee0fab6552e"> 2076</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_USBACN_POS                      2 </span></div><div class="line"><a name="l02077"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga432f37df792593d95da5dbc00872f2ca"> 2077</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_USBACN_POS)) </span></div><div class="line"><a name="l02079"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga95324901d39b0ad6baca4c8fdb737979"> 2079</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l02080"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gacf7d1b9ca36d5dcd628c79f0df775dcb"> 2080</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SYS0ACN_POS)) </span></div><div class="line"><a name="l02082"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga88ca992464198d232e6c874e228bc99a"> 2082</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l02083"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga89b6cfa1d6971fa27c3b094e35472328"> 2083</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SYS1ACN_POS)) </span></div><div class="line"><a name="l02085"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga3fa704a4ec82280641b41e6b729d4b1a"> 2085</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMADACN_POS                    5 </span></div><div class="line"><a name="l02086"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga75afa7f4a67c9579f26bd0362b930f51"> 2086</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SDMADACN_POS)) </span></div><div class="line"><a name="l02088"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga58b337d71807fa24029e1f48299e2a3e"> 2088</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l02089"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gabd0075bbe63b1479dd8b7a69f42922fd"> 2089</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SDMAIACN_POS)) </span></div><div class="line"><a name="l02091"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gae239aa16530c24b2ae5098310578e571"> 2091</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l02092"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga1327ebbda918052df18a24e8e4d4e545"> 2092</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02094"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#ga3c48b0db3b6a1fef2197d27527046270"> 2094</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDIOACN_POS                     8 </span></div><div class="line"><a name="l02095"></a><span class="lineno"><a class="line" href="group__RPU__TRNG.html#gad72208b646d8f7fc0ab242710e49f587"> 2095</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_TRNG_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_TRNG_SDIOACN_POS)) </span></div><div class="line"><a name="l02105"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaaffbf0e4e966f68adc0682af47c6fd08"> 2105</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA0ACN_POS                     0 </span></div><div class="line"><a name="l02106"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga1f98a9f87ed66d5af5823d0b0bece68f"> 2106</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_DMA0ACN_POS)) </span></div><div class="line"><a name="l02108"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gac6efc94a581a14782449c82a28bac4a6"> 2108</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA1ACN_POS                     1 </span></div><div class="line"><a name="l02109"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga0da2b6b392c9ab0a2dbb6ae07577658e"> 2109</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_DMA1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_DMA1ACN_POS)) </span></div><div class="line"><a name="l02111"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga02ed3d2ec1fc9ba327ac0c95ff33b05e"> 2111</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_USBACN_POS                      2 </span></div><div class="line"><a name="l02112"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga823829fed82b88104599d41247fb1046"> 2112</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_USBACN                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_USBACN_POS)) </span></div><div class="line"><a name="l02114"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaf28d0357fccf0f69ffda83f945ec1b4a"> 2114</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS0ACN_POS                     3 </span></div><div class="line"><a name="l02115"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga766f5d0e26e5a1a48ee20c67ba6cd238"> 2115</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS0ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SYS0ACN_POS)) </span></div><div class="line"><a name="l02117"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga9c21b4166f44d4ae4bfdc7e44190a6dd"> 2117</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS1ACN_POS                     4 </span></div><div class="line"><a name="l02118"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaef81a0b726c6deb72fb9834484462f6d"> 2118</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SYS1ACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SYS1ACN_POS)) </span></div><div class="line"><a name="l02120"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaaac8c4fb50ea1c44b348180c2c4a2fd6"> 2120</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMADACN_POS                    5 </span></div><div class="line"><a name="l02121"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gaf8809af5a801a452a3d162bb08557df3"> 2121</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMADACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SDMADACN_POS)) </span></div><div class="line"><a name="l02123"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga34535ec593fc175eb786d0f7479ef5b5"> 2123</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMAIACN_POS                    6 </span></div><div class="line"><a name="l02124"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#gadfacd8e713e3516b6257c279cb033f3c"> 2124</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDMAIACN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SDMAIACN_POS)) </span></div><div class="line"><a name="l02126"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga2a5051e61c8d2fb58aeac34d2f2279c2"> 2126</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_CRYPTOACN_POS                   7 </span></div><div class="line"><a name="l02127"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga2437f6bae874ea0407dba1b6138b3561"> 2127</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_CRYPTOACN                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_CRYPTOACN_POS)) </span></div><div class="line"><a name="l02129"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga92531949144558194dae649a7706ae9b"> 2129</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDIOACN_POS                     8 </span></div><div class="line"><a name="l02130"></a><span class="lineno"><a class="line" href="group__RPU__BTLE.html#ga2892aaa8578641018524ebf1436643df"> 2130</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_BTLE_SDIOACN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_BTLE_SDIOACN_POS)) </span></div><div class="line"><a name="l02140"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga66f26c810609b94ba95a0ea64af08197"> 2140</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNR_POS                   0 </span></div><div class="line"><a name="l02141"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga9ff21274af674228ebb7704a066024cc"> 2141</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02143"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga1388f71eac0bb93e3200a4118a6148b8"> 2143</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNW_POS                   1 </span></div><div class="line"><a name="l02144"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gac9259f9a36e566dc0d90d6c42b18151a"> 2144</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02146"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga9196372a613a9e144ee84656e13c153e"> 2146</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNR_POS                   2 </span></div><div class="line"><a name="l02147"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga946a114d7c88900abac14d474a6ee324"> 2147</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02149"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga37b877774cbfb438b9fb7e8b79e0e84f"> 2149</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNW_POS                   3 </span></div><div class="line"><a name="l02150"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga648e5b819bd9734a91471feca586ff39"> 2150</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_DMA1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02152"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga5b580f056625fec5f9b099dee788a059"> 2152</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNR_POS                    4 </span></div><div class="line"><a name="l02153"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga0d4b76280ad6ffe89a0183c10abed63f"> 2153</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_USBACNR_POS)) </span></div><div class="line"><a name="l02155"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga121bb6872b3b271af2b2b670909caece"> 2155</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNW_POS                    5 </span></div><div class="line"><a name="l02156"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaa6f8173695c50589b62f4d02fbeba485"> 2156</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_USBACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_USBACNW_POS)) </span></div><div class="line"><a name="l02158"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga6ad4446805d3726c276432b74c2caabd"> 2158</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNR_POS                   6 </span></div><div class="line"><a name="l02159"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaf48195d123b0ef5d912768768bf335d5"> 2159</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02161"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaa9f86282f0feed3d99ba0d1c51884e14"> 2161</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNW_POS                   7 </span></div><div class="line"><a name="l02162"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gabb5f0ea4eadcf7237921a4cd8b541c37"> 2162</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS0ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02164"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaab09a7f84e5487dae0e44150b52faad0"> 2164</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNR_POS                   8 </span></div><div class="line"><a name="l02165"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga43104e07ac771e333ee8ecad69cb7658"> 2165</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02167"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga42d8e254401450bbf5d91b2b8b6a8477"> 2167</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNW_POS                   9 </span></div><div class="line"><a name="l02168"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gaf3d2f6fb0e20892bb9a7092b9f26d3f7"> 2168</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SYS1ACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02170"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga407c8e22b0ad8271a2cb0c21cfd90ed0"> 2170</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNR_POS                  10 </span></div><div class="line"><a name="l02171"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga04ccc5722bc872635e46bf10e8bfbb96"> 2171</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMADACNR_POS)) </span></div><div class="line"><a name="l02173"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga67ea0aea0d66682b4858eb092cdccdd1"> 2173</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNW_POS                  11 </span></div><div class="line"><a name="l02174"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gae1ac812caecd99c42a24873fcac556a8"> 2174</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMADACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMADACNW_POS)) </span></div><div class="line"><a name="l02176"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gabdf9f3d6efc5692a3d166a49637a8ebc"> 2176</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNR_POS                  12 </span></div><div class="line"><a name="l02177"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga777bca5a8f1965584d7337f97ae47b82"> 2177</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02179"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga1f4f4e4f760628f2e1c8ae0ba8d82acf"> 2179</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNW_POS                  13 </span></div><div class="line"><a name="l02180"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga3d4e27a89e5bbefc17836661f6a44c7f"> 2180</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDMAIACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02182"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga293972c9b34a24851abbfec26f0c137f"> 2182</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNR_POS                 14 </span></div><div class="line"><a name="l02183"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga0583982ec0ea9ed48ee8cb61709a4665"> 2183</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02185"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga600a278679e91e8fe5221b80ab25e958"> 2185</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNW_POS                 15 </span></div><div class="line"><a name="l02186"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gac02e30eecfefceda1932f1267e7f873c"> 2186</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_CRYPTOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02188"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga6b043fc5f011d1fd0b4baeb9765778d5"> 2188</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNR_POS                   16 </span></div><div class="line"><a name="l02189"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#gacf682440db2559287571168ef88c6ea8"> 2189</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDIOACNR_POS)) </span></div><div class="line"><a name="l02191"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga079ba77fcba9935f864e8cd25d491f76"> 2191</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNW_POS                   17 </span></div><div class="line"><a name="l02192"></a><span class="lineno"><a class="line" href="group__RPU__USBHS.html#ga4a736402394a3c68d0433cf30e4495d0"> 2192</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_USBHS_SDIOACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_USBHS_SDIOACNW_POS)) </span></div><div class="line"><a name="l02202"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga94d8deb0bf8dc303e908b2e7b2a67314"> 2202</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNR_POS                    0 </span></div><div class="line"><a name="l02203"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga59d14bbcff780fb5465905fd3ad59313"> 2203</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02205"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga3f300995e258eb710874c8feb47aff6e"> 2205</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNW_POS                    1 </span></div><div class="line"><a name="l02206"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gabc9dd5ebf621efcbc776204eee9df79e"> 2206</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA0ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02208"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga10d9832e39fc7b555f65d7509ea1a57d"> 2208</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNR_POS                    2 </span></div><div class="line"><a name="l02209"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga3f0e14f512f52c7fe08e3a0d96dcd481"> 2209</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02211"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gae852b6ac0b0ff839de339ba0304a57c1"> 2211</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNW_POS                    3 </span></div><div class="line"><a name="l02212"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga8f0c799d3b7f22319a52ebe85b22e862"> 2212</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_DMA1ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02214"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaa1f67d7fdbfd2d8d9fb471f463fab360"> 2214</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNR_POS                     4 </span></div><div class="line"><a name="l02215"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaffa9c53c103bfa70a773e21027cd23fa"> 2215</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_USBACNR_POS)) </span></div><div class="line"><a name="l02217"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga21b00204c774d080a23601e426af28b8"> 2217</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNW_POS                     5 </span></div><div class="line"><a name="l02218"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gacd1f501b99750f6255d199ecbdf159aa"> 2218</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_USBACNW                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_USBACNW_POS)) </span></div><div class="line"><a name="l02220"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga5d3637710dfb0a292c28fa73fad2c693"> 2220</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNR_POS                    6 </span></div><div class="line"><a name="l02221"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gae31ca158724e85ae243f3a035c2a1e66"> 2221</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02223"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gacc3093f985523b0eeef66bd6b29841f8"> 2223</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNW_POS                    7 </span></div><div class="line"><a name="l02224"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaceaa0b96755a7414e32065c0332febf1"> 2224</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS0ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02226"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga088dbabc114e3fee456b14d0096afe53"> 2226</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNR_POS                    8 </span></div><div class="line"><a name="l02227"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga0367ac1403d8a6bc81846b52fcb4ed88"> 2227</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02229"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gacc0e9ed3f51d1c2ae18bf41cbf36fe31"> 2229</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNW_POS                    9 </span></div><div class="line"><a name="l02230"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gad1de49c9909752dee127f0d5196ed3a9"> 2230</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SYS1ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02232"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga4456f3809dc151953b1e582825941a1a"> 2232</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNR_POS                   10 </span></div><div class="line"><a name="l02233"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gac7e03323b968833afd0ac74e19b0af70"> 2233</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMADACNR_POS)) </span></div><div class="line"><a name="l02235"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga73a5dd35ea498fbad5aaafae54d8f947"> 2235</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNW_POS                   11 </span></div><div class="line"><a name="l02236"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaa2cb8c868551234f1da3cdc1bf5693f9"> 2236</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMADACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMADACNW_POS)) </span></div><div class="line"><a name="l02238"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaaedb58ec264486ebd8ac9df8928602c6"> 2238</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNR_POS                   12 </span></div><div class="line"><a name="l02239"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gab939b362781f566802f3a3ec696220f7"> 2239</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02241"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga68c6b67ad5b3d9defb8aab187bee195f"> 2241</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNW_POS                   13 </span></div><div class="line"><a name="l02242"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga88c4178a46e9639ce9f995157f421372"> 2242</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDMAIACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02244"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga9c29c73c83704c6f56257b71f6655e9d"> 2244</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNR_POS                  14 </span></div><div class="line"><a name="l02245"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gab0c6adff08f51c10c9e32337fd7175bd"> 2245</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02247"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gaeb221f5948b3f71296cfac2637514418"> 2247</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNW_POS                  15 </span></div><div class="line"><a name="l02248"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga4a09b3d09f094075695cd5493851f828"> 2248</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_CRYPTOACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02250"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga9e1147d8a3330dacb2c063f57b1731a6"> 2250</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNR_POS                    16 </span></div><div class="line"><a name="l02251"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga0bd09f3a9afb32fddc0a2c1fd0d788af"> 2251</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDIOACNR_POS)) </span></div><div class="line"><a name="l02253"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#gab422f60dbef7d0c9ee659a469fe28f6a"> 2253</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNW_POS                    17 </span></div><div class="line"><a name="l02254"></a><span class="lineno"><a class="line" href="group__RPU__SDIO.html#ga3b02473b8065b4e455ff4d0dd2094ecc"> 2254</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SDIO_SDIOACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SDIO_SDIOACNW_POS)) </span></div><div class="line"><a name="l02264"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gac978ca25e6a53403754912b53ddae8c0"> 2264</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS              0 </span></div><div class="line"><a name="l02265"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga5751cd82d105a9655c85b95d651aae7b"> 2265</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02267"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gac9ee5b4dd593f73d3adeab98134f8621"> 2267</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS              1 </span></div><div class="line"><a name="l02268"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gacd282314ae2e6f6b0352dd62755f9091"> 2268</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02270"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga53dcb6d0ced745208108f1ddce9f660a"> 2270</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS              2 </span></div><div class="line"><a name="l02271"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga75e17f1dbba4f9ab4e9604197b3a6eda"> 2271</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02273"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga6332f2e05ec0049cd2c5317cb0f79f29"> 2273</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS              3 </span></div><div class="line"><a name="l02274"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga74e1339e4bdb4dfb07f0d29148aff3c1"> 2274</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02276"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga4d3824a4409ac5631c307c5ab0d742f5"> 2276</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_USBACNR_POS               4 </span></div><div class="line"><a name="l02277"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gac1f60ab5599891dd1147730965bcfe10"> 2277</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_USBACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_USBACNR_POS)) </span></div><div class="line"><a name="l02279"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gae9e2774e41b6837d7e6ff14cb96f8292"> 2279</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_USBACNW_POS               5 </span></div><div class="line"><a name="l02280"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gacc3422de883a56eca86733b4b978bb1c"> 2280</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_USBACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_USBACNW_POS)) </span></div><div class="line"><a name="l02282"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga3ac5a2abe092bef71f61e578c2042899"> 2282</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS              6 </span></div><div class="line"><a name="l02283"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gabfe92780d53a33814a95da2f09dcf332"> 2283</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02285"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga98fda6ee7a19754eb6fb715a60c19211"> 2285</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS              7 </span></div><div class="line"><a name="l02286"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gaad0f51bb2160529b6ece24a9513f84cc"> 2286</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02288"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga0ad91eb647d84e8194f67d54cbbe77e0"> 2288</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS              8 </span></div><div class="line"><a name="l02289"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga31e6466c4f1de2b268fc7c6e8b5f5bda"> 2289</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02291"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga972bc873a404858f3a2e50772b2daa30"> 2291</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS              9 </span></div><div class="line"><a name="l02292"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga285f8d680b4b07b3d54dbcd6ffdcffd3"> 2292</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02294"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga4790cd55ea908a71b65abc364d7ab56e"> 2294</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS             10 </span></div><div class="line"><a name="l02295"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga67065416934e2a3b34d644d22a9b7a82"> 2295</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMADACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS)) </span></div><div class="line"><a name="l02297"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga6569aef5a4c23b034a32510dd4c64aea"> 2297</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS             11 </span></div><div class="line"><a name="l02298"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga8f713ee5ddd5a8dafcaea12331e14207"> 2298</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMADACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS)) </span></div><div class="line"><a name="l02300"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gad1e004b73c102282c9c1f02a58b5b62f"> 2300</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS             12 </span></div><div class="line"><a name="l02301"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga941ad8cb7be5711ee17e80836a144d7c"> 2301</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02303"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga66d6c55a4be013c65f2ff212caebf6d0"> 2303</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS             13 </span></div><div class="line"><a name="l02304"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga3d405b2ef7e28419ef13fa4f074264df"> 2304</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02306"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gac17aa0afb51d97861551266819c0ffbc"> 2306</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS            14 </span></div><div class="line"><a name="l02307"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gac43fb18299129ed392a3aa2f42485450"> 2307</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR                ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02309"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gacc53d6ce8307eed7a0d9ad2e40cff3f3"> 2309</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS            15 </span></div><div class="line"><a name="l02310"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga423952c6f09d245c81c561aada8a332f"> 2310</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW                ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02312"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gaff57fd5975a19c2ec1d541562822bb6d"> 2312</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS              16 </span></div><div class="line"><a name="l02313"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#gadee96def8c966eb99efdec191d7e559d"> 2313</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDIOACNR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS)) </span></div><div class="line"><a name="l02315"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga1341d82dcddd5c18226448c5ff8af506"> 2315</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS              17 </span></div><div class="line"><a name="l02316"></a><span class="lineno"><a class="line" href="group__RPU__SPIXM__FIFO.html#ga18b259bfc73c040aacddd124124eb98f"> 2316</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPIXM_FIFO_SDIOACNW                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS)) </span></div><div class="line"><a name="l02326"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gaab78ee846ce4e4c84dacd0640bab8eac"> 2326</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA0ACNR_POS                    0 </span></div><div class="line"><a name="l02327"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gaf608bbdbd1ee3e82ece8c238dd6bc7c1"> 2327</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA0ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02329"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga25c3d8ca2a3671cd3fa6a9d46d7eebaa"> 2329</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA0ACNW_POS                    1 </span></div><div class="line"><a name="l02330"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gae96f9f9e60b4cbc402cc189c80f1054c"> 2330</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA0ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02332"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga6c47c38bdf41a2e5c5a0f23a893a55b4"> 2332</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA1ACNR_POS                    2 </span></div><div class="line"><a name="l02333"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga23f37ef7306549de1933d73f197d4862"> 2333</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA1ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02335"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga65659835ec17fb0acf562286f76558e3"> 2335</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA1ACNW_POS                    3 </span></div><div class="line"><a name="l02336"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga1c7fc48ef339d247a2459b1e07208303"> 2336</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_DMA1ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02338"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga32b15e1cc38748ad5cdce17f7e279b75"> 2338</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_USBACNR_POS                     4 </span></div><div class="line"><a name="l02339"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga0fb2a2eb25dba4dc6b776f9bcfbf56bf"> 2339</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_USBACNR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_USBACNR_POS)) </span></div><div class="line"><a name="l02341"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gabbf0ac32d887faf191dbbb1e52737b8b"> 2341</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_USBACNW_POS                     5 </span></div><div class="line"><a name="l02342"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gad1389c0b7271bf2cff4cef34d253ebf1"> 2342</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_USBACNW                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_USBACNW_POS)) </span></div><div class="line"><a name="l02344"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga8d9a28881aed60c55ecd56596e5dc121"> 2344</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS0ACNR_POS                    6 </span></div><div class="line"><a name="l02345"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga8eaf46eae5987c5f32097f1fd293e05c"> 2345</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS0ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02347"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gabd8e4767a119a08dd4b7f2961856c16e"> 2347</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS0ACNW_POS                    7 </span></div><div class="line"><a name="l02348"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga07575f8f91902a6d9de3d3fb2cb45783"> 2348</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS0ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02350"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gaef150385556fcd9cea088b71b60ad8d3"> 2350</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS1ACNR_POS                    8 </span></div><div class="line"><a name="l02351"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga4c08efb12308b5adf83e813232adb049"> 2351</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS1ACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02353"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gaefd568cd5fb6d08f67b09bc5ef60d939"> 2353</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS1ACNW_POS                    9 </span></div><div class="line"><a name="l02354"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga9e0c8937521f180119038675ca1d8fcd"> 2354</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SYS1ACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02356"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga36d07bb75d855f58e6f00e55cd0b079f"> 2356</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMADACNR_POS                   10 </span></div><div class="line"><a name="l02357"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga111d384f85b487bb52b4efa973a8a33b"> 2357</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMADACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SDMADACNR_POS)) </span></div><div class="line"><a name="l02359"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gac0aca2942f05239d764c874b7450ef9c"> 2359</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMADACNW_POS                   11 </span></div><div class="line"><a name="l02360"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga5922671bc7c4f19ec5bc65771702b946"> 2360</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMADACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SDMADACNW_POS)) </span></div><div class="line"><a name="l02362"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga318e3bd5d53d0dc3d76db0e83f87141f"> 2362</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMAIACNR_POS                   12 </span></div><div class="line"><a name="l02363"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga03aaf32ad69a21ee8464bb677c2d15d5"> 2363</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMAIACNR                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02365"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gac898e8241f66008114d199bdc53af55d"> 2365</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMAIACNW_POS                   13 </span></div><div class="line"><a name="l02366"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gac9d043b8c922580849fa8854d0dd892d"> 2366</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDMAIACNW                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02368"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#gae9636bf46aa524552048ec16e4eebfc4"> 2368</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_CRYPTOACNR_POS                  14 </span></div><div class="line"><a name="l02369"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga852d96e449d76465b1390eceec543873"> 2369</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_CRYPTOACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02371"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga6b81942f2783a76debd2098e8ac9d143"> 2371</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_CRYPTOACNW_POS                  15 </span></div><div class="line"><a name="l02372"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga764ae3a9d206a2aee0d4e7bb036589ed"> 2372</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_CRYPTOACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02374"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga86de1922b3537045e338ec3ee375f7c1"> 2374</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDIOACNR_POS                    16 </span></div><div class="line"><a name="l02375"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga2efda68359b6921f2c32eaf8b6196d2d"> 2375</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDIOACNR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SDIOACNR_POS)) </span></div><div class="line"><a name="l02377"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga851e55de5726d860585aaf5a0f0b5042"> 2377</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDIOACNW_POS                    17 </span></div><div class="line"><a name="l02378"></a><span class="lineno"><a class="line" href="group__RPU__SPI0.html#ga3d7d123460f8aea7433bd2cdfba0e658"> 2378</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SPI0_SDIOACNW                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SPI0_SDIOACNW_POS)) </span></div><div class="line"><a name="l02388"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gacd6c4cb825c30cfb5e287701a98f8869"> 2388</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02389"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga7edc62f693fbf27d50106f950771767a"> 2389</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02391"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga6e6674a90908d0dd81d7f470a4708c74"> 2391</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02392"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gacdee3e6785477beddd42d28ba8c91bf6"> 2392</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02394"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga4c2bf258ec6ec9425349eb594172def0"> 2394</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02395"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga4fb970f25de9a890845ffa4a212776e0"> 2395</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02397"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga29d23ab5ffc33d8b551ae7721aaf2881"> 2397</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02398"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gafe4aec8b44b71a64445b0c83a46c7b77"> 2398</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02400"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga1555efa144f149b5244b01e6df27aca1"> 2400</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_USBACNR_POS                  4 </span></div><div class="line"><a name="l02401"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga92cb73d31e5c53d996c8957e349c5428"> 2401</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_USBACNR_POS)) </span></div><div class="line"><a name="l02403"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gada0f3f1efd0187ba01e9a62396af3cbd"> 2403</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_USBACNW_POS                  5 </span></div><div class="line"><a name="l02404"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga5a5b1037020550a0fbfe03e0bb0a69b8"> 2404</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_USBACNW_POS)) </span></div><div class="line"><a name="l02406"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga43e9d010184dc9fe6992091538ba92a4"> 2406</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02407"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga6f4947a243e63d0869a000cf9a4ac097"> 2407</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02409"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gae7c01d292de05ecc96bafc85f376277b"> 2409</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02410"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga76acb0760050d2f7a7804b3a40b65099"> 2410</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02412"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga9428438c03848ef741f1fa2a090485de"> 2412</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02413"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gade6f9f7a01cdfa4740ab8e044a180b22"> 2413</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02415"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga5a7feb16faff34174b18108938813706"> 2415</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02416"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga598308d2e54da35d8d4696c606e737e8"> 2416</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02418"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gaa8f726a49b19267b731beeb2b5114318"> 2418</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02419"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga49ea745e0ac0fbba33e32233d04650ee"> 2419</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SDMADACNR_POS)) </span></div><div class="line"><a name="l02421"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gacf9796225267947a1fa4168f0dc21a67"> 2421</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02422"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gaf6ef5f812989a3c743af64d794509d18"> 2422</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SDMADACNW_POS)) </span></div><div class="line"><a name="l02424"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga0bd26fcf9444074161aec06f2652f2aa"> 2424</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02425"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga4dd234f65c4e1dd75b42582cfad8c1e8"> 2425</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02427"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga73b45cde62a4ea44e16d760e3b705f97"> 2427</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02428"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga43948dbb6236170e40e0f3fff928e91f"> 2428</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02430"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga7729573941cd391469058afb94053c6b"> 2430</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02431"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga355eae6d9f26874050405c1b2adc04bd"> 2431</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02433"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga6b7d7a7ae60d716aeb43bc01e811413d"> 2433</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02434"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga6fb775ceace7547635b17147a4971060"> 2434</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02436"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gaf72fdbc36955fcfa92e05b007059e164"> 2436</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02437"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#gac2237b05e590707b46e6509ed864050d"> 2437</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SDIOACNR_POS)) </span></div><div class="line"><a name="l02439"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga6c836ce2dfc5f1bca11950a4b7726301"> 2439</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02440"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM0.html#ga354e4bfe7ca79260ec1d04510c928965"> 2440</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM0_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM0_SDIOACNW_POS)) </span></div><div class="line"><a name="l02450"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga20974ac5a8ff4a2f2722d0253f826888"> 2450</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02451"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga671b7741dee4913bfe5c0ad7a2dabe07"> 2451</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02453"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga0768cb9bb122ede38375c839755fdeac"> 2453</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02454"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga512f8a9e86296ee2ec8ea1cfdeafb52c"> 2454</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02456"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga627c9ca08aec07d71c2042564a5853a9"> 2456</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02457"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gad4d110495f789fb2fefa804360583b4f"> 2457</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02459"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gab705c0974b36b955087a150e586a2243"> 2459</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02460"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga39b11963862bfd7a416848683f560727"> 2460</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02462"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gae846b3fcfe2484eceac3818236f43fc2"> 2462</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_USBACNR_POS                  4 </span></div><div class="line"><a name="l02463"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gad02cb941640d2f73a5fc51cd56ceffcf"> 2463</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_USBACNR_POS)) </span></div><div class="line"><a name="l02465"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga9a38b48e7f68599986132559f1285ee9"> 2465</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_USBACNW_POS                  5 </span></div><div class="line"><a name="l02466"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga6e697c630e11b27f12333b04002408dc"> 2466</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_USBACNW_POS)) </span></div><div class="line"><a name="l02468"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga986479244a40ed950e3d15a5367ce3ac"> 2468</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02469"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga48cb5e2d13586bfe0b85bce0039ade33"> 2469</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02471"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga0c3fbb313ad1d624f7331302656c961b"> 2471</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02472"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga9663812a36894bf024625bb1aacb995e"> 2472</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02474"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gae8bc8193dfca1aa96cfb5bbb4c667251"> 2474</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02475"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga359497200a4779123f7b312513651185"> 2475</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02477"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gabcbef6a9ed92fa7c4efd423405b61e03"> 2477</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02478"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga8e7705bc7a577b9f9d63109022434641"> 2478</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02480"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gaef5422f050ef529623621d675aa38e53"> 2480</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02481"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga06a16f0d0ae39d09107f33a03f41fbe3"> 2481</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SDMADACNR_POS)) </span></div><div class="line"><a name="l02483"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga3e1c3ec60337cedf2eae5b047e6e2276"> 2483</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02484"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga82d8614b90efae51b8ca9caf7bab8b1b"> 2484</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SDMADACNW_POS)) </span></div><div class="line"><a name="l02486"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga314d5a56b786e4393d924865712abca9"> 2486</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02487"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga41ff9a521e800fb41607382cff27090f"> 2487</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02489"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga6d566cfaa20440bc43aa1b0aab9c381e"> 2489</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02490"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gaa6e05304af1f9125406313d0e4fe9c8e"> 2490</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02492"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga95d5885588964bdb5ba5240385b13d9c"> 2492</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02493"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga980b7d5d4971fd4e3edb35880a51f3ac"> 2493</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02495"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga81fae84a0ce0255cb7e34859923053d7"> 2495</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02496"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gaf5543c2f1c7c5496ce77fd0c508ec318"> 2496</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02498"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gacfa026273b1aef94fec36aa98769ac0c"> 2498</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02499"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#gaebbd6e6424f5ad41cf8d6ee78b278b2e"> 2499</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SDIOACNR_POS)) </span></div><div class="line"><a name="l02501"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga6afe2b67793ec399b1b4acd744117c0e"> 2501</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02502"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM1.html#ga844464d726f6e2fd63ccd4ce6f893f48"> 2502</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM1_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM1_SDIOACNW_POS)) </span></div><div class="line"><a name="l02512"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga56ec61d902c7277773e916ebd9ff7cbb"> 2512</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02513"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gab6a8404225e95471d81ffeadb5a8aa36"> 2513</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02515"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gae1cd7dc5c9e7942817d3481a0a39577e"> 2515</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02516"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga9977a4b95c924f096b7431d04c84f54d"> 2516</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02518"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga942b11f6e57119e0b62dec99febd559b"> 2518</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02519"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga0941e9474bab10d20a20bbcc0836ecad"> 2519</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02521"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga61892223e566e501138b5e635cc72f77"> 2521</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02522"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga9d1a8ed2d3e23850c9280d3c328dab39"> 2522</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02524"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gaa3e43e3d600ffb53ba5897e116ee98ee"> 2524</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_USBACNR_POS                  4 </span></div><div class="line"><a name="l02525"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga3c2f727949faeef67551a4cb4225da1f"> 2525</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_USBACNR_POS)) </span></div><div class="line"><a name="l02527"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gafde3c8c4e4cf277e6d6bc2387f0306b3"> 2527</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_USBACNW_POS                  5 </span></div><div class="line"><a name="l02528"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gae229f5fb5800a5e16c3d6c6985d63638"> 2528</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_USBACNW_POS)) </span></div><div class="line"><a name="l02530"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga45c51e70bed5a936797d8ab147da6c30"> 2530</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02531"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga7028d79fea36b67f1780b010c06274a7"> 2531</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02533"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gace315d03c4e12ce26bdd9aae22a448ec"> 2533</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02534"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gaa55098201693c8e29da9608bf9680a7b"> 2534</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02536"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga1741692d0af99f1511895d5193fc0c98"> 2536</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02537"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gad9626c1e43fb0a6a4634e4f6c2914b40"> 2537</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02539"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga6370e86e1758278b6986ecd7559824cb"> 2539</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02540"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga60cd294657c24f265301546ab4b4019a"> 2540</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02542"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gad8941959b1c657f97c02ed4398f3ded3"> 2542</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02543"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gae600f35b4f6183e30a7dea6480fa80a0"> 2543</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SDMADACNR_POS)) </span></div><div class="line"><a name="l02545"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gab80ac97409299648a5b3ea7ea1bfc4f7"> 2545</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02546"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga09a1817015bd4489cc027d9eb6529440"> 2546</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SDMADACNW_POS)) </span></div><div class="line"><a name="l02548"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga6d6ab56ae0686dabb7220b337aaddd3d"> 2548</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02549"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gad9782a0169d5dc02680e2b9de5df1ddc"> 2549</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02551"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gafcb99e837fb12c71956f966f64fbf7af"> 2551</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02552"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga8037de3e5c6075d1bdf3fdb6ef0ba4e1"> 2552</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02554"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga0e097f00a279fc9e6585992251e5f5ea"> 2554</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02555"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gade9688ac60cc2525065e7abee3f50c1d"> 2555</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02557"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gaa6e9c6c36e7335738a29a98707adcc9f"> 2557</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02558"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga2fe295ff339c3e5c7247493d3e24b0db"> 2558</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02560"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#gab44fcc055d46bcfbdce37bb91493dd90"> 2560</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02561"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga07d439559b31c2838852bbc187970590"> 2561</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SDIOACNR_POS)) </span></div><div class="line"><a name="l02563"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga32a2575dfe595439b9575487dc9e5eac"> 2563</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02564"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM2.html#ga45b992124acb5bd4ad823a02b47ec0ed"> 2564</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM2_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM2_SDIOACNW_POS)) </span></div><div class="line"><a name="l02574"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga8b5e83aa04809eb10cb7d1685418f800"> 2574</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02575"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga5de9397b3405f9ead921716ab594b695"> 2575</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02577"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gac1463ec19b1c7a83fa0e685991c79836"> 2577</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02578"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga8edeb9a029665d2f3ebcddbef961fc30"> 2578</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02580"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gac41d92dbe3f53f1b6354468bbdd6618f"> 2580</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02581"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga2c7624209de7254a2ef2db7ed9939297"> 2581</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02583"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga619f4da31bb5b8853a897f5f758e2a40"> 2583</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02584"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gae7f49618778be7796dd7a067557d8510"> 2584</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02586"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga78c27b850f01dfadd86394f2bceb01e8"> 2586</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_USBACNR_POS                  4 </span></div><div class="line"><a name="l02587"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gad3583fa5661968bc43e2cd8562f0216f"> 2587</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_USBACNR_POS)) </span></div><div class="line"><a name="l02589"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gab0c104106527fbbacf867f2ced4d116f"> 2589</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_USBACNW_POS                  5 </span></div><div class="line"><a name="l02590"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga3d66d07a73c034ba73db3aeb014a7175"> 2590</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_USBACNW_POS)) </span></div><div class="line"><a name="l02592"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga340902df75934ec49f1d8532afdab100"> 2592</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02593"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga22f1729c024cccde7cb1b2aeeb5ae9f3"> 2593</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02595"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gabc8052efa1be3e16e1d43c7f885c3df7"> 2595</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02596"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga9e433b04802ce7a5d13af37d071b7dc3"> 2596</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02598"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga3dc0b24c48f7265618989a7e08db9526"> 2598</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02599"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga278b8865cc61174da4befdb442e80925"> 2599</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02601"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gaee8ec7cd56488d6e44e50af79db087c3"> 2601</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02602"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gab220c96fbc3534dd00fc7bdb5ff2a36f"> 2602</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02604"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gad9b2a91abf77b2878f2cc857e7bd8cef"> 2604</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02605"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gaedae53ed1f98e30be536441923ef9318"> 2605</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SDMADACNR_POS)) </span></div><div class="line"><a name="l02607"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gac714633ab22dcbbf1e2b8e4564ac3ed1"> 2607</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02608"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga24dba585014b8557e012fb9909b93869"> 2608</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SDMADACNW_POS)) </span></div><div class="line"><a name="l02610"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gab29f8659f931e01fc9a56431dc61e314"> 2610</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02611"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga83fcce6d7662b9ee8f445e10ec68cdb9"> 2611</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02613"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga8c67ede2250597e5c1bf13faba2e153f"> 2613</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02614"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga1975ceb9224769443d783f5d82bed168"> 2614</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02616"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gabb6bed89dd272a5423c6e0766dd26d08"> 2616</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02617"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga100e77f525e26be664a057bcfafa0ba5"> 2617</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02619"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga7fb9d1fd9f1ae4115de6055843dd8660"> 2619</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02620"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga5944d2271b19c7a0f888d8261a08a339"> 2620</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02622"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga8149cc8b4738c318cc0cb507399e7590"> 2622</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02623"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#gab698144106a0d7c1b0c82e196b55c4af"> 2623</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SDIOACNR_POS)) </span></div><div class="line"><a name="l02625"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga5303aed4d532525bd5969c36134dd729"> 2625</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02626"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM3.html#ga65274ac1882699921017512f11e9edef"> 2626</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM3_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM3_SDIOACNW_POS)) </span></div><div class="line"><a name="l02636"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga9b74eaf6bbdd9a08d97b4a26d8799bfd"> 2636</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02637"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga2c3578ae4ee64e62c61728f04e01fe2d"> 2637</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02639"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga5d21f92542fc872bdb1d75436c9b5592"> 2639</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02640"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga41792d9e33638bbe76be04d11511809b"> 2640</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02642"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga4825307ec8c325e317b3136818b461ab"> 2642</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02643"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga1cf7283db0bee440e44b5d1ebc2400bc"> 2643</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02645"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gab7ef590ae4a7b4e4483f6155f0ee52e4"> 2645</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02646"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga353b8e54e298c3909a27704fd7a38e75"> 2646</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02648"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gafcf7d455464ba550033c586de92b2554"> 2648</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_USBACNR_POS                  4 </span></div><div class="line"><a name="l02649"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga9957c4c94b9d7fc88c3b3710aaa1a6f2"> 2649</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_USBACNR_POS)) </span></div><div class="line"><a name="l02651"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga5d88ce47a46b1b6f6c3e5d9662278d71"> 2651</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_USBACNW_POS                  5 </span></div><div class="line"><a name="l02652"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga98f7baa45e3cc395224ccd8e3e4275d4"> 2652</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_USBACNW_POS)) </span></div><div class="line"><a name="l02654"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gaaf3238575e98667d644f50724021f1e4"> 2654</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02655"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gafd10b5f6cbfbfdf4b0f9ac1a0edb3839"> 2655</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02657"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga0865fa9e694516d5613bd32d8a492577"> 2657</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02658"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga170a61e394f3f26eadd46503815ab8a4"> 2658</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02660"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga2a1bce0a25a77648138f7b5e8850b6bc"> 2660</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02661"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga91953ad08e78f6efb258ddad4c161a95"> 2661</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02663"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gab889bbfda430810fead2f87b0b85a99e"> 2663</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02664"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga246e8b7456037e223b646a15550bed64"> 2664</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02666"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga27d5f36d1311909f5417fe936136baf9"> 2666</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02667"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga15cc6cb973fb66ff1883d122d1df2d12"> 2667</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SDMADACNR_POS)) </span></div><div class="line"><a name="l02669"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga03c255db3ac3cd79ee9f71c61eb397df"> 2669</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02670"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gaff7da213a4a9cbb9f0b0298e974cffe5"> 2670</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SDMADACNW_POS)) </span></div><div class="line"><a name="l02672"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gad95998eaf07251ec549e55ba7ab5fb33"> 2672</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02673"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga10dc91e511beb671275644ad0ae6e20c"> 2673</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02675"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga52971066d3f2cb033d313ef85a061eeb"> 2675</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02676"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gae3ff16187f132a6b9842936e917573dc"> 2676</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02678"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga6833c4cf297633b8b63ada108f4c4976"> 2678</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02679"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga04fad0f5305f810d6c0f2f6e9183355c"> 2679</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02681"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga8b805d79392d9c135c876726f317031c"> 2681</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02682"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga5eb2e9ecf98dbea63d43ff656c398c83"> 2682</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02684"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga6dbb7c5682a6af43eacc7392601ac16e"> 2684</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02685"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#gaec0c0d968e7d514c5119e3bb1aa0e06c"> 2685</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SDIOACNR_POS)) </span></div><div class="line"><a name="l02687"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga31764e040d4eccb644067a00ebe567d3"> 2687</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02688"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM4.html#ga123811b6e053b8d00844ababc362ae53"> 2688</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM4_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM4_SDIOACNW_POS)) </span></div><div class="line"><a name="l02698"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gab6be376bca089b12c7d358cf23015a48"> 2698</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02699"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga70a44d1a8847a28037f2f2bbb6257534"> 2699</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02701"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga6de5531a5eb9ec977dccfef92455bd1c"> 2701</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02702"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gacfc0f2e108602ed862160ea85f6df049"> 2702</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02704"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga3647519b015b9e23f1a6c1ee75ef0e65"> 2704</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02705"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gac4a12798a5065bea40922f2d7b0bfef6"> 2705</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02707"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga28a163126ee9e78384325bb11801c4ce"> 2707</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02708"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga715360d30404ab450e2e747034072e13"> 2708</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02710"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga3e04fb5eaf4b29c391000e22bf4689ac"> 2710</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_USBACNR_POS                  4 </span></div><div class="line"><a name="l02711"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga80e7d3775e6e1a68b2bed67d7c72a9c3"> 2711</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_USBACNR_POS)) </span></div><div class="line"><a name="l02713"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga34b4ee20f9b57f39b114dfd78915bf7e"> 2713</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_USBACNW_POS                  5 </span></div><div class="line"><a name="l02714"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga11cf9303cab3674150082cf9ce54a7c4"> 2714</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_USBACNW_POS)) </span></div><div class="line"><a name="l02716"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gab04225bd97e811c80e3d644f37e94899"> 2716</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02717"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga4c578a178264ab658ae1dfc1117a14ab"> 2717</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02719"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gaca68ff267b5df6af961e755e61047ee0"> 2719</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02720"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga7e32f6edd93e700318967acacc7a2a3b"> 2720</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02722"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gaa0ecf3c44bf12f307eccd1164141cd2e"> 2722</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02723"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gafbb08a982cec1ff8b1447c0b83999fb4"> 2723</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02725"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga5d6a4c854a5329d54f36425a7e836440"> 2725</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02726"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga66992b0f41011c377de7d8c1bb79825f"> 2726</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02728"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga0f6d3479df5c894a9195c7dee119d818"> 2728</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02729"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga25137e94f6e374d03632d791bf0ea806"> 2729</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SDMADACNR_POS)) </span></div><div class="line"><a name="l02731"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga2b412d8bd32723dda6f40cea7118fe19"> 2731</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02732"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga5c706e81eb14bedaee2094e4771591d8"> 2732</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SDMADACNW_POS)) </span></div><div class="line"><a name="l02734"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga39a2f95faff5bce1cd80f348ba048fe2"> 2734</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02735"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gae299959d3e5843b350af472f6d8ad43d"> 2735</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02737"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga5bd555606e95c6c406948b7fdbc5882c"> 2737</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02738"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga0c30813013f0926b583f7b1bf45c15b3"> 2738</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02740"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gae1a85fa07526cf275187fbf2f02a9b90"> 2740</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02741"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga506b5598208b5c636daa6e45942cf45e"> 2741</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02743"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gadd9e22a170d6cc90d1bb9474e6e30eb2"> 2743</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02744"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga4bb7f541ff406f68f2b29a18908ac839"> 2744</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02746"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gac75cab82fdb6371b9451b8c2acd322c0"> 2746</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02747"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#gac9e364df61edc6e0f379210fef654ee7"> 2747</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SDIOACNR_POS)) </span></div><div class="line"><a name="l02749"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga32436212e12a5c55e6785c230d3684ed"> 2749</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02750"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM5.html#ga794bd6a83099d39aee394a5cfeaa279d"> 2750</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM5_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM5_SDIOACNW_POS)) </span></div><div class="line"><a name="l02760"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga6a3920a966c5a2953217bfcb8442ea0c"> 2760</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA0ACNR_POS                 0 </span></div><div class="line"><a name="l02761"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gacfa3cc83c7c7edb164bb92bbce0660ca"> 2761</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_DMA0ACNR_POS)) </span></div><div class="line"><a name="l02763"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga13c6eb32a60849153a8780186b312ec4"> 2763</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA0ACNW_POS                 1 </span></div><div class="line"><a name="l02764"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gaf243ae313491830b7ae49c1aa45e267c"> 2764</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_DMA0ACNW_POS)) </span></div><div class="line"><a name="l02766"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gab0bc9e2bc9a72902f60638874176fef8"> 2766</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA1ACNR_POS                 2 </span></div><div class="line"><a name="l02767"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga91432447e5d304186ad50e121dc50dd9"> 2767</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_DMA1ACNR_POS)) </span></div><div class="line"><a name="l02769"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gaa357694675ab53231fddece06825d5f6"> 2769</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA1ACNW_POS                 3 </span></div><div class="line"><a name="l02770"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga38b8133f97f6cdd267c767800f51a8b8"> 2770</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_DMA1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_DMA1ACNW_POS)) </span></div><div class="line"><a name="l02772"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gae32064dfb32a8269130b2a2269695b92"> 2772</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_USBACNR_POS                  4 </span></div><div class="line"><a name="l02773"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga99c0e4857cdbe4cf14ee23d6133a5a1c"> 2773</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_USBACNR                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_USBACNR_POS)) </span></div><div class="line"><a name="l02775"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga739b13377e68f770517c981e55659b8b"> 2775</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_USBACNW_POS                  5 </span></div><div class="line"><a name="l02776"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga01de80c6ed1d2b40beb4162320cd6143"> 2776</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_USBACNW                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_USBACNW_POS)) </span></div><div class="line"><a name="l02778"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga0f37efb8e8e06a7e948b2c3a53ef34b4"> 2778</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS0ACNR_POS                 6 </span></div><div class="line"><a name="l02779"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga5461e61892a60fd7fa4c571800b049ca"> 2779</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS0ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SYS0ACNR_POS)) </span></div><div class="line"><a name="l02781"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga228be8cab4d3a6dcb9fe86b1d434968f"> 2781</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS0ACNW_POS                 7 </span></div><div class="line"><a name="l02782"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gae66df934a07e57cbf70cc531703c25b4"> 2782</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS0ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SYS0ACNW_POS)) </span></div><div class="line"><a name="l02784"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga715460fbcc792b91d18950e700fbf11a"> 2784</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS1ACNR_POS                 8 </span></div><div class="line"><a name="l02785"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gadc85b3ddbfc4f5e1e1946171a576f83b"> 2785</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS1ACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SYS1ACNR_POS)) </span></div><div class="line"><a name="l02787"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gaaf02b543252d610baa104d97071dcdd6"> 2787</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS1ACNW_POS                 9 </span></div><div class="line"><a name="l02788"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga6a73d941a5af145cde9145804eb8c59a"> 2788</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SYS1ACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SYS1ACNW_POS)) </span></div><div class="line"><a name="l02790"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga316b6cee212d67c26894ccb278cc2751"> 2790</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMADACNR_POS                10 </span></div><div class="line"><a name="l02791"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga5af5059a070e46d3c34cc8c4bde35dcf"> 2791</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMADACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SDMADACNR_POS)) </span></div><div class="line"><a name="l02793"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga3cc7d47586b19ef4dc6198b2fc936f6d"> 2793</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMADACNW_POS                11 </span></div><div class="line"><a name="l02794"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga5918a9bc1fa120da502f4bb6c9bb594f"> 2794</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMADACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SDMADACNW_POS)) </span></div><div class="line"><a name="l02796"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga12e49a9095eb05dd0bb187577961a662"> 2796</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMAIACNR_POS                12 </span></div><div class="line"><a name="l02797"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga78fd24fdada7d1c7b724ac7ae8334a8f"> 2797</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMAIACNR                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SDMAIACNR_POS)) </span></div><div class="line"><a name="l02799"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gacbb14fae341a0b1639782d44d41c53c5"> 2799</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMAIACNW_POS                13 </span></div><div class="line"><a name="l02800"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gab39ac3dfa7bae2feb1d4f5c96bb59b8f"> 2800</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDMAIACNW                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SDMAIACNW_POS)) </span></div><div class="line"><a name="l02802"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga825132e7bb142f654989d3c87b6bb531"> 2802</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_CRYPTOACNR_POS               14 </span></div><div class="line"><a name="l02803"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga426958297c80cad537ce9059db2ffbfa"> 2803</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_CRYPTOACNR                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_CRYPTOACNR_POS)) </span></div><div class="line"><a name="l02805"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga3d0df3f9b8414c43287966bb6e536b5b"> 2805</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_CRYPTOACNW_POS               15 </span></div><div class="line"><a name="l02806"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#gaf7556a588001235d12c158ec7c78e4aa"> 2806</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_CRYPTOACNW                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_CRYPTOACNW_POS)) </span></div><div class="line"><a name="l02808"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga4c16a556309f42dcc1285c82e2e6630c"> 2808</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDIOACNR_POS                 16 </span></div><div class="line"><a name="l02809"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga92bad1a5f3fc09e5bf029f6702e3807b"> 2809</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDIOACNR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SDIOACNR_POS)) </span></div><div class="line"><a name="l02811"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga949394694e43636bbc22c2f71335412c"> 2811</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDIOACNW_POS                 17 </span></div><div class="line"><a name="l02812"></a><span class="lineno"><a class="line" href="group__RPU__SYSRAM6.html#ga8b6babf0e81c12fc3924663d1ce46874"> 2812</a></span>&#160;<span class="preprocessor"> #define MXC_F_RPU_SYSRAM6_SDIOACNW                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RPU_SYSRAM6_SDIOACNW_POS)) </span></div><div class="line"><a name="l02816"></a><span class="lineno"> 2816</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l02817"></a><span class="lineno"> 2817</span>&#160;}</div><div class="line"><a name="l02818"></a><span class="lineno"> 2818</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l02819"></a><span class="lineno"> 2819</span>&#160;</div><div class="line"><a name="l02820"></a><span class="lineno"> 2820</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RPU_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__rpu__regs__t_html_aa66553c7c4c2ff2a65e176af948e6399"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aa66553c7c4c2ff2a65e176af948e6399">mxc_rpu_regs_t::spixm_fifo</a></div><div class="ttdeci">__IO uint32_t spixm_fifo</div><div class="ttdoc">0x0BC0: RPU SPIXM_FIFO Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:187</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a086921af8001fdf0d9af8935b068f865"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a086921af8001fdf0d9af8935b068f865">mxc_rpu_regs_t::sysram6</a></div><div class="ttdeci">__IO uint32_t sysram6</div><div class="ttdoc">0x0F60: RPU SYSRAM6 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:203</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_aa617d084516acc758d283a33deed9a38"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aa617d084516acc758d283a33deed9a38">mxc_rpu_regs_t::spi2</a></div><div class="ttdeci">__IO uint32_t spi2</div><div class="ttdoc">0x0480: RPU SPI2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:175</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a955e4f7e17b11917f743d0887530a356"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a955e4f7e17b11917f743d0887530a356">mxc_rpu_regs_t::tmr1</a></div><div class="ttdeci">__IO uint32_t tmr1</div><div class="ttdoc">0x0110: RPU TMR1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:115</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_aa2846a575112b79bd39dc16bf16b260d"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aa2846a575112b79bd39dc16bf16b260d">mxc_rpu_regs_t::qspi0</a></div><div class="ttdeci">__IO uint32_t qspi0</div><div class="ttdoc">0x0BE0: RPU QSPI0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:189</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a7cf24cf377876560e35ce321484cf3a4"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a7cf24cf377876560e35ce321484cf3a4">mxc_rpu_regs_t::ptg_bus0</a></div><div class="ttdeci">__IO uint32_t ptg_bus0</div><div class="ttdoc">0x03C0: RPU PTG_BUS0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:161</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_aec838a3176ba946e9f886fbe6672df8a"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aec838a3176ba946e9f886fbe6672df8a">mxc_rpu_regs_t::usbhs</a></div><div class="ttdeci">__IO uint32_t usbhs</div><div class="ttdoc">0x0B10: RPU USBHS Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:183</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_ace3ea78cbad80bfeca273e59f9f7b9c1"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ace3ea78cbad80bfeca273e59f9f7b9c1">mxc_rpu_regs_t::srcc</a></div><div class="ttdeci">__IO uint32_t srcc</div><div class="ttdoc">0x0330: RPU SRCC Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:149</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a35801207272121e21d0a2a76430f1401"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a35801207272121e21d0a2a76430f1401">mxc_rpu_regs_t::fcr</a></div><div class="ttdeci">__IO uint32_t fcr</div><div class="ttdoc">0x08: RPU FCR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:91</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a33efdc41a5dab826941aff9e4ee47d0d"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a33efdc41a5dab826941aff9e4ee47d0d">mxc_rpu_regs_t::sysram3</a></div><div class="ttdeci">__IO uint32_t sysram3</div><div class="ttdoc">0x0F30: RPU SYSRAM3 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:197</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ac64bf03f5a31181627b9d7bff229bbae"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ac64bf03f5a31181627b9d7bff229bbae">mxc_rpu_regs_t::gcr</a></div><div class="ttdeci">__IO uint32_t gcr</div><div class="ttdoc">0x00: RPU GCR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:89</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_ab2184b645146cece7001515e57b190ad"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ab2184b645146cece7001515e57b190ad">mxc_rpu_regs_t::i2c2</a></div><div class="ttdeci">__IO uint32_t i2c2</div><div class="ttdoc">0x01F0: RPU I2C2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:133</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_af13a4525df9e31a7ac74da0fef71e39a"><div class="ttname"><a href="structmxc__rpu__regs__t.html#af13a4525df9e31a7ac74da0fef71e39a">mxc_rpu_regs_t::wut</a></div><div class="ttdeci">__IO uint32_t wut</div><div class="ttdoc">0x0064: RPU WUT Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:105</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_aee54ba2b716b8ec8eb511d6d7dee57a1"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aee54ba2b716b8ec8eb511d6d7dee57a1">mxc_rpu_regs_t::i2c0_bus0</a></div><div class="ttdeci">__IO uint32_t i2c0_bus0</div><div class="ttdoc">0x01D0: RPU I2C0_BUS0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:129</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a087785341ce79484506cfd7287728e3d"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a087785341ce79484506cfd7287728e3d">mxc_rpu_regs_t::dvs</a></div><div class="ttdeci">__IO uint32_t dvs</div><div class="ttdoc">0x0048: RPU DVS Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:100</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a835774853a29501e6a1f750d5a57956c"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a835774853a29501e6a1f750d5a57956c">mxc_rpu_regs_t::spixipmc</a></div><div class="ttdeci">__IO uint32_t spixipmc</div><div class="ttdoc">0x0270: RPU SPIXIPMC Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:137</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a578dd37f6abddf3a8daea235ce614185"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a578dd37f6abddf3a8daea235ce614185">mxc_rpu_regs_t::bbcr</a></div><div class="ttdeci">__IO uint32_t bbcr</div><div class="ttdoc">0x006C: RPU BBCR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:107</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_ab79390483fc759b36c1492da84c39142"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ab79390483fc759b36c1492da84c39142">mxc_rpu_regs_t::spixipmfifo</a></div><div class="ttdeci">__IO uint32_t spixipmfifo</div><div class="ttdoc">0x0BC0: RPU SPIXIPMFIFO Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:187</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a3f3c752957bc9e467f5c9d2e831f555f"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a3f3c752957bc9e467f5c9d2e831f555f">mxc_rpu_regs_t::icache0</a></div><div class="ttdeci">__IO uint32_t icache0</div><div class="ttdoc">0x02A0: RPU ICACHE0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:144</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_af36206f67702f1598a065ceacb42ed76"><div class="ttname"><a href="structmxc__rpu__regs__t.html#af36206f67702f1598a065ceacb42ed76">mxc_rpu_regs_t::sram1</a></div><div class="ttdeci">__IO uint32_t sram1</div><div class="ttdoc">0x0F10: RPU SRAM1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:193</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a26e3639950f8bd188d066afec39d2bfe"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a26e3639950f8bd188d066afec39d2bfe">mxc_rpu_regs_t::sysram5</a></div><div class="ttdeci">__IO uint32_t sysram5</div><div class="ttdoc">0x0F50: RPU SYSRAM5 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:201</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a46f94aa32bf20f1306dd0b30bad69ec6"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a46f94aa32bf20f1306dd0b30bad69ec6">mxc_rpu_regs_t::i2c2_bus0</a></div><div class="ttdeci">__IO uint32_t i2c2_bus0</div><div class="ttdoc">0x01F0: RPU I2C2_BUS0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:133</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a6a8f3593c33e8e2a2c07ed8389670108"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a6a8f3593c33e8e2a2c07ed8389670108">mxc_rpu_regs_t::spi1</a></div><div class="ttdeci">__IO uint32_t spi1</div><div class="ttdoc">0x0460: RPU SPI1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:173</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a326ba0b5ed008b242db40e9ab75500bc"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a326ba0b5ed008b242db40e9ab75500bc">mxc_rpu_regs_t::sysram0</a></div><div class="ttdeci">__IO uint32_t sysram0</div><div class="ttdoc">0x0F00: RPU SYSRAM0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:191</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a50e2d7f83a0c9bf0f7e97ed0e3fd0057"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a50e2d7f83a0c9bf0f7e97ed0e3fd0057">mxc_rpu_regs_t::pwrseq</a></div><div class="ttdeci">__IO uint32_t pwrseq</div><div class="ttdoc">0x0068: RPU PWRSEQ Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:106</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a0fa6182dc552923bce9dcbf52de361a3"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a0fa6182dc552923bce9dcbf52de361a3">mxc_rpu_regs_t::spixfm</a></div><div class="ttdeci">__IO uint32_t spixfm</div><div class="ttdoc">0x0260: RPU SPIXFM Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:135</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_aafa4124620f7faaef5a033b4309be329"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aafa4124620f7faaef5a033b4309be329">mxc_rpu_regs_t::icc1</a></div><div class="ttdeci">__IO uint32_t icc1</div><div class="ttdoc">0x02A4: RPU ICC1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:145</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ae6ec9c9f9232226c77892d5226e94fd7"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ae6ec9c9f9232226c77892d5226e94fd7">mxc_rpu_regs_t::dma1</a></div><div class="ttdeci">__IO uint32_t dma1</div><div class="ttdoc">0x0350: RPU DMA1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:153</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_ae1f643fe22f713dc8f1345ac2582a628"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ae1f643fe22f713dc8f1345ac2582a628">mxc_rpu_regs_t::i2c1_bus0</a></div><div class="ttdeci">__IO uint32_t i2c1_bus0</div><div class="ttdoc">0x01E0: RPU I2C1_BUS0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:131</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a39c567882dcac38cc5717fee6cbf2d29"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a39c567882dcac38cc5717fee6cbf2d29">mxc_rpu_regs_t::tmr2</a></div><div class="ttdeci">__IO uint32_t tmr2</div><div class="ttdoc">0x0120: RPU TMR2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:117</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a509d073c9df3c06db1dc8a5fe779f377"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a509d073c9df3c06db1dc8a5fe779f377">mxc_rpu_regs_t::bbsir</a></div><div class="ttdeci">__IO uint32_t bbsir</div><div class="ttdoc">0x0054: RPU BBSIR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:102</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a2fc656d8a513ec404aaff8da6f011fa8"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a2fc656d8a513ec404aaff8da6f011fa8">mxc_rpu_regs_t::adc</a></div><div class="ttdeci">__IO uint32_t adc</div><div class="ttdoc">0x0340: RPU ADC Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:151</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a5fc2a3b485206573e4054868b11ca9eb"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a5fc2a3b485206573e4054868b11ca9eb">mxc_rpu_regs_t::dcache</a></div><div class="ttdeci">__IO uint32_t dcache</div><div class="ttdoc">0x0330: RPU DCACHE Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:149</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_abe05f3718e793dfe14939c75bf94eca2"><div class="ttname"><a href="structmxc__rpu__regs__t.html#abe05f3718e793dfe14939c75bf94eca2">mxc_rpu_regs_t::gpio1</a></div><div class="ttdeci">__IO uint32_t gpio1</div><div class="ttdoc">0x0090: RPU GPIO1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:111</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a4aa815e028be017d2571b6c69a6c85aa"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a4aa815e028be017d2571b6c69a6c85aa">mxc_rpu_regs_t::sdhcctrl</a></div><div class="ttdeci">__IO uint32_t sdhcctrl</div><div class="ttdoc">0x0370: RPU SDHCCTRL Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:157</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_afce0eed072aa6ea690e311ea03098e96"><div class="ttname"><a href="structmxc__rpu__regs__t.html#afce0eed072aa6ea690e311ea03098e96">mxc_rpu_regs_t::sram4</a></div><div class="ttdeci">__IO uint32_t sram4</div><div class="ttdoc">0x0F40: RPU SRAM4 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:199</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_aa9bf22e9a1dc0d8436bace1228c1cfd1"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aa9bf22e9a1dc0d8436bace1228c1cfd1">mxc_rpu_regs_t::qspi2</a></div><div class="ttdeci">__IO uint32_t qspi2</div><div class="ttdoc">0x0480: RPU QSPI2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:175</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a171cf0c62b66f6b04ee8ff99ee230ba1"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a171cf0c62b66f6b04ee8ff99ee230ba1">mxc_rpu_regs_t::mcr</a></div><div class="ttdeci">__IO uint32_t mcr</div><div class="ttdoc">0x006C: RPU MCR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:107</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a88a5580a133bfd53a7761f992ec2881b"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a88a5580a133bfd53a7761f992ec2881b">mxc_rpu_regs_t::crypto</a></div><div class="ttdeci">__IO uint32_t crypto</div><div class="ttdoc">0x0C: RPU CRYPTO Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:92</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a0214735f8b048f0386a35b3db6832bb1"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a0214735f8b048f0386a35b3db6832bb1">mxc_rpu_regs_t::icachexip</a></div><div class="ttdeci">__IO uint32_t icachexip</div><div class="ttdoc">0x02F0: RPU ICACHEXIP Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:147</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_acd8b09dccd4281e8fa47a3f690e0c287"><div class="ttname"><a href="structmxc__rpu__regs__t.html#acd8b09dccd4281e8fa47a3f690e0c287">mxc_rpu_regs_t::spixipm</a></div><div class="ttdeci">__IO uint32_t spixipm</div><div class="ttdoc">0x0260: RPU SPIXIPM Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:135</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a05e9a4140c71fdab6518205e023c6313"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a05e9a4140c71fdab6518205e023c6313">mxc_rpu_regs_t::i2c1</a></div><div class="ttdeci">__IO uint32_t i2c1</div><div class="ttdoc">0x01E0: RPU I2C1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:131</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a343226a105b94929065ea2caebe3313f"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a343226a105b94929065ea2caebe3313f">mxc_rpu_regs_t::tmr3</a></div><div class="ttdeci">__IO uint32_t tmr3</div><div class="ttdoc">0x0130: RPU TMR3 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:119</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_acf032f7d78b6532dd6ad36ba8443a121"><div class="ttname"><a href="structmxc__rpu__regs__t.html#acf032f7d78b6532dd6ad36ba8443a121">mxc_rpu_regs_t::sysram1</a></div><div class="ttdeci">__IO uint32_t sysram1</div><div class="ttdoc">0x0F10: RPU SYSRAM1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:193</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a792a786a036390359f26f9be9c193850"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a792a786a036390359f26f9be9c193850">mxc_rpu_regs_t::simo</a></div><div class="ttdeci">__IO uint32_t simo</div><div class="ttdoc">0x0044: RPU SIMO Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:99</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a73401214b554adea90654ae4ee9e441a"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a73401214b554adea90654ae4ee9e441a">mxc_rpu_regs_t::sram0</a></div><div class="ttdeci">__IO uint32_t sram0</div><div class="ttdoc">0x0F00: RPU SRAM0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:191</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ad3099847a5ab4441c5465aec0c0d75ac"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ad3099847a5ab4441c5465aec0c0d75ac">mxc_rpu_regs_t::gpio0</a></div><div class="ttdeci">__IO uint32_t gpio0</div><div class="ttdoc">0x0080: RPU GPIO0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:109</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a107ce59e766452ddd16ba0c679c756c7"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a107ce59e766452ddd16ba0c679c756c7">mxc_rpu_regs_t::spid</a></div><div class="ttdeci">__IO uint32_t spid</div><div class="ttdoc">0x03A0: RPU SPID Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:159</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a31e99638858f7d9a5d3e0c13467e50e9"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a31e99638858f7d9a5d3e0c13467e50e9">mxc_rpu_regs_t::wdt1</a></div><div class="ttdeci">__IO uint32_t wdt1</div><div class="ttdoc">0x0034: RPU WDT1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:95</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a5877aea894835edc9344e9a0c9fab0d0"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a5877aea894835edc9344e9a0c9fab0d0">mxc_rpu_regs_t::qspi1</a></div><div class="ttdeci">__IO uint32_t qspi1</div><div class="ttdoc">0x0460: RPU QSPI1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:173</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a66a59e223df12aa7f8ddf8003bbbb4a7"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a66a59e223df12aa7f8ddf8003bbbb4a7">mxc_rpu_regs_t::htimer1</a></div><div class="ttdeci">__IO uint32_t htimer1</div><div class="ttdoc">0x01C0: RPU HTIMER1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:127</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a7f226e3d43e02fcba1bbe3c75b8818dd"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a7f226e3d43e02fcba1bbe3c75b8818dd">mxc_rpu_regs_t::sram5</a></div><div class="ttdeci">__IO uint32_t sram5</div><div class="ttdoc">0x0F50: RPU SRAM5 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:201</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html"><div class="ttname"><a href="structmxc__rpu__regs__t.html">mxc_rpu_regs_t</a></div><div class="ttdoc">Structure type to access the RPU Registers. </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:88</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_ac31f8fe960e70e7f63a3e9b355204150"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ac31f8fe960e70e7f63a3e9b355204150">mxc_rpu_regs_t::sram3</a></div><div class="ttdeci">__IO uint32_t sram3</div><div class="ttdoc">0x0F30: RPU SRAM3 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:197</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a9feb124206f57e0aaee54f8cc32e0422"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a9feb124206f57e0aaee54f8cc32e0422">mxc_rpu_regs_t::trng</a></div><div class="ttdeci">__IO uint32_t trng</div><div class="ttdoc">0x04D0: RPU TRNG Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:179</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a493a625cf6437fc4ea51aeb6433d377b"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a493a625cf6437fc4ea51aeb6433d377b">mxc_rpu_regs_t::spixr</a></div><div class="ttdeci">__IO uint32_t spixr</div><div class="ttdoc">0x03A0: RPU SPIXR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:159</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ab8395b7a2e0c8f984ec19d5b003d1aca"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ab8395b7a2e0c8f984ec19d5b003d1aca">mxc_rpu_regs_t::uart1</a></div><div class="ttdeci">__IO uint32_t uart1</div><div class="ttdoc">0x0430: RPU UART1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:169</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ab7c28ad4ea0a12610580d549a9e0a3e3"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ab7c28ad4ea0a12610580d549a9e0a3e3">mxc_rpu_regs_t::tmr5</a></div><div class="ttdeci">__IO uint32_t tmr5</div><div class="ttdoc">0x0150: RPU TMR5 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:123</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_ae1d1de4f98df3b2171e9635b742376d1"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ae1d1de4f98df3b2171e9635b742376d1">mxc_rpu_regs_t::sram2</a></div><div class="ttdeci">__IO uint32_t sram2</div><div class="ttdoc">0x0F20: RPU SRAM2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:195</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_ab3363e181a7630bc3d3201eb3b879dfa"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ab3363e181a7630bc3d3201eb3b879dfa">mxc_rpu_regs_t::spi0</a></div><div class="ttdeci">__IO uint32_t spi0</div><div class="ttdoc">0x0BE0: RPU SPI0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:189</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a8080c2b6a8f3a34c04a83d4255e96b61"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a8080c2b6a8f3a34c04a83d4255e96b61">mxc_rpu_regs_t::sfcc</a></div><div class="ttdeci">__IO uint32_t sfcc</div><div class="ttdoc">0x02F0: RPU SFCC Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:147</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ae0c2fff3d78c4cc13ea8ff6be0058747"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ae0c2fff3d78c4cc13ea8ff6be0058747">mxc_rpu_regs_t::wdt2</a></div><div class="ttdeci">__IO uint32_t wdt2</div><div class="ttdoc">0x0038: RPU WDT2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:96</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ac6f45bdc77bf6cadfd61e0ae8e2fc3ec"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ac6f45bdc77bf6cadfd61e0ae8e2fc3ec">mxc_rpu_regs_t::audio</a></div><div class="ttdeci">__IO uint32_t audio</div><div class="ttdoc">0x04C0: RPU AUDIO Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:177</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ae0b16e375ee045fc432c2151f7ac2cc7"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ae0b16e375ee045fc432c2151f7ac2cc7">mxc_rpu_regs_t::uart2</a></div><div class="ttdeci">__IO uint32_t uart2</div><div class="ttdoc">0x0440: RPU UART2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:171</div></div>
@@ -121,21 +120,22 @@ $(document).ready(function(){initNavTree('rpu__regs_8h_source.html','');});
 <div class="ttc" id="structmxc__rpu__regs__t_html_aab60df31ea3b2276598b3035cd9ba9c0"><div class="ttname"><a href="structmxc__rpu__regs__t.html#aab60df31ea3b2276598b3035cd9ba9c0">mxc_rpu_regs_t::rtc</a></div><div class="ttdeci">__IO uint32_t rtc</div><div class="ttdoc">0x0060: RPU RTC Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:104</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a895fe2a194714f0392686a608d450b67"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a895fe2a194714f0392686a608d450b67">mxc_rpu_regs_t::tmr4</a></div><div class="ttdeci">__IO uint32_t tmr4</div><div class="ttdoc">0x0140: RPU TMR4 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:121</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a96b9adef08b7f6d1d545e28264275a4c"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a96b9adef08b7f6d1d545e28264275a4c">mxc_rpu_regs_t::tmr0</a></div><div class="ttdeci">__IO uint32_t tmr0</div><div class="ttdoc">0x0100: RPU TMR0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:113</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a4f719bdddec9869dc1226debe906860d"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a4f719bdddec9869dc1226debe906860d">mxc_rpu_regs_t::icc0</a></div><div class="ttdeci">__IO uint32_t icc0</div><div class="ttdoc">0x02A0: RPU ICC0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:144</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a7ab74a3f9f055d17c3b1b426d8f1de0e"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a7ab74a3f9f055d17c3b1b426d8f1de0e">mxc_rpu_regs_t::htimer0</a></div><div class="ttdeci">__IO uint32_t htimer0</div><div class="ttdoc">0x01B0: RPU HTIMER0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:125</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a83957039806dc91bd297c2e10e0cd031"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a83957039806dc91bd297c2e10e0cd031">mxc_rpu_regs_t::smon</a></div><div class="ttdeci">__IO uint32_t smon</div><div class="ttdoc">0x0040: RPU SMON Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:98</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a3e54ff8fe1128e996d2b30bcf285bbaa"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a3e54ff8fe1128e996d2b30bcf285bbaa">mxc_rpu_regs_t::btle</a></div><div class="ttdeci">__IO uint32_t btle</div><div class="ttdoc">0x0500: RPU BTLE Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:181</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a5ae8ed804192af60d6d2ed665bc89de7"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a5ae8ed804192af60d6d2ed665bc89de7">mxc_rpu_regs_t::sir</a></div><div class="ttdeci">__IO uint32_t sir</div><div class="ttdoc">0x04: RPU SIR Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:90</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a8c9edc39d61f24c7df1c403a4a1b9e78"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a8c9edc39d61f24c7df1c403a4a1b9e78">mxc_rpu_regs_t::pt</a></div><div class="ttdeci">__IO uint32_t pt</div><div class="ttdoc">0x03C0: RPU PT Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:161</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a5c48ec12eab4ffc70cd1edce57d6718c"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a5c48ec12eab4ffc70cd1edce57d6718c">mxc_rpu_regs_t::flc1</a></div><div class="ttdeci">__IO uint32_t flc1</div><div class="ttdoc">0x0294: RPU FLC1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:142</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a43c49ff6f60b9f78f587cf97befee4da"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a43c49ff6f60b9f78f587cf97befee4da">mxc_rpu_regs_t::sdio</a></div><div class="ttdeci">__IO uint32_t sdio</div><div class="ttdoc">0x0B60: RPU SDIO Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:185</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a938e8c511fe710606bb950a76477b9a2"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a938e8c511fe710606bb950a76477b9a2">mxc_rpu_regs_t::spixfc</a></div><div class="ttdeci">__IO uint32_t spixfc</div><div class="ttdoc">0x0270: RPU SPIXFC Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:137</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a3922d90aa5c3a901375d2f07585ddb8c"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a3922d90aa5c3a901375d2f07585ddb8c">mxc_rpu_regs_t::flc0</a></div><div class="ttdeci">__IO uint32_t flc0</div><div class="ttdoc">0x0290: RPU FLC0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:141</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a35753561e0eecc1e5d1a5b15a78ab524"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a35753561e0eecc1e5d1a5b15a78ab524">mxc_rpu_regs_t::owm</a></div><div class="ttdeci">__IO uint32_t owm</div><div class="ttdoc">0x03D0: RPU OWM Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:163</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a7409b12c61b29a4fe257590a07c01ce4"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a7409b12c61b29a4fe257590a07c01ce4">mxc_rpu_regs_t::wdt0</a></div><div class="ttdeci">__IO uint32_t wdt0</div><div class="ttdoc">0x30: RPU WDT0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:94</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a2e1e85f1c673b9352d2afa16882f6b39"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a2e1e85f1c673b9352d2afa16882f6b39">mxc_rpu_regs_t::uart0</a></div><div class="ttdeci">__IO uint32_t uart0</div><div class="ttdoc">0x0420: RPU UART0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:167</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a70722dd45c3732d6e3d827e46e722c39"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a70722dd45c3732d6e3d827e46e722c39">mxc_rpu_regs_t::sysram4</a></div><div class="ttdeci">__IO uint32_t sysram4</div><div class="ttdoc">0x0F40: RPU SYSRAM4 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:199</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_ac874de1a295a40dd380470c64ed28eb0"><div class="ttname"><a href="structmxc__rpu__regs__t.html#ac874de1a295a40dd380470c64ed28eb0">mxc_rpu_regs_t::sdma</a></div><div class="ttdeci">__IO uint32_t sdma</div><div class="ttdoc">0x0360: RPU SDMA Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:155</div></div>
+<div class="ttc" id="structmxc__rpu__regs__t_html_a3d15538d060546e2f115288d3a9ab709"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a3d15538d060546e2f115288d3a9ab709">mxc_rpu_regs_t::sysram2</a></div><div class="ttdeci">__IO uint32_t sysram2</div><div class="ttdoc">0x0F20: RPU SYSRAM2 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:195</div></div>
 <div class="ttc" id="structmxc__rpu__regs__t_html_a62bc3fca3b262224cf1b86be2d7608ff"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a62bc3fca3b262224cf1b86be2d7608ff">mxc_rpu_regs_t::sema</a></div><div class="ttdeci">__IO uint32_t sema</div><div class="ttdoc">0x03E0: RPU SEMA Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:165</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a58cadc3c2770b44b7ebfa6c5f55635bd"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a58cadc3c2770b44b7ebfa6c5f55635bd">mxc_rpu_regs_t::icache1</a></div><div class="ttdeci">__IO uint32_t icache1</div><div class="ttdoc">0x02A4: RPU ICACHE1 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:145</div></div>
-<div class="ttc" id="structmxc__rpu__regs__t_html_a67f843cf68d636443ee57ce3133fbd12"><div class="ttname"><a href="structmxc__rpu__regs__t.html#a67f843cf68d636443ee57ce3133fbd12">mxc_rpu_regs_t::i2c0</a></div><div class="ttdeci">__IO uint32_t i2c0</div><div class="ttdoc">0x01D0: RPU I2C0 Register </div><div class="ttdef"><b>Definition:</b> rpu_regs.h:129</div></div>
 </div><!-- fragment --></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- HTML footer for doxygen 1.8.12-->
diff --git a/lib/sdk/Documentation/html/rtc_8h_source.html b/lib/sdk/Documentation/html/rtc_8h_source.html
index 0ef77fc4e94204684818fbd873b20e54b116d78c..f23dcf1419689bdf38781a69c2ebd345a88c76a8 100644
--- a/lib/sdk/Documentation/html/rtc_8h_source.html
+++ b/lib/sdk/Documentation/html/rtc_8h_source.html
@@ -71,15 +71,13 @@ $(document).ready(function(){initNavTree('rtc_8h_source.html','');});
 <div class="title">rtc.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Date: 2019-07-18 14:30:02 -0500 (Thu, 18 Jul 2019) $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> * $Revision: 44725 $</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _RTC_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _RTC_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="preprocessor">#include &quot;rtc_regs.h&quot;</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#include &quot;mxc_sys.h&quot;</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;</div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;</div><div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">   64</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aef8bf61bae255010f085e7315351cdad">   65</a></span>&#160;    <a class="code" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aef8bf61bae255010f085e7315351cdad">SQUARE_WAVE_DISABLED</a>, </div><div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aeb42ff04caea8907474bc72d995ba3dc">   66</a></span>&#160;    <a class="code" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aeb42ff04caea8907474bc72d995ba3dc">SQUARE_WAVE_ENABLED</a>,  </div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;} <a class="code" href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">rtc_sqwave_en_t</a>;</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;</div><div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">   69</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a4bb740521fd4eb8bb99a135b02474914">   70</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a4bb740521fd4eb8bb99a135b02474914">F_1HZ</a>   = <a class="code" href="group__RTC__CTRL.html#gada1707e9fe00e1bc7649d1721ab3150e">MXC_S_RTC_CTRL_FT_FREQ1HZ</a>,     </div><div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ad545c1c9e01db973cf4e3a44650ee9b0">   71</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ad545c1c9e01db973cf4e3a44650ee9b0">F_512HZ</a> = <a class="code" href="group__RTC__CTRL.html#gaaa7f8bd03f0f4d659299abbe22f5e944">MXC_S_RTC_CTRL_FT_FREQ512HZ</a>,   </div><div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ab3661228d5f5cec50fa88abf2c2cd8bb">   72</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ab3661228d5f5cec50fa88abf2c2cd8bb">F_4KHZ</a>  = <a class="code" href="group__RTC__CTRL.html#gac293dfe46dbd97843ad854b3496df501">MXC_S_RTC_CTRL_FT_FREQ4KHZ</a>,    </div><div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a04731f3590d4ccd81b66cdce850de85b">   73</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a04731f3590d4ccd81b66cdce850de85b">F_32KHZ</a> = 32,                          </div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;} <a class="code" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a>;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;</div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00077"></a><span class="lineno">   77</span>&#160;    NOISE_IMMUNE_MODE        = <a class="code" href="group__RTC__CTRL.html#ga251f7aa714e7b00d92b3e50ca3777b56">MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE</a>,</div><div class="line"><a name="l00078"></a><span class="lineno">   78</span>&#160;    QUIET_MODE               = <a class="code" href="group__RTC__CTRL.html#ga813fb0789bf6c8a7b20242959b1f0ec4">MXC_S_RTC_CTRL_X32KMD_QUIETMODE</a>,</div><div class="line"><a name="l00079"></a><span class="lineno">   79</span>&#160;    QUIET_STOP_WARMUP_MODE   = <a class="code" href="group__RTC__CTRL.html#ga3b7dd3ba7d9d95ac8f2bdd4cf1d89166">MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP</a>,</div><div class="line"><a name="l00080"></a><span class="lineno">   80</span>&#160;    QUIET_STOP_NOWARMUP_MODE = <a class="code" href="group__RTC__CTRL.html#gac5eec49851d441fae6a188f2b46ab53b">MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP</a>,</div><div class="line"><a name="l00081"></a><span class="lineno">   81</span>&#160;} rtc_osc_mode_t;</div><div class="line"><a name="l00082"></a><span class="lineno">   82</span>&#160;</div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga72669f5c905a1d17fdfa2f7b77bb41ce">RTC_EnableTimeofdayInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00091"></a><span class="lineno">   91</span>&#160;</div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gab320222809fa703752f607692ff19077">RTC_DisableTimeofdayInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga3301512bc423624900b309a1b0182f06">RTC_EnableSubsecondInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga8cd2332e3b126d3b36aa96ced6c590ee">RTC_DisableSubsecondInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00118"></a><span class="lineno">  118</span>&#160;</div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga4f07ac62555fa0f25554b899f58a4c64">RTC_SetTimeofdayAlarm</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, uint32_t ras);</div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;</div><div class="line"><a name="l00138"></a><span class="lineno">  138</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga908d1682dfc5eaedf8456f844c7063bb">RTC_SetSubsecondAlarm</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, uint32_t rssa);</div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;</div><div class="line"><a name="l00146"></a><span class="lineno">  146</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaa7efff0b3d541b21e72d395630e1f24f">RTC_EnableRTCE</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;</div><div class="line"><a name="l00154"></a><span class="lineno">  154</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga20a27a15332a491a002690a449340e90">RTC_DisableRTCE</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00155"></a><span class="lineno">  155</span>&#160;</div><div class="line"><a name="l00165"></a><span class="lineno">  165</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga47027279242aa1332c71ef5923b9ea49">RTC_Init</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, uint32_t sec, uint16_t ssec, sys_cfg_rtc_t *sys_cfg);</div><div class="line"><a name="l00166"></a><span class="lineno">  166</span>&#160;</div><div class="line"><a name="l00177"></a><span class="lineno">  177</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaf630f332cfe83aa088aaf8e51f51aeb7">RTC_SquareWave</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, rtc_sqwave_en_t sqe, <a class="code" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a> ft,</div><div class="line"><a name="l00178"></a><span class="lineno">  178</span>&#160;                   rtc_osc_mode_t x32kmd, <span class="keyword">const</span> sys_cfg_rtc_t* sys_cfg);</div><div class="line"><a name="l00179"></a><span class="lineno">  179</span>&#160;</div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga80d06f8c70e8e7c4237ea04c1a306eb5">RTC_Trim</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, int8_t trm);</div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;</div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gae7ca9b560bcf24222f45b99f74bfb29c">RTC_CheckBusy</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;</div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaff44ce9b4424c2b97de707e8131bda98">RTC_GetFlags</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00201"></a><span class="lineno">  201</span>&#160;</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga02597411ccf1060d4c269c8e841a91b5">RTC_ClearFlags</a>(<span class="keywordtype">int</span> flags);</div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga226746587cdf944f47b0aca73f05ca6d">RTC_GetSubSecond</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;</div><div class="line"><a name="l00218"></a><span class="lineno">  218</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaf48f4b08156d9534873dc65d1ab10290">RTC_GetSecond</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00219"></a><span class="lineno">  219</span>&#160;</div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gad5a12820a09a49b487eb0c82ffba1689">RTC_GetTime</a>(uint32_t* sec, uint32_t* subsec);</div><div class="line"><a name="l00231"></a><span class="lineno">  231</span>&#160;</div><div class="line"><a name="l00232"></a><span class="lineno">  232</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;}</div><div class="line"><a name="l00234"></a><span class="lineno">  234</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00235"></a><span class="lineno">  235</span>&#160;</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RTC_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__rtc_html_gaa7efff0b3d541b21e72d395630e1f24f"><div class="ttname"><a href="group__rtc.html#gaa7efff0b3d541b21e72d395630e1f24f">RTC_EnableRTCE</a></div><div class="ttdeci">int RTC_EnableRTCE(mxc_rtc_regs_t *rtc)</div><div class="ttdoc">Enable/Start the Real Time Clock. </div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Date: 2019-12-24 11:42:21 -0600 (Tue, 24 Dec 2019) $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> * $Revision: 50314 $</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _RTC_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _RTC_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;<span class="preprocessor">#include &quot;rtc_regs.h&quot;</span></div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#include &quot;mxc_sys.h&quot;</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;</div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;</div><div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">   64</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aef8bf61bae255010f085e7315351cdad">   65</a></span>&#160;    <a class="code" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aef8bf61bae255010f085e7315351cdad">SQUARE_WAVE_DISABLED</a>, </div><div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aeb42ff04caea8907474bc72d995ba3dc">   66</a></span>&#160;    <a class="code" href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aeb42ff04caea8907474bc72d995ba3dc">SQUARE_WAVE_ENABLED</a>,  </div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;} <a class="code" href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">rtc_sqwave_en_t</a>;</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;</div><div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">   69</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a4bb740521fd4eb8bb99a135b02474914">   70</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a4bb740521fd4eb8bb99a135b02474914">F_1HZ</a>   = <a class="code" href="group__RTC__CTRL.html#gada1707e9fe00e1bc7649d1721ab3150e">MXC_S_RTC_CTRL_FT_FREQ1HZ</a>,     </div><div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ad545c1c9e01db973cf4e3a44650ee9b0">   71</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ad545c1c9e01db973cf4e3a44650ee9b0">F_512HZ</a> = <a class="code" href="group__RTC__CTRL.html#gaaa7f8bd03f0f4d659299abbe22f5e944">MXC_S_RTC_CTRL_FT_FREQ512HZ</a>,   </div><div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ab3661228d5f5cec50fa88abf2c2cd8bb">   72</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ab3661228d5f5cec50fa88abf2c2cd8bb">F_4KHZ</a>  = <a class="code" href="group__RTC__CTRL.html#gac293dfe46dbd97843ad854b3496df501">MXC_S_RTC_CTRL_FT_FREQ4KHZ</a>,    </div><div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a04731f3590d4ccd81b66cdce850de85b">   73</a></span>&#160;    <a class="code" href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a04731f3590d4ccd81b66cdce850de85b">F_32KHZ</a> = 32,                          </div><div class="line"><a name="l00074"></a><span class="lineno">   74</span>&#160;} <a class="code" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a>;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;</div><div class="line"><a name="l00083"></a><span class="lineno">   83</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga72669f5c905a1d17fdfa2f7b77bb41ce">RTC_EnableTimeofdayInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00084"></a><span class="lineno">   84</span>&#160;</div><div class="line"><a name="l00092"></a><span class="lineno">   92</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gab320222809fa703752f607692ff19077">RTC_DisableTimeofdayInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;</div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga3301512bc423624900b309a1b0182f06">RTC_EnableSubsecondInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00102"></a><span class="lineno">  102</span>&#160;</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga8cd2332e3b126d3b36aa96ced6c590ee">RTC_DisableSubsecondInterrupt</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;</div><div class="line"><a name="l00120"></a><span class="lineno">  120</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga4f07ac62555fa0f25554b899f58a4c64">RTC_SetTimeofdayAlarm</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, uint32_t ras);</div><div class="line"><a name="l00121"></a><span class="lineno">  121</span>&#160;</div><div class="line"><a name="l00131"></a><span class="lineno">  131</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga908d1682dfc5eaedf8456f844c7063bb">RTC_SetSubsecondAlarm</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, uint32_t rssa);</div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;</div><div class="line"><a name="l00139"></a><span class="lineno">  139</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaa7efff0b3d541b21e72d395630e1f24f">RTC_EnableRTCE</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00140"></a><span class="lineno">  140</span>&#160;</div><div class="line"><a name="l00147"></a><span class="lineno">  147</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga20a27a15332a491a002690a449340e90">RTC_DisableRTCE</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc);</div><div class="line"><a name="l00148"></a><span class="lineno">  148</span>&#160;</div><div class="line"><a name="l00158"></a><span class="lineno">  158</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga47027279242aa1332c71ef5923b9ea49">RTC_Init</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, uint32_t sec, uint16_t ssec, sys_cfg_rtc_t *sys_cfg);</div><div class="line"><a name="l00159"></a><span class="lineno">  159</span>&#160;</div><div class="line"><a name="l00170"></a><span class="lineno">  170</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga3ec285956d9017f98476b4a672a6c9a2">RTC_SquareWave</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, rtc_sqwave_en_t sqe, <a class="code" href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a> ft,</div><div class="line"><a name="l00171"></a><span class="lineno">  171</span>&#160;                   <span class="keyword">const</span> sys_cfg_rtc_t* sys_cfg);</div><div class="line"><a name="l00172"></a><span class="lineno">  172</span>&#160;</div><div class="line"><a name="l00180"></a><span class="lineno">  180</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga80d06f8c70e8e7c4237ea04c1a306eb5">RTC_Trim</a>(<a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a> *rtc, int8_t trm);</div><div class="line"><a name="l00181"></a><span class="lineno">  181</span>&#160;</div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gae7ca9b560bcf24222f45b99f74bfb29c">RTC_CheckBusy</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;</div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaff44ce9b4424c2b97de707e8131bda98">RTC_GetFlags</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;</div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga02597411ccf1060d4c269c8e841a91b5">RTC_ClearFlags</a>(<span class="keywordtype">int</span> flags);</div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;</div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#ga226746587cdf944f47b0aca73f05ca6d">RTC_GetSubSecond</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;</div><div class="line"><a name="l00211"></a><span class="lineno">  211</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gaf48f4b08156d9534873dc65d1ab10290">RTC_GetSecond</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;</div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__rtc.html#gad5a12820a09a49b487eb0c82ffba1689">RTC_GetTime</a>(uint32_t* sec, uint32_t* subsec);</div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;</div><div class="line"><a name="l00225"></a><span class="lineno">  225</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00226"></a><span class="lineno">  226</span>&#160;}</div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;</div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RTC_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__rtc_html_gaa7efff0b3d541b21e72d395630e1f24f"><div class="ttname"><a href="group__rtc.html#gaa7efff0b3d541b21e72d395630e1f24f">RTC_EnableRTCE</a></div><div class="ttdeci">int RTC_EnableRTCE(mxc_rtc_regs_t *rtc)</div><div class="ttdoc">Enable/Start the Real Time Clock. </div></div>
 <div class="ttc" id="group__rtc_html_gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ab3661228d5f5cec50fa88abf2c2cd8bb"><div class="ttname"><a href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ab3661228d5f5cec50fa88abf2c2cd8bb">F_4KHZ</a></div><div class="ttdoc">4Khz </div><div class="ttdef"><b>Definition:</b> rtc.h:72</div></div>
 <div class="ttc" id="group__rtc_html_ga908d1682dfc5eaedf8456f844c7063bb"><div class="ttname"><a href="group__rtc.html#ga908d1682dfc5eaedf8456f844c7063bb">RTC_SetSubsecondAlarm</a></div><div class="ttdeci">int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa)</div><div class="ttdoc">Set Sub-Second alarm value and enable interrupt,. </div></div>
-<div class="ttc" id="group__RTC__CTRL_html_ga251f7aa714e7b00d92b3e50ca3777b56"><div class="ttname"><a href="group__RTC__CTRL.html#ga251f7aa714e7b00d92b3e50ca3777b56">MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE</div><div class="ttdoc">CTRL_X32KMD_NOISEIMMUNEMODE Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:196</div></div>
 <div class="ttc" id="group__rtc_html_ga3301512bc423624900b309a1b0182f06"><div class="ttname"><a href="group__rtc.html#ga3301512bc423624900b309a1b0182f06">RTC_EnableSubsecondInterrupt</a></div><div class="ttdeci">int RTC_EnableSubsecondInterrupt(mxc_rtc_regs_t *rtc)</div><div class="ttdoc">Enables Sub-Second&amp;#39;s Alarm Interrupt. </div></div>
 <div class="ttc" id="group__rtc_html_gaff44ce9b4424c2b97de707e8131bda98"><div class="ttname"><a href="group__rtc.html#gaff44ce9b4424c2b97de707e8131bda98">RTC_GetFlags</a></div><div class="ttdeci">int RTC_GetFlags(void)</div><div class="ttdoc">Gets Interrupt flags. </div></div>
 <div class="ttc" id="group__rtc_html_gab320222809fa703752f607692ff19077"><div class="ttname"><a href="group__rtc.html#gab320222809fa703752f607692ff19077">RTC_DisableTimeofdayInterrupt</a></div><div class="ttdeci">int RTC_DisableTimeofdayInterrupt(mxc_rtc_regs_t *rtc)</div><div class="ttdoc">Disable Time-of-Day&amp;#39;s Alarm Interrupt. </div></div>
 <div class="ttc" id="group__rtc_html_gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a4bb740521fd4eb8bb99a135b02474914"><div class="ttname"><a href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a4bb740521fd4eb8bb99a135b02474914">F_1HZ</a></div><div class="ttdoc">1Hz (Compensated) </div><div class="ttdef"><b>Definition:</b> rtc.h:70</div></div>
-<div class="ttc" id="group__RTC__CTRL_html_gac5eec49851d441fae6a188f2b46ab53b"><div class="ttname"><a href="group__RTC__CTRL.html#gac5eec49851d441fae6a188f2b46ab53b">MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP</div><div class="ttdoc">CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:202</div></div>
 <div class="ttc" id="group__rtc_html_ga4f07ac62555fa0f25554b899f58a4c64"><div class="ttname"><a href="group__rtc.html#ga4f07ac62555fa0f25554b899f58a4c64">RTC_SetTimeofdayAlarm</a></div><div class="ttdeci">int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras)</div><div class="ttdoc">Set Time-of-Day alarm value and enable Interrupt. </div></div>
 <div class="ttc" id="group__RTC__CTRL_html_gaaa7f8bd03f0f4d659299abbe22f5e944"><div class="ttname"><a href="group__RTC__CTRL.html#gaaa7f8bd03f0f4d659299abbe22f5e944">MXC_S_RTC_CTRL_FT_FREQ512HZ</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_FT_FREQ512HZ</div><div class="ttdoc">CTRL_FT_FREQ512HZ Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:187</div></div>
 <div class="ttc" id="structmxc__rtc__regs__t_html"><div class="ttname"><a href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a></div><div class="ttdoc">Structure type to access the RTC Registers. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:88</div></div>
@@ -88,18 +86,16 @@ $(document).ready(function(){initNavTree('rtc_8h_source.html','');});
 <div class="ttc" id="group__rtc_html_ga47027279242aa1332c71ef5923b9ea49"><div class="ttname"><a href="group__rtc.html#ga47027279242aa1332c71ef5923b9ea49">RTC_Init</a></div><div class="ttdeci">int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint16_t ssec, sys_cfg_rtc_t *sys_cfg)</div><div class="ttdoc">Initialize the sec and ssec registers and enable RTC. </div></div>
 <div class="ttc" id="group__rtc_html_gad5a12820a09a49b487eb0c82ffba1689"><div class="ttname"><a href="group__rtc.html#gad5a12820a09a49b487eb0c82ffba1689">RTC_GetTime</a></div><div class="ttdeci">int RTC_GetTime(uint32_t *sec, uint32_t *subsec)</div><div class="ttdoc">Read seconds, then subseconds, and finally seconds. </div></div>
 <div class="ttc" id="group__rtc_html_gaf48f4b08156d9534873dc65d1ab10290"><div class="ttname"><a href="group__rtc.html#gaf48f4b08156d9534873dc65d1ab10290">RTC_GetSecond</a></div><div class="ttdeci">int RTC_GetSecond(void)</div><div class="ttdoc">Get Second. </div></div>
-<div class="ttc" id="group__rtc_html_gaf630f332cfe83aa088aaf8e51f51aeb7"><div class="ttname"><a href="group__rtc.html#gaf630f332cfe83aa088aaf8e51f51aeb7">RTC_SquareWave</a></div><div class="ttdeci">int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft, rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t *sys_cfg)</div><div class="ttdoc">Allow generation of Square Wave on the SQW pin. </div></div>
+<div class="ttc" id="group__rtc_html_ga3ec285956d9017f98476b4a672a6c9a2"><div class="ttname"><a href="group__rtc.html#ga3ec285956d9017f98476b4a672a6c9a2">RTC_SquareWave</a></div><div class="ttdeci">int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft, const sys_cfg_rtc_t *sys_cfg)</div><div class="ttdoc">Allow generation of Square Wave on the SQW pin. </div></div>
 <div class="ttc" id="group__RTC__CTRL_html_gac293dfe46dbd97843ad854b3496df501"><div class="ttname"><a href="group__RTC__CTRL.html#gac293dfe46dbd97843ad854b3496df501">MXC_S_RTC_CTRL_FT_FREQ4KHZ</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_FT_FREQ4KHZ</div><div class="ttdoc">CTRL_FT_FREQ4KHZ Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:189</div></div>
 <div class="ttc" id="group__rtc_html_gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ad545c1c9e01db973cf4e3a44650ee9b0"><div class="ttname"><a href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90ad545c1c9e01db973cf4e3a44650ee9b0">F_512HZ</a></div><div class="ttdoc">512Hz (Compensated) </div><div class="ttdef"><b>Definition:</b> rtc.h:71</div></div>
 <div class="ttc" id="group__rtc_html_ga226746587cdf944f47b0aca73f05ca6d"><div class="ttname"><a href="group__rtc.html#ga226746587cdf944f47b0aca73f05ca6d">RTC_GetSubSecond</a></div><div class="ttdeci">int RTC_GetSubSecond(void)</div><div class="ttdoc">Get SubSecond. </div></div>
 <div class="ttc" id="group__rtc_html_ga1152d2062aceb06bd81067774b4736a8"><div class="ttname"><a href="group__rtc.html#ga1152d2062aceb06bd81067774b4736a8">rtc_sqwave_en_t</a></div><div class="ttdeci">rtc_sqwave_en_t</div><div class="ttdef"><b>Definition:</b> rtc.h:64</div></div>
 <div class="ttc" id="group__rtc_html_ga80d06f8c70e8e7c4237ea04c1a306eb5"><div class="ttname"><a href="group__rtc.html#ga80d06f8c70e8e7c4237ea04c1a306eb5">RTC_Trim</a></div><div class="ttdeci">int RTC_Trim(mxc_rtc_regs_t *rtc, int8_t trm)</div><div class="ttdoc">Set Trim register value. </div></div>
-<div class="ttc" id="group__RTC__CTRL_html_ga3b7dd3ba7d9d95ac8f2bdd4cf1d89166"><div class="ttname"><a href="group__RTC__CTRL.html#ga3b7dd3ba7d9d95ac8f2bdd4cf1d89166">MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP</div><div class="ttdoc">CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:200</div></div>
 <div class="ttc" id="group__rtc_html_gga1152d2062aceb06bd81067774b4736a8aeb42ff04caea8907474bc72d995ba3dc"><div class="ttname"><a href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aeb42ff04caea8907474bc72d995ba3dc">SQUARE_WAVE_ENABLED</a></div><div class="ttdoc">Sq. </div><div class="ttdef"><b>Definition:</b> rtc.h:66</div></div>
 <div class="ttc" id="group__rtc_html_ga8cd2332e3b126d3b36aa96ced6c590ee"><div class="ttname"><a href="group__rtc.html#ga8cd2332e3b126d3b36aa96ced6c590ee">RTC_DisableSubsecondInterrupt</a></div><div class="ttdeci">int RTC_DisableSubsecondInterrupt(mxc_rtc_regs_t *rtc)</div><div class="ttdoc">Disable Sub-Second&amp;#39;s Alarm Interrupt. </div></div>
 <div class="ttc" id="group__RTC__CTRL_html_gada1707e9fe00e1bc7649d1721ab3150e"><div class="ttname"><a href="group__RTC__CTRL.html#gada1707e9fe00e1bc7649d1721ab3150e">MXC_S_RTC_CTRL_FT_FREQ1HZ</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_FT_FREQ1HZ</div><div class="ttdoc">CTRL_FT_FREQ1HZ Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:185</div></div>
 <div class="ttc" id="group__rtc_html_gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a04731f3590d4ccd81b66cdce850de85b"><div class="ttname"><a href="group__rtc.html#gga2fb02dd2a7ccdc4a0600ba88a1fd9e90a04731f3590d4ccd81b66cdce850de85b">F_32KHZ</a></div><div class="ttdoc">32Khz </div><div class="ttdef"><b>Definition:</b> rtc.h:73</div></div>
-<div class="ttc" id="group__RTC__CTRL_html_ga813fb0789bf6c8a7b20242959b1f0ec4"><div class="ttname"><a href="group__RTC__CTRL.html#ga813fb0789bf6c8a7b20242959b1f0ec4">MXC_S_RTC_CTRL_X32KMD_QUIETMODE</a></div><div class="ttdeci">#define MXC_S_RTC_CTRL_X32KMD_QUIETMODE</div><div class="ttdoc">CTRL_X32KMD_QUIETMODE Setting. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:198</div></div>
 <div class="ttc" id="group__rtc_html_ga20a27a15332a491a002690a449340e90"><div class="ttname"><a href="group__rtc.html#ga20a27a15332a491a002690a449340e90">RTC_DisableRTCE</a></div><div class="ttdeci">int RTC_DisableRTCE(mxc_rtc_regs_t *rtc)</div><div class="ttdoc">Disable/Stop the Real Time Clock. </div></div>
 <div class="ttc" id="group__rtc_html_ga2fb02dd2a7ccdc4a0600ba88a1fd9e90"><div class="ttname"><a href="group__rtc.html#ga2fb02dd2a7ccdc4a0600ba88a1fd9e90">rtc_freq_sel_t</a></div><div class="ttdeci">rtc_freq_sel_t</div><div class="ttdef"><b>Definition:</b> rtc.h:69</div></div>
 <div class="ttc" id="group__rtc_html_gga1152d2062aceb06bd81067774b4736a8aef8bf61bae255010f085e7315351cdad"><div class="ttname"><a href="group__rtc.html#gga1152d2062aceb06bd81067774b4736a8aef8bf61bae255010f085e7315351cdad">SQUARE_WAVE_DISABLED</a></div><div class="ttdoc">Sq. </div><div class="ttdef"><b>Definition:</b> rtc.h:65</div></div>
diff --git a/lib/sdk/Documentation/html/rtc__regs_8h_source.html b/lib/sdk/Documentation/html/rtc__regs_8h_source.html
index 55d3ccda357e45d80b325de5b7c8d6421771cc78..236bf00a425b6d0addcbe760c7203fb745882849 100644
--- a/lib/sdk/Documentation/html/rtc__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/rtc__regs_8h_source.html
@@ -71,14 +71,14 @@ $(document).ready(function(){initNavTree('rtc__regs_8h_source.html','');});
 <div class="title">rtc_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _RTC_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _RTC_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a8320d62d31f9e18c6b0b0e0dac31debc">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a8320d62d31f9e18c6b0b0e0dac31debc">sec</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">ssec</a>;                 </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a312f52a6335fbc5d1bfab003689e725f">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a312f52a6335fbc5d1bfab003689e725f">ras</a>;                  </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a0227333293ec30e21fa6663eb80d6ac7">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a0227333293ec30e21fa6663eb80d6ac7">rssa</a>;                 </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#af1b09ede479284ab9df670cccafe9535">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#af1b09ede479284ab9df670cccafe9535">ctrl</a>;                 </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a8998f97220c7d7ca47f73e0e4aa48915">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a8998f97220c7d7ca47f73e0e4aa48915">trim</a>;                 </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a10afd2f5a46148353fa978b1bce5cf6f">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a10afd2f5a46148353fa978b1bce5cf6f">oscctrl</a>;              </div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;} <a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a>;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;<span class="comment">/* Register offsets for module RTC */</span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#gabf0da9eccd92c5ca44ce8db68738b909">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_SEC                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga0b804cf2902effaff65175a61d235de5">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_SSEC                     ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#gaeaf342d90a93fb76c1603ec3516991d7">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_RAS                      ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#gad31af67a2d6af2d6db65ac9ac21043cc">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_RSSA                     ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#gadc7531eecd760886122ea09834c53dcc">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_CTRL                     ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga3daeaab87adcfc4638d566a39fb1f8d1">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_TRIM                     ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga4e8e37868969f014b848abe7f1b5131b">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_OSCCTRL                  ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__RTC__SSEC.html#gab16841aee1aba935eb428d9ed58a471d">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_SSEC_RTSS_POS                        0 </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__RTC__SSEC.html#ga309c0ca5a1b0dd0d7f9dc1999156864a">  122</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_SSEC_RTSS                            ((uint32_t)(0xFFUL &lt;&lt; MXC_F_RTC_SSEC_RTSS_POS)) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__RTC__RAS.html#ga030a8707453a2966b6895c0cf8d48f4c">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_RAS_RAS_POS                          0 </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__RTC__RAS.html#ga39871faa804470b0535105aa1be37b74">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_RAS_RAS                              ((uint32_t)(0xFFFFFUL &lt;&lt; MXC_F_RTC_RAS_RAS_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__RTC__RSSA.html#ga982de3ebfa5d3b08b1df288bdefc1108">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_RSSA_RSSA_POS                        0 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__RTC__RSSA.html#gadf24b1af1a1603f0b56b36ca29d737a5">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_RSSA_RSSA                            ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_RTC_RSSA_RSSA_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga5e2a007a1a8b79746a02fdc27ef518b1">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RTCE_POS                        0 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga75cf17929520d8a3d422786e0b87d835">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RTCE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_RTCE_POS)) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga4642003917efb888b368e025a0add3bd">  158</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ADE_POS                         1 </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gafff8865bbf4c6550f49927512822d05f">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ADE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ADE_POS)) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga78e2041960140868345ed372a591ad28">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ASE_POS                         2 </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaad6db58ff25399908aceb409e128c87c">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ASE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ASE_POS)) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gabc94fb991519330488f0a6e1f22d401e">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_BUSY_POS                        3 </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga26ab37360fc1ab063b0570d07b6cf70e">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_BUSY                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_BUSY_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gab7b4c12ac2fbb19b63f0d15acb3cf12c">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDY_POS                         4 </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gac6add5486d52e65e1a1eaed4b05ff109">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDY                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_RDY_POS)) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0daca279d40bb118a5f74280aaa36ef7">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDYE_POS                        5 </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gab173e7f33e39d14ec8013adf172960c8">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDYE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_RDYE_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaba8f50c55157ea82037f73004d1974d7">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALDF_POS                        6 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga5211e1dd708249fec12c06420e6f4565">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALDF                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ALDF_POS)) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga79b61aad3a8fbb9b960f89af737278bb">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALSF_POS                        7 </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga7d790165ef155bc6e8e0723cb5acdd44">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALSF                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ALSF_POS)) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga6892da58b8b40f643da513fbac55ca82">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_SQE_POS                         8 </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga49bde315f1e839e7a284904436c3c6f7">  180</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_SQE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_SQE_POS)) </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga3275958e07a28d6cb208c7d1fda3f541">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_FT_POS                          9 </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gadd8d440e4b667089d9e8798e323c10c5">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_FT                              ((uint32_t)(0x3UL &lt;&lt; MXC_F_RTC_CTRL_FT_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaf42fa22ae763d2a88a1091f8a2281f47">  184</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_FREQ1HZ                      ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gada1707e9fe00e1bc7649d1721ab3150e">  185</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_FREQ1HZ                      (MXC_V_RTC_CTRL_FT_FREQ1HZ &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gacdf1a87e7dc13232f268f9041910f159">  186</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_FREQ512HZ                    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaaa7f8bd03f0f4d659299abbe22f5e944">  187</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_FREQ512HZ                    (MXC_V_RTC_CTRL_FT_FREQ512HZ &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga25452fdbf7103e331c7378383bf1063b">  188</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_FREQ4KHZ                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gac293dfe46dbd97843ad854b3496df501">  189</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_FREQ4KHZ                     (MXC_V_RTC_CTRL_FT_FREQ4KHZ &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga799e0db731c9ea6cd6ccd27454ebb22c">  190</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_CLKDIV8                      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0a8bb56daf6d48f4e188405632f33824">  191</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_CLKDIV8                      (MXC_V_RTC_CTRL_FT_CLKDIV8 &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0c161d4d10f64b4c493d4367cb56fc52">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_X32KMD_POS                      11 </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga6c4740ff6560947e20c007b402439029">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_X32KMD                          ((uint32_t)(0x3UL &lt;&lt; MXC_F_RTC_CTRL_X32KMD_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga835d22cc6d4a5fa9f5fd27c8692239b1">  195</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE          ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga251f7aa714e7b00d92b3e50ca3777b56">  196</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE          (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE &lt;&lt; MXC_F_RTC_CTRL_X32KMD_POS) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga24791aeed52f2e9c4138984dc9634306">  197</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE                ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga813fb0789bf6c8a7b20242959b1f0ec4">  198</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE                (MXC_V_RTC_CTRL_X32KMD_QUIETMODE &lt;&lt; MXC_F_RTC_CTRL_X32KMD_POS) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gab3e101b8e0d7df775156c73331d25321">  199</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga3b7dd3ba7d9d95ac8f2bdd4cf1d89166">  200</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP    (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP &lt;&lt; MXC_F_RTC_CTRL_X32KMD_POS) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaba7d72ae71e6a28d40d4bf07f8e5e06b">  201</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gac5eec49851d441fae6a188f2b46ab53b">  202</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP      (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP &lt;&lt; MXC_F_RTC_CTRL_X32KMD_POS) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga4739be528909e39a9553acafef0fac35">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_WE_POS                          15 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0c9e6afc326b67689c79a92fdefdbc9a">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_WE                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_WE_POS)) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#ga3e5fe62df8155f0fa9153a451e06207f">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_TRIM_POS                        0 </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#ga86e740da97d1b31153ee646c8a6ce2bc">  216</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_TRIM                            ((uint32_t)(0xFFUL &lt;&lt; MXC_F_RTC_TRIM_TRIM_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#gafea4cd0c0b3ac475a1d4d02cb2c40ca5">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_VBATTMR_POS                     8 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#gae8a3888487e827eb64f789d9ef4e1ad7">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_VBATTMR                         ((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_RTC_TRIM_VBATTMR_POS)) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gac274d2e29b74a2aa5ed123898ddc93d4">  229</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS                0 </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gac02cf3dcdfd69b65ca375d941751ab7a">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_FLITER_EN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga897faa6d3748b63af85075bf9ce05fd7">  232</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS                1 </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga5b7170691c36aacabffc09095b6d4c71">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_IBIAS_SEL                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga6f28dc9b67831f9d5be92f82ca92c549">  235</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_HYST_EN_POS                  2 </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga098602778a702042e0382fbc12ad2169">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_HYST_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_HYST_EN_POS)) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gaa86c524cdfae970ac9e2ce2fb429a2bb">  238</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS                 3 </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga034a87a474d3e22a607b143073f185a4">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_IBIAS_EN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gabdfa13739f8e7dffd1833c8e1ebf7492">  241</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_BYPASS_POS                   4 </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga4583f89840c39829a25caaa601b6b318">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_BYPASS                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_BYPASS_POS)) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga23f75384d51a2fdf4cb4e607f149ca4c">  244</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_32KOUT_POS                   5 </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gae90b1cd240ea3886779ab134f867288e">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_32KOUT                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_32KOUT_POS)) </span></div><div class="line"><a name="l00249"></a><span class="lineno">  249</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00250"></a><span class="lineno">  250</span>&#160;}</div><div class="line"><a name="l00251"></a><span class="lineno">  251</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00252"></a><span class="lineno">  252</span>&#160;</div><div class="line"><a name="l00253"></a><span class="lineno">  253</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RTC_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__rtc__regs__t_html_af1b09ede479284ab9df670cccafe9535"><div class="ttname"><a href="structmxc__rtc__regs__t.html#af1b09ede479284ab9df670cccafe9535">mxc_rtc_regs_t::ctrl</a></div><div class="ttdeci">__IO uint32_t ctrl</div><div class="ttdoc">0x10: RTC CTRL Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:93</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _RTC_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _RTC_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a8320d62d31f9e18c6b0b0e0dac31debc">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a8320d62d31f9e18c6b0b0e0dac31debc">sec</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">ssec</a>;                 </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#ad4a4f5073aea7dcc1a623e0b7e3ca3a5">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#ad4a4f5073aea7dcc1a623e0b7e3ca3a5">toda</a>;                 </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a5b608ffa87981e34088b40bada72144e">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a5b608ffa87981e34088b40bada72144e">sseca</a>;                </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#af1b09ede479284ab9df670cccafe9535">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#af1b09ede479284ab9df670cccafe9535">ctrl</a>;                 </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a8998f97220c7d7ca47f73e0e4aa48915">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a8998f97220c7d7ca47f73e0e4aa48915">trim</a>;                 </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__rtc__regs__t.html#a10afd2f5a46148353fa978b1bce5cf6f">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__rtc__regs__t.html#a10afd2f5a46148353fa978b1bce5cf6f">oscctrl</a>;              </div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;} <a class="code" href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a>;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;<span class="comment">/* Register offsets for module RTC */</span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#gabf0da9eccd92c5ca44ce8db68738b909">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_SEC                      ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga0b804cf2902effaff65175a61d235de5">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_SSEC                     ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga215206e26eff1208f093e3fedfbaf35e">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_TODA                     ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga5498549b108e81e22ae0a9e710906059">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_SSECA                    ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#gadc7531eecd760886122ea09834c53dcc">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_CTRL                     ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga3daeaab87adcfc4638d566a39fb1f8d1">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_TRIM                     ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__RTC__Register__Offsets.html#ga4e8e37868969f014b848abe7f1b5131b">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_RTC_OSCCTRL                  ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__RTC__SSEC.html#gafdaa58b891651572600f9431f43fe3a9">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_SSEC_SSEC_POS                        0 </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__RTC__SSEC.html#gaa638cc42213fa96b0a402679cdcb588a">  122</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_SSEC_SSEC                            ((uint32_t)(0xFFUL &lt;&lt; MXC_F_RTC_SSEC_SSEC_POS)) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__RTC__TODA.html#ga073d96ca04ace269124b9fb109db20fb">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TODA_TOD_ALARM_POS                   0 </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__RTC__TODA.html#gab21e9d34fdffcb561650af11304783ec">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TODA_TOD_ALARM                       ((uint32_t)(0xFFFFFUL &lt;&lt; MXC_F_RTC_TODA_TOD_ALARM_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__RTC__SSECA.html#ga931a51b7b73776149b20f9bcd0e4ef95">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_SSECA_SSEC_ALARM_POS                 0 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__RTC__SSECA.html#ga851dcc91e76b84e2633161f5b34c01d3">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_SSECA_SSEC_ALARM                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_RTC_SSECA_SSEC_ALARM_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga5e2a007a1a8b79746a02fdc27ef518b1">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RTCE_POS                        0 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga75cf17929520d8a3d422786e0b87d835">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RTCE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_RTCE_POS)) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga4642003917efb888b368e025a0add3bd">  158</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ADE_POS                         1 </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gafff8865bbf4c6550f49927512822d05f">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ADE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ADE_POS)) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga78e2041960140868345ed372a591ad28">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ASE_POS                         2 </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaad6db58ff25399908aceb409e128c87c">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ASE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ASE_POS)) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gabc94fb991519330488f0a6e1f22d401e">  164</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_BUSY_POS                        3 </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga26ab37360fc1ab063b0570d07b6cf70e">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_BUSY                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_BUSY_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gab7b4c12ac2fbb19b63f0d15acb3cf12c">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDY_POS                         4 </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gac6add5486d52e65e1a1eaed4b05ff109">  168</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDY                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_RDY_POS)) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0daca279d40bb118a5f74280aaa36ef7">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDYE_POS                        5 </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gab173e7f33e39d14ec8013adf172960c8">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_RDYE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_RDYE_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaba8f50c55157ea82037f73004d1974d7">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALDF_POS                        6 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga5211e1dd708249fec12c06420e6f4565">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALDF                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ALDF_POS)) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga79b61aad3a8fbb9b960f89af737278bb">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALSF_POS                        7 </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga7d790165ef155bc6e8e0723cb5acdd44">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_ALSF                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_ALSF_POS)) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga6892da58b8b40f643da513fbac55ca82">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_SQE_POS                         8 </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga49bde315f1e839e7a284904436c3c6f7">  180</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_SQE                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_SQE_POS)) </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga3275958e07a28d6cb208c7d1fda3f541">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_FT_POS                          9 </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gadd8d440e4b667089d9e8798e323c10c5">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_FT                              ((uint32_t)(0x3UL &lt;&lt; MXC_F_RTC_CTRL_FT_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaf42fa22ae763d2a88a1091f8a2281f47">  184</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_FREQ1HZ                      ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gada1707e9fe00e1bc7649d1721ab3150e">  185</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_FREQ1HZ                      (MXC_V_RTC_CTRL_FT_FREQ1HZ &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gacdf1a87e7dc13232f268f9041910f159">  186</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_FREQ512HZ                    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gaaa7f8bd03f0f4d659299abbe22f5e944">  187</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_FREQ512HZ                    (MXC_V_RTC_CTRL_FT_FREQ512HZ &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga25452fdbf7103e331c7378383bf1063b">  188</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_FREQ4KHZ                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#gac293dfe46dbd97843ad854b3496df501">  189</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_FREQ4KHZ                     (MXC_V_RTC_CTRL_FT_FREQ4KHZ &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga799e0db731c9ea6cd6ccd27454ebb22c">  190</a></span>&#160;<span class="preprocessor"> #define MXC_V_RTC_CTRL_FT_CLKDIV8                      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0a8bb56daf6d48f4e188405632f33824">  191</a></span>&#160;<span class="preprocessor"> #define MXC_S_RTC_CTRL_FT_CLKDIV8                      (MXC_V_RTC_CTRL_FT_CLKDIV8 &lt;&lt; MXC_F_RTC_CTRL_FT_POS) </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga4739be528909e39a9553acafef0fac35">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_WE_POS                          15 </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__RTC__CTRL.html#ga0c9e6afc326b67689c79a92fdefdbc9a">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_CTRL_WE                              ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_CTRL_WE_POS)) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#ga3e5fe62df8155f0fa9153a451e06207f">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_TRIM_POS                        0 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#ga86e740da97d1b31153ee646c8a6ce2bc">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_TRIM                            ((uint32_t)(0xFFUL &lt;&lt; MXC_F_RTC_TRIM_TRIM_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#gad50bc4a4caeccb1acbf1459f7ef5477c">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_VRTC_TMR_POS                    8 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__RTC__TRIM.html#ga2983c625e5b413f542e3503d2f8d5cb6">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_TRIM_VRTC_TMR                        ((uint32_t)(0xFFFFFFUL &lt;&lt; MXC_F_RTC_TRIM_VRTC_TMR_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gabdfa13739f8e7dffd1833c8e1ebf7492">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_BYPASS_POS                   4 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga4583f89840c39829a25caaa601b6b318">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_BYPASS                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_BYPASS_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#ga23f75384d51a2fdf4cb4e607f149ca4c">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_32KOUT_POS                   5 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__RTC__OSCCTRL.html#gae90b1cd240ea3886779ab134f867288e">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_RTC_OSCCTRL_32KOUT                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_RTC_OSCCTRL_32KOUT_POS)) </span></div><div class="line"><a name="l00226"></a><span class="lineno">  226</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00227"></a><span class="lineno">  227</span>&#160;}</div><div class="line"><a name="l00228"></a><span class="lineno">  228</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00229"></a><span class="lineno">  229</span>&#160;</div><div class="line"><a name="l00230"></a><span class="lineno">  230</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _RTC_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__rtc__regs__t_html_ad4a4f5073aea7dcc1a623e0b7e3ca3a5"><div class="ttname"><a href="structmxc__rtc__regs__t.html#ad4a4f5073aea7dcc1a623e0b7e3ca3a5">mxc_rtc_regs_t::toda</a></div><div class="ttdeci">__IO uint32_t toda</div><div class="ttdoc">0x08: RTC TODA Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:91</div></div>
+<div class="ttc" id="structmxc__rtc__regs__t_html_af1b09ede479284ab9df670cccafe9535"><div class="ttname"><a href="structmxc__rtc__regs__t.html#af1b09ede479284ab9df670cccafe9535">mxc_rtc_regs_t::ctrl</a></div><div class="ttdeci">__IO uint32_t ctrl</div><div class="ttdoc">0x10: RTC CTRL Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:93</div></div>
 <div class="ttc" id="structmxc__rtc__regs__t_html"><div class="ttname"><a href="structmxc__rtc__regs__t.html">mxc_rtc_regs_t</a></div><div class="ttdoc">Structure type to access the RTC Registers. </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:88</div></div>
 <div class="ttc" id="structmxc__rtc__regs__t_html_a9450e8a3ca72114d6686bcb46de95584"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a9450e8a3ca72114d6686bcb46de95584">mxc_rtc_regs_t::ssec</a></div><div class="ttdeci">__IO uint32_t ssec</div><div class="ttdoc">0x04: RTC SSEC Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:90</div></div>
 <div class="ttc" id="structmxc__rtc__regs__t_html_a10afd2f5a46148353fa978b1bce5cf6f"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a10afd2f5a46148353fa978b1bce5cf6f">mxc_rtc_regs_t::oscctrl</a></div><div class="ttdeci">__IO uint32_t oscctrl</div><div class="ttdoc">0x18: RTC OSCCTRL Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:95</div></div>
-<div class="ttc" id="structmxc__rtc__regs__t_html_a0227333293ec30e21fa6663eb80d6ac7"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a0227333293ec30e21fa6663eb80d6ac7">mxc_rtc_regs_t::rssa</a></div><div class="ttdeci">__IO uint32_t rssa</div><div class="ttdoc">0x0C: RTC RSSA Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:92</div></div>
+<div class="ttc" id="structmxc__rtc__regs__t_html_a5b608ffa87981e34088b40bada72144e"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a5b608ffa87981e34088b40bada72144e">mxc_rtc_regs_t::sseca</a></div><div class="ttdeci">__IO uint32_t sseca</div><div class="ttdoc">0x0C: RTC SSECA Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:92</div></div>
 <div class="ttc" id="structmxc__rtc__regs__t_html_a8998f97220c7d7ca47f73e0e4aa48915"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a8998f97220c7d7ca47f73e0e4aa48915">mxc_rtc_regs_t::trim</a></div><div class="ttdeci">__IO uint32_t trim</div><div class="ttdoc">0x14: RTC TRIM Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:94</div></div>
 <div class="ttc" id="structmxc__rtc__regs__t_html_a8320d62d31f9e18c6b0b0e0dac31debc"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a8320d62d31f9e18c6b0b0e0dac31debc">mxc_rtc_regs_t::sec</a></div><div class="ttdeci">__IO uint32_t sec</div><div class="ttdoc">0x00: RTC SEC Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:89</div></div>
-<div class="ttc" id="structmxc__rtc__regs__t_html_a312f52a6335fbc5d1bfab003689e725f"><div class="ttname"><a href="structmxc__rtc__regs__t.html#a312f52a6335fbc5d1bfab003689e725f">mxc_rtc_regs_t::ras</a></div><div class="ttdeci">__IO uint32_t ras</div><div class="ttdoc">0x08: RTC RAS Register </div><div class="ttdef"><b>Definition:</b> rtc_regs.h:91</div></div>
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diff --git a/lib/sdk/Documentation/html/spixf_8h_source.html b/lib/sdk/Documentation/html/spixf_8h_source.html
index fc768a82f762760b12796f300b8000fa78a7d65f..aab0ea80d7ac07cd50037a572647e03bc8cc6977 100644
--- a/lib/sdk/Documentation/html/spixf_8h_source.html
+++ b/lib/sdk/Documentation/html/spixf_8h_source.html
@@ -72,61 +72,61 @@ $(document).ready(function(){initNavTree('spixf_8h_source.html','');});
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 <div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* *****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> * $Date: 2018-10-31 10:32:51 -0500 (Wed, 31 Oct 2018) $</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Revision: 38826 $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> **************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#include &quot;mxc_config.h&quot;</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &quot;mxc_sys.h&quot;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;<span class="preprocessor">#include &quot;spixf_regs.h&quot;</span></div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;</div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#ifndef _SPIXF_H_</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#define _SPIXF_H_</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">/***** Definitions *****/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160; 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   spixf_cfg_mode_t   mode;    <span class="comment">//cfg</span></div><div class="line"><a name="l00187"></a><span class="lineno">  187</span>&#160;    spixf_cfg_sspol_t  sspol;</div><div class="line"><a name="l00188"></a><span class="lineno">  188</span>&#160;    uint32_t          baud;</div><div class="line"><a name="l00189"></a><span class="lineno">  189</span>&#160;    spixf_cfg_ssact_t  ssact;</div><div class="line"><a name="l00190"></a><span class="lineno">  190</span>&#160;    spixf_cfg_ssiact_t ssiact;</div><div class="line"><a name="l00191"></a><span class="lineno">  191</span>&#160;    </div><div class="line"><a name="l00192"></a><span class="lineno">  192</span>&#160;    uint8_t            cmdval;  <span class="comment">//fetch_cntl</span></div><div class="line"><a name="l00193"></a><span class="lineno">  193</span>&#160;    spixf_fctl_cmdwth_t cmdwth;</div><div class="line"><a name="l00194"></a><span class="lineno">  194</span>&#160;    spixf_fctl_adrwth_t adrwth;</div><div class="line"><a name="l00195"></a><span class="lineno">  195</span>&#160;    spixf_fctl_datwth_t datwth;</div><div class="line"><a name="l00196"></a><span class="lineno">  196</span>&#160;    spixf_fctl_addr4_t  addr4;</div><div class="line"><a name="l00197"></a><span class="lineno">  197</span>&#160;    </div><div class="line"><a name="l00198"></a><span class="lineno">  198</span>&#160;    uint8_t           mdclk;   <span class="comment">//mode_ctrl</span></div><div class="line"><a name="l00199"></a><span class="lineno">  199</span>&#160;    spixf_mctl_nocmd_t nocmd;</div><div class="line"><a name="l00200"></a><span class="lineno">  200</span>&#160;    </div><div class="line"><a name="l00201"></a><span class="lineno">  201</span>&#160;    uint16_t          mddata;  <span class="comment">//mod_data   </span></div><div class="line"><a name="l00202"></a><span class="lineno">  202</span>&#160;    uint16_t          mdoe;</div><div class="line"><a name="l00203"></a><span class="lineno">  203</span>&#160;    </div><div class="line"><a name="l00204"></a><span class="lineno">  204</span>&#160;    spixf_fctrl_fbmd_t fbmd;    <span class="comment">//fb_ctrl</span></div><div class="line"><a name="l00205"></a><span class="lineno">  205</span>&#160;    spixf_fctrl_finv_t finv;   </div><div class="line"><a name="l00206"></a><span class="lineno">  206</span>&#160;    </div><div class="line"><a name="l00207"></a><span class="lineno">  207</span>&#160;    uint32_t          busidle;</div><div class="line"><a name="l00208"></a><span class="lineno">  208</span>&#160;} <a class="code" href="structspixf__req__t.html">spixf_req_t</a>;</div><div class="line"><a name="l00209"></a><span class="lineno">  209</span>&#160;</div><div class="line"><a name="l00210"></a><span class="lineno">  210</span>&#160;</div><div class="line"><a name="l00211"></a><span class="lineno">  211</span>&#160;</div><div class="line"><a name="l00212"></a><span class="lineno">  212</span>&#160;<span class="comment">/***** Globals *****/</span></div><div class="line"><a name="l00213"></a><span class="lineno">  213</span>&#160;</div><div class="line"><a name="l00214"></a><span class="lineno">  214</span>&#160;<span class="comment">/***** Function Prototypes *****/</span></div><div class="line"><a name="l00215"></a><span class="lineno">  215</span>&#160;</div><div class="line"><a name="l00222"></a><span class="lineno">  222</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__spixf.html#gaafea70e0dada7a720231d29e4992af11">SPIXF_setup</a>(<a class="code" href="structmxc__spixf__regs__t.html">mxc_spixf_regs_t</a> *spixf, <a class="code" href="structspixf__req__t.html">spixf_req_t</a> *req);</div><div class="line"><a name="l00223"></a><span class="lineno">  223</span>&#160;</div><div class="line"><a name="l00224"></a><span class="lineno">  224</span>&#160;</div><div class="line"><a name="l00232"></a><span class="lineno">  232</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__spixf.html#gaf6c7f83876e7ce9c0731c5dc06ba2a25">SPIXF_ioctrl</a>(spixf_ioctl_sclk_t sclk_ds, spixf_ioctl_ss_t ss_ds, </div><div class="line"><a name="l00233"></a><span class="lineno">  233</span>&#160;                 spixf_ioctl_sdio_t sdio_ds, spixf_ioctl_pup_t pupdctrl);</div><div class="line"><a name="l00234"></a><span class="lineno">  234</span>&#160;</div><div class="line"><a name="l00235"></a><span class="lineno">  235</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00236"></a><span class="lineno">  236</span>&#160;}</div><div class="line"><a name="l00237"></a><span class="lineno">  237</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00238"></a><span class="lineno">  238</span>&#160;</div><div class="line"><a name="l00240"></a><span class="lineno">  240</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXF_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="group__spixf_html_gga010adfb744e153c1cd9962b9723aa432a3e8206afe606d1beef96b1e3ab97e549"><div class="ttname"><a href="group__spixf.html#gga010adfb744e153c1cd9962b9723aa432a3e8206afe606d1beef96b1e3ab97e549">SYS_CLOCKS_1</a></div><div class="ttdoc">1 system clocks </div><div class="ttdef"><b>Definition:</b> spixf.h:88</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gad4ab3b45aa23fffe1bfd698f2a565ef3"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gad4ab3b45aa23fffe1bfd698f2a565ef3">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_INVALID Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:204</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gad4ab3b45aa23fffe1bfd698f2a565ef3"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gad4ab3b45aa23fffe1bfd698f2a565ef3">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_INVALID Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:206</div></div>
 <div class="ttc" id="group__spixf_html_gaf6c7f83876e7ce9c0731c5dc06ba2a25"><div class="ttname"><a href="group__spixf.html#gaf6c7f83876e7ce9c0731c5dc06ba2a25">SPIXF_ioctrl</a></div><div class="ttdeci">void SPIXF_ioctrl(spixf_ioctl_sclk_t sclk_ds, spixf_ioctl_ss_t ss_ds, spixf_ioctl_sdio_t sdio_ds, spixf_ioctl_pup_t pupdctrl)</div><div class="ttdoc">Setup Drive Strength on the I/O pins. </div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga6ed49662e2e1e597f6b29372471b7624"><div class="ttname"><a href="group__SPIXF__CFG.html#ga6ed49662e2e1e597f6b29372471b7624">MXC_S_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING</div><div class="ttdoc">CFG_MODE_SCLK_HI_SAMPLE_RISING Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:124</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga6e35b0dfbb238f317e06b38a5fa0f17e"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga6e35b0dfbb238f317e06b38a5fa0f17e">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_INVALID Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:182</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga82b161c3845bce3359b1b5ea71c76f34"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga82b161c3845bce3359b1b5ea71c76f34">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_DUAL_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:189</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga6ed49662e2e1e597f6b29372471b7624"><div class="ttname"><a href="group__SPIXF__CFG.html#ga6ed49662e2e1e597f6b29372471b7624">MXC_S_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING</div><div class="ttdoc">CFG_MODE_SCLK_HI_SAMPLE_RISING Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:126</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga6e35b0dfbb238f317e06b38a5fa0f17e"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga6e35b0dfbb238f317e06b38a5fa0f17e">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_INVALID Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:184</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga82b161c3845bce3359b1b5ea71c76f34"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga82b161c3845bce3359b1b5ea71c76f34">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_DUAL_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:191</div></div>
 <div class="ttc" id="group__spixf_html_ga9b30ee9f22456151b805fa9a8627d765"><div class="ttname"><a href="group__spixf.html#ga9b30ee9f22456151b805fa9a8627d765">spixf_fctl_cmdwth_t</a></div><div class="ttdeci">spixf_fctl_cmdwth_t</div><div class="ttdoc">SPIXF_FETCH_CTRL. </div><div class="ttdef"><b>Definition:</b> spixf.h:99</div></div>
-<div class="ttc" id="group__SPIXF__SCLK__FB__CTRL_html_gaeb19afeac0f94326d3fbd718f8dbc590"><div class="ttname"><a href="group__SPIXF__SCLK__FB__CTRL.html#gaeb19afeac0f94326d3fbd718f8dbc590">MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN</a></div><div class="ttdeci">#define MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN</div><div class="ttdoc">SCLK_FB_CTRL_FB_EN Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:246</div></div>
-<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga7e1b8b9a1e472c8ceab48e10b54ebb2d"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga7e1b8b9a1e472c8ceab48e10b54ebb2d">MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE</a></div><div class="ttdeci">#define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE</div><div class="ttdoc">IO_CTRL_PU_PD_CTRL_TRI_STATE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:277</div></div>
+<div class="ttc" id="group__SPIXF__SCLK__FB__CTRL_html_gaeb19afeac0f94326d3fbd718f8dbc590"><div class="ttname"><a href="group__SPIXF__SCLK__FB__CTRL.html#gaeb19afeac0f94326d3fbd718f8dbc590">MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN</a></div><div class="ttdeci">#define MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN</div><div class="ttdoc">SCLK_FB_CTRL_FB_EN Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:251</div></div>
+<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga7e1b8b9a1e472c8ceab48e10b54ebb2d"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga7e1b8b9a1e472c8ceab48e10b54ebb2d">MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE</a></div><div class="ttdeci">#define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE</div><div class="ttdoc">IO_CTRL_PU_PD_CTRL_TRI_STATE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:282</div></div>
 <div class="ttc" id="group__spixf_html_gac9cf23bafadbbb3d19dec787385cd460"><div class="ttname"><a href="group__spixf.html#gac9cf23bafadbbb3d19dec787385cd460">spixf_fctrl_fbmd_t</a></div><div class="ttdeci">spixf_fctrl_fbmd_t</div><div class="ttdoc">SPIXF_FB_CTRL. </div><div class="ttdef"><b>Definition:</b> spixf.h:143</div></div>
 <div class="ttc" id="structspixf__req__t_html"><div class="ttname"><a href="structspixf__req__t.html">spixf_req_t</a></div><div class="ttdoc">SPIXF Transaction request. </div><div class="ttdef"><b>Definition:</b> spixf.h:185</div></div>
 <div class="ttc" id="group__spixf_html_ga1be91008e482f1ce3a3246e04a6b0bdf"><div class="ttname"><a href="group__spixf.html#ga1be91008e482f1ce3a3246e04a6b0bdf">spixf_fctl_adrwth_t</a></div><div class="ttdeci">spixf_fctl_adrwth_t</div><div class="ttdoc">Addr Width, # of data I/O used to send addr and mode/dummy clks. </div><div class="ttdef"><b>Definition:</b> spixf.h:107</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga0e9388203ba8c4c3725f175463fda7ee"><div class="ttname"><a href="group__SPIXF__CFG.html#ga0e9388203ba8c4c3725f175463fda7ee">MXC_S_SPIXF_CFG_SSACT_FOR_2_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_FOR_2_MOD_CLK</div><div class="ttdoc">CFG_SSACT_FOR_2_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:145</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga0e9388203ba8c4c3725f175463fda7ee"><div class="ttname"><a href="group__SPIXF__CFG.html#ga0e9388203ba8c4c3725f175463fda7ee">MXC_S_SPIXF_CFG_SSACT_FOR_2_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_FOR_2_MOD_CLK</div><div class="ttdoc">CFG_SSACT_FOR_2_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:147</div></div>
 <div class="ttc" id="group__spixf_html_ga010adfb744e153c1cd9962b9723aa432"><div class="ttname"><a href="group__spixf.html#ga010adfb744e153c1cd9962b9723aa432">spixf_cfg_ssiact_t</a></div><div class="ttdeci">spixf_cfg_ssiact_t</div><div class="ttdoc">Slave select Inactive timing. </div><div class="ttdef"><b>Definition:</b> spixf.h:87</div></div>
-<div class="ttc" id="group__SPIXF__SCLK__FB__CTRL_html_ga85684f058c2ea37bb41fbf51d25e5d7e"><div class="ttname"><a href="group__SPIXF__SCLK__FB__CTRL.html#ga85684f058c2ea37bb41fbf51d25e5d7e">MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN</a></div><div class="ttdeci">#define MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN</div><div class="ttdoc">SCLK_FB_CTRL_INVERT_EN Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:249</div></div>
+<div class="ttc" id="group__SPIXF__SCLK__FB__CTRL_html_ga85684f058c2ea37bb41fbf51d25e5d7e"><div class="ttname"><a href="group__SPIXF__SCLK__FB__CTRL.html#ga85684f058c2ea37bb41fbf51d25e5d7e">MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN</a></div><div class="ttdeci">#define MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN</div><div class="ttdoc">SCLK_FB_CTRL_INVERT_EN Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:254</div></div>
 <div class="ttc" id="group__spixf_html_ga2c40425c387ee332498c49297223edde"><div class="ttname"><a href="group__spixf.html#ga2c40425c387ee332498c49297223edde">spixf_ioctl_sclk_t</a></div><div class="ttdeci">spixf_ioctl_sclk_t</div><div class="ttdoc">SPIXF_IOCTRL. </div><div class="ttdef"><b>Definition:</b> spixf.h:159</div></div>
 <div class="ttc" id="group__spixf_html_gaafea70e0dada7a720231d29e4992af11"><div class="ttname"><a href="group__spixf.html#gaafea70e0dada7a720231d29e4992af11">SPIXF_setup</a></div><div class="ttdeci">void SPIXF_setup(mxc_spixf_regs_t *spixf, spixf_req_t *req)</div><div class="ttdoc">Setup SPIXF for Execute in Place. </div></div>
-<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga791f6219c5a3288534aaf45696cdd0f5"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga791f6219c5a3288534aaf45696cdd0f5">MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN</a></div><div class="ttdeci">#define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN</div><div class="ttdoc">IO_CTRL_PU_PD_CTRL_PULL_DOWN Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:281</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gabeebfc737165a60fd0945ba6496709be"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gabeebfc737165a60fd0945ba6496709be">MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR</a></div><div class="ttdeci">#define MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR</div><div class="ttdoc">FETCH_CTRL_FOUR_BYTE_ADDR Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:207</div></div>
+<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga791f6219c5a3288534aaf45696cdd0f5"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga791f6219c5a3288534aaf45696cdd0f5">MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN</a></div><div class="ttdeci">#define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN</div><div class="ttdoc">IO_CTRL_PU_PD_CTRL_PULL_DOWN Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:286</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gabeebfc737165a60fd0945ba6496709be"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gabeebfc737165a60fd0945ba6496709be">MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR</a></div><div class="ttdeci">#define MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR</div><div class="ttdoc">FETCH_CTRL_FOUR_BYTE_ADDR Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:209</div></div>
 <div class="ttc" id="group__spixf_html_gab29f8c1477ef1d18a9a087fc589b843a"><div class="ttname"><a href="group__spixf.html#gab29f8c1477ef1d18a9a087fc589b843a">spixf_ioctl_pup_t</a></div><div class="ttdeci">spixf_ioctl_pup_t</div><div class="ttdoc">IO pullup/pulldown Control. </div><div class="ttdef"><b>Definition:</b> spixf.h:177</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gab96ac2bd564ae6c4ef676e2d1e181266"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gab96ac2bd564ae6c4ef676e2d1e181266">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_SINGLE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:198</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga19a022d7f472afa978848a357d7f6395"><div class="ttname"><a href="group__SPIXF__CFG.html#ga19a022d7f472afa978848a357d7f6395">MXC_S_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_3_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:156</div></div>
-<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga84fb95de1f087d32fd68109a22edbfb5"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga84fb95de1f087d32fd68109a22edbfb5">MXC_F_SPIXF_IO_CTRL_SCLK_DS</a></div><div class="ttdeci">#define MXC_F_SPIXF_IO_CTRL_SCLK_DS</div><div class="ttdoc">IO_CTRL_SCLK_DS Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:266</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga5752386cffe21e5019b588fce786ae2c"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga5752386cffe21e5019b588fce786ae2c">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_DUAL_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:178</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gae0b742877e2f1746e6f47f08de935fb7"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gae0b742877e2f1746e6f47f08de935fb7">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_SINGLE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:176</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gaa215c39da4445a0d821b4d1be5422a0b"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gaa215c39da4445a0d821b4d1be5422a0b">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_QUAD_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:180</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga2f2113d5671aed57027596a6f914e367"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga2f2113d5671aed57027596a6f914e367">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_DUAL_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:200</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga13aeacb36034d70c85dd8673b3bdde4e"><div class="ttname"><a href="group__SPIXF__CFG.html#ga13aeacb36034d70c85dd8673b3bdde4e">MXC_F_SPIXF_CFG_SSPOL</a></div><div class="ttdeci">#define MXC_F_SPIXF_CFG_SSPOL</div><div class="ttdoc">CFG_SSPOL Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:129</div></div>
-<div class="ttc" id="group__SPIXF__MODE__CTRL_html_ga1dcec540b782ed05c494052c2e5b590d"><div class="ttname"><a href="group__SPIXF__MODE__CTRL.html#ga1dcec540b782ed05c494052c2e5b590d">MXC_F_SPIXF_MODE_CTRL_NO_CMD</a></div><div class="ttdeci">#define MXC_F_SPIXF_MODE_CTRL_NO_CMD</div><div class="ttdoc">MODE_CTRL_NO_CMD Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:221</div></div>
-<div class="ttc" id="group__SPIXF__IO__CTRL_html_gab44d76b59945715406e19daae3436e32"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#gab44d76b59945715406e19daae3436e32">MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP</a></div><div class="ttdeci">#define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP</div><div class="ttdoc">IO_CTRL_PU_PD_CTRL_PULL_UP Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:279</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gab96ac2bd564ae6c4ef676e2d1e181266"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gab96ac2bd564ae6c4ef676e2d1e181266">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_SINGLE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:200</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga19a022d7f472afa978848a357d7f6395"><div class="ttname"><a href="group__SPIXF__CFG.html#ga19a022d7f472afa978848a357d7f6395">MXC_S_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_3_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:158</div></div>
+<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga84fb95de1f087d32fd68109a22edbfb5"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga84fb95de1f087d32fd68109a22edbfb5">MXC_F_SPIXF_IO_CTRL_SCLK_DS</a></div><div class="ttdeci">#define MXC_F_SPIXF_IO_CTRL_SCLK_DS</div><div class="ttdoc">IO_CTRL_SCLK_DS Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:271</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga5752386cffe21e5019b588fce786ae2c"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga5752386cffe21e5019b588fce786ae2c">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_DUAL_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:180</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gae0b742877e2f1746e6f47f08de935fb7"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gae0b742877e2f1746e6f47f08de935fb7">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_SINGLE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:178</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_gaa215c39da4445a0d821b4d1be5422a0b"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#gaa215c39da4445a0d821b4d1be5422a0b">MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO</div><div class="ttdoc">FETCH_CTRL_CMD_WIDTH_QUAD_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:182</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga2f2113d5671aed57027596a6f914e367"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga2f2113d5671aed57027596a6f914e367">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_DUAL_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:202</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga13aeacb36034d70c85dd8673b3bdde4e"><div class="ttname"><a href="group__SPIXF__CFG.html#ga13aeacb36034d70c85dd8673b3bdde4e">MXC_F_SPIXF_CFG_SSPOL</a></div><div class="ttdeci">#define MXC_F_SPIXF_CFG_SSPOL</div><div class="ttdoc">CFG_SSPOL Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:131</div></div>
+<div class="ttc" id="group__SPIXF__MODE__CTRL_html_ga1dcec540b782ed05c494052c2e5b590d"><div class="ttname"><a href="group__SPIXF__MODE__CTRL.html#ga1dcec540b782ed05c494052c2e5b590d">MXC_F_SPIXF_MODE_CTRL_NO_CMD</a></div><div class="ttdeci">#define MXC_F_SPIXF_MODE_CTRL_NO_CMD</div><div class="ttdoc">MODE_CTRL_NO_CMD Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:223</div></div>
+<div class="ttc" id="group__SPIXF__IO__CTRL_html_gab44d76b59945715406e19daae3436e32"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#gab44d76b59945715406e19daae3436e32">MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP</a></div><div class="ttdeci">#define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP</div><div class="ttdoc">IO_CTRL_PU_PD_CTRL_PULL_UP Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:284</div></div>
 <div class="ttc" id="group__spixf_html_gafc70f58c37fb440f6063cf90d86e840e"><div class="ttname"><a href="group__spixf.html#gafc70f58c37fb440f6063cf90d86e840e">spixf_cfg_sspol_t</a></div><div class="ttdeci">spixf_cfg_sspol_t</div><div class="ttdoc">Polarity of slave select. </div><div class="ttdef"><b>Definition:</b> spixf.h:73</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga7cb8d9cef579472d211d7cde1bae4e94"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga7cb8d9cef579472d211d7cde1bae4e94">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_INVALID Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:193</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga7cb8d9cef579472d211d7cde1bae4e94"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga7cb8d9cef579472d211d7cde1bae4e94">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_INVALID Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:195</div></div>
 <div class="ttc" id="group__spixf_html_gacf8b4c30444e4ae8970d87779245d902"><div class="ttname"><a href="group__spixf.html#gacf8b4c30444e4ae8970d87779245d902">spixf_cfg_ssact_t</a></div><div class="ttdeci">spixf_cfg_ssact_t</div><div class="ttdoc">Slave select active timing. </div><div class="ttdef"><b>Definition:</b> spixf.h:79</div></div>
-<div class="ttc" id="group__SPIXF__IO__CTRL_html_gaa82f8f63521f065a53133e9cf831919c"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#gaa82f8f63521f065a53133e9cf831919c">MXC_F_SPIXF_IO_CTRL_SDIO_DS</a></div><div class="ttdeci">#define MXC_F_SPIXF_IO_CTRL_SDIO_DS</div><div class="ttdoc">IO_CTRL_SDIO_DS Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:272</div></div>
+<div class="ttc" id="group__SPIXF__IO__CTRL_html_gaa82f8f63521f065a53133e9cf831919c"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#gaa82f8f63521f065a53133e9cf831919c">MXC_F_SPIXF_IO_CTRL_SDIO_DS</a></div><div class="ttdeci">#define MXC_F_SPIXF_IO_CTRL_SDIO_DS</div><div class="ttdoc">IO_CTRL_SDIO_DS Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:277</div></div>
 <div class="ttc" id="group__spixf_html_gga010adfb744e153c1cd9962b9723aa432a7ca57cf66ffda91ebddc59bf0bd86a04"><div class="ttname"><a href="group__spixf.html#gga010adfb744e153c1cd9962b9723aa432a7ca57cf66ffda91ebddc59bf0bd86a04">SYS_CLOCKS_3</a></div><div class="ttdoc">3 system clocks </div><div class="ttdef"><b>Definition:</b> spixf.h:89</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga0b49609db664adc30abc703ad74384ac"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga0b49609db664adc30abc703ad74384ac">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_SINGLE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:187</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga0b49609db664adc30abc703ad74384ac"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga0b49609db664adc30abc703ad74384ac">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_SINGLE Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:189</div></div>
 <div class="ttc" id="group__spixf_html_gabc10b112c0d8e465b5bc4ea0a9c9bc56"><div class="ttname"><a href="group__spixf.html#gabc10b112c0d8e465b5bc4ea0a9c9bc56">spixf_cfg_mode_t</a></div><div class="ttdeci">spixf_cfg_mode_t</div><div class="ttdoc">SPIXF_CFG. </div><div class="ttdef"><b>Definition:</b> spixf.h:67</div></div>
 <div class="ttc" id="structmxc__spixf__regs__t_html"><div class="ttname"><a href="structmxc__spixf__regs__t.html">mxc_spixf_regs_t</a></div><div class="ttdoc">Structure type to access the SPIXF Registers. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:88</div></div>
 <div class="ttc" id="group__spixf_html_gae5685f7faa281b90b992ef52fa118011"><div class="ttname"><a href="group__spixf.html#gae5685f7faa281b90b992ef52fa118011">spixf_mctl_nocmd_t</a></div><div class="ttdeci">spixf_mctl_nocmd_t</div><div class="ttdoc">SPIXF_MODE_CTRL. </div><div class="ttdef"><b>Definition:</b> spixf.h:133</div></div>
 <div class="ttc" id="group__spixf_html_ga4b6a0246eed505970c5bdd0c3793b8c0"><div class="ttname"><a href="group__spixf.html#ga4b6a0246eed505970c5bdd0c3793b8c0">spixf_fctl_datwth_t</a></div><div class="ttdeci">spixf_fctl_datwth_t</div><div class="ttdoc">Data Width, # of data I/O used to rcv data. </div><div class="ttdef"><b>Definition:</b> spixf.h:115</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_gac9d27962a278992b29eab60c623126e6"><div class="ttname"><a href="group__SPIXF__CFG.html#gac9d27962a278992b29eab60c623126e6">MXC_S_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_5_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:158</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga5c890d4f232e2ca4ca3f37b7b6aa2ea6"><div class="ttname"><a href="group__SPIXF__CFG.html#ga5c890d4f232e2ca4ca3f37b7b6aa2ea6">MXC_S_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING</div><div class="ttdoc">CFG_MODE_SCLK_LO_SAMPLE_FAILLING Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:126</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_gac9d27962a278992b29eab60c623126e6"><div class="ttname"><a href="group__SPIXF__CFG.html#gac9d27962a278992b29eab60c623126e6">MXC_S_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_5_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:160</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga5c890d4f232e2ca4ca3f37b7b6aa2ea6"><div class="ttname"><a href="group__SPIXF__CFG.html#ga5c890d4f232e2ca4ca3f37b7b6aa2ea6">MXC_S_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING</div><div class="ttdoc">CFG_MODE_SCLK_LO_SAMPLE_FAILLING Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:128</div></div>
 <div class="ttc" id="group__spixf_html_gacf0b5f83c14772c0d3d8c42dfb3a329a"><div class="ttname"><a href="group__spixf.html#gacf0b5f83c14772c0d3d8c42dfb3a329a">spixf_fctl_addr4_t</a></div><div class="ttdeci">spixf_fctl_addr4_t</div><div class="ttdoc">3 or 4 byte address mode flash </div><div class="ttdef"><b>Definition:</b> spixf.h:123</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga5eed60f17dd21b749ea9f6b4a7d7a906"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga5eed60f17dd21b749ea9f6b4a7d7a906">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_QUAD_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:191</div></div>
-<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga2b320fe6f4442ba6aca39c445001101e"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga2b320fe6f4442ba6aca39c445001101e">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_QUAD_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:202</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga5eed60f17dd21b749ea9f6b4a7d7a906"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga5eed60f17dd21b749ea9f6b4a7d7a906">MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO</div><div class="ttdoc">FETCH_CTRL_ADDR_WIDTH_QUAD_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:193</div></div>
+<div class="ttc" id="group__SPIXF__FETCH__CTRL_html_ga2b320fe6f4442ba6aca39c445001101e"><div class="ttname"><a href="group__SPIXF__FETCH__CTRL.html#ga2b320fe6f4442ba6aca39c445001101e">MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO</a></div><div class="ttdeci">#define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO</div><div class="ttdoc">FETCH_CTRL_DATA_WIDTH_QUAD_IO Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:204</div></div>
 <div class="ttc" id="group__spixf_html_ga682548fc6191526162680bb14290d29e"><div class="ttname"><a href="group__spixf.html#ga682548fc6191526162680bb14290d29e">spixf_ioctl_ss_t</a></div><div class="ttdeci">spixf_ioctl_ss_t</div><div class="ttdoc">Slave Sel. Drive Strength. </div><div class="ttdef"><b>Definition:</b> spixf.h:165</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga780005d14c635b4a8e4a4022ca51b930"><div class="ttname"><a href="group__SPIXF__CFG.html#ga780005d14c635b4a8e4a4022ca51b930">MXC_S_SPIXF_CFG_SSACT_FOR_4_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_FOR_4_MOD_CLK</div><div class="ttdoc">CFG_SSACT_FOR_4_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:147</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga780005d14c635b4a8e4a4022ca51b930"><div class="ttname"><a href="group__SPIXF__CFG.html#ga780005d14c635b4a8e4a4022ca51b930">MXC_S_SPIXF_CFG_SSACT_FOR_4_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_FOR_4_MOD_CLK</div><div class="ttdoc">CFG_SSACT_FOR_4_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:149</div></div>
 <div class="ttc" id="group__spixf_html_gga010adfb744e153c1cd9962b9723aa432a5505b1a67fb53f471e9c559e3b552aac"><div class="ttname"><a href="group__spixf.html#gga010adfb744e153c1cd9962b9723aa432a5505b1a67fb53f471e9c559e3b552aac">SYS_CLOCKS_9</a></div><div class="ttdoc">9 system clocks </div><div class="ttdef"><b>Definition:</b> spixf.h:91</div></div>
 <div class="ttc" id="group__spixf_html_ga8ff57eb8cad638673beede7cf17647ae"><div class="ttname"><a href="group__spixf.html#ga8ff57eb8cad638673beede7cf17647ae">spixf_fctrl_finv_t</a></div><div class="ttdeci">spixf_fctrl_finv_t</div><div class="ttdoc">Feedback clock invert. </div><div class="ttdef"><b>Definition:</b> spixf.h:149</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga289197f2f2bbe69976f91cca856d1037"><div class="ttname"><a href="group__SPIXF__CFG.html#ga289197f2f2bbe69976f91cca856d1037">MXC_S_SPIXF_CFG_SSACT_OFF</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_OFF</div><div class="ttdoc">CFG_SSACT_OFF Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:143</div></div>
-<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga412e73030c77bdd82e15c16e84582c71"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga412e73030c77bdd82e15c16e84582c71">MXC_F_SPIXF_IO_CTRL_SS_DS</a></div><div class="ttdeci">#define MXC_F_SPIXF_IO_CTRL_SS_DS</div><div class="ttdoc">IO_CTRL_SS_DS Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:269</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga289197f2f2bbe69976f91cca856d1037"><div class="ttname"><a href="group__SPIXF__CFG.html#ga289197f2f2bbe69976f91cca856d1037">MXC_S_SPIXF_CFG_SSACT_OFF</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_OFF</div><div class="ttdoc">CFG_SSACT_OFF Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:145</div></div>
+<div class="ttc" id="group__SPIXF__IO__CTRL_html_ga412e73030c77bdd82e15c16e84582c71"><div class="ttname"><a href="group__SPIXF__IO__CTRL.html#ga412e73030c77bdd82e15c16e84582c71">MXC_F_SPIXF_IO_CTRL_SS_DS</a></div><div class="ttdeci">#define MXC_F_SPIXF_IO_CTRL_SS_DS</div><div class="ttdoc">IO_CTRL_SS_DS Mask. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:274</div></div>
 <div class="ttc" id="group__spixf_html_gga010adfb744e153c1cd9962b9723aa432a2b21fe294fc1c70e148cc5fea76161ae"><div class="ttname"><a href="group__spixf.html#gga010adfb744e153c1cd9962b9723aa432a2b21fe294fc1c70e148cc5fea76161ae">SYS_CLOCKS_5</a></div><div class="ttdoc">5 system clocks </div><div class="ttdef"><b>Definition:</b> spixf.h:90</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga9d2de9db0e4bfd7333e7dbcae487ff94"><div class="ttname"><a href="group__SPIXF__CFG.html#ga9d2de9db0e4bfd7333e7dbcae487ff94">MXC_S_SPIXF_CFG_SSACT_FOR_8_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_FOR_8_MOD_CLK</div><div class="ttdoc">CFG_SSACT_FOR_8_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:149</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga667c7daf613c259c5bf9ed45c6b030d9"><div class="ttname"><a href="group__SPIXF__CFG.html#ga667c7daf613c259c5bf9ed45c6b030d9">MXC_S_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_1_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:154</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga9d2de9db0e4bfd7333e7dbcae487ff94"><div class="ttname"><a href="group__SPIXF__CFG.html#ga9d2de9db0e4bfd7333e7dbcae487ff94">MXC_S_SPIXF_CFG_SSACT_FOR_8_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSACT_FOR_8_MOD_CLK</div><div class="ttdoc">CFG_SSACT_FOR_8_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:151</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga667c7daf613c259c5bf9ed45c6b030d9"><div class="ttname"><a href="group__SPIXF__CFG.html#ga667c7daf613c259c5bf9ed45c6b030d9">MXC_S_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_1_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:156</div></div>
 <div class="ttc" id="group__spixf_html_gac8c2e9ed1b722e8e55c7c3a6cb73d854"><div class="ttname"><a href="group__spixf.html#gac8c2e9ed1b722e8e55c7c3a6cb73d854">spixf_ioctl_sdio_t</a></div><div class="ttdeci">spixf_ioctl_sdio_t</div><div class="ttdoc">SDIO Drive Strength. </div><div class="ttdef"><b>Definition:</b> spixf.h:171</div></div>
-<div class="ttc" id="group__SPIXF__CFG_html_ga74a6a58b2049ef86e652a9b2016411cd"><div class="ttname"><a href="group__SPIXF__CFG.html#ga74a6a58b2049ef86e652a9b2016411cd">MXC_S_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_9_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:160</div></div>
+<div class="ttc" id="group__SPIXF__CFG_html_ga74a6a58b2049ef86e652a9b2016411cd"><div class="ttname"><a href="group__SPIXF__CFG.html#ga74a6a58b2049ef86e652a9b2016411cd">MXC_S_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK</a></div><div class="ttdeci">#define MXC_S_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK</div><div class="ttdoc">CFG_SSIACT_FOR_9_MOD_CLK Setting. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:162</div></div>
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diff --git a/lib/sdk/Documentation/html/spixf__regs_8h_source.html b/lib/sdk/Documentation/html/spixf__regs_8h_source.html
index 3a6dbab72d48784bc401f5ae75f25403b70d275f..1110b3578a5209be4d905d53f063b562dee40758 100644
--- a/lib/sdk/Documentation/html/spixf__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/spixf__regs_8h_source.html
@@ -71,8 +71,9 @@ $(document).ready(function(){initNavTree('spixf__regs_8h_source.html','');});
 <div class="title">spixf_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _SPIXF_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _SPIXF_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#a6007ad338bef5054bf155ab858e74ecf">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#a6007ad338bef5054bf155ab858e74ecf">cfg</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#ac90f4cefd271b3a99ddcd695e300c8a4">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#ac90f4cefd271b3a99ddcd695e300c8a4">fetch_ctrl</a>;           </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#a72ec38a58e3ec2863cbe6572357e25a6">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#a72ec38a58e3ec2863cbe6572357e25a6">mode_ctrl</a>;            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#a0a7bba2f4efb96a698fab5e7ea24a5ce">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#a0a7bba2f4efb96a698fab5e7ea24a5ce">mode_data</a>;            </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#aac2e72ecd9b116a5b173ac97fde7f57f">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#aac2e72ecd9b116a5b173ac97fde7f57f">sclk_fb_ctrl</a>;         </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    __R  uint32_t rsv_0x14_0x1b[2];</div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#ad1a60cec6d2bb81d701e3ab3837deaf5">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#ad1a60cec6d2bb81d701e3ab3837deaf5">io_ctrl</a>;              </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#ac371b60a0d855e78325f945c91912b3f">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#ac371b60a0d855e78325f945c91912b3f">memseccn</a>;             </div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;} <a class="code" href="structmxc__spixf__regs__t.html">mxc_spixf_regs_t</a>;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;<span class="comment">/* Register offsets for module SPIXF */</span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga1c1580c3d423e1da95d1ecf0ef06e2fc">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_CFG                    ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#gab755b136be36108101b42d67ec67cd72">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_FETCH_CTRL             ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga5f329ca128ba100840b283e104192700">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_MODE_CTRL              ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#gae1938fd60a95813864497d23ba5c7d27">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_MODE_DATA              ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga9da623ffb00dc8191ba27d11a858708a">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_SCLK_FB_CTRL           ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga40eade3daa7d0aa833b9ec5482964369">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_IO_CTRL                ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga70b69216b6afbeb6a25d6544a9971524">  112</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_MEMSECCN               ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gaf2d57a3439f7d2dbdfd80283dd984a38">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_MODE_POS                       0 </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga0079077ea9284aae79f85e0db80189ed">  122</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_MODE                           ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_CFG_MODE_POS)) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gae599b76d5eb5187aa26c54219975269e">  123</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga6ed49662e2e1e597f6b29372471b7624">  124</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING     (MXC_V_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING &lt;&lt; MXC_F_SPIXF_CFG_MODE_POS) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gabd138b2c532bb5685e10039a7939fdf2">  125</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga5c890d4f232e2ca4ca3f37b7b6aa2ea6">  126</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING   (MXC_V_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING &lt;&lt; MXC_F_SPIXF_CFG_MODE_POS) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga0a7579e95b1ca5a11bc14fabf3d0ea42">  128</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSPOL_POS                      2 </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga13aeacb36034d70c85dd8673b3bdde4e">  129</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSPOL                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_CFG_SSPOL_POS)) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gad8a021b1283e18a88bc0838cd0d1212c">  131</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSEL_POS                       4 </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga8512807e58464a2a3e3b00af23e8e4fc">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSEL                           ((uint32_t)(0x7UL &lt;&lt; MXC_F_SPIXF_CFG_SSEL_POS)) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gaa6d9d9b762d7a1092edb3bb400e8df53">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_LO_CLK_POS                     8 </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga59a6be4c42edd08772293ce25bf2bacf">  135</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_LO_CLK                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXF_CFG_LO_CLK_POS)) </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gad211488cdad0a96fe674579566e28adb">  137</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_HI_CLK_POS                     12 </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga4cf5944e3b9d97e4cbd1a3e538cf335d">  138</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_HI_CLK                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXF_CFG_HI_CLK_POS)) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga31550bcbc169483b2983b67acf6266e3">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSACT_POS                      16 </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga64196abb9a12a6218b67b75b7f263211">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSACT                          ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS)) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga9b8a074ea836ddd0442d18a776b897c5">  142</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_OFF                      ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga289197f2f2bbe69976f91cca856d1037">  143</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_OFF                      (MXC_V_SPIXF_CFG_SSACT_OFF &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga02d3063e556a5dbb0f339de676226219">  144</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_FOR_2_MOD_CLK            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga0e9388203ba8c4c3725f175463fda7ee">  145</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_FOR_2_MOD_CLK            (MXC_V_SPIXF_CFG_SSACT_FOR_2_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga36a664315cbb940f79187421af53af52">  146</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_FOR_4_MOD_CLK            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga780005d14c635b4a8e4a4022ca51b930">  147</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_FOR_4_MOD_CLK            (MXC_V_SPIXF_CFG_SSACT_FOR_4_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga77d5aac2869701e8ac410692222f844d">  148</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_FOR_8_MOD_CLK            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga9d2de9db0e4bfd7333e7dbcae487ff94">  149</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_FOR_8_MOD_CLK            (MXC_V_SPIXF_CFG_SSACT_FOR_8_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gad417937dadb82892b83e2aacffe36d05">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSIACT_POS                     18 </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga26bd6645cf775f23ef4f75fdc66c11a5">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSIACT                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS)) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga33fb8bfd2e6cb7862d82fd1867f12d16">  153</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK           ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga667c7daf613c259c5bf9ed45c6b030d9">  154</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga5ff0af8abaab868be3043e2ae245cf94">  155</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga19a022d7f472afa978848a357d7f6395">  156</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gaffa747b2d8305acbdf898c5dfa938921">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gac9d27962a278992b29eab60c623126e6">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga084fc202f3dd15cf52490d047761b289">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK           ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga74a6a58b2049ef86e652a9b2016411cd">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gab9d274c145991916101196a8a0e4538d">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMDVAL_POS              0 </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaf59a0892cb3b307b3c2085cd2db6226b">  171</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMDVAL                  ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMDVAL_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga0a74b4909bf1fd135f03d56f1bdc8ae3">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS           8 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga7397ad80caf43757a3dcacc577da1134">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH               ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga66fa809d88481a29991ce1f4a8015819">  175</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gae0b742877e2f1746e6f47f08de935fb7">  176</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE        (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga20bdedc7a2b99314687d2b37761dec8a">  177</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO       ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga5752386cffe21e5019b588fce786ae2c">  178</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO       (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga439d2c39941ee493fbb1cd7cb259bedd">  179</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaa215c39da4445a0d821b4d1be5422a0b">  180</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO       (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gac6f47a922f4d26cdb724a7fc3a0988ce">  181</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID       ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga6e35b0dfbb238f317e06b38a5fa0f17e">  182</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID       (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gafcd07f067a70cdb5794e6398bbc81f0f">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS          10 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaec7b03d6b85ec0e62f0ab7cd63ba8544">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH              ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS)) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga642b9230d14cbf5f637f52100803f963">  186</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga0b49609db664adc30abc703ad74384ac">  187</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE       (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gae08660d9cc2dc947d0666ac016cb0cf3">  188</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga82b161c3845bce3359b1b5ea71c76f34">  189</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO      (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga593b77e6daad57ba1c85611b7706e469">  190</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO      ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga5eed60f17dd21b749ea9f6b4a7d7a906">  191</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO      (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga18ff723261de9efd0ecf7e2d81854375">  192</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga7cb8d9cef579472d211d7cde1bae4e94">  193</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID      (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga21af539289650e85ce0bc2fce04d7007">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS          12 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga8f8ea6f3f7dde9a4326724a074786b2b">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH              ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS)) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga6b643dceb8627980b07b95faaca7549b">  197</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gab96ac2bd564ae6c4ef676e2d1e181266">  198</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE       (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaca2b14710561480fafaaeb4a33162628">  199</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga2f2113d5671aed57027596a6f914e367">  200</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO      (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaadc24330688530f37f8304184edcb231">  201</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO      ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga2b320fe6f4442ba6aca39c445001101e">  202</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO      (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gad7a0b8958ca6ecfea236a3a1b8236aab">  203</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gad4ab3b45aa23fffe1bfd698f2a565ef3">  204</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID      (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga55df8351c2bc2cf9858ede1cd28059df">  206</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR_POS      16 </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gabeebfc737165a60fd0945ba6496709be">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) </span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#gaeb624605c998afe086009cc752a05ab1">  217</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_MDCLK_POS                0 </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#ga291a7580b88617cda178be4a7b9340e5">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_MDCLK                    ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXF_MODE_CTRL_MDCLK_POS)) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#gab2c5f199491f54905e886b6cd73532bd">  220</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS               8 </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#ga1dcec540b782ed05c494052c2e5b590d">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_NO_CMD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS)) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#gab4ec343a4968236c1753b57fec20e784">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_DATA_POS                 0 </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#ga3905fe215ace0755865bb6bc434fc447">  232</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_DATA                     ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXF_MODE_DATA_DATA_POS)) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#ga486077e99213e2a158de67b0e08157a2">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_OUT_EN_POS               16 </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#ga0c2b451603a79a02bef1389a92e95d9a">  235</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_OUT_EN                   ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXF_MODE_DATA_OUT_EN_POS)) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#gaf4c3d5d90b8c53520b5e0f54031b389b">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN_POS             0 </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#gaeb19afeac0f94326d3fbd718f8dbc590">  246</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN_POS)) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga918c8b362657dcbbd03ebf9a01df2701">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN_POS         1 </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga85684f058c2ea37bb41fbf51d25e5d7e">  249</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN             ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN_POS)) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#gad81fdab4857ecd870de2ae44da8eb6c1">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_POS       4 </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga343560210c00d87741e6780cadd30758">  252</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS           ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_POS)) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga82b3e260ee9b219237cc7a055a23abd1">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga840777643146ebf57f832ea772c860d3">  255</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_NO_CMD    ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga510423fd082dea8dc21d478915eda605">  265</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SCLK_DS_POS                0 </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga84fb95de1f087d32fd68109a22edbfb5">  266</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SCLK_DS                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_SCLK_DS_POS)) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga3891ae4a6a5b746a498990058e8660c6">  268</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SS_DS_POS                  1 </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga412e73030c77bdd82e15c16e84582c71">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SS_DS                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_SS_DS_POS)) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gad5ad3cdac52b0766d3c8e10ef096a754">  271</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS                2 </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gaa82f8f63521f065a53133e9cf831919c">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SDIO_DS                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS)) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga6e9d99cca415f31d07ba8ce4daf60863">  274</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS             3 </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gafd095f1d327ff383d5902238ab991aed">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL                 ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS)) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gaa109bf6ec701cd0bacd710ca9875b37d">  276</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga7e1b8b9a1e472c8ceab48e10b54ebb2d">  277</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE       (MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga0830f7e82c3b95e12a7c303af600e42a">  278</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP         ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gab44d76b59945715406e19daae3436e32">  279</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP         (MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gae3ad3f1c83650a92f8c96f9927aac5bb">  280</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga791f6219c5a3288534aaf45696cdd0f5">  281</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN       (MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__SPIXF__MEMSECCN.html#ga9e11706516d3d72a8ebe9878b9855de3">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MEMSECCN_DECEN_POS                 0 </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__SPIXF__MEMSECCN.html#ga76b351beb675241b60add0c8e284602a">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MEMSECCN_DECEN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MEMSECCN_DECEN_POS)) </span></div><div class="line"><a name="l00296"></a><span class="lineno">  296</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00297"></a><span class="lineno">  297</span>&#160;}</div><div class="line"><a name="l00298"></a><span class="lineno">  298</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00299"></a><span class="lineno">  299</span>&#160;</div><div class="line"><a name="l00300"></a><span class="lineno">  300</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXF_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__spixf__regs__t_html_ac90f4cefd271b3a99ddcd695e300c8a4"><div class="ttname"><a href="structmxc__spixf__regs__t.html#ac90f4cefd271b3a99ddcd695e300c8a4">mxc_spixf_regs_t::fetch_ctrl</a></div><div class="ttdeci">__IO uint32_t fetch_ctrl</div><div class="ttdoc">0x04: SPIXF FETCH_CTRL Register </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:90</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _SPIXF_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _SPIXF_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#a6007ad338bef5054bf155ab858e74ecf">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#a6007ad338bef5054bf155ab858e74ecf">cfg</a>;                  </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#ac90f4cefd271b3a99ddcd695e300c8a4">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#ac90f4cefd271b3a99ddcd695e300c8a4">fetch_ctrl</a>;           </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#a72ec38a58e3ec2863cbe6572357e25a6">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#a72ec38a58e3ec2863cbe6572357e25a6">mode_ctrl</a>;            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#a0a7bba2f4efb96a698fab5e7ea24a5ce">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#a0a7bba2f4efb96a698fab5e7ea24a5ce">mode_data</a>;            </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#aac2e72ecd9b116a5b173ac97fde7f57f">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#aac2e72ecd9b116a5b173ac97fde7f57f">sclk_fb_ctrl</a>;         </div><div class="line"><a name="l00094"></a><span class="lineno">   94</span>&#160;    __R  uint32_t rsv_0x14_0x1b[2];</div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#ad1a60cec6d2bb81d701e3ab3837deaf5">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#ad1a60cec6d2bb81d701e3ab3837deaf5">io_ctrl</a>;              </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#ac371b60a0d855e78325f945c91912b3f">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#ac371b60a0d855e78325f945c91912b3f">memseccn</a>;             </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__spixf__regs__t.html#adb6d248035b8e5ce0de141816df4d6dc">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixf__regs__t.html#adb6d248035b8e5ce0de141816df4d6dc">bus_idle</a>;             </div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;} <a class="code" href="structmxc__spixf__regs__t.html">mxc_spixf_regs_t</a>;</div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;</div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;<span class="comment">/* Register offsets for module SPIXF */</span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga1c1580c3d423e1da95d1ecf0ef06e2fc">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_CFG                    ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#gab755b136be36108101b42d67ec67cd72">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_FETCH_CTRL             ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga5f329ca128ba100840b283e104192700">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_MODE_CTRL              ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#gae1938fd60a95813864497d23ba5c7d27">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_MODE_DATA              ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga9da623ffb00dc8191ba27d11a858708a">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_SCLK_FB_CTRL           ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga40eade3daa7d0aa833b9ec5482964369">  112</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_IO_CTRL                ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga70b69216b6afbeb6a25d6544a9971524">  113</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_MEMSECCN               ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="group__SPIXF__Register__Offsets.html#ga4810c9ad8281456cb75a401834622df6">  114</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXF_BUS_IDLE               ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gaf2d57a3439f7d2dbdfd80283dd984a38">  123</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_MODE_POS                       0 </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga0079077ea9284aae79f85e0db80189ed">  124</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_MODE                           ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_CFG_MODE_POS)) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gae599b76d5eb5187aa26c54219975269e">  125</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga6ed49662e2e1e597f6b29372471b7624">  126</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING     (MXC_V_SPIXF_CFG_MODE_SCLK_HI_SAMPLE_RISING &lt;&lt; MXC_F_SPIXF_CFG_MODE_POS) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gabd138b2c532bb5685e10039a7939fdf2">  127</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga5c890d4f232e2ca4ca3f37b7b6aa2ea6">  128</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING   (MXC_V_SPIXF_CFG_MODE_SCLK_LO_SAMPLE_FAILLING &lt;&lt; MXC_F_SPIXF_CFG_MODE_POS) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga0a7579e95b1ca5a11bc14fabf3d0ea42">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSPOL_POS                      2 </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga13aeacb36034d70c85dd8673b3bdde4e">  131</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSPOL                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_CFG_SSPOL_POS)) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gad8a021b1283e18a88bc0838cd0d1212c">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSEL_POS                       4 </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga8512807e58464a2a3e3b00af23e8e4fc">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSEL                           ((uint32_t)(0x7UL &lt;&lt; MXC_F_SPIXF_CFG_SSEL_POS)) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gaa6d9d9b762d7a1092edb3bb400e8df53">  136</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_LO_CLK_POS                     8 </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga59a6be4c42edd08772293ce25bf2bacf">  137</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_LO_CLK                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXF_CFG_LO_CLK_POS)) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gad211488cdad0a96fe674579566e28adb">  139</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_HI_CLK_POS                     12 </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga4cf5944e3b9d97e4cbd1a3e538cf335d">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_HI_CLK                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXF_CFG_HI_CLK_POS)) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga31550bcbc169483b2983b67acf6266e3">  142</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSACT_POS                      16 </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga64196abb9a12a6218b67b75b7f263211">  143</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSACT                          ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS)) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga9b8a074ea836ddd0442d18a776b897c5">  144</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_OFF                      ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga289197f2f2bbe69976f91cca856d1037">  145</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_OFF                      (MXC_V_SPIXF_CFG_SSACT_OFF &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga02d3063e556a5dbb0f339de676226219">  146</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_FOR_2_MOD_CLK            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga0e9388203ba8c4c3725f175463fda7ee">  147</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_FOR_2_MOD_CLK            (MXC_V_SPIXF_CFG_SSACT_FOR_2_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga36a664315cbb940f79187421af53af52">  148</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_FOR_4_MOD_CLK            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga780005d14c635b4a8e4a4022ca51b930">  149</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_FOR_4_MOD_CLK            (MXC_V_SPIXF_CFG_SSACT_FOR_4_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga77d5aac2869701e8ac410692222f844d">  150</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSACT_FOR_8_MOD_CLK            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga9d2de9db0e4bfd7333e7dbcae487ff94">  151</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSACT_FOR_8_MOD_CLK            (MXC_V_SPIXF_CFG_SSACT_FOR_8_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSACT_POS) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gad417937dadb82892b83e2aacffe36d05">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSIACT_POS                     18 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga26bd6645cf775f23ef4f75fdc66c11a5">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_CFG_SSIACT                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga33fb8bfd2e6cb7862d82fd1867f12d16">  155</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK           ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga667c7daf613c259c5bf9ed45c6b030d9">  156</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_1_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga5ff0af8abaab868be3043e2ae245cf94">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK           ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga19a022d7f472afa978848a357d7f6395">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_3_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gaffa747b2d8305acbdf898c5dfa938921">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK           ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#gac9d27962a278992b29eab60c623126e6">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_5_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga084fc202f3dd15cf52490d047761b289">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK           ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__SPIXF__CFG.html#ga74a6a58b2049ef86e652a9b2016411cd">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK           (MXC_V_SPIXF_CFG_SSIACT_FOR_9_MOD_CLK &lt;&lt; MXC_F_SPIXF_CFG_SSIACT_POS) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gab9d274c145991916101196a8a0e4538d">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMDVAL_POS              0 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaf59a0892cb3b307b3c2085cd2db6226b">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMDVAL                  ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMDVAL_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga0a74b4909bf1fd135f03d56f1bdc8ae3">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS           8 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga7397ad80caf43757a3dcacc577da1134">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH               ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS)) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga66fa809d88481a29991ce1f4a8015819">  177</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE        ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gae0b742877e2f1746e6f47f08de935fb7">  178</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE        (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_SINGLE &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga20bdedc7a2b99314687d2b37761dec8a">  179</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO       ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga5752386cffe21e5019b588fce786ae2c">  180</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO       (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_DUAL_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga439d2c39941ee493fbb1cd7cb259bedd">  181</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaa215c39da4445a0d821b4d1be5422a0b">  182</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO       (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_QUAD_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gac6f47a922f4d26cdb724a7fc3a0988ce">  183</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID       ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga6e35b0dfbb238f317e06b38a5fa0f17e">  184</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID       (MXC_V_SPIXF_FETCH_CTRL_CMD_WIDTH_INVALID &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_CMD_WIDTH_POS) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gafcd07f067a70cdb5794e6398bbc81f0f">  186</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS          10 </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaec7b03d6b85ec0e62f0ab7cd63ba8544">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH              ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS)) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga642b9230d14cbf5f637f52100803f963">  188</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga0b49609db664adc30abc703ad74384ac">  189</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE       (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_SINGLE &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gae08660d9cc2dc947d0666ac016cb0cf3">  190</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga82b161c3845bce3359b1b5ea71c76f34">  191</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO      (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_DUAL_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga593b77e6daad57ba1c85611b7706e469">  192</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO      ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga5eed60f17dd21b749ea9f6b4a7d7a906">  193</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO      (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_QUAD_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga18ff723261de9efd0ecf7e2d81854375">  194</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga7cb8d9cef579472d211d7cde1bae4e94">  195</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID      (MXC_V_SPIXF_FETCH_CTRL_ADDR_WIDTH_INVALID &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_ADDR_WIDTH_POS) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga21af539289650e85ce0bc2fce04d7007">  197</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS          12 </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga8f8ea6f3f7dde9a4326724a074786b2b">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH              ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS)) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga6b643dceb8627980b07b95faaca7549b">  199</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gab96ac2bd564ae6c4ef676e2d1e181266">  200</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE       (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_SINGLE &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaca2b14710561480fafaaeb4a33162628">  201</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga2f2113d5671aed57027596a6f914e367">  202</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO      (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_DUAL_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gaadc24330688530f37f8304184edcb231">  203</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO      ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga2b320fe6f4442ba6aca39c445001101e">  204</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO      (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_QUAD_IO &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gad7a0b8958ca6ecfea236a3a1b8236aab">  205</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gad4ab3b45aa23fffe1bfd698f2a565ef3">  206</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID      (MXC_V_SPIXF_FETCH_CTRL_DATA_WIDTH_INVALID &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#ga55df8351c2bc2cf9858ede1cd28059df">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR_POS      16 </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__SPIXF__FETCH__CTRL.html#gabeebfc737165a60fd0945ba6496709be">  209</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_FETCH_CTRL_FOUR_BYTE_ADDR_POS)) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#gaeb624605c998afe086009cc752a05ab1">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_MDCLK_POS                0 </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#ga291a7580b88617cda178be4a7b9340e5">  220</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_MDCLK                    ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXF_MODE_CTRL_MDCLK_POS)) </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#gab2c5f199491f54905e886b6cd73532bd">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS               8 </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#ga1dcec540b782ed05c494052c2e5b590d">  223</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_NO_CMD                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS)) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#ga31cf36c4851b11c4ea53d04768a0d1dd">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS            9 </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__CTRL.html#gac39dd7ba7ce6bdd2a0a969bee52729aa">  226</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_CTRL_MODE_SEND                ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS)) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#gab4ec343a4968236c1753b57fec20e784">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_DATA_POS                 0 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#ga3905fe215ace0755865bb6bc434fc447">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_DATA                     ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXF_MODE_DATA_DATA_POS)) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#ga486077e99213e2a158de67b0e08157a2">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_OUT_EN_POS               16 </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__SPIXF__MODE__DATA.html#ga0c2b451603a79a02bef1389a92e95d9a">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MODE_DATA_OUT_EN                   ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXF_MODE_DATA_OUT_EN_POS)) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#gaf4c3d5d90b8c53520b5e0f54031b389b">  250</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN_POS             0 </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#gaeb19afeac0f94326d3fbd718f8dbc590">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_FB_EN_POS)) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga918c8b362657dcbbd03ebf9a01df2701">  253</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN_POS         1 </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga85684f058c2ea37bb41fbf51d25e5d7e">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN             ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_INVERT_EN_POS)) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#gad81fdab4857ecd870de2ae44da8eb6c1">  256</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_POS       4 </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga343560210c00d87741e6780cadd30758">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS           ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_POS)) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga82b3e260ee9b219237cc7a055a23abd1">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS 12 </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__SPIXF__SCLK__FB__CTRL.html#ga840777643146ebf57f832ea772c860d3">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_NO_CMD    ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXF_SCLK_FB_CTRL_IGNORE_CLKS_NO_CMD_POS)) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga510423fd082dea8dc21d478915eda605">  270</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SCLK_DS_POS                0 </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga84fb95de1f087d32fd68109a22edbfb5">  271</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SCLK_DS                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_SCLK_DS_POS)) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga3891ae4a6a5b746a498990058e8660c6">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SS_DS_POS                  1 </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga412e73030c77bdd82e15c16e84582c71">  274</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SS_DS                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_SS_DS_POS)) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gad5ad3cdac52b0766d3c8e10ef096a754">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS                2 </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gaa82f8f63521f065a53133e9cf831919c">  277</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_SDIO_DS                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_SDIO_DS_POS)) </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga6e9d99cca415f31d07ba8ce4daf60863">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS             3 </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gafd095f1d327ff383d5902238ab991aed">  280</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL                 ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS)) </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gaa109bf6ec701cd0bacd710ca9875b37d">  281</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga7e1b8b9a1e472c8ceab48e10b54ebb2d">  282</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE       (MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_TRI_STATE &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga0830f7e82c3b95e12a7c303af600e42a">  283</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP         ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gab44d76b59945715406e19daae3436e32">  284</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP         (MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_UP &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#gae3ad3f1c83650a92f8c96f9927aac5bb">  285</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__SPIXF__IO__CTRL.html#ga791f6219c5a3288534aaf45696cdd0f5">  286</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN       (MXC_V_SPIXF_IO_CTRL_PU_PD_CTRL_PULL_DOWN &lt;&lt; MXC_F_SPIXF_IO_CTRL_PU_PD_CTRL_POS) </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__SPIXF__MEMSECCN.html#ga9e11706516d3d72a8ebe9878b9855de3">  296</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MEMSECCN_DECEN_POS                 0 </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__SPIXF__MEMSECCN.html#ga76b351beb675241b60add0c8e284602a">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MEMSECCN_DECEN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MEMSECCN_DECEN_POS)) </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__SPIXF__MEMSECCN.html#ga7b0672e6dfd0ac3d6ac2eb7a3eb12ef9">  299</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS          1 </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__SPIXF__MEMSECCN.html#ga32b82a2d7de4a644b46febd47b647113">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE              ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS)) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__SPIXF__BUS__IDLE.html#ga383dd31610501ff21fa820e4424b8ed4">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS               0 </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__SPIXF__BUS__IDLE.html#ga7e7635989dd7965a7985bb887c96578d">  311</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXF_BUS_IDLE_BUSIDLE                   ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS)) </span></div><div class="line"><a name="l00315"></a><span class="lineno">  315</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00316"></a><span class="lineno">  316</span>&#160;}</div><div class="line"><a name="l00317"></a><span class="lineno">  317</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00318"></a><span class="lineno">  318</span>&#160;</div><div class="line"><a name="l00319"></a><span class="lineno">  319</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXF_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__spixf__regs__t_html_ac90f4cefd271b3a99ddcd695e300c8a4"><div class="ttname"><a href="structmxc__spixf__regs__t.html#ac90f4cefd271b3a99ddcd695e300c8a4">mxc_spixf_regs_t::fetch_ctrl</a></div><div class="ttdeci">__IO uint32_t fetch_ctrl</div><div class="ttdoc">0x04: SPIXF FETCH_CTRL Register </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:90</div></div>
 <div class="ttc" id="structmxc__spixf__regs__t_html_ad1a60cec6d2bb81d701e3ab3837deaf5"><div class="ttname"><a href="structmxc__spixf__regs__t.html#ad1a60cec6d2bb81d701e3ab3837deaf5">mxc_spixf_regs_t::io_ctrl</a></div><div class="ttdeci">__IO uint32_t io_ctrl</div><div class="ttdoc">0x1C: SPIXF IO_CTRL Register </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:95</div></div>
+<div class="ttc" id="structmxc__spixf__regs__t_html_adb6d248035b8e5ce0de141816df4d6dc"><div class="ttname"><a href="structmxc__spixf__regs__t.html#adb6d248035b8e5ce0de141816df4d6dc">mxc_spixf_regs_t::bus_idle</a></div><div class="ttdeci">__IO uint32_t bus_idle</div><div class="ttdoc">0x24: SPIXF BUS_IDLE Register </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:97</div></div>
 <div class="ttc" id="structmxc__spixf__regs__t_html_a6007ad338bef5054bf155ab858e74ecf"><div class="ttname"><a href="structmxc__spixf__regs__t.html#a6007ad338bef5054bf155ab858e74ecf">mxc_spixf_regs_t::cfg</a></div><div class="ttdeci">__IO uint32_t cfg</div><div class="ttdoc">0x00: SPIXF CFG Register </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:89</div></div>
 <div class="ttc" id="structmxc__spixf__regs__t_html"><div class="ttname"><a href="structmxc__spixf__regs__t.html">mxc_spixf_regs_t</a></div><div class="ttdoc">Structure type to access the SPIXF Registers. </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:88</div></div>
 <div class="ttc" id="structmxc__spixf__regs__t_html_aac2e72ecd9b116a5b173ac97fde7f57f"><div class="ttname"><a href="structmxc__spixf__regs__t.html#aac2e72ecd9b116a5b173ac97fde7f57f">mxc_spixf_regs_t::sclk_fb_ctrl</a></div><div class="ttdeci">__IO uint32_t sclk_fb_ctrl</div><div class="ttdoc">0x10: SPIXF SCLK_FB_CTRL Register </div><div class="ttdef"><b>Definition:</b> spixf_regs.h:93</div></div>
diff --git a/lib/sdk/Documentation/html/spixfc__regs_8h_source.html b/lib/sdk/Documentation/html/spixfc__regs_8h_source.html
index e48269284ff9c917abd45fc7aa49d6e6f54d1fef..9117c419d646200494aa0f331fed7b3b69665ce6 100644
--- a/lib/sdk/Documentation/html/spixfc__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/spixfc__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('spixfc__regs_8h_source.html','');});
 <div class="title">spixfc_regs.h</div>  </div>
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 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _SPIXFC_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _SPIXFC_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a9c26dce1736f1e91cfcb9f84b10090f7">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a9c26dce1736f1e91cfcb9f84b10090f7">config</a>;               </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">ss_pol</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a8e0da2cd9d0235b9b068e3ed43b89662">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a8e0da2cd9d0235b9b068e3ed43b89662">gen_ctrl</a>;             </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a3a558d490dc5854ea9bcd4f48185fce0">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a3a558d490dc5854ea9bcd4f48185fce0">fifo_ctrl</a>;            </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">spctrl</a>;               </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a4c87b0a4aa8969293067bcdeee7ef445">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a4c87b0a4aa8969293067bcdeee7ef445">intfl</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#afa8f13d9d0ee33dc3ef0d427e5229f61">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#afa8f13d9d0ee33dc3ef0d427e5229f61">inten</a>;                </div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;} <a class="code" href="structmxc__spixfc__regs__t.html">mxc_spixfc_regs_t</a>;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;<span class="comment">/* Register offsets for module SPIXFC */</span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#gaea07ca13e2ac24863c9a579694e143c3">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_CONFIG                ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#gaad3d743127dee62f8751bb796bc4c050">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_SS_POL                ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga35d6e8b9b2a33bd9293a555c01bd9123">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_GEN_CTRL              ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#gafb53da46a57d92402655a3d734331b07">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_FIFO_CTRL             ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga04472eb1e845b4e82f73598804ec202b">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_SPCTRL                ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga315f86e8778afb2406ffa2decb91d955">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_INTFL                 ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga28511ddaca951e14a1e527df644ee5e0">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_INTEN                 ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gad36566bf0b0a970adef3681e11b88106">  120</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SSEL_POS                   0 </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga8abe7cd99990301bc96123649d3d7a71">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SSEL                       ((uint32_t)(0x7UL &lt;&lt; MXC_F_SPIXFC_CONFIG_SSEL_POS)) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga53921ebc4b031656b7208ea440baebdc">  122</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_0               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaf7f08d1b3d514f7ef92f3f4004cbe79f">  123</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SSEL_SLAVE_0               (MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_0 &lt;&lt; MXC_F_SPIXFC_CONFIG_SSEL_POS) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gac7a55fb4a8ddae54746aecd53b369a15">  124</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_1               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga949ad2ab72686522c1d43e95fd288ba9">  125</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SSEL_SLAVE_1               (MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_1 &lt;&lt; MXC_F_SPIXFC_CONFIG_SSEL_POS) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga152d1cc17a44965dfe6a31b86a437901">  127</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_MODE_POS                   4 </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga8aa1bd408722e9d44b53e8097f81f9dd">  128</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_MODE                       ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_MODE_POS)) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga7d1f2846cfdfc546ac7fead669d8fd9d">  129</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_0           ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga623951afcfce9ac2f5bedabef2d4a9ea">  130</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_MODE_SPIX_MODE_0           (MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_0 &lt;&lt; MXC_F_SPIXFC_CONFIG_MODE_POS) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga3fdd8504256ec5c173df4c9ebe8b1b81">  131</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_3           ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga2314857cae4d5319b002e0bd3d12b5cc">  132</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_MODE_SPIX_MODE_3           (MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_3 &lt;&lt; MXC_F_SPIXFC_CONFIG_MODE_POS) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaeb43bcc0e3d8ec4d04977d08d6ca1fbe">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS              6 </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga667fb973740be7b5743d72c9760c8a14">  135</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_PAGE_SIZE                  ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS)) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga128fb4bc4cdf382537875c2a9deef101">  136</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES          ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga0a3aad3df9382b4455480c88447bff29">  137</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES          (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga34d2d90b0c6c1817187a6351e2a59f43">  138</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES          ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaab2b61b8cd57eeae1477caf27fad4304">  139</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES          (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga053d2a09267dec94f0db3bf455f0944c">  140</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES         ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga8bf92908616b135156e1732214a329fe">  141</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES         (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga1f570f387d71c40479f904ce6ddf2712">  142</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES         ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga961e0275c2891390cfca5435fce86ed7">  143</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES         (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga82db6eca8e8a1658ccff1d9663be624c">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_HI_CLK_POS                 8 </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga6708aa0c18787524f770d05eb23ee875">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_HI_CLK                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_CONFIG_HI_CLK_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gae95360b500bdeacb52e6eadb24ac99e8">  147</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_HI_CLK_16_SCLK             ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaf6e24de6322ff44d6c23358d36edc53a">  148</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_HI_CLK_16_SCLK             (MXC_V_SPIXFC_CONFIG_HI_CLK_16_SCLK &lt;&lt; MXC_F_SPIXFC_CONFIG_HI_CLK_POS) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaaad4b5914b7b4fa4b21302006d59805a">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_LO_CLK_POS                 12 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga04cb58543db43870962c4a5dbb1d3863">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_LO_CLK                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_CONFIG_LO_CLK_POS)) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga2d6b321afdcafb9b2d42ef812de30730">  152</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_LO_CLK_16_SCLK             ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga81eaa5e8408ccd3e1a157a2522d5535b">  153</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_LO_CLK_16_SCLK             (MXC_V_SPIXFC_CONFIG_LO_CLK_16_SCLK &lt;&lt; MXC_F_SPIXFC_CONFIG_LO_CLK_POS) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaa7b1a202016c8ee1436002800d98116e">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_ACT_POS                 16 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gadf1059e093b5feaafa4ac2f872bda034">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_ACT                     ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga9a3288090aac6fd875a87bb0c895ec0e">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_0_CLKS              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaacf7cb142fc669c16ffe2b0d9dde4a1f">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_0_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_0_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga572a12443284388ccdd0a6149ed27213">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_2_CLKS              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gab32b2f3eac21f546b644144ac3e75110">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_2_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_2_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga016dacaf832487ee35499d6f1642a264">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_4_CLKS              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gad3432819e85eebb5fedb173894dd8533">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_4_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_4_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga2bf59ff70511990bc6f67c4fb1e4fffd">  163</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_8_CLKS              ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaf0ea2057b0422679a998cb4c41c61efc">  164</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_8_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_8_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga519e62a15f9f684b6825afb9f0b4a9bf">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_INACT_POS               18 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga96e6f436dcd2d44812cafbc18f2a439e">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_INACT                   ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS)) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gadbe15676a741f1888ec9455a82f789d3">  168</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_4_CLKS            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga1086ca03213f63ad0ac263e9398df94f">  169</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_4_CLKS            (MXC_V_SPIXFC_CONFIG_SS_INACT_4_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaee99b88229f5bd0219d584f32751acba">  170</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_6_CLKS            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gae95b5540f10a90983f6e4416b2d02c51">  171</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_6_CLKS            (MXC_V_SPIXFC_CONFIG_SS_INACT_6_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga9e993c05c8beaf5b8a96d40ec587fb5b">  172</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_8_CLKS            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaed7060476cf20263f471bcfc45b9b485">  173</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_8_CLKS            (MXC_V_SPIXFC_CONFIG_SS_INACT_8_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gab4a5dcaa3b714f2f234e544ff0d4a80a">  174</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS           ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gabd2725b013c9eab22fc0ee1302590166">  175</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_12_CLKS           (MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__SPIXFC__SS__POL.html#ga9d1752d81a3f3537abc8cd65ec87b032">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SS_POL_SS_POLARITY_POS            0 </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__SPIXFC__SS__POL.html#ga5b595f92127c71252764ed0a225fc0a4">  186</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SS_POL_SS_POLARITY                ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_SS_POL_SS_POLARITY_POS)) </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga1a1d44b2ff579a331f6933423c1be521">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS               0 </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga79ea31c47b28b135f6647ba764830930">  197</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_ENABLE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS)) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga2c9a06ffa5e6c16d9147122211271e74">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS           1 </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gae116d5f3bfc3155f8d1e60d909d22714">  200</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga200e65d8497c8a0d40b62891466fff7c">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS           2 </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gacd18c38e4195fa9d45d1b04d391dfe47">  203</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gafb5d0ec03b4dfad2394483d2e5d21f80">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS               3 </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga6750f92014b8bbf7d84d59506407a34b">  206</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BBMODE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS)) </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga2452de2dfa100a0ab908c4857061a599">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SSDR_POS                 4 </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gadee38c3f8a5d997f88cdf8591c09983d">  209</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SSDR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SSDR_POS)) </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga52237a24d0f659a66015d47c08044f8b">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS              6 </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaad6193aab5e45538dfaa1148083e1150">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS)) </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gab7f47fb5432176911bdbd6f96d823151">  214</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS         8 </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga7b5884b159f84ed78a417ad6b78d2838">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN             ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS)) </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga628476ff108922a68dd4ea66e76128b1">  216</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga56462f18d3c01425c7ccd8795bedc284">  217</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gab18366a2b5f8154ea9bcb73664ee8a73">  218</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1       ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gafcce6ea036722238694013d752759d70">  219</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga906892eca34dbd22a18324838715335d">  220</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga5d268682871cbd3d20501756d49a1afb">  221</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga4e3eefecbe85aaf71ea7e885365916c0">  222</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3       ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gabec0ca4dca3212d14de2bfa32395c3bb">  223</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga651779eb2756f83de3eef1bb20091353">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS              12 </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gabd45c794d180c2e4fb802ecd51632f1a">  226</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA                  ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga0cfa95a93920b7aee75c5315decabdd5">  227</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga0e0b3b289150a81ca1a83b332976f67b">  228</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO0            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaadfbbf8d49343f5db421fd852617d084">  229</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga6aafc7af2e23de31ff04075d17e8b8dd">  230</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO1            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gac9e5728e544b2396995fbd42a44a3c86">  231</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gacd7dea8ade5957a388e41c4916733b16">  232</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO2            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga4d3830882c95fcbffc8f04a467097444">  233</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaa0992bf22a98ef5587491b97f6477f91">  234</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO3            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga83326cd5a8337f60a94b5018e1168048">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS       16 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga8bdb215cdeb0c68f0571286769564603">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN           ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS)) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gab664ccd9908eb237c7fe8274571db3bc">  238</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga52201a403931de42bd299d3eca720e12">  239</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gad762e5aa7319bbd70b11be46e70a0626">  240</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga7f3015a3bc35bce2cb9046a2e2c5fc9c">  241</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga2c4a4fdb270e0d77442a03a21a2a0e17">  242</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaef84b747273545893dbb363c3cae54a2">  243</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga16d872a0b828b6ae088bb26515ffa42c">  244</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga3121d67538aa0a4ac2229dcbf4f515ed">  245</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga5bc076c350b3f52e0ecd85b1c83c2e71">  247</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS              24 </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga767eed2b4cca468c6940dbff2374b2d0">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS)) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga8d1dfdfe6e4f613a92af09425a068a17">  258</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS      0 </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#gad2c68d6d056bea6b657fdc2b77e4a9e6">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL          ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga8f5f260f63a9763b468bb7829195b0de">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS         8 </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga54ffa8ff051e5eac082deafb478dd9e3">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT             ((uint32_t)(0x1FUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga76a7df58aa0078b7a4d991ffeb034343">  264</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS      16 </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#gace917953daab11c52cac9cea93290c77">  265</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL          ((uint32_t)(0x1FUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga4f3ef5f9c4adc2807deebd6a31389067">  267</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS         24 </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga67829d654b28c7a191cded92a51a9d5c">  268</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT             ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gabeea3ce4191040a3dd37409eeb97e909">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS               16 </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gac8c6922683b739695b92fe453f6ede78">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SCLKINH3                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS)) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga924cdda8d74e1aeb45065870ca80bb57">  289</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_STALLED_POS              0 </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga9340c168012e58872febc007ca01fad1">  290</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_TX_STALLED_POS)) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga6a12bfc2106fbeec97a8725d12dd4c75">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_STALLED_POS              1 </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#gacf515393e646f5a48745f0f7697be003">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_RX_STALLED_POS)) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga77ae3cbc6bf22a8cec83d4f30ace0036">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_READY_POS                2 </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga7c65af2eff14dac8d381357f00d97b32">  296</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_READY                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_TX_READY_POS)) </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#gac10f61f6c9680bc8c0bcf2d22302b30c">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_DONE_POS                 3 </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga375daa03fbff1a3ff858a2b70343f453">  299</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_DONE                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_RX_DONE_POS)) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga55cf51601fb27e46705ae7e3731af754">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS              4 </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga9e5656989aa24ba39ef88c1b6c903e01">  302</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS)) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#gac88acf2eaf6da9bf982102617006c168">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS              5 </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga0c586383ba4f2ee05516c56f654dfd4c">  305</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS)) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga2ecc4e309eb2e34bdba5fe028428ac78">  315</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_STALLED_POS              0 </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#gab012b05605721c48220873eaa6e56935">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_TX_STALLED_POS)) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga755d1befb719f68a55476d73b12303dd">  318</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_STALLED_POS              1 </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga4caa994fafb9de76795d8e77272b2803">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_RX_STALLED_POS)) </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga36e8de2dbeb47901c3b0f2f2149ab277">  321</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_READY_POS                2 </span></div><div class="line"><a name="l00322"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#gacc979cda4b5ed9ac4d639d8277291fd0">  322</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_READY                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_TX_READY_POS)) </span></div><div class="line"><a name="l00324"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga4fbb71d97a40adea073e306c9c40d15d">  324</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_DONE_POS                 3 </span></div><div class="line"><a name="l00325"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga4705218202aa4c45d72c68b37cc4596f">  325</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_DONE                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_RX_DONE_POS)) </span></div><div class="line"><a name="l00327"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga88232d1de5116e1bcc987aeacd7f5743">  327</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS              4 </span></div><div class="line"><a name="l00328"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga52067871b9f6ecce4f12e9b778f08766">  328</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS)) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga004e4734f0603ecb4cc4c140547e7aeb">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS              5 </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga0b71d23ece89f20bed6f13b921dd79ca">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS)) </span></div><div class="line"><a name="l00335"></a><span class="lineno">  335</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00336"></a><span class="lineno">  336</span>&#160;}</div><div class="line"><a name="l00337"></a><span class="lineno">  337</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00338"></a><span class="lineno">  338</span>&#160;</div><div class="line"><a name="l00339"></a><span class="lineno">  339</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXFC_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__spixfc__regs__t_html_a4c87b0a4aa8969293067bcdeee7ef445"><div class="ttname"><a href="structmxc__spixfc__regs__t.html#a4c87b0a4aa8969293067bcdeee7ef445">mxc_spixfc_regs_t::intfl</a></div><div class="ttdeci">__IO uint32_t intfl</div><div class="ttdoc">0x14: SPIXFC INTFL Register </div><div class="ttdef"><b>Definition:</b> spixfc_regs.h:94</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _SPIXFC_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _SPIXFC_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a9c26dce1736f1e91cfcb9f84b10090f7">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a9c26dce1736f1e91cfcb9f84b10090f7">config</a>;               </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">ss_pol</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a8e0da2cd9d0235b9b068e3ed43b89662">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a8e0da2cd9d0235b9b068e3ed43b89662">gen_ctrl</a>;             </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a3a558d490dc5854ea9bcd4f48185fce0">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a3a558d490dc5854ea9bcd4f48185fce0">fifo_ctrl</a>;            </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">spctrl</a>;               </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#a4c87b0a4aa8969293067bcdeee7ef445">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#a4c87b0a4aa8969293067bcdeee7ef445">intfl</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__spixfc__regs__t.html#afa8f13d9d0ee33dc3ef0d427e5229f61">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixfc__regs__t.html#afa8f13d9d0ee33dc3ef0d427e5229f61">inten</a>;                </div><div class="line"><a name="l00096"></a><span class="lineno">   96</span>&#160;} <a class="code" href="structmxc__spixfc__regs__t.html">mxc_spixfc_regs_t</a>;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;<span class="comment">/* Register offsets for module SPIXFC */</span></div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#gaea07ca13e2ac24863c9a579694e143c3">  105</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_CONFIG                ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#gaad3d743127dee62f8751bb796bc4c050">  106</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_SS_POL                ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga35d6e8b9b2a33bd9293a555c01bd9123">  107</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_GEN_CTRL              ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#gafb53da46a57d92402655a3d734331b07">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_FIFO_CTRL             ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga04472eb1e845b4e82f73598804ec202b">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_SPCTRL                ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga315f86e8778afb2406ffa2decb91d955">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_INTFL                 ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__SPIXFC__Register__Offsets.html#ga28511ddaca951e14a1e527df644ee5e0">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXFC_INTEN                 ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gad36566bf0b0a970adef3681e11b88106">  120</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SSEL_POS                   0 </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga8abe7cd99990301bc96123649d3d7a71">  121</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SSEL                       ((uint32_t)(0x7UL &lt;&lt; MXC_F_SPIXFC_CONFIG_SSEL_POS)) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga53921ebc4b031656b7208ea440baebdc">  122</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_0               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaf7f08d1b3d514f7ef92f3f4004cbe79f">  123</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SSEL_SLAVE_0               (MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_0 &lt;&lt; MXC_F_SPIXFC_CONFIG_SSEL_POS) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gac7a55fb4a8ddae54746aecd53b369a15">  124</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_1               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga949ad2ab72686522c1d43e95fd288ba9">  125</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SSEL_SLAVE_1               (MXC_V_SPIXFC_CONFIG_SSEL_SLAVE_1 &lt;&lt; MXC_F_SPIXFC_CONFIG_SSEL_POS) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga152d1cc17a44965dfe6a31b86a437901">  127</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_MODE_POS                   4 </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga8aa1bd408722e9d44b53e8097f81f9dd">  128</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_MODE                       ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_MODE_POS)) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga7d1f2846cfdfc546ac7fead669d8fd9d">  129</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_0           ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga623951afcfce9ac2f5bedabef2d4a9ea">  130</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_MODE_SPIX_MODE_0           (MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_0 &lt;&lt; MXC_F_SPIXFC_CONFIG_MODE_POS) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga3fdd8504256ec5c173df4c9ebe8b1b81">  131</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_3           ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga2314857cae4d5319b002e0bd3d12b5cc">  132</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_MODE_SPIX_MODE_3           (MXC_V_SPIXFC_CONFIG_MODE_SPIX_MODE_3 &lt;&lt; MXC_F_SPIXFC_CONFIG_MODE_POS) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaeb43bcc0e3d8ec4d04977d08d6ca1fbe">  134</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS              6 </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga667fb973740be7b5743d72c9760c8a14">  135</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_PAGE_SIZE                  ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS)) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga128fb4bc4cdf382537875c2a9deef101">  136</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES          ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga0a3aad3df9382b4455480c88447bff29">  137</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES          (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_4_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga34d2d90b0c6c1817187a6351e2a59f43">  138</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES          ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaab2b61b8cd57eeae1477caf27fad4304">  139</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES          (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_8_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga053d2a09267dec94f0db3bf455f0944c">  140</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES         ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga8bf92908616b135156e1732214a329fe">  141</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES         (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_16_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00142"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga1f570f387d71c40479f904ce6ddf2712">  142</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES         ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga961e0275c2891390cfca5435fce86ed7">  143</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES         (MXC_V_SPIXFC_CONFIG_PAGE_SIZE_32_BYTES &lt;&lt; MXC_F_SPIXFC_CONFIG_PAGE_SIZE_POS) </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga82db6eca8e8a1658ccff1d9663be624c">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_HI_CLK_POS                 8 </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga6708aa0c18787524f770d05eb23ee875">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_HI_CLK                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_CONFIG_HI_CLK_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gae95360b500bdeacb52e6eadb24ac99e8">  147</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_HI_CLK_16_SCLK             ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaf6e24de6322ff44d6c23358d36edc53a">  148</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_HI_CLK_16_SCLK             (MXC_V_SPIXFC_CONFIG_HI_CLK_16_SCLK &lt;&lt; MXC_F_SPIXFC_CONFIG_HI_CLK_POS) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaaad4b5914b7b4fa4b21302006d59805a">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_LO_CLK_POS                 12 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga04cb58543db43870962c4a5dbb1d3863">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_LO_CLK                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_CONFIG_LO_CLK_POS)) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga2d6b321afdcafb9b2d42ef812de30730">  152</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_LO_CLK_16_SCLK             ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga81eaa5e8408ccd3e1a157a2522d5535b">  153</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_LO_CLK_16_SCLK             (MXC_V_SPIXFC_CONFIG_LO_CLK_16_SCLK &lt;&lt; MXC_F_SPIXFC_CONFIG_LO_CLK_POS) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaa7b1a202016c8ee1436002800d98116e">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_ACT_POS                 16 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gadf1059e093b5feaafa4ac2f872bda034">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_ACT                     ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga9a3288090aac6fd875a87bb0c895ec0e">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_0_CLKS              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaacf7cb142fc669c16ffe2b0d9dde4a1f">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_0_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_0_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga572a12443284388ccdd0a6149ed27213">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_2_CLKS              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gab32b2f3eac21f546b644144ac3e75110">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_2_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_2_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga016dacaf832487ee35499d6f1642a264">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_4_CLKS              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gad3432819e85eebb5fedb173894dd8533">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_4_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_4_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga2bf59ff70511990bc6f67c4fb1e4fffd">  163</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_ACT_8_CLKS              ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaf0ea2057b0422679a998cb4c41c61efc">  164</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_ACT_8_CLKS              (MXC_V_SPIXFC_CONFIG_SS_ACT_8_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_ACT_POS) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga519e62a15f9f684b6825afb9f0b4a9bf">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_INACT_POS               18 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga96e6f436dcd2d44812cafbc18f2a439e">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_SS_INACT                   ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS)) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gadbe15676a741f1888ec9455a82f789d3">  168</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_4_CLKS            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga1086ca03213f63ad0ac263e9398df94f">  169</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_4_CLKS            (MXC_V_SPIXFC_CONFIG_SS_INACT_4_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaee99b88229f5bd0219d584f32751acba">  170</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_6_CLKS            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gae95b5540f10a90983f6e4416b2d02c51">  171</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_6_CLKS            (MXC_V_SPIXFC_CONFIG_SS_INACT_6_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga9e993c05c8beaf5b8a96d40ec587fb5b">  172</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_8_CLKS            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gaed7060476cf20263f471bcfc45b9b485">  173</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_8_CLKS            (MXC_V_SPIXFC_CONFIG_SS_INACT_8_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gab4a5dcaa3b714f2f234e544ff0d4a80a">  174</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS           ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gabd2725b013c9eab22fc0ee1302590166">  175</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_CONFIG_SS_INACT_12_CLKS           (MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS &lt;&lt; MXC_F_SPIXFC_CONFIG_SS_INACT_POS) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#gac74d504d9231746bc49cefa243d250dd">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_IOSMPL_POS                 20 </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__SPIXFC__CONFIG.html#ga7c64c73b1857df74c0cc12d0e6f8f135">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_CONFIG_IOSMPL                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_CONFIG_IOSMPL_POS)) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__SPIXFC__SS__POL.html#ga9d1752d81a3f3537abc8cd65ec87b032">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SS_POL_SS_POLARITY_POS            0 </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__SPIXFC__SS__POL.html#ga5b595f92127c71252764ed0a225fc0a4">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SS_POL_SS_POLARITY                ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_SS_POL_SS_POLARITY_POS)) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga1a1d44b2ff579a331f6933423c1be521">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS               0 </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga79ea31c47b28b135f6647ba764830930">  200</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_ENABLE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_ENABLE_POS)) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga2c9a06ffa5e6c16d9147122211271e74">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS           1 </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gae116d5f3bfc3155f8d1e60d909d22714">  203</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_TX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga200e65d8497c8a0d40b62891466fff7c">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS           2 </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gacd18c38e4195fa9d45d1b04d391dfe47">  206</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN               ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_RX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gafb5d0ec03b4dfad2394483d2e5d21f80">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS               3 </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga6750f92014b8bbf7d84d59506407a34b">  209</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BBMODE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BBMODE_POS)) </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga2452de2dfa100a0ab908c4857061a599">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SSDR_POS                 4 </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gadee38c3f8a5d997f88cdf8591c09983d">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SSDR                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SSDR_POS)) </span></div><div class="line"><a name="l00214"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga52237a24d0f659a66015d47c08044f8b">  214</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS              6 </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaad6193aab5e45538dfaa1148083e1150">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_DR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SCLK_DR_POS)) </span></div><div class="line"><a name="l00217"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gab7f47fb5432176911bdbd6f96d823151">  217</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS         8 </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga7b5884b159f84ed78a417ad6b78d2838">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN             ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS)) </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga628476ff108922a68dd4ea66e76128b1">  219</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0       ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga56462f18d3c01425c7ccd8795bedc284">  220</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO0 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gab18366a2b5f8154ea9bcb73664ee8a73">  221</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1       ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gafcce6ea036722238694013d752759d70">  222</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO1 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga906892eca34dbd22a18324838715335d">  223</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga5d268682871cbd3d20501756d49a1afb">  224</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO2 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga4e3eefecbe85aaf71ea7e885365916c0">  225</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3       ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00226"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gabec0ca4dca3212d14de2bfa32395c3bb">  226</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3       (MXC_V_SPIXFC_GEN_CTRL_SDIO_DATA_IN_SDIO3 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SDIO_DATA_IN_POS) </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga651779eb2756f83de3eef1bb20091353">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS              12 </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gabd45c794d180c2e4fb802ecd51632f1a">  229</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA                  ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga0cfa95a93920b7aee75c5315decabdd5">  230</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga0e0b3b289150a81ca1a83b332976f67b">  231</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO0            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO0 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaadfbbf8d49343f5db421fd852617d084">  232</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga6aafc7af2e23de31ff04075d17e8b8dd">  233</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO1            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO1 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gac9e5728e544b2396995fbd42a44a3c86">  234</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gacd7dea8ade5957a388e41c4916733b16">  235</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO2            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO2 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga4d3830882c95fcbffc8f04a467097444">  236</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaa0992bf22a98ef5587491b97f6477f91">  237</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_SDIO3            (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_SDIO3 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_POS) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga83326cd5a8337f60a94b5018e1168048">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS       16 </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga8bdb215cdeb0c68f0571286769564603">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN           ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS)) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gab664ccd9908eb237c7fe8274571db3bc">  241</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga52201a403931de42bd299d3eca720e12">  242</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO0 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gad762e5aa7319bbd70b11be46e70a0626">  243</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga7f3015a3bc35bce2cb9046a2e2c5fc9c">  244</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO1 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga2c4a4fdb270e0d77442a03a21a2a0e17">  245</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaef84b747273545893dbb363c3cae54a2">  246</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO2 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga16d872a0b828b6ae088bb26515ffa42c">  247</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga3121d67538aa0a4ac2229dcbf4f515ed">  248</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3     (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaef7f0691612c6d823049eb01d72af1a4">  250</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS               20 </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga5d3c4aa7140c781c2ce2a64c48cfc97e">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS)) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaa82399326332c0820222c79258133c4e">  253</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS             21 </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga8e7477fb8933b11eb5e9164f6f5ce7fb">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS)) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gac1be82614a59928257c3bc3dce18aed0">  256</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS               22 </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga400feac06e267fa73d25e650ab0c26ed">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS)) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga5bc076c350b3f52e0ecd85b1c83c2e71">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS              24 </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga767eed2b4cca468c6940dbff2374b2d0">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS)) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#gaad4c03803ea42c014dfd8f1d24e376f5">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS             25 </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__SPIXFC__GEN__CTRL.html#ga677bbeac63a8de9508434d3efd6047f2">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS)) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga8d1dfdfe6e4f613a92af09425a068a17">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS      0 </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#gad2c68d6d056bea6b657fdc2b77e4a9e6">  274</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL          ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_AE_LVL_POS)) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga8f5f260f63a9763b468bb7829195b0de">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS         8 </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga54ffa8ff051e5eac082deafb478dd9e3">  277</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT             ((uint32_t)(0x1FUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_TX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga76a7df58aa0078b7a4d991ffeb034343">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS      16 </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#gace917953daab11c52cac9cea93290c77">  280</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL          ((uint32_t)(0x1FUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_AF_LVL_POS)) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga4f3ef5f9c4adc2807deebd6a31389067">  282</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS         24 </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__SPIXFC__FIFO__CTRL.html#ga67829d654b28c7a191cded92a51a9d5c">  283</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT             ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXFC_FIFO_CTRL_RX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga7d0d6d355ddaebe32c52cd70349b89db">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SAMPL_POS                  0 </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gacd895c1752c7ff306b65cbce7dc89481">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SAMPL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_SPCTRL_SAMPL_POS)) </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga5904d6a5d33ce55586bce59bc600702c">  296</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS                4 </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gaa78289098181770f0b76b55f905aa78c">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SDIOOUT                    ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS)) </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gaf224704d4cc922f3416b59ec378682ef">  298</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO0              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gad7f8626e2f903e63b2fa0d03279f9b1c">  299</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO0              (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO0 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga1d2dbbe71d3a37e5f555751168bf692b">  300</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO1              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gad70521d8033587d12bb8c260407516e7">  301</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO1              (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO1 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) </span></div><div class="line"><a name="l00302"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga0804b614317b8c9462fdde6df1d1af9b">  302</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO2              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga3bfe3ce7bca02aa7768ef4db7bdefb14">  303</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO2              (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO2 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gad45bfc611d31898f1b5324f4df555429">  304</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO3              ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gabdde52cd8b9c72594e6bc8ff7cbcf110">  305</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO3              (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO3 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga98fe85db4a13884a4cb39f316f541893">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SDIOOE_POS                 8 </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga04aad439623fb6cf63e8fb4c9d1ea14b">  308</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SDIOOE                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOE_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga706e7b21d26c1f93b34c7ee044dece95">  309</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO0               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gaaee4a164689c0899008e2997ae5fe375">  310</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO0               (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO0 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gae605f37724bd56e79e6b06ae07cf3883">  311</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO1               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga7cc359250a0b3911becbc6d108d62f40">  312</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO1               (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO1 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga716b17eaa6709f1d5bde325eb6d30f3e">  313</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO2               ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga009b1687cfbfcfff61f5775b0b32c7a1">  314</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO2               (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO2 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gaaa7cf5fe16b7c13ed00d661c41f4e0af">  315</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO3               ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#ga6ca403b324f7d7f5f552d44d89ed8fbe">  316</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO3               (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO3 &lt;&lt; MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gabeea3ce4191040a3dd37409eeb97e909">  318</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS               16 </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__SPIXFC__SPCTRL.html#gac8c6922683b739695b92fe453f6ede78">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_SPCTRL_SCLKINH3                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS)) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga924cdda8d74e1aeb45065870ca80bb57">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_STALLED_POS              0 </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga9340c168012e58872febc007ca01fad1">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_TX_STALLED_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga6a12bfc2106fbeec97a8725d12dd4c75">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_STALLED_POS              1 </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#gacf515393e646f5a48745f0f7697be003">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_RX_STALLED_POS)) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga77ae3cbc6bf22a8cec83d4f30ace0036">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_READY_POS                2 </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga7c65af2eff14dac8d381357f00d97b32">  336</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_READY                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_TX_READY_POS)) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#gac10f61f6c9680bc8c0bcf2d22302b30c">  338</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_DONE_POS                 3 </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga375daa03fbff1a3ff858a2b70343f453">  339</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_DONE                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_RX_DONE_POS)) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga55cf51601fb27e46705ae7e3731af754">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS              4 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga9e5656989aa24ba39ef88c1b6c903e01">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_TX_FIFO_AE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_TX_FIFO_AE_POS)) </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#gac88acf2eaf6da9bf982102617006c168">  344</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS              5 </span></div><div class="line"><a name="l00345"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTFL.html#ga0c586383ba4f2ee05516c56f654dfd4c">  345</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTFL_RX_FIFO_AF                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTFL_RX_FIFO_AF_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga2ecc4e309eb2e34bdba5fe028428ac78">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_STALLED_POS              0 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#gab012b05605721c48220873eaa6e56935">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_TX_STALLED_POS)) </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga755d1befb719f68a55476d73b12303dd">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_STALLED_POS              1 </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga4caa994fafb9de76795d8e77272b2803">  359</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_STALLED                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_RX_STALLED_POS)) </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga36e8de2dbeb47901c3b0f2f2149ab277">  361</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_READY_POS                2 </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#gacc979cda4b5ed9ac4d639d8277291fd0">  362</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_READY                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_TX_READY_POS)) </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga4fbb71d97a40adea073e306c9c40d15d">  364</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_DONE_POS                 3 </span></div><div class="line"><a name="l00365"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga4705218202aa4c45d72c68b37cc4596f">  365</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_DONE                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_RX_DONE_POS)) </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga88232d1de5116e1bcc987aeacd7f5743">  367</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS              4 </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga52067871b9f6ecce4f12e9b778f08766">  368</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_TX_FIFO_AE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_TX_FIFO_AE_POS)) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga004e4734f0603ecb4cc4c140547e7aeb">  370</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS              5 </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__SPIXFC__INTEN.html#ga0b71d23ece89f20bed6f13b921dd79ca">  371</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXFC_INTEN_RX_FIFO_AF                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXFC_INTEN_RX_FIFO_AF_POS)) </span></div><div class="line"><a name="l00375"></a><span class="lineno">  375</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00376"></a><span class="lineno">  376</span>&#160;}</div><div class="line"><a name="l00377"></a><span class="lineno">  377</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00378"></a><span class="lineno">  378</span>&#160;</div><div class="line"><a name="l00379"></a><span class="lineno">  379</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXFC_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__spixfc__regs__t_html_a4c87b0a4aa8969293067bcdeee7ef445"><div class="ttname"><a href="structmxc__spixfc__regs__t.html#a4c87b0a4aa8969293067bcdeee7ef445">mxc_spixfc_regs_t::intfl</a></div><div class="ttdeci">__IO uint32_t intfl</div><div class="ttdoc">0x14: SPIXFC INTFL Register </div><div class="ttdef"><b>Definition:</b> spixfc_regs.h:94</div></div>
 <div class="ttc" id="structmxc__spixfc__regs__t_html_a9aa0d0b2d1502d48acae87caa4d0cf42"><div class="ttname"><a href="structmxc__spixfc__regs__t.html#a9aa0d0b2d1502d48acae87caa4d0cf42">mxc_spixfc_regs_t::ss_pol</a></div><div class="ttdeci">__IO uint32_t ss_pol</div><div class="ttdoc">0x04: SPIXFC SS_POL Register </div><div class="ttdef"><b>Definition:</b> spixfc_regs.h:90</div></div>
 <div class="ttc" id="structmxc__spixfc__regs__t_html_a1d4090f49a3cdf7c021ef0e2f378ae00"><div class="ttname"><a href="structmxc__spixfc__regs__t.html#a1d4090f49a3cdf7c021ef0e2f378ae00">mxc_spixfc_regs_t::spctrl</a></div><div class="ttdeci">__IO uint32_t spctrl</div><div class="ttdoc">0x10: SPIXFC SPCTRL Register </div><div class="ttdef"><b>Definition:</b> spixfc_regs.h:93</div></div>
 <div class="ttc" id="structmxc__spixfc__regs__t_html_afa8f13d9d0ee33dc3ef0d427e5229f61"><div class="ttname"><a href="structmxc__spixfc__regs__t.html#afa8f13d9d0ee33dc3ef0d427e5229f61">mxc_spixfc_regs_t::inten</a></div><div class="ttdeci">__IO uint32_t inten</div><div class="ttdoc">0x18: SPIXFC INTEN Register </div><div class="ttdef"><b>Definition:</b> spixfc_regs.h:95</div></div>
diff --git a/lib/sdk/Documentation/html/spixr_8h_source.html b/lib/sdk/Documentation/html/spixr_8h_source.html
index 4dca8527d7bc269fc4d2c872ef7d9b86a2500435..f150bb0bf0c5bd482908d6398535b0729b32f477 100644
--- a/lib/sdk/Documentation/html/spixr_8h_source.html
+++ b/lib/sdk/Documentation/html/spixr_8h_source.html
@@ -73,7 +73,7 @@ $(document).ready(function(){initNavTree('spixr_8h_source.html','');});
 <div class="contents">
 <div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> * $Date: 2018-09-10 16:20:17 -0500 (Mon, 10 Sep 2018) $</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> * $Revision: 37771 $</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;</div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;<span class="comment">/* Define to prevent redundant inclusion */</span></div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="preprocessor">#ifndef _SPIXR_H_</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#define _SPIXR_H_</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="preprocessor">#include &quot;spixr_regs.h&quot;</span></div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#include &quot;mxc_sys.h&quot;</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160;</div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160;</div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;</div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="group__spixr.html#ga094b949f53b8f95ba11fae8c8860484f">   65</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">enum</span> {</div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;    SPIXR_MONO = <a class="code" href="group__SPIXR__CTRL3.html#gaba9302df431fdb6b27661ed3f0bd5d4a">MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO</a>,</div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;    SPIXR_DUAL = <a class="code" href="group__SPIXR__CTRL3.html#ga501b19f852a94c804f95bd2e193429a7">MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL</a>,</div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;    SPIXR_QUAD = <a class="code" href="group__SPIXR__CTRL3.html#gaa9f6d3afae7396e6b449068083259c6a">MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD</a></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;} <a class="code" href="group__spixr.html#ga094b949f53b8f95ba11fae8c8860484f">spixr_width_t</a>;</div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;</div><div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html">   74</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#a027033a071fde77a803cd81afba8aa56">   75</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#a027033a071fde77a803cd81afba8aa56">ssel</a>;          </div><div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#a464da5fe3565682c18057a5241fe0111">   77</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#a464da5fe3565682c18057a5241fe0111">numbits</a>;       </div><div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#aedbf77a5da7ac1cec9b9655faa9e0c00">   78</a></span>&#160;    spixr_width_t <a class="code" href="structspixr__cfg__t.html#aedbf77a5da7ac1cec9b9655faa9e0c00">data_width</a>;    </div><div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#adb46b0cb8f462bed16b6f797deed8606">   80</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#adb46b0cb8f462bed16b6f797deed8606">ssel_act_1</a>;    </div><div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#a9ed8cf82d3d962e3eb6cfe3e9415b3d3">   81</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#a9ed8cf82d3d962e3eb6cfe3e9415b3d3">ssel_act_2</a>;    </div><div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#a8aa495d0c430dd7ae920c7f80d715ff2">   82</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#a8aa495d0c430dd7ae920c7f80d715ff2">ssel_inact</a>;    </div><div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#a3807380bd59576193e85bccea718c8cf">   84</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#a3807380bd59576193e85bccea718c8cf">baud_freq</a>;     </div><div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="structspixr__cfg__t.html#a66c378f5c62d5ad13a8e644e4b01bb5b">   85</a></span>&#160;    uint32_t <a class="code" href="structspixr__cfg__t.html#a66c378f5c62d5ad13a8e644e4b01bb5b">baud_scale</a>;    </div><div class="line"><a name="l00086"></a><span class="lineno">   86</span>&#160;} <a class="code" href="structspixr__cfg__t.html">spixr_cfg_t</a>;</div><div class="line"><a name="l00087"></a><span class="lineno">   87</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno">   88</span>&#160;</div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;<span class="comment">/* **** Function Prototypes **** */</span></div><div class="line"><a name="l00090"></a><span class="lineno">   90</span>&#160;</div><div class="line"><a name="l00097"></a><span class="lineno">   97</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__spixr.html#ga93e1b158c2218bb8f3b20e38b9b8cbf7">SPIXR_Config</a>(<span class="keyword">const</span> <a class="code" href="structspixr__cfg__t.html">spixr_cfg_t</a>* cfg) ;</div><div class="line"><a name="l00098"></a><span class="lineno">   98</span>&#160;</div><div class="line"><a name="l00103"></a><span class="lineno">  103</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__spixr.html#ga15a640c2edb9eead9cff90b1ce78bd49">SPIXR_Enable</a>(<span class="keyword">const</span> <a class="code" href="structsys__cfg__spixr__t.html">sys_cfg_spixr_t</a>* sys_cfg);</div><div class="line"><a name="l00104"></a><span class="lineno">  104</span>&#160;</div><div class="line"><a name="l00111"></a><span class="lineno">  111</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__spixr.html#ga85b37e14961a1ccc325977186c5ab357">SPIXR_Send_Command</a>(uint8_t* cmd, uint32_t length, uint32_t tx_num_char);</div><div class="line"><a name="l00112"></a><span class="lineno">  112</span>&#160;</div><div class="line"><a name="l00116"></a><span class="lineno">  116</span>&#160;<span class="keywordtype">void</span> <a class="code" href="group__spixr.html#gaa622d2864f1b3a906baf2022a37aa6ef">SPIXR_Disable</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00117"></a><span class="lineno">  117</span>&#160;</div><div class="line"><a name="l00125"></a><span class="lineno">  125</span>&#160;<span class="keywordtype">int</span> <a class="code" href="group__spixr.html#ga947586336fdb05aa71adc1dcc3c10898">SPIXR_Busy</a>(<span class="keywordtype">void</span>);</div><div class="line"><a name="l00126"></a><span class="lineno">  126</span>&#160;</div><div class="line"><a name="l00127"></a><span class="lineno">  127</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00128"></a><span class="lineno">  128</span>&#160;}</div><div class="line"><a name="l00129"></a><span class="lineno">  129</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00130"></a><span class="lineno">  130</span>&#160;</div><div class="line"><a name="l00132"></a><span class="lineno">  132</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXR_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structsys__cfg__spixr__t_html"><div class="ttname"><a href="structsys__cfg__spixr__t.html">sys_cfg_spixr_t</a></div><div class="ttdoc">SPIXR Configuration Object. </div><div class="ttdef"><b>Definition:</b> mxc_sys.h:195</div></div>
 <div class="ttc" id="group__spixr_html_ga15a640c2edb9eead9cff90b1ce78bd49"><div class="ttname"><a href="group__spixr.html#ga15a640c2edb9eead9cff90b1ce78bd49">SPIXR_Enable</a></div><div class="ttdeci">void SPIXR_Enable(const sys_cfg_spixr_t *sys_cfg)</div><div class="ttdoc">Enable the SPI RAM XIP Data module. </div></div>
-<div class="ttc" id="group__SPIXR__CTRL3_html_ga501b19f852a94c804f95bd2e193429a7"><div class="ttname"><a href="group__SPIXR__CTRL3.html#ga501b19f852a94c804f95bd2e193429a7">MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL</a></div><div class="ttdeci">#define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL</div><div class="ttdoc">CTRL3_DATA_WIDTH_DUAL Value. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:253</div></div>
+<div class="ttc" id="group__SPIXR__CTRL3_html_ga501b19f852a94c804f95bd2e193429a7"><div class="ttname"><a href="group__SPIXR__CTRL3.html#ga501b19f852a94c804f95bd2e193429a7">MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL</a></div><div class="ttdeci">#define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL</div><div class="ttdoc">CTRL3_DATA_WIDTH_DUAL Value. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:252</div></div>
 <div class="ttc" id="structspixr__cfg__t_html_a3807380bd59576193e85bccea718c8cf"><div class="ttname"><a href="structspixr__cfg__t.html#a3807380bd59576193e85bccea718c8cf">spixr_cfg_t::baud_freq</a></div><div class="ttdeci">uint32_t baud_freq</div><div class="ttdoc">Desired baud rate duty cycle control. </div><div class="ttdef"><b>Definition:</b> spixr.h:84</div></div>
 <div class="ttc" id="structspixr__cfg__t_html_a464da5fe3565682c18057a5241fe0111"><div class="ttname"><a href="structspixr__cfg__t.html#a464da5fe3565682c18057a5241fe0111">spixr_cfg_t::numbits</a></div><div class="ttdeci">uint32_t numbits</div><div class="ttdoc">Number of Bits per character. </div><div class="ttdef"><b>Definition:</b> spixr.h:77</div></div>
 <div class="ttc" id="structspixr__cfg__t_html_a9ed8cf82d3d962e3eb6cfe3e9415b3d3"><div class="ttname"><a href="structspixr__cfg__t.html#a9ed8cf82d3d962e3eb6cfe3e9415b3d3">spixr_cfg_t::ssel_act_2</a></div><div class="ttdeci">uint32_t ssel_act_2</div><div class="ttdoc">Slave Select Action delay 2. </div><div class="ttdef"><b>Definition:</b> spixr.h:81</div></div>
@@ -81,7 +81,7 @@ $(document).ready(function(){initNavTree('spixr_8h_source.html','');});
 <div class="ttc" id="group__spixr_html_ga85b37e14961a1ccc325977186c5ab357"><div class="ttname"><a href="group__spixr.html#ga85b37e14961a1ccc325977186c5ab357">SPIXR_Send_Command</a></div><div class="ttdeci">void SPIXR_Send_Command(uint8_t *cmd, uint32_t length, uint32_t tx_num_char)</div><div class="ttdoc">Send a SPI formatted instruction to external RAM. </div></div>
 <div class="ttc" id="group__spixr_html_gaa622d2864f1b3a906baf2022a37aa6ef"><div class="ttname"><a href="group__spixr.html#gaa622d2864f1b3a906baf2022a37aa6ef">SPIXR_Disable</a></div><div class="ttdeci">void SPIXR_Disable(void)</div><div class="ttdoc">Disable the SPI RAM XIP Data module. </div></div>
 <div class="ttc" id="structspixr__cfg__t_html_aedbf77a5da7ac1cec9b9655faa9e0c00"><div class="ttname"><a href="structspixr__cfg__t.html#aedbf77a5da7ac1cec9b9655faa9e0c00">spixr_cfg_t::data_width</a></div><div class="ttdeci">spixr_width_t data_width</div><div class="ttdoc">SPI Data width. </div><div class="ttdef"><b>Definition:</b> spixr.h:78</div></div>
-<div class="ttc" id="group__SPIXR__CTRL3_html_gaba9302df431fdb6b27661ed3f0bd5d4a"><div class="ttname"><a href="group__SPIXR__CTRL3.html#gaba9302df431fdb6b27661ed3f0bd5d4a">MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO</a></div><div class="ttdeci">#define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO</div><div class="ttdoc">CTRL3_DATA_WIDTH_MONO Value. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:251</div></div>
+<div class="ttc" id="group__SPIXR__CTRL3_html_gaba9302df431fdb6b27661ed3f0bd5d4a"><div class="ttname"><a href="group__SPIXR__CTRL3.html#gaba9302df431fdb6b27661ed3f0bd5d4a">MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO</a></div><div class="ttdeci">#define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO</div><div class="ttdoc">CTRL3_DATA_WIDTH_MONO Value. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:250</div></div>
 <div class="ttc" id="group__spixr_html_ga93e1b158c2218bb8f3b20e38b9b8cbf7"><div class="ttname"><a href="group__spixr.html#ga93e1b158c2218bb8f3b20e38b9b8cbf7">SPIXR_Config</a></div><div class="ttdeci">int SPIXR_Config(const spixr_cfg_t *cfg)</div><div class="ttdoc">Initialize the SPI RAM XIP Data module. </div></div>
 <div class="ttc" id="group__spixr_html_ga947586336fdb05aa71adc1dcc3c10898"><div class="ttname"><a href="group__spixr.html#ga947586336fdb05aa71adc1dcc3c10898">SPIXR_Busy</a></div><div class="ttdeci">int SPIXR_Busy(void)</div><div class="ttdoc">SPI active status. </div></div>
 <div class="ttc" id="structspixr__cfg__t_html"><div class="ttname"><a href="structspixr__cfg__t.html">spixr_cfg_t</a></div><div class="ttdoc">Structure type for configuring a SPIXR port. </div><div class="ttdef"><b>Definition:</b> spixr.h:74</div></div>
@@ -89,7 +89,7 @@ $(document).ready(function(){initNavTree('spixr_8h_source.html','');});
 <div class="ttc" id="group__spixr_html_ga094b949f53b8f95ba11fae8c8860484f"><div class="ttname"><a href="group__spixr.html#ga094b949f53b8f95ba11fae8c8860484f">spixr_width_t</a></div><div class="ttdeci">spixr_width_t</div><div class="ttdoc">Enum to define SPIXR data width. </div><div class="ttdef"><b>Definition:</b> spixr.h:65</div></div>
 <div class="ttc" id="structspixr__cfg__t_html_adb46b0cb8f462bed16b6f797deed8606"><div class="ttname"><a href="structspixr__cfg__t.html#adb46b0cb8f462bed16b6f797deed8606">spixr_cfg_t::ssel_act_1</a></div><div class="ttdeci">uint32_t ssel_act_1</div><div class="ttdoc">Slave Select Action delay 1. </div><div class="ttdef"><b>Definition:</b> spixr.h:80</div></div>
 <div class="ttc" id="structspixr__cfg__t_html_a66c378f5c62d5ad13a8e644e4b01bb5b"><div class="ttname"><a href="structspixr__cfg__t.html#a66c378f5c62d5ad13a8e644e4b01bb5b">spixr_cfg_t::baud_scale</a></div><div class="ttdeci">uint32_t baud_scale</div><div class="ttdoc">System Clock scale factor. </div><div class="ttdef"><b>Definition:</b> spixr.h:85</div></div>
-<div class="ttc" id="group__SPIXR__CTRL3_html_gaa9f6d3afae7396e6b449068083259c6a"><div class="ttname"><a href="group__SPIXR__CTRL3.html#gaa9f6d3afae7396e6b449068083259c6a">MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD</a></div><div class="ttdeci">#define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD</div><div class="ttdoc">CTRL3_DATA_WIDTH_QUAD Value. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:255</div></div>
+<div class="ttc" id="group__SPIXR__CTRL3_html_gaa9f6d3afae7396e6b449068083259c6a"><div class="ttname"><a href="group__SPIXR__CTRL3.html#gaa9f6d3afae7396e6b449068083259c6a">MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD</a></div><div class="ttdeci">#define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD</div><div class="ttdoc">CTRL3_DATA_WIDTH_QUAD Value. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:254</div></div>
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diff --git a/lib/sdk/Documentation/html/spixr__regs_8h_source.html b/lib/sdk/Documentation/html/spixr__regs_8h_source.html
index 4f5ffc917502c33ef3587b6b5bb70c5e2f08f5e8..b5c62a17b5559b1ed03011aec69225276fce9654 100644
--- a/lib/sdk/Documentation/html/spixr__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/spixr__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('spixr__regs_8h_source.html','');});
 <div class="title">spixr_regs.h</div>  </div>
 </div><!--header-->
 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _SPIXR_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _SPIXR_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;  <span class="keyword">union</span>{</div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#abf4598e6b6401e68b54614250834a231">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#abf4598e6b6401e68b54614250834a231">data32</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a3f2c53c0ee00b0486ed88ee3c1c45481">   91</a></span>&#160;    __IO uint16_t data16[2];            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a903143d87a5110b8d223a093ee28682c">   92</a></span>&#160;    __IO uint8_t  data8[4];             </div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;  };</div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a661e2879ea52ba18153757482845a8f0">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a661e2879ea52ba18153757482845a8f0">ctrl1</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a753c4fc439e94fa35b6d29a6075add3d">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a753c4fc439e94fa35b6d29a6075add3d">ctrl2</a>;                </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a36ae9d4c3d470f49dc519eed1a8ac02a">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a36ae9d4c3d470f49dc519eed1a8ac02a">ctrl3</a>;                </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a6a681c5f9aa124a8105168e58539c1fa">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a6a681c5f9aa124a8105168e58539c1fa">ctrl4</a>;                </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a959af8bccf851f69ace9c85e4d16f930">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a959af8bccf851f69ace9c85e4d16f930">brg_ctrl</a>;             </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a90608b29b3f3212205facf083fc3864e">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a90608b29b3f3212205facf083fc3864e">i2s_ctrl</a>;             </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a22c165cb4836264617f9ca7084933cba">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a22c165cb4836264617f9ca7084933cba">dma</a>;                  </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a0e2efcc6a2ea9a09315cd1bf411f1612">  101</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a0e2efcc6a2ea9a09315cd1bf411f1612">irq</a>;                  </div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a694583dda0ca9d64b70e997c6ed41584">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a694583dda0ca9d64b70e997c6ed41584">irqe</a>;                 </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a8be3ba10d6c326e1e6cf5fb74788032a">  103</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a8be3ba10d6c326e1e6cf5fb74788032a">wake</a>;                 </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#ad3be5055a12fdff0e232874b09de6cf8">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#ad3be5055a12fdff0e232874b09de6cf8">wakee</a>;                </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a483ed058b60736400e947a6abdec6c53">  105</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a483ed058b60736400e947a6abdec6c53">stat</a>;                 </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a5ba44f6f49bfb1e8245abb85bba9a215">  106</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a5ba44f6f49bfb1e8245abb85bba9a215">xmem_ctrl</a>;            </div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;} <a class="code" href="structmxc__spixr__regs__t.html">mxc_spixr_regs_t</a>;</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;<span class="comment">/* Register offsets for module SPIXR */</span></div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga77ca249f0943bf672fd1cdd04937192a">  116</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DATA32                 ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga4a82bbd891d805fe14609e258b8e190c">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DATA16                 ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga2245f24219cbda0313f5b1734907f160">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DATA8                  ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gafd9b6458fa10d014391d8f8e8d8335c7">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL1                  ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gab549c09b4db9177463213627e1ef04df">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL2                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gab66881e95a2dd102d7d3a93f3ac9d08b">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL3                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gab6e44d192d452963b8d9fa153534bf3e">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL4                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga34dc7a0b8cfe6da9c8e21acd06195289">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_BRG_CTRL               ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga225fa8aeed7a6a2c4cc96a723fe989ff">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_I2S_CTRL               ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga2ba4ee6f38355ef4b673983fd00266b9">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DMA                    ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga1e23de67b56bfd1bd520932d58943218">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_IRQ                    ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gae45de56f172b245b29aa20d054cd4e7d">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_IRQE                   ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga3dc6c0a9f4dd702e4dd012fbb2746104">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_WAKE                   ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gacf62a5e692ccc83d18685f20f2e481d0">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_WAKEE                  ((uint32_t)0x0000002CUL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gad1e8a473dc9c65e14721d1e171c3f9b1">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_STAT                   ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gaba9f55bbb4942e12a6a5db141eb2c347">  131</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_XMEM_CTRL              ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA32.html#ga4b1dd303250954863ab8a348fa2bc6f7">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA32_DATA_POS                    0 </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA32.html#ga531b373edff737b81c91043a5ccbccf5">  141</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA32_DATA                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_SPIXR_DATA32_DATA_POS)) </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA16.html#gaf3d78f5ae31c77da60fa6767f46f3f77">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA16_DATA_POS                    0 </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA16.html#ga6dff9c6f72915a3741c911fdf4a5f439">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA16_DATA                        ((uint16_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXR_DATA16_DATA_POS)) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA8.html#gaf44aebbe1c7a8a036d5b89692e818c01">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA8_DATA_POS                     0 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA8.html#ga45f92341eba3f6c6f4964055607540b3">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA8_DATA                         ((uint8_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_DATA8_DATA_POS)) </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga6af08d7796a7b6d40a10f7ed1d33ef25">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SPIEN_POS                    0 </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaca68ef87ef496509156923c8672d32a6">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SPIEN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_SPIEN_POS)) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga75f9f4eeb0d9bd4a522885e456186f46">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_MMEN_POS                     1 </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga8301972e034e1ed03bb564623a1ef4ca">  177</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_MMEN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_MMEN_POS)) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga8db613bd7aceffaa0f55f43f4940f763">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TIMER_POS                    2 </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gab1c2f9f5b552620f056850ff28f05e9c">  180</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TIMER                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_TIMER_POS)) </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga396a0a9436f16be4d71e3b869d197901">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_FL_EN_POS                    3 </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga4e7418304f5cb7193322dca5f1600a81">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_FL_EN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_FL_EN_POS)) </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga43bc0cf64ae352c0b8b55b173348a970">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SSIO_POS                     4 </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga501380edfa099120940d16faa82a887a">  186</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SSIO                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_SSIO_POS)) </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga63125b2fd4257b1ae9d891f5a8a69225">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TX_START_POS                 5 </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga5edd45a6ae27b2c62b95cc9d1d08b238">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TX_START                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_TX_START_POS)) </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaba51d2f85b772d9a40bffb02de3f83d5">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS_CTRL_POS                  8 </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga6ac2a6efe9f68449649fd303ff8f6619">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS_CTRL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga316aa2c295612fcdf2b12217bdfbe186">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS_POS                       16 </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gae38941e2050c4748ed8735ee7d73440f">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS)) </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga6cebe1b5e6c3c92724ab631f50f829f3">  196</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS0                       ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaeffc65d28ebdbff107288ff3218011b2">  197</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS0                       (MXC_V_SPIXR_CTRL1_SS_SS0 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaa081bc7ad90a92e266f486855b642c5a">  198</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS1                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga0a3c0b703797d47e0e276934806b7bb7">  199</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS1                       (MXC_V_SPIXR_CTRL1_SS_SS1 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga3b60a33da53e29a49ed9e033cdda26a8">  200</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS2                       ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga4b2bdd86df5e294db549c35fcb09871b">  201</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS2                       (MXC_V_SPIXR_CTRL1_SS_SS2 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga4e12d58da5bb76286d6d38f1ca7a8d73">  202</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS3                       ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga27c961ace8b4fa58fddde0fed7a3717e">  203</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS3                       (MXC_V_SPIXR_CTRL1_SS_SS3 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gad98c8e52732fccc0fa901e325a2ff019">  204</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS4                       ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga9743590eaba724cfb97439ccc411b8ab">  205</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS4                       (MXC_V_SPIXR_CTRL1_SS_SS4 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga41de92d188048fd049b9368c88d0ae00">  206</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS5                       ((uint32_t)0x20UL) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga2e3a36d0d73eea6ce3e6c46a667f9b3a">  207</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS5                       (MXC_V_SPIXR_CTRL1_SS_SS5 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaf314bcd4edc109509fffca1c326941e9">  208</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS6                       ((uint32_t)0x40UL) </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga566e758be6777d6fed3632e55d3536af">  209</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS6                       (MXC_V_SPIXR_CTRL1_SS_SS6 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gad466a63522d06a875de28a9811de4076">  210</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS7                       ((uint32_t)0x80UL) </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga50bcf0801ae69c68fff96693c25666bf">  211</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS7                       (MXC_V_SPIXR_CTRL1_SS_SS7 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#gacbaf336870e0f9944c02b11016d04680">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS              0 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#ga6aa252309c06b310871d2433fc556f24">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR                  ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#gaa1eac4780438e4be68b131ea91de488c">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS              16 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#ga3f58d343e5b6d73fce0ac3d6b06bcd76">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR                  ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga4b11876ecc25a8e6c1bc27fc2fcf674d">  235</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPHA_POS                     0 </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gabba68fca9dfce649faf1b5fdb021ed3b">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPHA                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_CPHA_POS)) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga6f162efd235f31ff5d8ccca8cf0b9a02">  238</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPOL_POS                     1 </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gadbc104c1bedc25c733e5d1998f345931">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPOL                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_CPOL_POS)) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga8fe5e0f6d447c59c7022bd6d1939ad11">  241</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS              4 </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gab275a86417de6b198e5916a7f35264b7">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS)) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga91b76b94078c0301bd192e57fece5f81">  244</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_NUMBITS_POS                  8 </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga729307f82aa327acc538033bdc169653">  245</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_NUMBITS                      ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXR_CTRL3_NUMBITS_POS)) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga209a660bc1850b69be1b7a267aa43174">  246</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_NUMBITS_0                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga5a02872e3d7ce0b41e850766016ab853">  247</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_NUMBITS_0                    (MXC_V_SPIXR_CTRL3_NUMBITS_0 &lt;&lt; MXC_F_SPIXR_CTRL3_NUMBITS_POS) </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga3f826806f8db0b293b8fae158ed40a0b">  249</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS               12 </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga5ed09cdf6961712e29b1d0885ef7d5bc">  250</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_DATA_WIDTH                   ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaba9302df431fdb6b27661ed3f0bd5d4a">  251</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gac1e5159330e80ab5d779868045f169cf">  252</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO              (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga501b19f852a94c804f95bd2e193429a7">  253</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga1f1814f269ea319019fb7c716994ab61">  254</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL              (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaa9f6d3afae7396e6b449068083259c6a">  255</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga27c19862a4ed143d1298c254c9930aab">  256</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD              (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaee1916a80ad335df0fd57af11ebf67dd">  258</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_THREE_WIRE_POS               15 </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga9c2a6765dcde506f7bd03e6b939a941e">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_THREE_WIRE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga7d846b606f417e6f2c391acd6a657712">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SSPOL_POS                    16 </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga1c55886ba52368b84921648499f5d859">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SSPOL                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS)) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga954fecde54aa7785b70b59331de248e9">  263</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga3c8a6c82ee20d08c3d16053f3251c784">  264</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS0_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga18b1e549f43eaa0dd9793c9ff4764960">  265</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH               ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaeb671a7a0b983b08ab67ee699f6d5659">  266</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS1_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gae98c3ecf9f45d63cc8cbd12946a8ab26">  267</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH               ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gae51ccf558348cdc0815aa9d008400d9d">  268</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS2_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaa6f25fa3068747b72185c49767d23867">  269</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH               ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga6744e5d12841e8d77ad65e59be8b5c48">  270</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS3_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga72a1096a5051e718e0a447645019af78">  271</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH               ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gad3dbfc4e70c697e2bb87830fbdc1d7bf">  272</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS4_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gad653055ce5f36383aadf895c34b5c4ef">  273</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH               ((uint32_t)0x20UL) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gab5f499c8237af114d7d5a00e656e75a4">  274</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS5_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gabed03f10abacbd7cb8e7a2edc5ba9adc">  275</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH               ((uint32_t)0x40UL) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga981a55d835fec6bb5eca323dca8c24c3">  276</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS6_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaef7b39213d1c82bb2f1f7f001204af48">  277</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH               ((uint32_t)0x80UL) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga37ad300c017e8efc94c78d33cf7483be">  278</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS7_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gab99ec1f1073ede8b666d903262866ac0">  280</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SRPOL_POS                    24 </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga4e6ce15c0e564868edb8335270aff247">  281</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SRPOL                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS)) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga42efc7feacb08e9ad0d9c5be2527987e">  282</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR0_HIGH               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga9cc16f6c311c258c2bf29a17f4fd5a0f">  283</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR0_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR0_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga27391242e97710218f7985b7ad87b5bb">  284</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR1_HIGH               ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gafd324d2b2a0ce2dd9f124af08559c1cf">  285</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR1_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR1_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga811be40e45b40a745e074b538b711103">  286</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR2_HIGH               ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga20d0537695d194d743b5704a619b1d58">  287</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR2_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR2_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga40eb988d5a5c7e80ccc3974fdbeed0c6">  288</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR3_HIGH               ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga5d004182ea285e49b85960b9725700a9">  289</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR3_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR3_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga4d03d4efd01cc92cc601ee8e3c7d8414">  290</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR4_HIGH               ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga3efe941b5cba9c1bbd2827d2897f336e">  291</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR4_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR4_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gae0d55b7b27f72fb3a96c8afefe0f2676">  292</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR5_HIGH               ((uint32_t)0x20UL) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga4416802dbafc9c2c28417a08ccd8d0d8">  293</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR5_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR5_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga0335f7abdd7191e050a16cc61d344f5f">  294</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR6_HIGH               ((uint32_t)0x40UL) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gae88526136a84549ab21229380592afe9">  295</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR6_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR6_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00296"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga1667ba9f7616f10f4abdbd6393f0b4af">  296</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SRPOL_SR7_HIGH               ((uint32_t)0x80UL) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga08a4ffdea8a0b704ea4efd32282d71dc">  297</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SRPOL_SR7_HIGH               (MXC_V_SPIXR_CTRL3_SRPOL_SR7_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SRPOL_POS) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga8b96a1f5d931b27ee39582a3d535b7b7">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT1_POS                   0 </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#gabddce60f80d67c1cb4cbc48a640b12fc">  308</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT1                       ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT1_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga3cd012031bd7500799d7efefc919a8fe">  309</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL4_SSACT1_256                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga33aff3c83748fcf75662203940754168">  310</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL4_SSACT1_256                   (MXC_V_SPIXR_CTRL4_SSACT1_256 &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT1_POS) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga3051ad2d70a93006d8f94412db6a29b3">  312</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT2_POS                   8 </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga25de22ff0df30637b2f984645723ae73">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT2                       ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT2_POS)) </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#gac89da83cb7e17cb66e245a6eb90002a2">  314</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL4_SSACT2_256                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga4b3f54b8b47d2fb53a9f92cc8ad54744">  315</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL4_SSACT2_256                   (MXC_V_SPIXR_CTRL4_SSACT2_256 &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT2_POS) </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga396fbae7be78ccde37b1f26443548424">  317</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSINACT_POS                  16 </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga1b00d04fc0af11b712d40286f890b069">  318</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSINACT                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL4_SSINACT_POS)) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga8da20ed89bb89edd59129b1f2a65a476">  319</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL4_SSINACT_256                  ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#gad706155c448a59d2cfd193600a8ee115">  320</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL4_SSINACT_256                  (MXC_V_SPIXR_CTRL4_SSINACT_256 &lt;&lt; MXC_F_SPIXR_CTRL4_SSINACT_POS) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gab7a4ffafc6fcc442816c09fe4592e9d8">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_LOW_POS                   0 </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga99af5e9ebc16118188c92917ca92be5b">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_LOW                       ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_BRG_CTRL_LOW_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga377c040e6b8bdbb7042a92765fed08ae">  332</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_BRG_CTRL_LOW_DIS                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gaf6ed6f588c04fc4b0b76cdc99de966e9">  333</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_BRG_CTRL_LOW_DIS                   (MXC_V_SPIXR_BRG_CTRL_LOW_DIS &lt;&lt; MXC_F_SPIXR_BRG_CTRL_LOW_POS) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga0d6d4c7594fdb9943c0731258a82bf98">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_HI_POS                    8 </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gada5b87fe20f4b833b01e8bd44dcea01d">  336</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_HI                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_BRG_CTRL_HI_POS)) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga6398ec36157a546ed9b6c5603d39f5a6">  337</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_BRG_CTRL_HI_DIS                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga8e53975f0269ac14eb03608c7cca828d">  338</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_BRG_CTRL_HI_DIS                    (MXC_V_SPIXR_BRG_CTRL_HI_DIS &lt;&lt; MXC_F_SPIXR_BRG_CTRL_HI_POS) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gaa2b4a5e1c784ce920daaf80f2aa83150">  340</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_SCALE_POS                 16 </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga9382e7732d19135a9f6cf6273b5558c6">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_SCALE                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) </span></div><div class="line"><a name="l00351"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#gacfcaeb8569997db178aa752918e8ce10">  351</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_EN_POS                0 </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#gae2469c932d5926e214bfdd7a1b4da0ec">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_EN                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_I2S_CTRL_I2S_EN_POS)) </span></div><div class="line"><a name="l00354"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#ga7e8e37946e7a539ee77758bc2c5c4d46">  354</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_MUTE_POS              1 </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#ga7539b5c3d3016720593e25626c0f2ea3">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_MUTE                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_I2S_CTRL_I2S_MUTE_POS)) </span></div><div class="line"><a name="l00357"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#ga5d136c80a71ce04baa497d6f7d32a056">  357</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_PAUSE_POS             2 </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#gaa53191bbd2602c3828c97780fb85e743">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_PAUSE                 ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_I2S_CTRL_I2S_PAUSE_POS)) </span></div><div class="line"><a name="l00360"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#gad085e0b61b7a08a9f649bda41d3fb8f5">  360</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_MONO_POS              3 </span></div><div class="line"><a name="l00361"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#gadcb4ddee7f413e56044af7e2fa2440f4">  361</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_MONO                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_I2S_CTRL_I2S_MONO_POS)) </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#ga62f308dfadb73a12c0ccf64c3e024781">  363</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_LJ_POS                4 </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__SPIXR__I2S__CTRL.html#gaf490ec69370cb7ee3710474cbeca54ab">  364</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_I2S_CTRL_I2S_LJ                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_I2S_CTRL_I2S_LJ_POS)) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga4e0608f1891aec68f1614db9d1e39281">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS              0 </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga6b846b917ef4a4ecc9b86d514eb9e820">  375</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gacc8199087e4dbf740ab0f6cddbfa335d">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS                 6 </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gadebcc9411a3469eafc60417253060a45">  378</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_EN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga4f66a3461075882b496fd86a6da27d93">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS              7 </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga815f62233f9388a75d5ebdbabedcc3ee">  381</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gac9bd5c93e34553e7d1c7c42995314fcf">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS                8 </span></div><div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gaef4e5bb56040b8c7b4b94cb053371ced">  384</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CNT                    ((uint32_t)(0x1FUL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gaec8041a10ae73695b26c4d400058dece">  386</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_DMA_EN_POS                  15 </span></div><div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga11f990840b60511332dcc9ab5c648975">  387</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_DMA_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) </span></div><div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga4774b8ba75f34d8f08c7bf821d2408d5">  389</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS              16 </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga07ade7acc4c881d6de57a53ba22bd9d8">  390</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga8bfe9bada9f5b35e9fc14b71dd75e6bc">  392</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS                 22 </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga5949d1e12050fa542a68a34a5557b227">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_EN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga52684362e8227205816a9daaa0c67c23">  395</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS              23 </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gae5b6b13626601e1ac183b848de3c0b98">  396</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) </span></div><div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga560bd871cd78e58b023a810e1669da3b">  398</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS                24 </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gab4f579010d2ab9ed035d1042d2f0df3b">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CNT                    ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gac563edfdd5db2fcb6e6bd5dfaad71320">  401</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_DMA_EN_POS                  31 </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gaf63b0d8e1ab4ed5aa1e2b28d6d9f59bd">  402</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_DMA_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) </span></div><div class="line"><a name="l00413"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga5a755516bc35f98ff76aec449f483d08">  413</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_THRESH_POS                  0 </span></div><div class="line"><a name="l00414"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gac909243efa0c7a666b58093ff4d7b18c">  414</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_THRESH                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_THRESH_POS)) </span></div><div class="line"><a name="l00416"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gaa41982fff77e3c1527865e9156e70edf">  416</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_EMPTY_POS                   1 </span></div><div class="line"><a name="l00417"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gaf38528d2a52018871d2bcb78dfd89ede">  417</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_EMPTY                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00419"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga967d39cd6857dfb824c77a197a34c930">  419</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_THRESH_POS                  2 </span></div><div class="line"><a name="l00420"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga6fa85aa350c3d1245c2d56ac8cc62494">  420</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_THRESH                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_THRESH_POS)) </span></div><div class="line"><a name="l00422"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga1ce2e3fda4345addae1e4ec052d1779f">  422</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_FULL_POS                    3 </span></div><div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga9574644a3e2a479e6ce9c141c223993c">  423</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_FULL                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_FULL_POS)) </span></div><div class="line"><a name="l00425"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gad4d3ee9dfa81085fc8c376ad0bb51c97">  425</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSA_POS                        4 </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gaeb20fc143d1894ec6d6ab151df462a28">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSA                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SSA_POS)) </span></div><div class="line"><a name="l00428"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga689bc1c6166b57663342dd878697f7fb">  428</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSD_POS                        5 </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga81e8ce35dc0fbd10e753f38facae5603">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSD                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SSD_POS)) </span></div><div class="line"><a name="l00431"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga3b35d2b563c4a87a82b39f67215a9d54">  431</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_FAULT_POS                      8 </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga8be8c63f2de0227449a8c51c4415b3b2">  432</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_FAULT                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_FAULT_POS)) </span></div><div class="line"><a name="l00434"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga1a9c3d1ea7748f31ad562136b31bc147">  434</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_ABORT_POS                      9 </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga77c41cc89f87b6292bd6e83ae1b46823">  435</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_ABORT                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_ABORT_POS)) </span></div><div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga5eab5abf06cf004258d4666e4120a4c1">  437</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TIMEOUT_POS                    10 </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gafcd1bb73e33d035de58d21f5dcc9d388">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TIMEOUT                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TIMEOUT_POS)) </span></div><div class="line"><a name="l00440"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga02062dca9c5c3ffbbdb1b447e21e4201">  440</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_M_DONE_POS                     11 </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gac8637d8c77e37b13a4005490d8410516">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_M_DONE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_M_DONE_POS)) </span></div><div class="line"><a name="l00443"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga3fb2e1a5f7c568af297e1c9c299a8d51">  443</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_OVR_POS                     12 </span></div><div class="line"><a name="l00444"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga6f5304847af9d2611c65f32ea81d5d3e">  444</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_OVR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_OVR_POS)) </span></div><div class="line"><a name="l00446"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga7ccc337322ffc27aa4ec4b45295f2143">  446</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_UND_POS                     13 </span></div><div class="line"><a name="l00447"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga8959a6f78ea056bc0569ea19a67ae15d">  447</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_UND                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_UND_POS)) </span></div><div class="line"><a name="l00449"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga382577a6fb53c52ae23b8750cba59cfb">  449</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_OVR_POS                     14 </span></div><div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga553faaa3e9820c393f4e6a7e61a0b48d">  450</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_OVR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_OVR_POS)) </span></div><div class="line"><a name="l00452"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga5f784abbbdffc2a19b1721ff3a735319">  452</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_UND_POS                     15 </span></div><div class="line"><a name="l00453"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga177fac38055f74bf130d630f09a090e5">  453</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_UND                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_UND_POS)) </span></div><div class="line"><a name="l00455"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga60a2bbe9ff7f39f6c69820ac876477fd">  455</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR0A_POS                       16 </span></div><div class="line"><a name="l00456"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga6a07a387320bc362964a4dedafcac838">  456</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR0A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR0A_POS)) </span></div><div class="line"><a name="l00458"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga400722ab96c78e3983e0ba3b2bc12df2">  458</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR1A_POS                       17 </span></div><div class="line"><a name="l00459"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga36bcc5b3587e0a326dde86c90be1974c">  459</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR1A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR1A_POS)) </span></div><div class="line"><a name="l00461"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga4a20140c119d3db946978bf3e9622c07">  461</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR2A_POS                       18 </span></div><div class="line"><a name="l00462"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga13005f45c8e5b60850aee82aead81bf8">  462</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR2A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR2A_POS)) </span></div><div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gae2d30196cb9bbb28a2af3093ba728e82">  464</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR3A_POS                       19 </span></div><div class="line"><a name="l00465"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gacdea4e812d205eee1fda8e556a0ebb43">  465</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR3A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR3A_POS)) </span></div><div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga9253a959f55632249d8b47328056ddeb">  467</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR4A_POS                       20 </span></div><div class="line"><a name="l00468"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga4d8ca4fa01626dffbf5e32a2ff721a8e">  468</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR4A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR4A_POS)) </span></div><div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga769e5db855f1d1f4d12e79ee489d59a9">  470</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR5A_POS                       21 </span></div><div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga15c0ba7818efc3499cb9bb0654260e77">  471</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR5A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR5A_POS)) </span></div><div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga290dea21b7055be386fc1099c7252d4c">  473</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR6A_POS                       22 </span></div><div class="line"><a name="l00474"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gad379401c97e7066d133214dc86547390">  474</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR6A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR6A_POS)) </span></div><div class="line"><a name="l00476"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga12336062ab9df83457ef7c7e8a4479b8">  476</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR7A_POS                       23 </span></div><div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga626c631a04a927fd03b34d4e78332b2d">  477</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SR7A                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SR7A_POS)) </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gabb659588e6f2046f016de9e26509f306">  487</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_THRESH_POS                 0 </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gad2143dfa3b064f775a5080a9181dd554">  488</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_THRESH_POS)) </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga9847387d123d092db42e0459e665a562">  490</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_EMPTY_POS                  1 </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga22517e90f42f31e605d94143be7cbb2f">  491</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00493"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gab7c9bbd5dcc619b2538f36313080f412">  493</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_THRESH_POS                 2 </span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaf52fd414abccafc2873404755f3fab3d">  494</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_THRESH_POS)) </span></div><div class="line"><a name="l00496"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga62be1216972e8162f0b5a68e91b96d1c">  496</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_FULL_POS                   3 </span></div><div class="line"><a name="l00497"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gabde517c2ee054171103c951cc8afbd39">  497</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_FULL_POS)) </span></div><div class="line"><a name="l00499"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gae67ff05ae90c0d599e28b835c2da3141">  499</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSA_POS                       4 </span></div><div class="line"><a name="l00500"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga2f5d93c091f40b1ca702faeb9ed2917e">  500</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSA                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SSA_POS)) </span></div><div class="line"><a name="l00502"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaa010b2bd66244ea231efab81b63c71cc">  502</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSD_POS                       5 </span></div><div class="line"><a name="l00503"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga1ace8c3cf0543536790f08c58da8f8ed">  503</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSD                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SSD_POS)) </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaeb6a73d160d8e9ab8071c37183fd063c">  505</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_FAULT_POS                     8 </span></div><div class="line"><a name="l00506"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gad7d082320d774d22a3c0bfbf91def727">  506</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_FAULT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_FAULT_POS)) </span></div><div class="line"><a name="l00508"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gac79c5ec42c1283b7d508757ef4381231">  508</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_ABORT_POS                     9 </span></div><div class="line"><a name="l00509"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gabd01395c01eb1760cf1522df3ff40f9d">  509</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_ABORT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_ABORT_POS)) </span></div><div class="line"><a name="l00511"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaef73c1aa5a18cc39c1e2fd3c81d76848">  511</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TIMEOUT_POS                   10 </span></div><div class="line"><a name="l00512"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaf8eedfd93bae073a546b28c36360c07c">  512</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TIMEOUT                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TIMEOUT_POS)) </span></div><div class="line"><a name="l00514"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga51f852b4e6717369ed2e4599e9f8a00c">  514</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_M_DONE_POS                    11 </span></div><div class="line"><a name="l00515"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gab3237d1c64c3ead640f2b74581ca3590">  515</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_M_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_M_DONE_POS)) </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga442f88f50025236b91ef65715bf29218">  517</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_OVR_POS                    12 </span></div><div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gada0757f0c5fd29d05feb53efd56cf625">  518</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_OVR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_OVR_POS)) </span></div><div class="line"><a name="l00520"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga18eaf3680908411f1d6cbd32926de17f">  520</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_UND_POS                    13 </span></div><div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaa5f0428e77ee3422bbe6631abc7bc94a">  521</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_UND                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_UND_POS)) </span></div><div class="line"><a name="l00523"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga00fba2d9d71ae525610c2b0cbc53612c">  523</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_OVR_POS                    14 </span></div><div class="line"><a name="l00524"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga614b31e611efcb721ebd2383510daee1">  524</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_OVR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_OVR_POS)) </span></div><div class="line"><a name="l00526"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga132cbf2b7c7c8baa50e694fd61942818">  526</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_UND_POS                    15 </span></div><div class="line"><a name="l00527"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gac338f3acd8af2328efc334bcabfed971">  527</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_UND                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_UND_POS)) </span></div><div class="line"><a name="l00529"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga554d8b890644528b218eb3575275a5e7">  529</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR0A_POS                      16 </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga3769c955c257126ebb9783940c08e032">  530</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR0A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR0A_POS)) </span></div><div class="line"><a name="l00532"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga0aa554db81b6f9ce209664a73d72b7ac">  532</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR1A_POS                      17 </span></div><div class="line"><a name="l00533"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga0adb168d964a951187f66cfa6ccc9574">  533</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR1A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR1A_POS)) </span></div><div class="line"><a name="l00535"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga2df0cd8db593b81aa43d9daf745906d1">  535</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR2A_POS                      18 </span></div><div class="line"><a name="l00536"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga7815051fe517230bfbce4a1675bead1f">  536</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR2A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR2A_POS)) </span></div><div class="line"><a name="l00538"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaf6cb1817f209d521966c154e8015c05e">  538</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR3A_POS                      19 </span></div><div class="line"><a name="l00539"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga77a6e73b154f7c70df113b573fa627f4">  539</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR3A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR3A_POS)) </span></div><div class="line"><a name="l00541"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gae1b897cf0ffa57405f5262e4403b25c2">  541</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR4A_POS                      20 </span></div><div class="line"><a name="l00542"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga10b702a26f8a608d112c86f2b922d4fd">  542</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR4A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR4A_POS)) </span></div><div class="line"><a name="l00544"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga74ca53e7f795882a0e4c71cb90d7f416">  544</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR5A_POS                      21 </span></div><div class="line"><a name="l00545"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga9f22d32d49df47d9e86fd3b02cd541c4">  545</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR5A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR5A_POS)) </span></div><div class="line"><a name="l00547"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga2abc323fb53390b2963f4a747c9bba49">  547</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR6A_POS                      22 </span></div><div class="line"><a name="l00548"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gae2c1d5475f06cdda44613298100f50ac">  548</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR6A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR6A_POS)) </span></div><div class="line"><a name="l00550"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gafb399bd9198fa72a6b3cdd98778f8805">  550</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR7A_POS                      23 </span></div><div class="line"><a name="l00551"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga8c56485c6e6dd59206dd99f1f82ff749">  551</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SR7A                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SR7A_POS)) </span></div><div class="line"><a name="l00561"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga011f892cb5f4f7a04cd3c8a877470583">  561</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_THRESH_POS                 0 </span></div><div class="line"><a name="l00562"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga6878604766a7c3101322e885a7b4e399">  562</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_TX_THRESH_POS)) </span></div><div class="line"><a name="l00564"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#gaa114f12c0c4366826f27ae4306d1d35e">  564</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_EMPTY_POS                  1 </span></div><div class="line"><a name="l00565"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#gaa8b2ce954c02fcb82e110ff09f1bd46d">  565</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00567"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga5e54c285b3353609ece5b13fac884b21">  567</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_THRESH_POS                 2 </span></div><div class="line"><a name="l00568"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga245c718c30ea07b7ca416ad3e9f7adcb">  568</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_RX_THRESH_POS)) </span></div><div class="line"><a name="l00570"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga8ff5f09fd4d9196419a240965cfa44dd">  570</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_FULL_POS                   3 </span></div><div class="line"><a name="l00571"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#gab3d60cb5994fd23648a725da32e9a7f7">  571</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_RX_FULL_POS)) </span></div><div class="line"><a name="l00581"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gaae626ff03038fdac08706f3fa384cfc7">  581</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_THRESH_POS                0 </span></div><div class="line"><a name="l00582"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gafa438988158c44111bd4675842223187">  582</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_TX_THRESH_POS)) </span></div><div class="line"><a name="l00584"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gadad32f054b737a166748a3e67415f5f5">  584</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_EMPTY_POS                 1 </span></div><div class="line"><a name="l00585"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gae8b2abb097b13bd4b17dda2ea6404a99">  585</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_EMPTY                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00587"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#ga86c906304e4266168a71045990351bf4">  587</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_THRESH_POS                2 </span></div><div class="line"><a name="l00588"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#ga8db5a58326d49007b8fa32967a8f2fdc">  588</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_RX_THRESH_POS)) </span></div><div class="line"><a name="l00590"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gab974280e3e77dad2271ab5f0e20d44ba">  590</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_FULL_POS                  3 </span></div><div class="line"><a name="l00591"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gac51800c5e98cc6fd1bbfcf16cb3d8936">  591</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_FULL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_RX_FULL_POS)) </span></div><div class="line"><a name="l00601"></a><span class="lineno"><a class="line" href="group__SPIXR__STAT.html#gaf1b5599ed2707ce062923c22a65ac32d">  601</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_STAT_BUSY_POS                      0 </span></div><div class="line"><a name="l00602"></a><span class="lineno"><a class="line" href="group__SPIXR__STAT.html#ga363069a321b449c2d605cbdcf9ab3c8f">  602</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_STAT_BUSY                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_STAT_BUSY_POS)) </span></div><div class="line"><a name="l00612"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#ga5c19af2c5876047913a059cbc3a77794">  612</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS               0 </span></div><div class="line"><a name="l00613"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaafbbf5b7e40998a24aca9621fb7a8527">  613</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD                   ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS)) </span></div><div class="line"><a name="l00615"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#ga5da6552156cbf4dcc6293de0bcb40dfb">  615</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS               8 </span></div><div class="line"><a name="l00616"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaa2b7138b38740607cf3d1cd6458bf421">  616</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD                   ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS)) </span></div><div class="line"><a name="l00618"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gac7ea84b07a04fef41b95708186102e60">  618</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS            16 </span></div><div class="line"><a name="l00619"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaea7aa42efac71da9666f3cd9f8aaad41">  619</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK                ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS)) </span></div><div class="line"><a name="l00621"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gabdc6757e648e7bee99d58c51d31b99a4">  621</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS              31 </span></div><div class="line"><a name="l00622"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaf443581ce8dbb886323567ed998bbcf1">  622</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) </span></div><div class="line"><a name="l00626"></a><span class="lineno">  626</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00627"></a><span class="lineno">  627</span>&#160;}</div><div class="line"><a name="l00628"></a><span class="lineno">  628</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00629"></a><span class="lineno">  629</span>&#160;</div><div class="line"><a name="l00630"></a><span class="lineno">  630</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXR_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__spixr__regs__t_html_a8be3ba10d6c326e1e6cf5fb74788032a"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a8be3ba10d6c326e1e6cf5fb74788032a">mxc_spixr_regs_t::wake</a></div><div class="ttdeci">__IO uint32_t wake</div><div class="ttdoc">0x28: SPIXR WAKE Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:103</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _SPIXR_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _SPIXR_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span 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name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno">   89</span>&#160;  <span class="keyword">union</span>{</div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#abf4598e6b6401e68b54614250834a231">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#abf4598e6b6401e68b54614250834a231">data32</a>;               </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a3f2c53c0ee00b0486ed88ee3c1c45481">   91</a></span>&#160;    __IO uint16_t data16[2];            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a903143d87a5110b8d223a093ee28682c">   92</a></span>&#160;    __IO uint8_t  data8[4];             </div><div class="line"><a name="l00093"></a><span class="lineno">   93</span>&#160;  };</div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a661e2879ea52ba18153757482845a8f0">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a661e2879ea52ba18153757482845a8f0">ctrl1</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a753c4fc439e94fa35b6d29a6075add3d">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a753c4fc439e94fa35b6d29a6075add3d">ctrl2</a>;                </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a36ae9d4c3d470f49dc519eed1a8ac02a">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a36ae9d4c3d470f49dc519eed1a8ac02a">ctrl3</a>;                </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a6a681c5f9aa124a8105168e58539c1fa">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a6a681c5f9aa124a8105168e58539c1fa">ctrl4</a>;                </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a959af8bccf851f69ace9c85e4d16f930">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a959af8bccf851f69ace9c85e4d16f930">brg_ctrl</a>;             </div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;    __R  uint32_t rsv_0x18;</div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a22c165cb4836264617f9ca7084933cba">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a22c165cb4836264617f9ca7084933cba">dma</a>;                  </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a0e2efcc6a2ea9a09315cd1bf411f1612">  101</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a0e2efcc6a2ea9a09315cd1bf411f1612">irq</a>;                  </div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a694583dda0ca9d64b70e997c6ed41584">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a694583dda0ca9d64b70e997c6ed41584">irqe</a>;                 </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a8be3ba10d6c326e1e6cf5fb74788032a">  103</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a8be3ba10d6c326e1e6cf5fb74788032a">wake</a>;                 </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#ad3be5055a12fdff0e232874b09de6cf8">  104</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#ad3be5055a12fdff0e232874b09de6cf8">wakee</a>;                </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a483ed058b60736400e947a6abdec6c53">  105</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a483ed058b60736400e947a6abdec6c53">stat</a>;                 </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__spixr__regs__t.html#a5ba44f6f49bfb1e8245abb85bba9a215">  106</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__spixr__regs__t.html#a5ba44f6f49bfb1e8245abb85bba9a215">xmem_ctrl</a>;            </div><div class="line"><a name="l00107"></a><span class="lineno">  107</span>&#160;} <a class="code" href="structmxc__spixr__regs__t.html">mxc_spixr_regs_t</a>;</div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;<span class="comment">/* Register offsets for module SPIXR */</span></div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga77ca249f0943bf672fd1cdd04937192a">  116</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DATA32                 ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga4a82bbd891d805fe14609e258b8e190c">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DATA16                 ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga2245f24219cbda0313f5b1734907f160">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DATA8                  ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gafd9b6458fa10d014391d8f8e8d8335c7">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL1                  ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gab549c09b4db9177463213627e1ef04df">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL2                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gab66881e95a2dd102d7d3a93f3ac9d08b">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL3                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gab6e44d192d452963b8d9fa153534bf3e">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_CTRL4                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga34dc7a0b8cfe6da9c8e21acd06195289">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_BRG_CTRL               ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga2ba4ee6f38355ef4b673983fd00266b9">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_DMA                    ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga1e23de67b56bfd1bd520932d58943218">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_IRQ                    ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gae45de56f172b245b29aa20d054cd4e7d">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_IRQE                   ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#ga3dc6c0a9f4dd702e4dd012fbb2746104">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_WAKE                   ((uint32_t)0x00000028UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gacf62a5e692ccc83d18685f20f2e481d0">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_WAKEE                  ((uint32_t)0x0000002CUL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gad1e8a473dc9c65e14721d1e171c3f9b1">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_STAT                   ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__SPIXR__Register__Offsets.html#gaba9f55bbb4942e12a6a5db141eb2c347">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_SPIXR_XMEM_CTRL              ((uint32_t)0x00000034UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA32.html#ga4b1dd303250954863ab8a348fa2bc6f7">  139</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA32_DATA_POS                    0 </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA32.html#ga531b373edff737b81c91043a5ccbccf5">  140</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA32_DATA                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_SPIXR_DATA32_DATA_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA16.html#gaf3d78f5ae31c77da60fa6767f46f3f77">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA16_DATA_POS                    0 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA16.html#ga6dff9c6f72915a3741c911fdf4a5f439">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA16_DATA                        ((uint16_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXR_DATA16_DATA_POS)) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA8.html#gaf44aebbe1c7a8a036d5b89692e818c01">  161</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA8_DATA_POS                     0 </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__SPIXR__DATA8.html#ga45f92341eba3f6c6f4964055607540b3">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DATA8_DATA                         ((uint8_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_DATA8_DATA_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga6af08d7796a7b6d40a10f7ed1d33ef25">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SPIEN_POS                    0 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaca68ef87ef496509156923c8672d32a6">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SPIEN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_SPIEN_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga75f9f4eeb0d9bd4a522885e456186f46">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_MMEN_POS                     1 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga8301972e034e1ed03bb564623a1ef4ca">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_MMEN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_MMEN_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga8db613bd7aceffaa0f55f43f4940f763">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TIMER_POS                    2 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gab1c2f9f5b552620f056850ff28f05e9c">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TIMER                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_TIMER_POS)) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga396a0a9436f16be4d71e3b869d197901">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_FL_EN_POS                    3 </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga4e7418304f5cb7193322dca5f1600a81">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_FL_EN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_FL_EN_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga43bc0cf64ae352c0b8b55b173348a970">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SSIO_POS                     4 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga501380edfa099120940d16faa82a887a">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SSIO                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_SSIO_POS)) </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga63125b2fd4257b1ae9d891f5a8a69225">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TX_START_POS                 5 </span></div><div class="line"><a name="l00188"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga5edd45a6ae27b2c62b95cc9d1d08b238">  188</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_TX_START                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_TX_START_POS)) </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaba51d2f85b772d9a40bffb02de3f83d5">  190</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS_CTRL_POS                  8 </span></div><div class="line"><a name="l00191"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga6ac2a6efe9f68449649fd303ff8f6619">  191</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS_CTRL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga316aa2c295612fcdf2b12217bdfbe186">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS_POS                       16 </span></div><div class="line"><a name="l00194"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gae38941e2050c4748ed8735ee7d73440f">  194</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL1_SS                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga6cebe1b5e6c3c92724ab631f50f829f3">  195</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS0                       ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaeffc65d28ebdbff107288ff3218011b2">  196</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS0                       (MXC_V_SPIXR_CTRL1_SS_SS0 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00197"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaa081bc7ad90a92e266f486855b642c5a">  197</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS1                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga0a3c0b703797d47e0e276934806b7bb7">  198</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS1                       (MXC_V_SPIXR_CTRL1_SS_SS1 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga3b60a33da53e29a49ed9e033cdda26a8">  199</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS2                       ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00200"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga4b2bdd86df5e294db549c35fcb09871b">  200</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS2                       (MXC_V_SPIXR_CTRL1_SS_SS2 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga4e12d58da5bb76286d6d38f1ca7a8d73">  201</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS3                       ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga27c961ace8b4fa58fddde0fed7a3717e">  202</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS3                       (MXC_V_SPIXR_CTRL1_SS_SS3 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00203"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gad98c8e52732fccc0fa901e325a2ff019">  203</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS4                       ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga9743590eaba724cfb97439ccc411b8ab">  204</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS4                       (MXC_V_SPIXR_CTRL1_SS_SS4 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga41de92d188048fd049b9368c88d0ae00">  205</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS5                       ((uint32_t)0x20UL) </span></div><div class="line"><a name="l00206"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga2e3a36d0d73eea6ce3e6c46a667f9b3a">  206</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS5                       (MXC_V_SPIXR_CTRL1_SS_SS5 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gaf314bcd4edc109509fffca1c326941e9">  207</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS6                       ((uint32_t)0x40UL) </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga566e758be6777d6fed3632e55d3536af">  208</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS6                       (MXC_V_SPIXR_CTRL1_SS_SS6 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00209"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#gad466a63522d06a875de28a9811de4076">  209</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL1_SS_SS7                       ((uint32_t)0x80UL) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL1.html#ga50bcf0801ae69c68fff96693c25666bf">  210</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL1_SS_SS7                       (MXC_V_SPIXR_CTRL1_SS_SS7 &lt;&lt; MXC_F_SPIXR_CTRL1_SS_POS) </span></div><div class="line"><a name="l00220"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#gacbaf336870e0f9944c02b11016d04680">  220</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS              0 </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#ga6aa252309c06b310871d2433fc556f24">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_TX_NUM_CHAR                  ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) </span></div><div class="line"><a name="l00223"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#gaa1eac4780438e4be68b131ea91de488c">  223</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS              16 </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL2.html#ga3f58d343e5b6d73fce0ac3d6b06bcd76">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL2_RX_NUM_CHAR                  ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga4b11876ecc25a8e6c1bc27fc2fcf674d">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPHA_POS                     0 </span></div><div class="line"><a name="l00235"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gabba68fca9dfce649faf1b5fdb021ed3b">  235</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPHA                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_CPHA_POS)) </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga6f162efd235f31ff5d8ccca8cf0b9a02">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPOL_POS                     1 </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gadbc104c1bedc25c733e5d1998f345931">  238</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_CPOL                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_CPOL_POS)) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga8fe5e0f6d447c59c7022bd6d1939ad11">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS              4 </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gab275a86417de6b198e5916a7f35264b7">  241</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SCLK_FB_INV                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS)) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga91b76b94078c0301bd192e57fece5f81">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_NUMBITS_POS                  8 </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga729307f82aa327acc538033bdc169653">  244</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_NUMBITS                      ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXR_CTRL3_NUMBITS_POS)) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga209a660bc1850b69be1b7a267aa43174">  245</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_NUMBITS_0                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga5a02872e3d7ce0b41e850766016ab853">  246</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_NUMBITS_0                    (MXC_V_SPIXR_CTRL3_NUMBITS_0 &lt;&lt; MXC_F_SPIXR_CTRL3_NUMBITS_POS) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga3f826806f8db0b293b8fae158ed40a0b">  248</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS               12 </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga5ed09cdf6961712e29b1d0885ef7d5bc">  249</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_DATA_WIDTH                   ((uint32_t)(0x3UL &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) </span></div><div class="line"><a name="l00250"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaba9302df431fdb6b27661ed3f0bd5d4a">  250</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO              ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gac1e5159330e80ab5d779868045f169cf">  251</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO              (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga501b19f852a94c804f95bd2e193429a7">  252</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga1f1814f269ea319019fb7c716994ab61">  253</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL              (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaa9f6d3afae7396e6b449068083259c6a">  254</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga27c19862a4ed143d1298c254c9930aab">  255</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD              (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD &lt;&lt; MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaee1916a80ad335df0fd57af11ebf67dd">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_THREE_WIRE_POS               15 </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga9c2a6765dcde506f7bd03e6b939a941e">  258</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_THREE_WIRE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga7d846b606f417e6f2c391acd6a657712">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SSPOL_POS                    16 </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga1c55886ba52368b84921648499f5d859">  261</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL3_SSPOL                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS)) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga954fecde54aa7785b70b59331de248e9">  262</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH               ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga3c8a6c82ee20d08c3d16053f3251c784">  263</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS0_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00264"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga18b1e549f43eaa0dd9793c9ff4764960">  264</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH               ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaeb671a7a0b983b08ab67ee699f6d5659">  265</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS1_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gae98c3ecf9f45d63cc8cbd12946a8ab26">  266</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH               ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00267"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gae51ccf558348cdc0815aa9d008400d9d">  267</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS2_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaa6f25fa3068747b72185c49767d23867">  268</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH               ((uint32_t)0x8UL) </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga6744e5d12841e8d77ad65e59be8b5c48">  269</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS3_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00270"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga72a1096a5051e718e0a447645019af78">  270</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH               ((uint32_t)0x10UL) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gad3dbfc4e70c697e2bb87830fbdc1d7bf">  271</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS4_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gad653055ce5f36383aadf895c34b5c4ef">  272</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH               ((uint32_t)0x20UL) </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gab5f499c8237af114d7d5a00e656e75a4">  273</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS5_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gabed03f10abacbd7cb8e7a2edc5ba9adc">  274</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH               ((uint32_t)0x40UL) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga981a55d835fec6bb5eca323dca8c24c3">  275</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS6_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#gaef7b39213d1c82bb2f1f7f001204af48">  276</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH               ((uint32_t)0x80UL) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL3.html#ga37ad300c017e8efc94c78d33cf7483be">  277</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL3_SSPOL_SS7_HIGH               (MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH &lt;&lt; MXC_F_SPIXR_CTRL3_SSPOL_POS) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga8b96a1f5d931b27ee39582a3d535b7b7">  287</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT1_POS                   0 </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#gabddce60f80d67c1cb4cbc48a640b12fc">  288</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT1                       ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT1_POS)) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga3cd012031bd7500799d7efefc919a8fe">  289</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL4_SSACT1_256                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga33aff3c83748fcf75662203940754168">  290</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL4_SSACT1_256                   (MXC_V_SPIXR_CTRL4_SSACT1_256 &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT1_POS) </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga3051ad2d70a93006d8f94412db6a29b3">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT2_POS                   8 </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga25de22ff0df30637b2f984645723ae73">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSACT2                       ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT2_POS)) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#gac89da83cb7e17cb66e245a6eb90002a2">  294</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL4_SSACT2_256                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga4b3f54b8b47d2fb53a9f92cc8ad54744">  295</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL4_SSACT2_256                   (MXC_V_SPIXR_CTRL4_SSACT2_256 &lt;&lt; MXC_F_SPIXR_CTRL4_SSACT2_POS) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga396fbae7be78ccde37b1f26443548424">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSINACT_POS                  16 </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga1b00d04fc0af11b712d40286f890b069">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_CTRL4_SSINACT                      ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_CTRL4_SSINACT_POS)) </span></div><div class="line"><a name="l00299"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#ga8da20ed89bb89edd59129b1f2a65a476">  299</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_CTRL4_SSINACT_256                  ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__SPIXR__CTRL4.html#gad706155c448a59d2cfd193600a8ee115">  300</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_CTRL4_SSINACT_256                  (MXC_V_SPIXR_CTRL4_SSINACT_256 &lt;&lt; MXC_F_SPIXR_CTRL4_SSINACT_POS) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gab7a4ffafc6fcc442816c09fe4592e9d8">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_LOW_POS                   0 </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga99af5e9ebc16118188c92917ca92be5b">  311</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_LOW                       ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_BRG_CTRL_LOW_POS)) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga377c040e6b8bdbb7042a92765fed08ae">  312</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_BRG_CTRL_LOW_DIS                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gaf6ed6f588c04fc4b0b76cdc99de966e9">  313</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_BRG_CTRL_LOW_DIS                   (MXC_V_SPIXR_BRG_CTRL_LOW_DIS &lt;&lt; MXC_F_SPIXR_BRG_CTRL_LOW_POS) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga0d6d4c7594fdb9943c0731258a82bf98">  315</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_HI_POS                    8 </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gada5b87fe20f4b833b01e8bd44dcea01d">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_HI                        ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_BRG_CTRL_HI_POS)) </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga6398ec36157a546ed9b6c5603d39f5a6">  317</a></span>&#160;<span class="preprocessor"> #define MXC_V_SPIXR_BRG_CTRL_HI_DIS                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga8e53975f0269ac14eb03608c7cca828d">  318</a></span>&#160;<span class="preprocessor"> #define MXC_S_SPIXR_BRG_CTRL_HI_DIS                    (MXC_V_SPIXR_BRG_CTRL_HI_DIS &lt;&lt; MXC_F_SPIXR_BRG_CTRL_HI_POS) </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#gaa2b4a5e1c784ce920daaf80f2aa83150">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_SCALE_POS                 16 </span></div><div class="line"><a name="l00321"></a><span class="lineno"><a class="line" href="group__SPIXR__BRG__CTRL.html#ga9382e7732d19135a9f6cf6273b5558c6">  321</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_BRG_CTRL_SCALE                     ((uint32_t)(0xFUL &lt;&lt; MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga4e0608f1891aec68f1614db9d1e39281">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS              0 </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga6b846b917ef4a4ecc9b86d514eb9e820">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_LEVEL                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gacc8199087e4dbf740ab0f6cddbfa335d">  334</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_EN_POS                 6 </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gadebcc9411a3469eafc60417253060a45">  335</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_EN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga4f66a3461075882b496fd86a6da27d93">  337</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS              7 </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga815f62233f9388a75d5ebdbabedcc3ee">  338</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CLEAR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gac9bd5c93e34553e7d1c7c42995314fcf">  340</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS                8 </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gaef4e5bb56040b8c7b4b94cb053371ced">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_FIFO_CNT                    ((uint32_t)(0x1FUL &lt;&lt; MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00343"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gaec8041a10ae73695b26c4d400058dece">  343</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_DMA_EN_POS                  15 </span></div><div class="line"><a name="l00344"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga11f990840b60511332dcc9ab5c648975">  344</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_TX_DMA_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) </span></div><div class="line"><a name="l00346"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga4774b8ba75f34d8f08c7bf821d2408d5">  346</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS              16 </span></div><div class="line"><a name="l00347"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga07ade7acc4c881d6de57a53ba22bd9d8">  347</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_LEVEL                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) </span></div><div class="line"><a name="l00349"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga8bfe9bada9f5b35e9fc14b71dd75e6bc">  349</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_EN_POS                 22 </span></div><div class="line"><a name="l00350"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga5949d1e12050fa542a68a34a5557b227">  350</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_EN                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga52684362e8227205816a9daaa0c67c23">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS              23 </span></div><div class="line"><a name="l00353"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gae5b6b13626601e1ac183b848de3c0b98">  353</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CLEAR                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) </span></div><div class="line"><a name="l00355"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#ga560bd871cd78e58b023a810e1669da3b">  355</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS                24 </span></div><div class="line"><a name="l00356"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gab4f579010d2ab9ed035d1042d2f0df3b">  356</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_FIFO_CNT                    ((uint32_t)(0x3FUL &lt;&lt; MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00358"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gac563edfdd5db2fcb6e6bd5dfaad71320">  358</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_DMA_EN_POS                  31 </span></div><div class="line"><a name="l00359"></a><span class="lineno"><a class="line" href="group__SPIXR__DMA.html#gaf63b0d8e1ab4ed5aa1e2b28d6d9f59bd">  359</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_DMA_RX_DMA_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga5a755516bc35f98ff76aec449f483d08">  370</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_THRESH_POS                  0 </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gac909243efa0c7a666b58093ff4d7b18c">  371</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_THRESH                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_THRESH_POS)) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gaa41982fff77e3c1527865e9156e70edf">  373</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_EMPTY_POS                   1 </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gaf38528d2a52018871d2bcb78dfd89ede">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_EMPTY                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga967d39cd6857dfb824c77a197a34c930">  376</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_THRESH_POS                  2 </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga6fa85aa350c3d1245c2d56ac8cc62494">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_THRESH                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_THRESH_POS)) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga1ce2e3fda4345addae1e4ec052d1779f">  379</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_FULL_POS                    3 </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga9574644a3e2a479e6ce9c141c223993c">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_FULL                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_FULL_POS)) </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gad4d3ee9dfa81085fc8c376ad0bb51c97">  382</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSA_POS                        4 </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gaeb20fc143d1894ec6d6ab151df462a28">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSA                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SSA_POS)) </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga689bc1c6166b57663342dd878697f7fb">  385</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSD_POS                        5 </span></div><div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga81e8ce35dc0fbd10e753f38facae5603">  386</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_SSD                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_SSD_POS)) </span></div><div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga3b35d2b563c4a87a82b39f67215a9d54">  388</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_FAULT_POS                      8 </span></div><div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga8be8c63f2de0227449a8c51c4415b3b2">  389</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_FAULT                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_FAULT_POS)) </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga1a9c3d1ea7748f31ad562136b31bc147">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_ABORT_POS                      9 </span></div><div class="line"><a name="l00392"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga77c41cc89f87b6292bd6e83ae1b46823">  392</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_ABORT                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_ABORT_POS)) </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga02062dca9c5c3ffbbdb1b447e21e4201">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_M_DONE_POS                     11 </span></div><div class="line"><a name="l00395"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#gac8637d8c77e37b13a4005490d8410516">  395</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_M_DONE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_M_DONE_POS)) </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga3fb2e1a5f7c568af297e1c9c299a8d51">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_OVR_POS                     12 </span></div><div class="line"><a name="l00398"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga6f5304847af9d2611c65f32ea81d5d3e">  398</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_OVR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_OVR_POS)) </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga7ccc337322ffc27aa4ec4b45295f2143">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_UND_POS                     13 </span></div><div class="line"><a name="l00401"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga8959a6f78ea056bc0569ea19a67ae15d">  401</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_TX_UND                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_TX_UND_POS)) </span></div><div class="line"><a name="l00403"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga382577a6fb53c52ae23b8750cba59cfb">  403</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_OVR_POS                     14 </span></div><div class="line"><a name="l00404"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga553faaa3e9820c393f4e6a7e61a0b48d">  404</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_OVR                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_OVR_POS)) </span></div><div class="line"><a name="l00406"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga5f784abbbdffc2a19b1721ff3a735319">  406</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_UND_POS                     15 </span></div><div class="line"><a name="l00407"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQ.html#ga177fac38055f74bf130d630f09a090e5">  407</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQ_RX_UND                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQ_RX_UND_POS)) </span></div><div class="line"><a name="l00417"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gabb659588e6f2046f016de9e26509f306">  417</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_THRESH_POS                 0 </span></div><div class="line"><a name="l00418"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gad2143dfa3b064f775a5080a9181dd554">  418</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_THRESH_POS)) </span></div><div class="line"><a name="l00420"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga9847387d123d092db42e0459e665a562">  420</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_EMPTY_POS                  1 </span></div><div class="line"><a name="l00421"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga22517e90f42f31e605d94143be7cbb2f">  421</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gab7c9bbd5dcc619b2538f36313080f412">  423</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_THRESH_POS                 2 </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaf52fd414abccafc2873404755f3fab3d">  424</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_THRESH_POS)) </span></div><div class="line"><a name="l00426"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga62be1216972e8162f0b5a68e91b96d1c">  426</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_FULL_POS                   3 </span></div><div class="line"><a name="l00427"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gabde517c2ee054171103c951cc8afbd39">  427</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_FULL_POS)) </span></div><div class="line"><a name="l00429"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gae67ff05ae90c0d599e28b835c2da3141">  429</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSA_POS                       4 </span></div><div class="line"><a name="l00430"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga2f5d93c091f40b1ca702faeb9ed2917e">  430</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSA                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SSA_POS)) </span></div><div class="line"><a name="l00432"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaa010b2bd66244ea231efab81b63c71cc">  432</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSD_POS                       5 </span></div><div class="line"><a name="l00433"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga1ace8c3cf0543536790f08c58da8f8ed">  433</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_SSD                           ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_SSD_POS)) </span></div><div class="line"><a name="l00435"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaeb6a73d160d8e9ab8071c37183fd063c">  435</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_FAULT_POS                     8 </span></div><div class="line"><a name="l00436"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gad7d082320d774d22a3c0bfbf91def727">  436</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_FAULT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_FAULT_POS)) </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gac79c5ec42c1283b7d508757ef4381231">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_ABORT_POS                     9 </span></div><div class="line"><a name="l00439"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gabd01395c01eb1760cf1522df3ff40f9d">  439</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_ABORT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_ABORT_POS)) </span></div><div class="line"><a name="l00441"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga51f852b4e6717369ed2e4599e9f8a00c">  441</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_M_DONE_POS                    11 </span></div><div class="line"><a name="l00442"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gab3237d1c64c3ead640f2b74581ca3590">  442</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_M_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_M_DONE_POS)) </span></div><div class="line"><a name="l00444"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga442f88f50025236b91ef65715bf29218">  444</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_OVR_POS                    12 </span></div><div class="line"><a name="l00445"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gada0757f0c5fd29d05feb53efd56cf625">  445</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_OVR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_OVR_POS)) </span></div><div class="line"><a name="l00447"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga18eaf3680908411f1d6cbd32926de17f">  447</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_UND_POS                    13 </span></div><div class="line"><a name="l00448"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gaa5f0428e77ee3422bbe6631abc7bc94a">  448</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_TX_UND                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_TX_UND_POS)) </span></div><div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga00fba2d9d71ae525610c2b0cbc53612c">  450</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_OVR_POS                    14 </span></div><div class="line"><a name="l00451"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga614b31e611efcb721ebd2383510daee1">  451</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_OVR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_OVR_POS)) </span></div><div class="line"><a name="l00453"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#ga132cbf2b7c7c8baa50e694fd61942818">  453</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_UND_POS                    15 </span></div><div class="line"><a name="l00454"></a><span class="lineno"><a class="line" href="group__SPIXR__IRQE.html#gac338f3acd8af2328efc334bcabfed971">  454</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_IRQE_RX_UND                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_IRQE_RX_UND_POS)) </span></div><div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga011f892cb5f4f7a04cd3c8a877470583">  464</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_THRESH_POS                 0 </span></div><div class="line"><a name="l00465"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga6878604766a7c3101322e885a7b4e399">  465</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_TX_THRESH_POS)) </span></div><div class="line"><a name="l00467"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#gaa114f12c0c4366826f27ae4306d1d35e">  467</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_EMPTY_POS                  1 </span></div><div class="line"><a name="l00468"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#gaa8b2ce954c02fcb82e110ff09f1bd46d">  468</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_TX_EMPTY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00470"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga5e54c285b3353609ece5b13fac884b21">  470</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_THRESH_POS                 2 </span></div><div class="line"><a name="l00471"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga245c718c30ea07b7ca416ad3e9f7adcb">  471</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_THRESH                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_RX_THRESH_POS)) </span></div><div class="line"><a name="l00473"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#ga8ff5f09fd4d9196419a240965cfa44dd">  473</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_FULL_POS                   3 </span></div><div class="line"><a name="l00474"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKE.html#gab3d60cb5994fd23648a725da32e9a7f7">  474</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKE_RX_FULL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKE_RX_FULL_POS)) </span></div><div class="line"><a name="l00484"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gaae626ff03038fdac08706f3fa384cfc7">  484</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_THRESH_POS                0 </span></div><div class="line"><a name="l00485"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gafa438988158c44111bd4675842223187">  485</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_TX_THRESH_POS)) </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gadad32f054b737a166748a3e67415f5f5">  487</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_EMPTY_POS                 1 </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gae8b2abb097b13bd4b17dda2ea6404a99">  488</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_TX_EMPTY                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#ga86c906304e4266168a71045990351bf4">  490</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_THRESH_POS                2 </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#ga8db5a58326d49007b8fa32967a8f2fdc">  491</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_THRESH                    ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_RX_THRESH_POS)) </span></div><div class="line"><a name="l00493"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gab974280e3e77dad2271ab5f0e20d44ba">  493</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_FULL_POS                  3 </span></div><div class="line"><a name="l00494"></a><span class="lineno"><a class="line" href="group__SPIXR__WAKEE.html#gac51800c5e98cc6fd1bbfcf16cb3d8936">  494</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_WAKEE_RX_FULL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_WAKEE_RX_FULL_POS)) </span></div><div class="line"><a name="l00504"></a><span class="lineno"><a class="line" href="group__SPIXR__STAT.html#gaf1b5599ed2707ce062923c22a65ac32d">  504</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_STAT_BUSY_POS                      0 </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group__SPIXR__STAT.html#ga363069a321b449c2d605cbdcf9ab3c8f">  505</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_STAT_BUSY                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_STAT_BUSY_POS)) </span></div><div class="line"><a name="l00515"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#ga5c19af2c5876047913a059cbc3a77794">  515</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS               0 </span></div><div class="line"><a name="l00516"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaafbbf5b7e40998a24aca9621fb7a8527">  516</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_RD_CMD                   ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS)) </span></div><div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#ga5da6552156cbf4dcc6293de0bcb40dfb">  518</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS               8 </span></div><div class="line"><a name="l00519"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaa2b7138b38740607cf3d1cd6458bf421">  519</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_WR_CMD                   ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS)) </span></div><div class="line"><a name="l00521"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gac7ea84b07a04fef41b95708186102e60">  521</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS            16 </span></div><div class="line"><a name="l00522"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaea7aa42efac71da9666f3cd9f8aaad41">  522</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK                ((uint32_t)(0xFFUL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS)) </span></div><div class="line"><a name="l00524"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gabdc6757e648e7bee99d58c51d31b99a4">  524</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS              31 </span></div><div class="line"><a name="l00525"></a><span class="lineno"><a class="line" href="group__SPIXR__XMEM__CTRL.html#gaf443581ce8dbb886323567ed998bbcf1">  525</a></span>&#160;<span class="preprocessor"> #define MXC_F_SPIXR_XMEM_CTRL_XMEM_EN                  ((uint32_t)(0x1UL &lt;&lt; MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) </span></div><div class="line"><a name="l00529"></a><span class="lineno">  529</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00530"></a><span class="lineno">  530</span>&#160;}</div><div class="line"><a name="l00531"></a><span class="lineno">  531</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00532"></a><span class="lineno">  532</span>&#160;</div><div class="line"><a name="l00533"></a><span class="lineno">  533</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _SPIXR_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__spixr__regs__t_html_a8be3ba10d6c326e1e6cf5fb74788032a"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a8be3ba10d6c326e1e6cf5fb74788032a">mxc_spixr_regs_t::wake</a></div><div class="ttdeci">__IO uint32_t wake</div><div class="ttdoc">0x28: SPIXR WAKE Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:103</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html_a22c165cb4836264617f9ca7084933cba"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a22c165cb4836264617f9ca7084933cba">mxc_spixr_regs_t::dma</a></div><div class="ttdeci">__IO uint32_t dma</div><div class="ttdoc">0x1C: SPIXR DMA Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:100</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html_a6a681c5f9aa124a8105168e58539c1fa"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a6a681c5f9aa124a8105168e58539c1fa">mxc_spixr_regs_t::ctrl4</a></div><div class="ttdeci">__IO uint32_t ctrl4</div><div class="ttdoc">0x10: SPIXR CTRL4 Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:97</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html_a483ed058b60736400e947a6abdec6c53"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a483ed058b60736400e947a6abdec6c53">mxc_spixr_regs_t::stat</a></div><div class="ttdeci">__I uint32_t stat</div><div class="ttdoc">0x30: SPIXR STAT Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:105</div></div>
@@ -83,7 +83,6 @@ $(document).ready(function(){initNavTree('spixr__regs_8h_source.html','');});
 <div class="ttc" id="structmxc__spixr__regs__t_html_a5ba44f6f49bfb1e8245abb85bba9a215"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a5ba44f6f49bfb1e8245abb85bba9a215">mxc_spixr_regs_t::xmem_ctrl</a></div><div class="ttdeci">__IO uint32_t xmem_ctrl</div><div class="ttdoc">0x34: SPIXR XMEM_CTRL Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:106</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html_a661e2879ea52ba18153757482845a8f0"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a661e2879ea52ba18153757482845a8f0">mxc_spixr_regs_t::ctrl1</a></div><div class="ttdeci">__IO uint32_t ctrl1</div><div class="ttdoc">0x04: SPIXR CTRL1 Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:94</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html_a753c4fc439e94fa35b6d29a6075add3d"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a753c4fc439e94fa35b6d29a6075add3d">mxc_spixr_regs_t::ctrl2</a></div><div class="ttdeci">__IO uint32_t ctrl2</div><div class="ttdoc">0x08: SPIXR CTRL2 Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:95</div></div>
-<div class="ttc" id="structmxc__spixr__regs__t_html_a90608b29b3f3212205facf083fc3864e"><div class="ttname"><a href="structmxc__spixr__regs__t.html#a90608b29b3f3212205facf083fc3864e">mxc_spixr_regs_t::i2s_ctrl</a></div><div class="ttdeci">__IO uint32_t i2s_ctrl</div><div class="ttdoc">0x18: SPIXR I2S_CTRL Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:99</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html"><div class="ttname"><a href="structmxc__spixr__regs__t.html">mxc_spixr_regs_t</a></div><div class="ttdoc">Structure type to access the SPIXR Registers. </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:88</div></div>
 <div class="ttc" id="structmxc__spixr__regs__t_html_ad3be5055a12fdff0e232874b09de6cf8"><div class="ttname"><a href="structmxc__spixr__regs__t.html#ad3be5055a12fdff0e232874b09de6cf8">mxc_spixr_regs_t::wakee</a></div><div class="ttdeci">__IO uint32_t wakee</div><div class="ttdoc">0x2C: SPIXR WAKEE Register </div><div class="ttdef"><b>Definition:</b> spixr_regs.h:104</div></div>
 </div><!-- fragment --></div><!-- contents -->
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 <hr/>The documentation for this struct was generated from the following file:<ul>
 <li><a class="el" href="pwrseq__regs_8h_source.html">pwrseq_regs.h</a></li>
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diff --git a/lib/sdk/Documentation/html/structmxc__rpu__regs__t.html b/lib/sdk/Documentation/html/structmxc__rpu__regs__t.html
index 48ced22ff5532ccbbaf73edb471f3264f429b1bf..cc90fadb1434bbe92d55508d63efceb224ac534b 100644
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 <hr/>The documentation for this struct was generated from the following file:<ul>
 <li><a class="el" href="rpu__regs_8h_source.html">rpu_regs.h</a></li>
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 <hr/>The documentation for this struct was generated from the following file:<ul>
 <li><a class="el" href="spixf__regs_8h_source.html">spixf_regs.h</a></li>
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-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. 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97</a></span>&#160;    __O  uint32_t din[4];               </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a0bf2f520b1749fa09614dab3c49ccaa6">   98</a></span>&#160;    __I  uint32_t dout[4];              </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a04cfbc3711cdeede6a53cd54aaeddd8a">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a04cfbc3711cdeede6a53cd54aaeddd8a">crc_poly</a>;             </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a211246cae50e17b2cd2184ab2c393388">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a211246cae50e17b2cd2184ab2c393388">crc_val</a>;              </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#af5b7b889d42f860c490733857a63f6cc">  101</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__tpu__regs__t.html#af5b7b889d42f860c490733857a63f6cc">crc_prng</a>;             </div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a59bd78da163966649f52f8ae5936b464">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a59bd78da163966649f52f8ae5936b464">ham_ecc</a>;              </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a5845efef90dfc1934a2c443ded11b17a">  103</a></span>&#160;    __IO uint32_t cipher_init[4];       </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#abde07012be6c77b24cd874cbdb1f97ac">  104</a></span>&#160;    __O  uint32_t cipher_key[8];        </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a11f8d39bfc89eac8096acb7962c7bfde">  105</a></span>&#160;    __IO uint32_t hash_digest[16];      </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a0e1ab4f2789032777463fb3543eb26d6">  106</a></span>&#160;    __IO uint32_t hash_msg_sz[4];       </div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a39d63fb6f5a645c9442a1f3a2b8ac5ce">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a39d63fb6f5a645c9442a1f3a2b8ac5ce">maa_maws</a>;             </div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;} <a class="code" href="structmxc__tpu__regs__t.html">mxc_tpu_regs_t</a>;</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;<span class="comment">/* Register offsets for module TPU */</span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga9b90235e0e6cdc04035302a7ecd70eb6">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CTRL                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga71b00749b9e113af749cd01db398c999">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CIPHER_CTRL              ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaa5b92daab067925c0f1f841c0c1357b6">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HASH_CTRL                ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaf6d472a37a2342e740967d62d394b596">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_CTRL                 ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaec4b2bc1fdc199088fd66b7f44f729ee">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DMA_SRC                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga2719564f5d611bee5a2641c756d4f92d">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DMA_DEST                 ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga43aeece711ee37737ab17a2151145c6b">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DMA_CNT                  ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga370213f0d79b4ac2e8514da6096722e7">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_MAA_CTRL                 ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga3c4bd802a2c5da03f96e5ef3a6771cc3">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DIN                      ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga968d62e5ff676c6ac9fce3bef2be0883">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DOUT                     ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga21b620a30d49a346c30930e5ec4e4ead">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_POLY                 ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga4bfe7f4adac952b4c4a2bf62bd1e6178">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_VAL                  ((uint32_t)0x00000044UL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga8b599cd0151fb4e2345884be55862c05">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_PRNG                 ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaa23d85e07ce3ac03340fb9c9738fb26c">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HAM_ECC                  ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga1d86e37c3f16cc513ca8843200694dc2">  131</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CIPHER_INIT              ((uint32_t)0x00000050UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gab7f7ac7ad207de056563de9900ccd9e8">  132</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CIPHER_KEY               ((uint32_t)0x00000060UL) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gad1190093b1a89180f4dcefa8e4e7fbaf">  133</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HASH_DIGEST              ((uint32_t)0x00000080UL) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gab318a33f2e91571727978ffe3e922d8e">  134</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HASH_MSG_SZ              ((uint32_t)0x000000C0UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga00d10e0d576f8d08e463c66f4e912e73">  135</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_MAA_MAWS                 ((uint32_t)0x000000D0UL) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gabbbe0f27d11384d28acb8f1b4e954011">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RST_POS                         0 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gad3e19787952ee8127e329880905ebd66">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_RST_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga639147b157731be67d7febf6d96b1fff">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_INTR_POS                        1 </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaa24e825f76d0b32f30ec6a029a09fc67">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_INTR                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_INTR_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga7fd033c2f8a2b44dabc1a065f325584e">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_SRC_POS                         2 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga207b247b5e83528d1fdbc2a7d724f64c">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_SRC                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_SRC_POS)) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaa0846dbb96cf7c6faf4b92b209bf393d">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSO_POS                         4 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3e406fb83b8c52bedb4207d5c4e7a2b3">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSO                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_BSO_POS)) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaeb3c8e8924330519ca199cc579c9a83f">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSI_POS                         5 </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga44ce01dff842981362bd6a7e709c3db4">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSI                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_BSI_POS)) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gae2fc57c0b70ba46c28650655f1871229">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_EN_POS                     6 </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga5dc38e8e9705ddb8beb674a4deb0b990">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_EN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_WAIT_EN_POS)) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga9ad1d5e72f5d547e43878d91ff62abcb">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_POL_POS                    7 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga25f45a368d5f33d02efdd2189509ee24">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_POL                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_WAIT_POL_POS)) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3bd2a7376da4e880c57696fe4d28bc2e">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WRSRC_POS                       8 </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga80b654d77a5b72e9412657f759f941b4">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WRSRC                           ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_CTRL_WRSRC_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga893e8b9ac852b59eff8a6723a97d7fec">  167</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_WRSRC_NONE                      ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaf90b9cfa37d2d6ffa5651bdbf29a089d">  168</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_WRSRC_NONE                      (MXC_V_TPU_CTRL_WRSRC_NONE &lt;&lt; MXC_F_TPU_CTRL_WRSRC_POS) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga0629f5ae6f0fe590408b9f254a7b5eff">  169</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT    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name="l00174"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaf70cff22a853abcfae41fb8cd744f698">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDSRC_POS                       10 </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gadd98bccf78f8aaa5e8d9cfad99617b5b">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDSRC                           ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS)) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga2ed0580d352d11e0fc3f3fd540b4069a">  176</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_RDSRC_DMADISABLED               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3df0ce544b0cf5c945f2b1231c6e487a">  177</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_RDSRC_DMADISABLED               (MXC_V_TPU_CTRL_RDSRC_DMADISABLED &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gae52b9d124131c78a04f61e720ab1ad76">  178</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_RDSRC_DMAORAPB                  ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga34c67d3744ff35675ad89574c5f525b8">  179</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_RDSRC_DMAORAPB                  (MXC_V_TPU_CTRL_RDSRC_DMAORAPB &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS) </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga204fd4f48ee421a68ea1b946ad838433">  180</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_RDSRC_RNG                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3f0baa02daf42954913a4ad4805d48c2">  181</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_RDSRC_RNG                       (MXC_V_TPU_CTRL_RDSRC_RNG &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS) </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaa09201c24ac6956be3f9e7c3b34569d4">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_FLAG_MODE_POS                   14 </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga26744a0ba2242f1d5a6edda25303a1a5">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_FLAG_MODE                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_FLAG_MODE_POS)) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaafbc036b88573bc80d81d835b1232853">  186</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMADNEMSK_POS                   15 </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gab02e3d8fbd415d7c49c320eb3a45fd14">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMADNEMSK                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_DMADNEMSK_POS)) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga1d84a1c9574d25c3ffef48e4e2a051f5">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMA_DONE_POS                    24 </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga8a0a0e2ccf214775a4ea194883564fd7">  190</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMA_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_DMA_DONE_POS)) </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaef3d4129169904139eae3b0fdf0b6232">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_GLS_DONE_POS                    25 </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga115e4f37d01122eab5e8d6aa3f64185a">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_GLS_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_GLS_DONE_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga7c7a2c341c7c5fc5dd700d4721826c80">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_HSH_DONE_POS                    26 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga092749da81fe2d453df3461ffa3b58e6">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_HSH_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_HSH_DONE_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gac6afbcc9b38bf95cac2221669fe2677f">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_CPH_DONE_POS                    27 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3057349f0659f5b9b12b9f59ba87fc48">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_CPH_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_CPH_DONE_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga529e9f99bf57a446ae26a3df976fb8dd">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_MAA_DONE_POS                    28 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga42d89e9e3a68beff44bfc2b68acf170b">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_MAA_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_MAA_DONE_POS)) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga8db0ae217f9c2e418b6f265ece6b5742">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_ERR_POS                         29 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga8f6d1aad20bb9321d853f7489dfeccb0">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_ERR                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_ERR_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3450aef79694fabcc46ce1e079562791">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDY_POS                         30 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga4b888ecaa9337c4775336279f5ccd0ad">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDY                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_RDY_POS)) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gac4619156ed42d8de46358b037d0a334d">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DONE_POS                        31 </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga541093e93516f26ab030b602c3a14271">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DONE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_DONE_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae0980dddfc36bad667b67336f47723c9">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_ENC_POS                  0 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga4ca0536fc51da6260d593f3e3902f784">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_ENC                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_ENC_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga77874b956bc436778fe00efe871eda16">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_KEY_POS                  1 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaca36d68d2f2a30b92fcbd2d0f2954ce1">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_KEY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_KEY_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga2d2f3009211f5ece6fa8e71cfbb3329f">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_SRC_POS                  2 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga5d5056d08f064ddb252508b5164fdac8">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_SRC                      ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS)) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gadc618d92fc7fb514cd06c848867e4b5b">  229</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga0d406eba8016a51193d651c306f0449c">  230</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY            (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga0ab60bb160fe73ebafeb5ab3ae8a6a36">  231</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga1c161b85522d1720f3c691603479fb88">  232</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE              (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga4985927492db85c4a75638103018752d">  233</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaa1a90182456d409cb3cea9f4a270027e">  234</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE      (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gad14053f9b0624eafcdea997923c79232">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS               4 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaf100190fb11555a7ad8aebc92644cd25">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_CIPHER                   ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga69e93b182092994dcb828ac94490ec7d">  238</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaad85731f4ab73b5e2cbf9323a100733c">  239</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS               (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga74eb76bd1833bb274b3d9562890fc6f6">  240</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga8982350b66fc1b456876a3fcb590d269">  241</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128            (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga3ad5eef988419fc2c9ae8960ad591510">  242</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae843a1340e83e3b3ecd27fcaed1424da">  243</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192            (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaa2f4869292d84a212061c50e03fb8966">  244</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae163023f26fb8112c99c58de7a686eae">  245</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256            (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga85660b3e44b19b214ed8beeb8d2e3720">  246</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES               ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga82ba96f2a0ee312a39f4321e50ab2c2a">  247</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES               (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaba4049cde6f3d43d0970ad2413ce0a2f">  248</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES              ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga2b8524a69728dd33d00e4bcb1d5f3c56">  249</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES              (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga5ce932b51178512d97e0796390d5c339">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_MODE_POS                 8 </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae89ec32da6dae9becb9cbe47a4109848">  252</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_MODE                     ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS)) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga9841599d3e516b20b75eda05a7d67755">  253</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_ECB                 ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gac67c0005fd89251bf3105918bac0e923">  254</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_ECB                 (MXC_V_TPU_CIPHER_CTRL_MODE_ECB &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaa742bc84a3d8cf5c82366e5bd1ad2579">  255</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_CBC                 ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gade29372cf128cff9900893c8a1fce18a">  256</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_CBC                 (MXC_V_TPU_CIPHER_CTRL_MODE_CBC &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga32fccf088eea39ee5a3151f133dd9168">  257</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_CFB                 ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae2a24a0893d0d755e2a7a3d6ca7ee25c">  258</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_CFB                 (MXC_V_TPU_CIPHER_CTRL_MODE_CFB &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gab68c10e45d4d6f85fbc07bba15f0d874">  259</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_OFB                 ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga3b3f18ea61a76130d9aaafdecfec60f0">  260</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_OFB                 (MXC_V_TPU_CIPHER_CTRL_MODE_OFB &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae3418cea719487e4e26d1b1d40c4e71e">  261</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_CTR                 ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaf75965ae997d92cf1e3bb9a4bbabe347">  262</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_CTR                 (MXC_V_TPU_CIPHER_CTRL_MODE_CTR &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga915a7eb2b699c05473070acd4761fb94">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_INIT_POS                   0 </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga172bbd10ce23736b0e2eb94fb375d284">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_INIT                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HASH_CTRL_INIT_POS)) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga5285584cc5da6500a802204e9e841989">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_XOR_POS                    1 </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaa99b5feeeae989688561bb418f1fd40f">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_XOR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HASH_CTRL_XOR_POS)) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaecafcb91bf7190d1b8d2e0cc70820d97">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_HASH_POS                   2 </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gac3b5bd01a1e011085c5aac7d22c0fbd6">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_HASH                       ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS)) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga22a4f209694ff07494d69d08ac880fd3">  280</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_DIS                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga0c92ece57e7925ac7c8f253200b14ef4">  281</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_DIS                   (MXC_V_TPU_HASH_CTRL_HASH_DIS &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gafadd2a841da7968d02359d4b93f61779">  282</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA1                  ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga99a07c9f10d44ed18cbb6d14de2d7b46">  283</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA1                  (MXC_V_TPU_HASH_CTRL_HASH_SHA1 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga7e625063c05a6bfa2de0ea355b04402e">  284</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA224                ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga9ed56d6ab8be867c7e7440d85a5bbb4c">  285</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA224                (MXC_V_TPU_HASH_CTRL_HASH_SHA224 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga520c1d2f7d9191c4be30e2b0fc43389b">  286</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA256                ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga5bea20ef6fbc4c8d6a28920cc47fc305">  287</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA256                (MXC_V_TPU_HASH_CTRL_HASH_SHA256 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gacee679a8f75f7d934f33258f2a679fc1">  288</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA384                ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga09830fead73f429019889cd7d3b04249">  289</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA384                (MXC_V_TPU_HASH_CTRL_HASH_SHA384 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaffbe6b4385618a861bb8b8a7d160c903">  290</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA512                ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gab65fd32044bf5a75062a2f395ad76f8c">  291</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA512                (MXC_V_TPU_HASH_CTRL_HASH_SHA512 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaf41cac83ad328894465e7d656598fa6f">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_LAST_POS                   5 </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga9fc82a5e3833fd894a14bc7f7b7b8178">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_LAST                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HASH_CTRL_LAST_POS)) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga1ff0c34a2d96dc786986bf4ed79fa2fa">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_CRC_POS                     0 </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga91b177797e2625818f5d6b381ba57b54">  305</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_CRC                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_CRC_POS)) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga77101b0d592754b2dee71a9f2109ef60">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_MSB_POS                     1 </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaab99efbdc3c3729c3deb047396f786b0">  308</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_MSB                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_MSB_POS)) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gade18733e556ba5c5753ca533a578b8ad">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_PRNG_POS                    2 </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaacc426a4342dfbc3d2f48574b3ff2c17">  311</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_PRNG                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_PRNG_POS)) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gad79a573cb818b0ec30461dc89b58987b">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_ENT_POS                     3 </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga2b3e004ca6339388c59bb5d905ee2da6">  314</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_ENT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_ENT_POS)) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gacf94f956b9c641dbbde085e028de73f9">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HAM_POS                     4 </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaf5e63ab37f1bb0540141a4bbf55a7149">  317</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HAM                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_HAM_POS)) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga710c4055a1b0621ef73fef6a81bb41dd">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HRST_POS                    5 </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaf4694ff5049a584bada0e1dd96ec605c">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HRST                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_HRST_POS)) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__TPU__DMA__SRC.html#ga0ada2de9f3c8b2a41a0d2ed6fc30e9fa">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_SRC_ADDR_POS                     0 </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__TPU__DMA__SRC.html#ga9aa962213037ca5e16c884d8b313ecc7">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_SRC_ADDR                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DMA_SRC_ADDR_POS)) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__TPU__DMA__DEST.html#ga35def1b8a97ef8c9e1601e95cbb50a33">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_DEST_ADDR_POS                    0 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__TPU__DMA__DEST.html#ga7c5bd80c00860c2255ce67015d9c61c6">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_DEST_ADDR                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DMA_DEST_ADDR_POS)) </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__TPU__DMA__CNT.html#ga55939cfcf13b3f5e95b699c4552b8545">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_CNT_ADDR_POS                     0 </span></div><div class="line"><a name="l00353"></a><span class="lineno"><a class="line" href="group__TPU__DMA__CNT.html#gad80a471a7e3aba41a0040634aa3ec577">  353</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_CNT_ADDR                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DMA_CNT_ADDR_POS)) </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga0fb02865b6d48afabca8d7e6f521cf3e">  363</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_STC_POS                     0 </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga4696f027692b28a406caf56930a4507e">  364</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_STC                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_MAA_CTRL_STC_POS)) </span></div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga96490cd3b68fac9a71fdcd02f4416e7a">  366</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_CLC_POS                     1 </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaff020799aba131c24b41442a59b42f1e">  367</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_CLC                         ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS)) </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga63271db03d60725dcf80074f98b3f121">  368</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_EXP                     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga1e86863139378b344192149110c20373">  369</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_EXP                     (MXC_V_TPU_MAA_CTRL_CLC_EXP &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga7359a3bbbe8ad1c23baac8f4d302bdb3">  370</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_SQ                      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gad166d149afcc15223d155e8ee71c3edc">  371</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_SQ                      (MXC_V_TPU_MAA_CTRL_CLC_SQ &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaac98a3ef3475e989801be9c5cadcd89a">  372</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_MUL                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gad746b8e51fcccbcff98dfced3f471985">  373</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_MUL                     (MXC_V_TPU_MAA_CTRL_CLC_MUL &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga6a85715d262feb610bd77abbd712eed9">  374</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_SQMUL                   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga042426579028763439bdd35185c438b6">  375</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_SQMUL                   (MXC_V_TPU_MAA_CTRL_CLC_SQMUL &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga196d2ac1e7197b6d30cd7882979bf625">  376</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_ADD                     ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga89326d071f987a791d5d65fe84208528">  377</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_ADD                     (MXC_V_TPU_MAA_CTRL_CLC_ADD &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gada106b9c5327c5ebed18b95175869382">  378</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_SUB                     ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga62d5e2e8e42685c2b40131137a8ed440">  379</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_SUB                     (MXC_V_TPU_MAA_CTRL_CLC_SUB &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaa28eedff175b571dab047ebdc1c1cb67">  381</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_OCALC_POS                   4 </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaf9ccc0e6f737bf59dd45c502a72c287b">  382</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_OCALC                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_MAA_CTRL_OCALC_POS)) </span></div><div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga32774fc4945cd3af8b0a5c40b98f7e99">  384</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MAAER_POS                   7 </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga5731f16c12feab22f32fe75b685f445b">  385</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MAAER                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_MAA_CTRL_MAAER_POS)) </span></div><div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga1131142a333ea84e86271221353c29a4">  387</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMS_POS                     8 </span></div><div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga8ed0de7a83e39f5779a003964805674c">  388</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_AMS_POS)) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaace0acb44c620c11d960d82a61023352">  390</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_BMS_POS                     10 </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga922028e4ff3e1c9995463acf2c2f1dfa">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_BMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_BMS_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaa9bdce683b168db88edb37235c983d5a">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_EMS_POS                     12 </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga82a797d9a2254fda6f3437ab4000ace1">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_EMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_EMS_POS)) </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga77017321109b1004502928183b07f818">  396</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MMS_POS                     14 </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga34d2125033dc1f0e940e0dd3ac8f11be">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_MMS_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gace10de676166d95a58d9e7b52a984315">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMA_POS                     16 </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gacc726643bb17e2c5921d82cfb5313729">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMA                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_TPU_MAA_CTRL_AMA_POS)) </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga47c93b58e9e12102ac0777775cb6c3f5">  402</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_BMA_POS                     20 </span></div><div class="line"><a name="l00403"></a><span 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href="group__TPU__MAA__CTRL.html#ga5f548e79ee8daf4d16e3ff4ae067b280">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_TMA_POS                     28 </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga61d8de9c77f92ad64812b6b325ba529d">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_TMA                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_TPU_MAA_CTRL_TMA_POS)) </span></div><div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group__TPU__DIN.html#gafacc2048f6134c08dc61d989bf99ad0c">  423</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DIN_DATA_POS                         0 </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group__TPU__DIN.html#ga0a038578988a7baad09b82ea22159701">  424</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DIN_DATA                  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476</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_PRNG_PRNG_POS                    0 </span></div><div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="group__TPU__CRC__PRNG.html#ga0e0edfbda7a090dc3079338803acf5f5">  477</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_PRNG_PRNG                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CRC_PRNG_PRNG_POS)) </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#ga442bd53f7c227b2c86bcf6bf78b6e4bf">  487</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_ECC_POS                      0 </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#ga60186a9df4ef9a0de15f0537aad85c87">  488</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_ECC                          ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_TPU_HAM_ECC_ECC_POS)) </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#ga38bf432e5099ff2d4bb191bf83c3b5ca">  490</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_PAR_POS                      16 </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#gaed00f4f52f2265aeb759080eac65c104">  491</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_PAR                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HAM_ECC_PAR_POS)) </span></div><div class="line"><a name="l00504"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__INIT.html#ga4a43edf6e4ac5a10a38cb32f46c2e1fb">  504</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_INIT_IVEC_POS                 0 </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__INIT.html#gaa64fc3823c9b5de5e3b59b2a4728e096">  505</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_INIT_IVEC                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CIPHER_INIT_IVEC_POS)) </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__KEY.html#gaf79a3c51b0a0935046f6fd610b31716f">  517</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_KEY_KEY_POS                   0 </span></div><div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__KEY.html#gaad15fabba1781c708c7050f69fe0aa86">  518</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_KEY_KEY                       ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CIPHER_KEY_KEY_POS)) </span></div><div class="line"><a name="l00529"></a><span class="lineno"><a class="line" href="group__TPU__HASH__DIGEST.html#ga80a0d4a8b0be68af650507354923d795">  529</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_DIGEST_HASH_POS                 0 </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__TPU__HASH__DIGEST.html#ga6f729ad2d0443ad8cd1bc1c275dc1d99">  530</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_DIGEST_HASH                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_HASH_DIGEST_HASH_POS)) </span></div><div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group__TPU__HASH__MSG__SZ.html#ga3ee63c71bcf2d4278eed6d71a36da0cb">  540</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS                0 </span></div><div class="line"><a name="l00541"></a><span class="lineno"><a class="line" href="group__TPU__HASH__MSG__SZ.html#ga846f33739b9b4df01977822bbf232fa9">  541</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ                    ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) </span></div><div class="line"><a name="l00554"></a><span class="lineno"><a class="line" href="group__TPU__MAA__MAWS.html#ga2433639055e7de96929eb58881bb0925">  554</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_MAWS_MAWS_POS                    0 </span></div><div class="line"><a name="l00555"></a><span class="lineno"><a class="line" href="group__TPU__MAA__MAWS.html#gac99c082bc55e64ae001b09bcc808ac5c">  555</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_MAWS_MAWS                        ((uint32_t)(0xFFFUL &lt;&lt; MXC_F_TPU_MAA_MAWS_MAWS_POS)) </span></div><div class="line"><a name="l00559"></a><span class="lineno">  559</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00560"></a><span class="lineno">  560</span>&#160;}</div><div class="line"><a name="l00561"></a><span class="lineno">  561</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00562"></a><span class="lineno">  562</span>&#160;</div><div class="line"><a name="l00563"></a><span class="lineno">  563</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _TPU_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__tpu__regs__t_html_a3958f62fed97499e0909e5f69ddb43d7"><div class="ttname"><a href="structmxc__tpu__regs__t.html#a3958f62fed97499e0909e5f69ddb43d7">mxc_tpu_regs_t::ctrl</a></div><div class="ttdeci">__IO uint32_t ctrl</div><div class="ttdoc">0x00: TPU CTRL Register </div><div class="ttdef"><b>Definition:</b> tpu_regs.h:89</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _TPU_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _TPU_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a3958f62fed97499e0909e5f69ddb43d7">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a3958f62fed97499e0909e5f69ddb43d7">ctrl</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#ad6b3f984740b9ae0cf10317cf7e85848">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#ad6b3f984740b9ae0cf10317cf7e85848">cipher_ctrl</a>;          </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a9cc570428b85774eec9b94a3bf49adc4">   91</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a9cc570428b85774eec9b94a3bf49adc4">hash_ctrl</a>;            </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#ad9b8966022c1dd30520f790952df945c">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#ad9b8966022c1dd30520f790952df945c">crc_ctrl</a>;             </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#af8857a2a785fe29462609e32d76b38e0">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#af8857a2a785fe29462609e32d76b38e0">dma_src</a>;              </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a4cc827b3561f0ca9f5d78d07d5a688fe">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a4cc827b3561f0ca9f5d78d07d5a688fe">dma_dest</a>;             </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a2bebf05744da0588db005661058cb8e8">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a2bebf05744da0588db005661058cb8e8">dma_cnt</a>;              </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a46af8f8034d6f60c09bbe49b5bccaa34">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a46af8f8034d6f60c09bbe49b5bccaa34">maa_ctrl</a>;             </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a04befd7fbebc5732869b59ad898e4109">   97</a></span>&#160;    __O  uint32_t din[4];               </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a0bf2f520b1749fa09614dab3c49ccaa6">   98</a></span>&#160;    __I  uint32_t dout[4];              </div><div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a04cfbc3711cdeede6a53cd54aaeddd8a">   99</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a04cfbc3711cdeede6a53cd54aaeddd8a">crc_poly</a>;             </div><div class="line"><a name="l00100"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a211246cae50e17b2cd2184ab2c393388">  100</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a211246cae50e17b2cd2184ab2c393388">crc_val</a>;              </div><div class="line"><a name="l00101"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#af5b7b889d42f860c490733857a63f6cc">  101</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__tpu__regs__t.html#af5b7b889d42f860c490733857a63f6cc">crc_prng</a>;             </div><div class="line"><a name="l00102"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a59bd78da163966649f52f8ae5936b464">  102</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a59bd78da163966649f52f8ae5936b464">ham_ecc</a>;              </div><div class="line"><a name="l00103"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a5845efef90dfc1934a2c443ded11b17a">  103</a></span>&#160;    __IO uint32_t cipher_init[4];       </div><div class="line"><a name="l00104"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#abde07012be6c77b24cd874cbdb1f97ac">  104</a></span>&#160;    __O  uint32_t cipher_key[8];        </div><div class="line"><a name="l00105"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a11f8d39bfc89eac8096acb7962c7bfde">  105</a></span>&#160;    __IO uint32_t hash_digest[16];      </div><div class="line"><a name="l00106"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a0e1ab4f2789032777463fb3543eb26d6">  106</a></span>&#160;    __IO uint32_t hash_msg_sz[4];       </div><div class="line"><a name="l00107"></a><span class="lineno"><a class="line" href="structmxc__tpu__regs__t.html#a39d63fb6f5a645c9442a1f3a2b8ac5ce">  107</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__tpu__regs__t.html#a39d63fb6f5a645c9442a1f3a2b8ac5ce">maa_maws</a>;             </div><div class="line"><a name="l00108"></a><span class="lineno">  108</span>&#160;} <a class="code" href="structmxc__tpu__regs__t.html">mxc_tpu_regs_t</a>;</div><div class="line"><a name="l00109"></a><span class="lineno">  109</span>&#160;</div><div class="line"><a name="l00110"></a><span class="lineno">  110</span>&#160;<span class="comment">/* Register offsets for module TPU */</span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga9b90235e0e6cdc04035302a7ecd70eb6">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CTRL                     ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00118"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga71b00749b9e113af749cd01db398c999">  118</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CIPHER_CTRL              ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00119"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaa5b92daab067925c0f1f841c0c1357b6">  119</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HASH_CTRL                ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00120"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaf6d472a37a2342e740967d62d394b596">  120</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_CTRL                 ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00121"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaec4b2bc1fdc199088fd66b7f44f729ee">  121</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DMA_SRC                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00122"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga2719564f5d611bee5a2641c756d4f92d">  122</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DMA_DEST                 ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00123"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga43aeece711ee37737ab17a2151145c6b">  123</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DMA_CNT                  ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00124"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga370213f0d79b4ac2e8514da6096722e7">  124</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_MAA_CTRL                 ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00125"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga3c4bd802a2c5da03f96e5ef3a6771cc3">  125</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DIN                      ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga968d62e5ff676c6ac9fce3bef2be0883">  126</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_DOUT                     ((uint32_t)0x00000030UL) </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga21b620a30d49a346c30930e5ec4e4ead">  127</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_POLY                 ((uint32_t)0x00000040UL) </span></div><div class="line"><a name="l00128"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga4bfe7f4adac952b4c4a2bf62bd1e6178">  128</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_VAL                  ((uint32_t)0x00000044UL) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga8b599cd0151fb4e2345884be55862c05">  129</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CRC_PRNG                 ((uint32_t)0x00000048UL) </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gaa23d85e07ce3ac03340fb9c9738fb26c">  130</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HAM_ECC                  ((uint32_t)0x0000004CUL) </span></div><div class="line"><a name="l00131"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga1d86e37c3f16cc513ca8843200694dc2">  131</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CIPHER_INIT              ((uint32_t)0x00000050UL) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gab7f7ac7ad207de056563de9900ccd9e8">  132</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_CIPHER_KEY               ((uint32_t)0x00000060UL) </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gad1190093b1a89180f4dcefa8e4e7fbaf">  133</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HASH_DIGEST              ((uint32_t)0x00000080UL) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#gab318a33f2e91571727978ffe3e922d8e">  134</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_HASH_MSG_SZ              ((uint32_t)0x000000C0UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__TPU__Register__Offsets.html#ga00d10e0d576f8d08e463c66f4e912e73">  135</a></span>&#160;<span class="preprocessor"> #define MXC_R_TPU_MAA_MAWS                 ((uint32_t)0x000000D0UL) </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gabbbe0f27d11384d28acb8f1b4e954011">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RST_POS                         0 </span></div><div class="line"><a name="l00145"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gad3e19787952ee8127e329880905ebd66">  145</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RST                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_RST_POS)) </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga639147b157731be67d7febf6d96b1fff">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_INTR_POS                        1 </span></div><div class="line"><a name="l00148"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaa24e825f76d0b32f30ec6a029a09fc67">  148</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_INTR                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_INTR_POS)) </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga7fd033c2f8a2b44dabc1a065f325584e">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_SRC_POS                         2 </span></div><div class="line"><a name="l00151"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga207b247b5e83528d1fdbc2a7d724f64c">  151</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_SRC                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_SRC_POS)) </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaa0846dbb96cf7c6faf4b92b209bf393d">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSO_POS                         4 </span></div><div class="line"><a name="l00154"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3e406fb83b8c52bedb4207d5c4e7a2b3">  154</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSO                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_BSO_POS)) </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaeb3c8e8924330519ca199cc579c9a83f">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSI_POS                         5 </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga44ce01dff842981362bd6a7e709c3db4">  157</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_BSI                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_BSI_POS)) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gae2fc57c0b70ba46c28650655f1871229">  159</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_EN_POS                     6 </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga5dc38e8e9705ddb8beb674a4deb0b990">  160</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_EN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_WAIT_EN_POS)) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga9ad1d5e72f5d547e43878d91ff62abcb">  162</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_POL_POS                    7 </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga25f45a368d5f33d02efdd2189509ee24">  163</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WAIT_POL                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_WAIT_POL_POS)) </span></div><div class="line"><a name="l00165"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3bd2a7376da4e880c57696fe4d28bc2e">  165</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WRSRC_POS                       8 </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga80b654d77a5b72e9412657f759f941b4">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_WRSRC                           ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_CTRL_WRSRC_POS)) </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga893e8b9ac852b59eff8a6723a97d7fec">  167</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_WRSRC_NONE                      ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00168"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaf90b9cfa37d2d6ffa5651bdbf29a089d">  168</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_WRSRC_NONE                      (MXC_V_TPU_CTRL_WRSRC_NONE &lt;&lt; MXC_F_TPU_CTRL_WRSRC_POS) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga0629f5ae6f0fe590408b9f254a7b5eff">  169</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT              ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga1ff5321d58b2c9d69867285d4bea6b63">  170</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT              (MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT &lt;&lt; MXC_F_TPU_CTRL_WRSRC_POS) </span></div><div class="line"><a name="l00171"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga16872f85c39a323b9dbb3a464606d85a">  171</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_WRSRC_READFIFO                  ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gae6420652ea3f0a69b48e9828a9887b1c">  172</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_WRSRC_READFIFO                  (MXC_V_TPU_CTRL_WRSRC_READFIFO &lt;&lt; MXC_F_TPU_CTRL_WRSRC_POS) </span></div><div class="line"><a name="l00174"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaf70cff22a853abcfae41fb8cd744f698">  174</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDSRC_POS                       10 </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gadd98bccf78f8aaa5e8d9cfad99617b5b">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDSRC                           ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS)) </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga2ed0580d352d11e0fc3f3fd540b4069a">  176</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_RDSRC_DMADISABLED               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00177"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3df0ce544b0cf5c945f2b1231c6e487a">  177</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_RDSRC_DMADISABLED               (MXC_V_TPU_CTRL_RDSRC_DMADISABLED &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gae52b9d124131c78a04f61e720ab1ad76">  178</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_RDSRC_DMAORAPB                  ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga34c67d3744ff35675ad89574c5f525b8">  179</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_RDSRC_DMAORAPB                  (MXC_V_TPU_CTRL_RDSRC_DMAORAPB &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS) </span></div><div class="line"><a name="l00180"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga204fd4f48ee421a68ea1b946ad838433">  180</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CTRL_RDSRC_RNG                       ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3f0baa02daf42954913a4ad4805d48c2">  181</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CTRL_RDSRC_RNG                       (MXC_V_TPU_CTRL_RDSRC_RNG &lt;&lt; MXC_F_TPU_CTRL_RDSRC_POS) </span></div><div class="line"><a name="l00183"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaa09201c24ac6956be3f9e7c3b34569d4">  183</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_FLAG_MODE_POS                   14 </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga26744a0ba2242f1d5a6edda25303a1a5">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_FLAG_MODE                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_FLAG_MODE_POS)) </span></div><div class="line"><a name="l00186"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaafbc036b88573bc80d81d835b1232853">  186</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMADNEMSK_POS                   15 </span></div><div class="line"><a name="l00187"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gab02e3d8fbd415d7c49c320eb3a45fd14">  187</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMADNEMSK                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_DMADNEMSK_POS)) </span></div><div class="line"><a name="l00189"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga1d84a1c9574d25c3ffef48e4e2a051f5">  189</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMA_DONE_POS                    24 </span></div><div class="line"><a name="l00190"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga8a0a0e2ccf214775a4ea194883564fd7">  190</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DMA_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_DMA_DONE_POS)) </span></div><div class="line"><a name="l00192"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gaef3d4129169904139eae3b0fdf0b6232">  192</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_GLS_DONE_POS                    25 </span></div><div class="line"><a name="l00193"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga115e4f37d01122eab5e8d6aa3f64185a">  193</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_GLS_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_GLS_DONE_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga7c7a2c341c7c5fc5dd700d4721826c80">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_HSH_DONE_POS                    26 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga092749da81fe2d453df3461ffa3b58e6">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_HSH_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_HSH_DONE_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gac6afbcc9b38bf95cac2221669fe2677f">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_CPH_DONE_POS                    27 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3057349f0659f5b9b12b9f59ba87fc48">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_CPH_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_CPH_DONE_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga529e9f99bf57a446ae26a3df976fb8dd">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_MAA_DONE_POS                    28 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga42d89e9e3a68beff44bfc2b68acf170b">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_MAA_DONE                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_MAA_DONE_POS)) </span></div><div class="line"><a name="l00204"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga8db0ae217f9c2e418b6f265ece6b5742">  204</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_ERR_POS                         29 </span></div><div class="line"><a name="l00205"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga8f6d1aad20bb9321d853f7489dfeccb0">  205</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_ERR                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_ERR_POS)) </span></div><div class="line"><a name="l00207"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga3450aef79694fabcc46ce1e079562791">  207</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDY_POS                         30 </span></div><div class="line"><a name="l00208"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga4b888ecaa9337c4775336279f5ccd0ad">  208</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_RDY                             ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_RDY_POS)) </span></div><div class="line"><a name="l00210"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#gac4619156ed42d8de46358b037d0a334d">  210</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DONE_POS                        31 </span></div><div class="line"><a name="l00211"></a><span class="lineno"><a class="line" href="group__TPU__CTRL.html#ga541093e93516f26ab030b602c3a14271">  211</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CTRL_DONE                            ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CTRL_DONE_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae0980dddfc36bad667b67336f47723c9">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_ENC_POS                  0 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga4ca0536fc51da6260d593f3e3902f784">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_ENC                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_ENC_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga77874b956bc436778fe00efe871eda16">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_KEY_POS                  1 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaca36d68d2f2a30b92fcbd2d0f2954ce1">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_KEY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_KEY_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga2d2f3009211f5ece6fa8e71cfbb3329f">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_SRC_POS                  2 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga5d5056d08f064ddb252508b5164fdac8">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_SRC                      ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS)) </span></div><div class="line"><a name="l00229"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gadc618d92fc7fb514cd06c848867e4b5b">  229</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY            ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga0d406eba8016a51193d651c306f0449c">  230</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY            (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS) </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga0ab60bb160fe73ebafeb5ab3ae8a6a36">  231</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE              ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00232"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga1c161b85522d1720f3c691603479fb88">  232</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE              (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga4985927492db85c4a75638103018752d">  233</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE      ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaa1a90182456d409cb3cea9f4a270027e">  234</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE      (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE &lt;&lt; MXC_F_TPU_CIPHER_CTRL_SRC_POS) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gad14053f9b0624eafcdea997923c79232">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS               4 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaf100190fb11555a7ad8aebc92644cd25">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_CIPHER                   ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) </span></div><div class="line"><a name="l00238"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga69e93b182092994dcb828ac94490ec7d">  238</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS               ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaad85731f4ab73b5e2cbf9323a100733c">  239</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS               (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga74eb76bd1833bb274b3d9562890fc6f6">  240</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128            ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00241"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga8982350b66fc1b456876a3fcb590d269">  241</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128            (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga3ad5eef988419fc2c9ae8960ad591510">  242</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192            ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae843a1340e83e3b3ecd27fcaed1424da">  243</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192            (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00244"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaa2f4869292d84a212061c50e03fb8966">  244</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256            ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00245"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae163023f26fb8112c99c58de7a686eae">  245</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256            (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00246"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga85660b3e44b19b214ed8beeb8d2e3720">  246</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES               ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00247"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga82ba96f2a0ee312a39f4321e50ab2c2a">  247</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES               (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00248"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaba4049cde6f3d43d0970ad2413ce0a2f">  248</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES              ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00249"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga2b8524a69728dd33d00e4bcb1d5f3c56">  249</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES              (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES &lt;&lt; MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) </span></div><div class="line"><a name="l00251"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga5ce932b51178512d97e0796390d5c339">  251</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_MODE_POS                 8 </span></div><div class="line"><a name="l00252"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae89ec32da6dae9becb9cbe47a4109848">  252</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_CTRL_MODE                     ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS)) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga9841599d3e516b20b75eda05a7d67755">  253</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_ECB                 ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gac67c0005fd89251bf3105918bac0e923">  254</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_ECB                 (MXC_V_TPU_CIPHER_CTRL_MODE_ECB &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00255"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaa742bc84a3d8cf5c82366e5bd1ad2579">  255</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_CBC                 ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gade29372cf128cff9900893c8a1fce18a">  256</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_CBC                 (MXC_V_TPU_CIPHER_CTRL_MODE_CBC &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga32fccf088eea39ee5a3151f133dd9168">  257</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_CFB                 ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00258"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae2a24a0893d0d755e2a7a3d6ca7ee25c">  258</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_CFB                 (MXC_V_TPU_CIPHER_CTRL_MODE_CFB &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gab68c10e45d4d6f85fbc07bba15f0d874">  259</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_OFB                 ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#ga3b3f18ea61a76130d9aaafdecfec60f0">  260</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_OFB                 (MXC_V_TPU_CIPHER_CTRL_MODE_OFB &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00261"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gae3418cea719487e4e26d1b1d40c4e71e">  261</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_CIPHER_CTRL_MODE_CTR                 ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__CTRL.html#gaf75965ae997d92cf1e3bb9a4bbabe347">  262</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_CIPHER_CTRL_MODE_CTR                 (MXC_V_TPU_CIPHER_CTRL_MODE_CTR &lt;&lt; MXC_F_TPU_CIPHER_CTRL_MODE_POS) </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga915a7eb2b699c05473070acd4761fb94">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_INIT_POS                   0 </span></div><div class="line"><a name="l00273"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga172bbd10ce23736b0e2eb94fb375d284">  273</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_INIT                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HASH_CTRL_INIT_POS)) </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga5285584cc5da6500a802204e9e841989">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_XOR_POS                    1 </span></div><div class="line"><a name="l00276"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaa99b5feeeae989688561bb418f1fd40f">  276</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_XOR                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HASH_CTRL_XOR_POS)) </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaecafcb91bf7190d1b8d2e0cc70820d97">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_HASH_POS                   2 </span></div><div class="line"><a name="l00279"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gac3b5bd01a1e011085c5aac7d22c0fbd6">  279</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_HASH                       ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS)) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga22a4f209694ff07494d69d08ac880fd3">  280</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_DIS                   ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga0c92ece57e7925ac7c8f253200b14ef4">  281</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_DIS                   (MXC_V_TPU_HASH_CTRL_HASH_DIS &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00282"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gafadd2a841da7968d02359d4b93f61779">  282</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA1                  ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00283"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga99a07c9f10d44ed18cbb6d14de2d7b46">  283</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA1                  (MXC_V_TPU_HASH_CTRL_HASH_SHA1 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00284"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga7e625063c05a6bfa2de0ea355b04402e">  284</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA224                ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00285"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga9ed56d6ab8be867c7e7440d85a5bbb4c">  285</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA224                (MXC_V_TPU_HASH_CTRL_HASH_SHA224 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00286"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga520c1d2f7d9191c4be30e2b0fc43389b">  286</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA256                ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00287"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga5bea20ef6fbc4c8d6a28920cc47fc305">  287</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA256                (MXC_V_TPU_HASH_CTRL_HASH_SHA256 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00288"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gacee679a8f75f7d934f33258f2a679fc1">  288</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA384                ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00289"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga09830fead73f429019889cd7d3b04249">  289</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA384                (MXC_V_TPU_HASH_CTRL_HASH_SHA384 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00290"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaffbe6b4385618a861bb8b8a7d160c903">  290</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_HASH_CTRL_HASH_SHA512                ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gab65fd32044bf5a75062a2f395ad76f8c">  291</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_HASH_CTRL_HASH_SHA512                (MXC_V_TPU_HASH_CTRL_HASH_SHA512 &lt;&lt; MXC_F_TPU_HASH_CTRL_HASH_POS) </span></div><div class="line"><a name="l00293"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#gaf41cac83ad328894465e7d656598fa6f">  293</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_LAST_POS                   5 </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__TPU__HASH__CTRL.html#ga9fc82a5e3833fd894a14bc7f7b7b8178">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_CTRL_LAST                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HASH_CTRL_LAST_POS)) </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga1ff0c34a2d96dc786986bf4ed79fa2fa">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_CRC_POS                     0 </span></div><div class="line"><a name="l00305"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga91b177797e2625818f5d6b381ba57b54">  305</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_CRC                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_CRC_POS)) </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga77101b0d592754b2dee71a9f2109ef60">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_MSB_POS                     1 </span></div><div class="line"><a name="l00308"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaab99efbdc3c3729c3deb047396f786b0">  308</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_MSB                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_MSB_POS)) </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gade18733e556ba5c5753ca533a578b8ad">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_PRNG_POS                    2 </span></div><div class="line"><a name="l00311"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaacc426a4342dfbc3d2f48574b3ff2c17">  311</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_PRNG                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_PRNG_POS)) </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gad79a573cb818b0ec30461dc89b58987b">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_ENT_POS                     3 </span></div><div class="line"><a name="l00314"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga2b3e004ca6339388c59bb5d905ee2da6">  314</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_ENT                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_ENT_POS)) </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gacf94f956b9c641dbbde085e028de73f9">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HAM_POS                     4 </span></div><div class="line"><a name="l00317"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaf5e63ab37f1bb0540141a4bbf55a7149">  317</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HAM                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_HAM_POS)) </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#ga710c4055a1b0621ef73fef6a81bb41dd">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HRST_POS                    5 </span></div><div class="line"><a name="l00320"></a><span class="lineno"><a class="line" href="group__TPU__CRC__CTRL.html#gaf4694ff5049a584bada0e1dd96ec605c">  320</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_CTRL_HRST                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_CRC_CTRL_HRST_POS)) </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__TPU__DMA__SRC.html#ga0ada2de9f3c8b2a41a0d2ed6fc30e9fa">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_SRC_ADDR_POS                     0 </span></div><div class="line"><a name="l00331"></a><span class="lineno"><a class="line" href="group__TPU__DMA__SRC.html#ga9aa962213037ca5e16c884d8b313ecc7">  331</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_SRC_ADDR                         ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DMA_SRC_ADDR_POS)) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__TPU__DMA__DEST.html#ga35def1b8a97ef8c9e1601e95cbb50a33">  341</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_DEST_ADDR_POS                    0 </span></div><div class="line"><a name="l00342"></a><span class="lineno"><a class="line" href="group__TPU__DMA__DEST.html#ga7c5bd80c00860c2255ce67015d9c61c6">  342</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_DEST_ADDR                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DMA_DEST_ADDR_POS)) </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__TPU__DMA__CNT.html#ga0729ed3035dd2a7a4ac6675c9994fca4">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_CNT_COUNT_POS                    0 </span></div><div class="line"><a name="l00353"></a><span class="lineno"><a class="line" href="group__TPU__DMA__CNT.html#gaa68cdae5364d4218a7527f919ac90f33">  353</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DMA_CNT_COUNT                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DMA_CNT_COUNT_POS)) </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga0fb02865b6d48afabca8d7e6f521cf3e">  363</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_STC_POS                     0 </span></div><div class="line"><a name="l00364"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga4696f027692b28a406caf56930a4507e">  364</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_STC                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_MAA_CTRL_STC_POS)) </span></div><div class="line"><a name="l00366"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga96490cd3b68fac9a71fdcd02f4416e7a">  366</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_CLC_POS                     1 </span></div><div class="line"><a name="l00367"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaff020799aba131c24b41442a59b42f1e">  367</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_CLC                         ((uint32_t)(0x7UL &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS)) </span></div><div class="line"><a name="l00368"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga63271db03d60725dcf80074f98b3f121">  368</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_EXP                     ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00369"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga1e86863139378b344192149110c20373">  369</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_EXP                     (MXC_V_TPU_MAA_CTRL_CLC_EXP &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00370"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga7359a3bbbe8ad1c23baac8f4d302bdb3">  370</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_SQ                      ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00371"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gad166d149afcc15223d155e8ee71c3edc">  371</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_SQ                      (MXC_V_TPU_MAA_CTRL_CLC_SQ &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00372"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaac98a3ef3475e989801be9c5cadcd89a">  372</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_MUL                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gad746b8e51fcccbcff98dfced3f471985">  373</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_MUL                     (MXC_V_TPU_MAA_CTRL_CLC_MUL &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga6a85715d262feb610bd77abbd712eed9">  374</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_SQMUL                   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00375"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga042426579028763439bdd35185c438b6">  375</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_SQMUL                   (MXC_V_TPU_MAA_CTRL_CLC_SQMUL &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga196d2ac1e7197b6d30cd7882979bf625">  376</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_ADD                     ((uint32_t)0x4UL) </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga89326d071f987a791d5d65fe84208528">  377</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_ADD                     (MXC_V_TPU_MAA_CTRL_CLC_ADD &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00378"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gada106b9c5327c5ebed18b95175869382">  378</a></span>&#160;<span class="preprocessor"> #define MXC_V_TPU_MAA_CTRL_CLC_SUB                     ((uint32_t)0x5UL) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga62d5e2e8e42685c2b40131137a8ed440">  379</a></span>&#160;<span class="preprocessor"> #define MXC_S_TPU_MAA_CTRL_CLC_SUB                     (MXC_V_TPU_MAA_CTRL_CLC_SUB &lt;&lt; MXC_F_TPU_MAA_CTRL_CLC_POS) </span></div><div class="line"><a name="l00381"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaa28eedff175b571dab047ebdc1c1cb67">  381</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_OCALC_POS                   4 </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaf9ccc0e6f737bf59dd45c502a72c287b">  382</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_OCALC                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_MAA_CTRL_OCALC_POS)) </span></div><div class="line"><a name="l00384"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga32774fc4945cd3af8b0a5c40b98f7e99">  384</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MAAER_POS                   7 </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga5731f16c12feab22f32fe75b685f445b">  385</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MAAER                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_MAA_CTRL_MAAER_POS)) </span></div><div class="line"><a name="l00387"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga1131142a333ea84e86271221353c29a4">  387</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMS_POS                     8 </span></div><div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga8ed0de7a83e39f5779a003964805674c">  388</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_AMS_POS)) </span></div><div class="line"><a name="l00390"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaace0acb44c620c11d960d82a61023352">  390</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_BMS_POS                     10 </span></div><div class="line"><a name="l00391"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga922028e4ff3e1c9995463acf2c2f1dfa">  391</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_BMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_BMS_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gaa9bdce683b168db88edb37235c983d5a">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_EMS_POS                     12 </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga82a797d9a2254fda6f3437ab4000ace1">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_EMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_EMS_POS)) </span></div><div class="line"><a name="l00396"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga77017321109b1004502928183b07f818">  396</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MMS_POS                     14 </span></div><div class="line"><a name="l00397"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga34d2125033dc1f0e940e0dd3ac8f11be">  397</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_MMS                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_TPU_MAA_CTRL_MMS_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gace10de676166d95a58d9e7b52a984315">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMA_POS                     16 </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#gacc726643bb17e2c5921d82cfb5313729">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_AMA                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_TPU_MAA_CTRL_AMA_POS)) </span></div><div class="line"><a name="l00402"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga47c93b58e9e12102ac0777775cb6c3f5">  402</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_BMA_POS                     20 </span></div><div class="line"><a name="l00403"></a><span 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href="group__TPU__MAA__CTRL.html#ga5f548e79ee8daf4d16e3ff4ae067b280">  408</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_TMA_POS                     28 </span></div><div class="line"><a name="l00409"></a><span class="lineno"><a class="line" href="group__TPU__MAA__CTRL.html#ga61d8de9c77f92ad64812b6b325ba529d">  409</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_CTRL_TMA                         ((uint32_t)(0xFUL &lt;&lt; MXC_F_TPU_MAA_CTRL_TMA_POS)) </span></div><div class="line"><a name="l00423"></a><span class="lineno"><a class="line" href="group__TPU__DIN.html#gafacc2048f6134c08dc61d989bf99ad0c">  423</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DIN_DATA_POS                         0 </span></div><div class="line"><a name="l00424"></a><span class="lineno"><a class="line" href="group__TPU__DIN.html#ga0a038578988a7baad09b82ea22159701">  424</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DIN_DATA                             ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DIN_DATA_POS)) </span></div><div class="line"><a name="l00437"></a><span class="lineno"><a class="line" href="group__TPU__DOUT.html#ga530ec6ce22b8952d837ad5e3d5734b1a">  437</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DOUT_DATA_POS                        0 </span></div><div class="line"><a name="l00438"></a><span class="lineno"><a class="line" href="group__TPU__DOUT.html#gab7c20992a9d5b4471fda1dd7f5711a60">  438</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_DOUT_DATA                            ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_DOUT_DATA_POS)) </span></div><div class="line"><a name="l00450"></a><span class="lineno"><a class="line" href="group__TPU__CRC__POLY.html#ga32a8738660f6d9b3d6536398b01edc45">  450</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_POLY_POLY_POS                    0 </span></div><div class="line"><a name="l00451"></a><span class="lineno"><a class="line" href="group__TPU__CRC__POLY.html#ga3e2dc42749430d864d0e19744cb7b0e5">  451</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_POLY_POLY                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CRC_POLY_POLY_POS)) </span></div><div class="line"><a name="l00463"></a><span class="lineno"><a class="line" href="group__TPU__CRC__VAL.html#gaee4f11991caa89b9d06fb474e32eb71c">  463</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_VAL_VAL_POS                      0 </span></div><div class="line"><a name="l00464"></a><span class="lineno"><a class="line" href="group__TPU__CRC__VAL.html#ga7b2802f71b0f29e1373f4a4ce82b1aa9">  464</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_VAL_VAL                          ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CRC_VAL_VAL_POS)) </span></div><div class="line"><a name="l00476"></a><span class="lineno"><a class="line" href="group__TPU__CRC__PRNG.html#ga4322fa38c288fcbc39e15a800b11aaf7">  476</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_PRNG_PRNG_POS                    0 </span></div><div class="line"><a name="l00477"></a><span class="lineno"><a class="line" href="group__TPU__CRC__PRNG.html#ga0e0edfbda7a090dc3079338803acf5f5">  477</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CRC_PRNG_PRNG                        ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CRC_PRNG_PRNG_POS)) </span></div><div class="line"><a name="l00487"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#ga442bd53f7c227b2c86bcf6bf78b6e4bf">  487</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_ECC_POS                      0 </span></div><div class="line"><a name="l00488"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#ga60186a9df4ef9a0de15f0537aad85c87">  488</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_ECC                          ((uint32_t)(0xFFFFUL &lt;&lt; MXC_F_TPU_HAM_ECC_ECC_POS)) </span></div><div class="line"><a name="l00490"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#ga38bf432e5099ff2d4bb191bf83c3b5ca">  490</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_PAR_POS                      16 </span></div><div class="line"><a name="l00491"></a><span class="lineno"><a class="line" href="group__TPU__HAM__ECC.html#gaed00f4f52f2265aeb759080eac65c104">  491</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HAM_ECC_PAR                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_TPU_HAM_ECC_PAR_POS)) </span></div><div class="line"><a name="l00504"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__INIT.html#ga4a43edf6e4ac5a10a38cb32f46c2e1fb">  504</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_INIT_IVEC_POS                 0 </span></div><div class="line"><a name="l00505"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__INIT.html#gaa64fc3823c9b5de5e3b59b2a4728e096">  505</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_INIT_IVEC                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CIPHER_INIT_IVEC_POS)) </span></div><div class="line"><a name="l00517"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__KEY.html#gaf79a3c51b0a0935046f6fd610b31716f">  517</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_KEY_KEY_POS                   0 </span></div><div class="line"><a name="l00518"></a><span class="lineno"><a class="line" href="group__TPU__CIPHER__KEY.html#gaad15fabba1781c708c7050f69fe0aa86">  518</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_CIPHER_KEY_KEY                       ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_CIPHER_KEY_KEY_POS)) </span></div><div class="line"><a name="l00529"></a><span class="lineno"><a class="line" href="group__TPU__HASH__DIGEST.html#ga80a0d4a8b0be68af650507354923d795">  529</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_DIGEST_HASH_POS                 0 </span></div><div class="line"><a name="l00530"></a><span class="lineno"><a class="line" href="group__TPU__HASH__DIGEST.html#ga6f729ad2d0443ad8cd1bc1c275dc1d99">  530</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_DIGEST_HASH                     ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_HASH_DIGEST_HASH_POS)) </span></div><div class="line"><a name="l00540"></a><span class="lineno"><a class="line" href="group__TPU__HASH__MSG__SZ.html#ga3ee63c71bcf2d4278eed6d71a36da0cb">  540</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS                0 </span></div><div class="line"><a name="l00541"></a><span class="lineno"><a class="line" href="group__TPU__HASH__MSG__SZ.html#ga846f33739b9b4df01977822bbf232fa9">  541</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ                    ((uint32_t)(0xFFFFFFFFUL &lt;&lt; MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) </span></div><div class="line"><a name="l00554"></a><span class="lineno"><a class="line" href="group__TPU__MAA__MAWS.html#ga2433639055e7de96929eb58881bb0925">  554</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_MAWS_MAWS_POS                    0 </span></div><div class="line"><a name="l00555"></a><span class="lineno"><a class="line" href="group__TPU__MAA__MAWS.html#gac99c082bc55e64ae001b09bcc808ac5c">  555</a></span>&#160;<span class="preprocessor"> #define MXC_F_TPU_MAA_MAWS_MAWS                        ((uint32_t)(0xFFFUL &lt;&lt; MXC_F_TPU_MAA_MAWS_MAWS_POS)) </span></div><div class="line"><a name="l00559"></a><span class="lineno">  559</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00560"></a><span class="lineno">  560</span>&#160;}</div><div class="line"><a name="l00561"></a><span class="lineno">  561</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00562"></a><span class="lineno">  562</span>&#160;</div><div class="line"><a name="l00563"></a><span class="lineno">  563</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _TPU_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__tpu__regs__t_html_a3958f62fed97499e0909e5f69ddb43d7"><div class="ttname"><a href="structmxc__tpu__regs__t.html#a3958f62fed97499e0909e5f69ddb43d7">mxc_tpu_regs_t::ctrl</a></div><div class="ttdeci">__IO uint32_t ctrl</div><div class="ttdoc">0x00: TPU CTRL Register </div><div class="ttdef"><b>Definition:</b> tpu_regs.h:89</div></div>
 <div class="ttc" id="structmxc__tpu__regs__t_html_a2bebf05744da0588db005661058cb8e8"><div class="ttname"><a href="structmxc__tpu__regs__t.html#a2bebf05744da0588db005661058cb8e8">mxc_tpu_regs_t::dma_cnt</a></div><div class="ttdeci">__IO uint32_t dma_cnt</div><div class="ttdoc">0x18: TPU DMA_CNT Register </div><div class="ttdef"><b>Definition:</b> tpu_regs.h:95</div></div>
 <div class="ttc" id="structmxc__tpu__regs__t_html_a4cc827b3561f0ca9f5d78d07d5a688fe"><div class="ttname"><a href="structmxc__tpu__regs__t.html#a4cc827b3561f0ca9f5d78d07d5a688fe">mxc_tpu_regs_t::dma_dest</a></div><div class="ttdeci">__IO uint32_t dma_dest</div><div class="ttdoc">0x14: TPU DMA_DEST Register </div><div class="ttdef"><b>Definition:</b> tpu_regs.h:94</div></div>
 <div class="ttc" id="structmxc__tpu__regs__t_html_a59bd78da163966649f52f8ae5936b464"><div class="ttname"><a href="structmxc__tpu__regs__t.html#a59bd78da163966649f52f8ae5936b464">mxc_tpu_regs_t::ham_ecc</a></div><div class="ttdeci">__IO uint32_t ham_ecc</div><div class="ttdoc">0x4C: TPU HAM_ECC Register </div><div class="ttdef"><b>Definition:</b> tpu_regs.h:102</div></div>
diff --git a/lib/sdk/Documentation/html/uart__regs_8h_source.html b/lib/sdk/Documentation/html/uart__regs_8h_source.html
index 413d48a08c25edc2062a5c9db424ac2afa867b07..cafe7c089e4bd7ef23c850c04d3edc4c932f7cd0 100644
--- a/lib/sdk/Documentation/html/uart__regs_8h_source.html
+++ b/lib/sdk/Documentation/html/uart__regs_8h_source.html
@@ -71,7 +71,7 @@ $(document).ready(function(){initNavTree('uart__regs_8h_source.html','');});
 <div class="title">uart_regs.h</div>  </div>
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 <div class="contents">
-<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _UART_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _UART_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; </div><div class="line"><a name="l00050"></a><span class="lineno">   50</span>&#160;<span class="preprocessor">#if defined (__ICCARM__)</span></div><div class="line"><a name="l00051"></a><span class="lineno">   51</span>&#160;<span class="preprocessor">  #pragma system_include</span></div><div class="line"><a name="l00052"></a><span class="lineno">   52</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00053"></a><span class="lineno">   53</span>&#160; </div><div class="line"><a name="l00054"></a><span class="lineno">   54</span>&#160;<span class="preprocessor">#if defined (__CC_ARM)</span></div><div class="line"><a name="l00055"></a><span class="lineno">   55</span>&#160;<span class="preprocessor">  #pragma anon_unions</span></div><div class="line"><a name="l00056"></a><span class="lineno">   56</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00057"></a><span class="lineno">   57</span>&#160;<span class="comment">/*</span></div><div class="line"><a name="l00059"></a><span class="lineno">   59</span>&#160;<span class="comment">    If types are not defined elsewhere (CMSIS) define them here</span></div><div class="line"><a name="l00060"></a><span class="lineno">   60</span>&#160;<span class="comment">*/</span></div><div class="line"><a name="l00061"></a><span class="lineno">   61</span>&#160;<span class="preprocessor">#ifndef __IO</span></div><div class="line"><a name="l00062"></a><span class="lineno">   62</span>&#160;<span class="preprocessor">#define __IO volatile</span></div><div class="line"><a name="l00063"></a><span class="lineno">   63</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00064"></a><span class="lineno">   64</span>&#160;<span class="preprocessor">#ifndef __I</span></div><div class="line"><a name="l00065"></a><span class="lineno">   65</span>&#160;<span class="preprocessor">#define __I  volatile const</span></div><div class="line"><a name="l00066"></a><span class="lineno">   66</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00067"></a><span class="lineno">   67</span>&#160;<span class="preprocessor">#ifndef __O</span></div><div class="line"><a name="l00068"></a><span class="lineno">   68</span>&#160;<span class="preprocessor">#define __O  volatile</span></div><div class="line"><a name="l00069"></a><span class="lineno">   69</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00070"></a><span class="lineno">   70</span>&#160;<span class="preprocessor">#ifndef __R</span></div><div class="line"><a name="l00071"></a><span class="lineno">   71</span>&#160;<span class="preprocessor">#define __R  volatile const</span></div><div class="line"><a name="l00072"></a><span class="lineno">   72</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00073"></a><span class="lineno">   73</span>&#160;</div><div class="line"><a name="l00075"></a><span class="lineno">   75</span>&#160;<span class="comment">/* **** Definitions **** */</span></div><div class="line"><a name="l00076"></a><span class="lineno">   76</span>&#160;</div><div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html">   88</a></span>&#160;<span class="keyword">typedef</span> <span class="keyword">struct </span>{</div><div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#ac83f829f778be11ab5bfae7f7f5e18a5">   89</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#ac83f829f778be11ab5bfae7f7f5e18a5">ctrl</a>;                 </div><div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#a1d690df16fc63efee16083325c6e825d">   90</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#a1d690df16fc63efee16083325c6e825d">thresh_ctrl</a>;          </div><div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#a3766e1a576f2bbc8afcf2888cf67a657">   91</a></span>&#160;    __I  uint32_t <a class="code" href="structmxc__uart__regs__t.html#a3766e1a576f2bbc8afcf2888cf67a657">status</a>;               </div><div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#a0472317b1fc5e3022c2f7d3489a91524">   92</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#a0472317b1fc5e3022c2f7d3489a91524">int_en</a>;               </div><div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#aca2dbb139bffbd1e52cfacd02c38eb46">   93</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#aca2dbb139bffbd1e52cfacd02c38eb46">int_fl</a>;               </div><div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#a8d1ee5f15adf137a3e49387428029b92">   94</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#a8d1ee5f15adf137a3e49387428029b92">baud0</a>;                </div><div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#ac5e0e67d1af815c24d1fa602727e7811">   95</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#ac5e0e67d1af815c24d1fa602727e7811">baud1</a>;                </div><div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#adac2e943b5c2bf2f289181b1bced2d06">   96</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#adac2e943b5c2bf2f289181b1bced2d06">fifo</a>;                 </div><div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#acde0a8841a0ffc15ca28a4e49cb38e1e">   97</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#acde0a8841a0ffc15ca28a4e49cb38e1e">dma</a>;                  </div><div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="structmxc__uart__regs__t.html#a64f1d854472d4efb9131ac5fea240582">   98</a></span>&#160;    __IO uint32_t <a class="code" href="structmxc__uart__regs__t.html#a64f1d854472d4efb9131ac5fea240582">tx_fifo</a>;              </div><div class="line"><a name="l00099"></a><span class="lineno">   99</span>&#160;} <a class="code" href="structmxc__uart__regs__t.html">mxc_uart_regs_t</a>;</div><div class="line"><a name="l00100"></a><span class="lineno">  100</span>&#160;</div><div class="line"><a name="l00101"></a><span class="lineno">  101</span>&#160;<span class="comment">/* Register offsets for module UART */</span></div><div class="line"><a name="l00108"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga158cc90a8b98f2dc63dbf0867154c6e2">  108</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_CTRL                    ((uint32_t)0x00000000UL) </span></div><div class="line"><a name="l00109"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga7e3b66763fd395c4cb4558ad72c7454a">  109</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_THRESH_CTRL             ((uint32_t)0x00000004UL) </span></div><div class="line"><a name="l00110"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga6de941a37ca6b89305cd60eb27409a08">  110</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_STATUS                  ((uint32_t)0x00000008UL) </span></div><div class="line"><a name="l00111"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga39bd15e90213142077e1e119622d00b9">  111</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_INT_EN                  ((uint32_t)0x0000000CUL) </span></div><div class="line"><a name="l00112"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga2fc03c0d46dd05cf457012968068b23f">  112</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_INT_FL                  ((uint32_t)0x00000010UL) </span></div><div class="line"><a name="l00113"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga4df731b5357857910b184dcfbb16b493">  113</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_BAUD0                   ((uint32_t)0x00000014UL) </span></div><div class="line"><a name="l00114"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#gaaa838969e6015889f8d73f553dd7af6a">  114</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_BAUD1                   ((uint32_t)0x00000018UL) </span></div><div class="line"><a name="l00115"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga5d338e2b16dc5760ac99ae1260ab933f">  115</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_FIFO                    ((uint32_t)0x0000001CUL) </span></div><div class="line"><a name="l00116"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga620db415f2a471c08853e2a95f0ae777">  116</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_DMA                     ((uint32_t)0x00000020UL) </span></div><div class="line"><a name="l00117"></a><span class="lineno"><a class="line" href="group__UART__Register__Offsets.html#ga654222bdd5d718011a3f062070f28380">  117</a></span>&#160;<span class="preprocessor"> #define MXC_R_UART_TX_FIFO                 ((uint32_t)0x00000024UL) </span></div><div class="line"><a name="l00126"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga44b28eeb5944ae951385f33033e6ece8">  126</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_ENABLE_POS                     0 </span></div><div class="line"><a name="l00127"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga9c3bc441f96f5b89943165ddc389f4bd">  127</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_ENABLE                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_ENABLE_POS)) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga4082d26275162ff2d280bda901e30741">  129</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY_EN_POS                  1 </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga02f4af6301212e5d8e9b6ed8c7dde9b9">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_PARITY_EN_POS)) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga26b15888eeef7f47e2e7ed0d55294af9">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY_POS                     2 </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga1747cd4aff4032a793585954accdaae8">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_UART_CTRL_PARITY_POS)) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga711c48c5e4a3f2608c23b92a1ba23164">  134</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_EVEN                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga2a7828fbbbd1f112c34c6c0a475ef617">  135</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_EVEN                    (MXC_V_UART_CTRL_PARITY_EVEN &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gae6a6dfb0f632419b007cc50acde0bfe9">  136</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_ODD                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga18eab6b837ed20e7de88f7197666b489">  137</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_ODD                     (MXC_V_UART_CTRL_PARITY_ODD &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gac444c23a278a6aafc5bf44cf04a7e1fa">  138</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_MARK                    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gadaf4027fe0ab4bb48c72855ccb33f932">  139</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_MARK                    (MXC_V_UART_CTRL_PARITY_MARK &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gae6a74b198e7612963a46b49a1b7a641e">  140</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_SPACE                   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga935715a96e0954cf1b628565f9b37f81">  141</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_SPACE                   (MXC_V_UART_CTRL_PARITY_SPACE &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga7b6bda9e8bffe28c3234ada305e5f3e9">  143</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARMD_POS                      4 </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga8b8907499e05d62c8b85ecbdfa6f2f42">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARMD                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_PARMD_POS)) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaa258ffd300e3885d28d44c5071c825a7">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_TX_FLUSH_POS                   5 </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gab13812e9325ed3c975155683f4686bb4">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_TX_FLUSH                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_TX_FLUSH_POS)) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gad5ffbfe195a47654daab94d6bed98339">  149</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_FLUSH_POS                   6 </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga2c03ca3405dfb54b6e48ee1821b6be10">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_FLUSH                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_RX_FLUSH_POS)) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga79f5d1b77808472a9be4bd2d492421ad">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BITACC_POS                     7 </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaddcab42fd77602664796e03695f93815">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BITACC                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_BITACC_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga1c09238a1318f0eb0649dfb400adf566">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CHAR_SIZE_POS                  8 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaf1bd2dfb833f344d0b3b94fbda78499b">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CHAR_SIZE                      ((uint32_t)(0x3UL &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaf76d42569176fa1b84ed8670747faa3e">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_5                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga91bdab569b26937a1acef5c409a917b6">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_5                    (MXC_V_UART_CTRL_CHAR_SIZE_5 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gabf31f6eac5d5a28ee9a3df8de3f9c03c">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_6                    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga39a47340f9b5cc0cc1ae83ac760d2151">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_6                    (MXC_V_UART_CTRL_CHAR_SIZE_6 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaa2f5789016cec430027f883bbd712ba2">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_7                    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaae55160878331b04f53c9ee72bc95421">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_7                    (MXC_V_UART_CTRL_CHAR_SIZE_7 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga7e1df3e533686b075e8149b0e5d96dfd">  163</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_8                    ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gab465b46e44c6448d8109482fedb41eee">  164</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_8                    (MXC_V_UART_CTRL_CHAR_SIZE_8 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gabd7766119d0feb975e7ddbd74b2050a7">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_STOPBITS_POS                   10 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaa4ee214fdb58673130de839d45697931">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_STOPBITS                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_STOPBITS_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gab28e00ffd4ccd32acdc7d1781b8cb481">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_CTRL_POS                  11 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga09fc5d412ce0fbdbcd2816203d8b6909">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_CTRL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_FLOW_CTRL_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gac2b58d0d643321b7234d98e30fefe3e2">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_POL_POS                   12 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga68648c38ee320e22a0c698f626756d0f">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_POL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_FLOW_POL_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gad75b84da8bd3af91051f922480d8c9c0">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_NULL_MODEM_POS                 13 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaee237e0868929c1ddfe745c560c26fa9">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_NULL_MODEM                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_NULL_MODEM_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaabab19d04b4407b09fa473a33c822cfa">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BREAK_POS                      14 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga60928b71b7e752f1ebc03bb26b43d39f">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BREAK                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_BREAK_POS)) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga35c8c02141a960258511775e15d721e3">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CLKSEL_POS                     15 </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga4d1b8919bf25658dcfb6f6b41cffa892">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CLKSEL                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_CLKSEL_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga9795d5baa5a4ad193dfafcbd85d2a97b">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_TO_POS                      16 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gae857f800888c75c1ddf246a5b53f96d4">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_TO                          ((uint32_t)(0xFFUL &lt;&lt; MXC_F_UART_CTRL_RX_TO_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#ga9d61418fefb2adaf92605ad995dc382d">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS      0 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#gacaa928252553a81e8649cbd4c8e8b700">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH          ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#ga1b8af94d4c5c4461e29f609644262912">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS      8 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#ga59d030e4e47ddea5342540b32366b7a4">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH          ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#gac2726fd4879697d1e8ea3386593ba94d">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS     16 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#gad89a46d7b694e4bbf1ba638216fad23f">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH         ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga83593b5f2c92e49483b51569b464d766">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_BUSY_POS                  0 </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga8cc2eed60ed7624934d4b66f2fefae9d">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_BUSY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_TX_BUSY_POS)) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gae93d3edd20f8a24eaee4a61b79ce8601">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_BUSY_POS                  1 </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga27da1282ba12a6a13d984e30650360f1">  216</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_BUSY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_BUSY_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gafa95389bb3928632741ed28a700d2f5c">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_PARITY_POS                   2 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga3752f78f7c2e9df0104b6c4f093a9aed">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_PARITY                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_PARITY_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga013ca1be4bfa363fdd9cc9997125d89b">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_BREAK_POS                    3 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gaf0d3550c623dd81db570bd8605030df7">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_BREAK                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_BREAK_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga81bbda5993a9bca73acd93a0f8e414b7">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_EMPTY_POS                 4 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga8885509d7b7db7272c4d71cef613e490">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_EMPTY                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_EMPTY_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga9eb77b73836f713eb8a49ec055652e21">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FULL_POS                  5 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga919e76985c9ea024988bac9f9afabf90">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FULL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_FULL_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gacf6ef413e5c55958b76460180b26477b">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_EMPTY_POS                 6 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gae98eedaceea22e182a02e5b34c3438b9">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_EMPTY                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga85d3afe938ec1f376737c8ab316432ab">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FULL_POS                  7 </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga57bb5519616b26db1343818ac1d5dd2d">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FULL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_TX_FULL_POS)) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga73871110f934990531377f0425abe0fc">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FIFO_CNT_POS              8 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga73ece69c53dc19412c995a37126e9186">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FIFO_CNT                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gae81453de93965234b8a0e8e00058bd8e">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FIFO_CNT_POS              16 </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gad88895a51f3f9c21053f8647d602555f">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FIFO_CNT                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga44c2ed658a865a5e6b389b384bd6e322">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_TO_POS                    24 </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gac07d6d7729484b30e01bb318694318a4">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_TO                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_TO_POS)) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga10bc37740966726bb28bd08ba49347f8">  253</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS           0 </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga4d91f98a13e7a4ea1025c4fbf7d85e3f">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FRAME_ERROR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gad96696b3bc6f03dac8037d08d4ee6bc9">  256</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS          1 </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga558c501711ca6637859c13fccc348aa6">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_PARITY_ERROR              ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga2af68525b76cafc9d7efbe048e53cb6e">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_CTS_CHANGE_POS               2 </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga3496d76e7678c94f6f26df5c6d773324">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_CTS_CHANGE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_CTS_CHANGE_POS)) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga45b4aa40bd72f85d10d934159f154a79">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_OVERRUN_POS               3 </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga3aef5c7f31afdd01e6c616a5ff448fd4">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_OVERRUN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_OVERRUN_POS)) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga3036730c439dbea0d8d7fef38c785b4a">  265</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS           4 </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga9542b8f06f6dd4b04ffdee6ec6aac66d">  266</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gace43800e2e7baa961c56f93d67d627b3">  268</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS     5 </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga92edc4747439a6f8643e7a22764a000f">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga2303a706fb172d1117de3c045620d9b2">  271</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS           6 </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga4a344df2cadd7e5044845788f5e22c35">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gabb7351a3eeddfcb605536a8fa81580de">  274</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_BREAK_POS                    7 </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gae8102b6122d177c40deb6b7e7a1cbe7c">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_BREAK                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_BREAK_POS)) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga098abc604ee08a2462d6f55eca948756">  277</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS               8 </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga123f0baa1af6ade5eaff00674a0e51d8">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_TIMEOUT                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gaec95971b9b1ffcfb553bd52f570d6722">  280</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_LAST_BREAK_POS               9 </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga0188244ae78b51a50c8d2e66f09302bd">  281</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_LAST_BREAK                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_LAST_BREAK_POS)) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga0ef9a7350f665bb13d41dc9e94f19f14">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS           0 </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga1a90e7f460b986c3117885c4665f52b0">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FRAME_ERROR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga470e9215c5ec2615abbdf6ea16b65f60">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS          1 </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga2e5b178286e522f9f256ded32518339d">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_PARITY_ERROR              ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga89b8389e4ea289a35f3ecea6fa925c43">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_CTS_CHANGE_POS               2 </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga368fcf1876edf37e85407ecee7336990">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_CTS_CHANGE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_CTS_CHANGE_POS)) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga63084779427149fabc3b258f0024a79e">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_OVERRUN_POS               3 </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gae86085eaf55374c22681d49171e4c268">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_OVERRUN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_OVERRUN_POS)) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gabb43b97f4791a4c7c43a3eb52f330ba3">  303</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS           4 </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gaa66bf839a8f8f2247881283f02693967">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gaae8f0e102ebbff8b96f601abf6d340c9">  306</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS     5 </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga684c47940ae09668cca8b8c6a9b86d1f">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga1ac961cd3521ff28220dfae542180fe9">  309</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS           6 </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga450805b61fc9ca2ae1158f6b4c22209b">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga6c7cb6a41c1855f7897d720f37f56e3a">  312</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_BREAK_POS                    7 </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga3acf449ed778f492255d42d3c53b1a50">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_BREAK                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_BREAK_POS)) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gaa34d3345b290f3eb1fcffdd15a3f0ec2">  315</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS               8 </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga85226d808a144ea16f7959fd309f44e9">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_TIMEOUT                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga262c37466a5e6d2e5bf82d8145f3af0b">  318</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_LAST_BREAK_POS               9 </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga6322e81603821f38894ea0265edc072e">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_LAST_BREAK                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_LAST_BREAK_POS)) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gace7dc223b33036fd16893ac77a05b263">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_IBAUD_POS                     0 </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#ga096a9e851335b9b1c704d44583ba5fad">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_IBAUD                         ((uint32_t)(0xFFFUL &lt;&lt; MXC_F_UART_BAUD0_IBAUD_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#ga5d0f19c8c9a45e5d0a79f3ecce67cf08">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_FACTOR_POS                    16 </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gad9ef6621304a83bc7d7dfec8deb4537d">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_FACTOR                        ((uint32_t)(0x3UL &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS)) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#ga7f117abab71faef9628ed3d1aec0d9c4">  334</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_128                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gabbb7dc04e52aac001f3fc3c033c7e06b">  335</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_128                    (MXC_V_UART_BAUD0_FACTOR_128 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gad8bf13aa6f15dd3764ddddd3ace21e8e">  336</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_64                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gab44699d4723bf00e15a506109fb38104">  337</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_64                     (MXC_V_UART_BAUD0_FACTOR_64 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gacc2c6dcfafa5b5a36c12bff9262a5d05">  338</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_32                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gaa85451a5dcfeeab5dec3653799f965a1">  339</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_32                     (MXC_V_UART_BAUD0_FACTOR_32 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gaf9bbef9a6d6c7d56db9ad0ef07119857">  340</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_16                     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gaf7ac099b24090005f6274a329f83a402">  341</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_16                     (MXC_V_UART_BAUD0_FACTOR_16 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00351"></a><span class="lineno"><a class="line" href="group__UART__BAUD1.html#ga864987b16ec670142872e42587e07c8c">  351</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD1_DBAUD_POS                     0 </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__UART__BAUD1.html#ga75f253137e900b9c5902a384ad004410">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD1_DBAUD                         ((uint32_t)(0xFFFUL &lt;&lt; MXC_F_UART_BAUD1_DBAUD_POS)) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__UART__FIFO.html#gac32f8db97fecb7931ab0241d767f7796">  362</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_FIFO_FIFO_POS                       0 </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__UART__FIFO.html#ga393a38e4a9a75c0fcfbc96d1bb790d8f">  363</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_FIFO_FIFO                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_UART_FIFO_FIFO_POS)) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gabf796cd48d76f982569d92e74e22f93c">  373</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TDMA_EN_POS                     0 </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gadf4bfcec181fbb27009155519f0685c0">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TDMA_EN                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_TDMA_EN_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gaa04a7beef7f509b5fab449818e62e5dc">  376</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_EN_POS                    1 </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gac96cf5a87e82fc202dd6e0007150ff4e">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_EN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_RXDMA_EN_POS)) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gae752540ed4cfe99f7ea8ab1c9b3d6f05">  379</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TXDMA_LEVEL_POS                 8 </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga1fa761deacc326a55af7438669b01b21">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TXDMA_LEVEL                     ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_DMA_TXDMA_LEVEL_POS)) </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga324fd0547f84fa0bc10517d662f0837a">  382</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_LEVEL_POS                 16 </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga3d955f60a334ff70d4ff27fa4fa2e41e">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_LEVEL                     ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_DMA_RXDMA_LEVEL_POS)) </span></div><div class="line"><a name="l00393"></a><span class="lineno"><a class="line" href="group__UART__TX__FIFO.html#ga87ac9140fc8734560ea176bdd6afec8e">  393</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_TX_FIFO_DATA_POS                    0 </span></div><div class="line"><a name="l00394"></a><span class="lineno"><a class="line" href="group__UART__TX__FIFO.html#gae4ef05d4fb99b14b0d9201a048006962">  394</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_TX_FIFO_DATA                        ((uint32_t)(0x7FUL &lt;&lt; MXC_F_UART_TX_FIFO_DATA_POS)) </span></div><div class="line"><a name="l00398"></a><span class="lineno">  398</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00399"></a><span class="lineno">  399</span>&#160;}</div><div class="line"><a name="l00400"></a><span class="lineno">  400</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00401"></a><span class="lineno">  401</span>&#160;</div><div class="line"><a name="l00402"></a><span class="lineno">  402</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _UART_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__uart__regs__t_html_a8d1ee5f15adf137a3e49387428029b92"><div class="ttname"><a href="structmxc__uart__regs__t.html#a8d1ee5f15adf137a3e49387428029b92">mxc_uart_regs_t::baud0</a></div><div class="ttdeci">__IO uint32_t baud0</div><div class="ttdoc">0x14: UART BAUD0 Register </div><div class="ttdef"><b>Definition:</b> uart_regs.h:94</div></div>
+<div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno">    1</span>&#160;</div><div class="line"><a name="l00006"></a><span class="lineno">    6</span>&#160;<span class="comment">/* ****************************************************************************</span></div><div class="line"><a name="l00007"></a><span class="lineno">    7</span>&#160;<span class="comment"> * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.</span></div><div class="line"><a name="l00008"></a><span class="lineno">    8</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00009"></a><span class="lineno">    9</span>&#160;<span class="comment"> * Permission is hereby granted, free of charge, to any person obtaining a</span></div><div class="line"><a name="l00010"></a><span class="lineno">   10</span>&#160;<span class="comment"> * copy of this software and associated documentation files (the &quot;Software&quot;),</span></div><div class="line"><a name="l00011"></a><span class="lineno">   11</span>&#160;<span class="comment"> * to deal in the Software without restriction, including without limitation</span></div><div class="line"><a name="l00012"></a><span class="lineno">   12</span>&#160;<span class="comment"> * the rights to use, copy, modify, merge, publish, distribute, sublicense,</span></div><div class="line"><a name="l00013"></a><span class="lineno">   13</span>&#160;<span class="comment"> * and/or sell copies of the Software, and to permit persons to whom the</span></div><div class="line"><a name="l00014"></a><span class="lineno">   14</span>&#160;<span class="comment"> * Software is furnished to do so, subject to the following conditions:</span></div><div class="line"><a name="l00015"></a><span class="lineno">   15</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00016"></a><span class="lineno">   16</span>&#160;<span class="comment"> * The above copyright notice and this permission notice shall be included</span></div><div class="line"><a name="l00017"></a><span class="lineno">   17</span>&#160;<span class="comment"> * in all copies or substantial portions of the Software.</span></div><div class="line"><a name="l00018"></a><span class="lineno">   18</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00019"></a><span class="lineno">   19</span>&#160;<span class="comment"> * THE SOFTWARE IS PROVIDED &quot;AS IS&quot;, WITHOUT WARRANTY OF ANY KIND, EXPRESS</span></div><div class="line"><a name="l00020"></a><span class="lineno">   20</span>&#160;<span class="comment"> * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF</span></div><div class="line"><a name="l00021"></a><span class="lineno">   21</span>&#160;<span class="comment"> * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.</span></div><div class="line"><a name="l00022"></a><span class="lineno">   22</span>&#160;<span class="comment"> * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES</span></div><div class="line"><a name="l00023"></a><span class="lineno">   23</span>&#160;<span class="comment"> * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,</span></div><div class="line"><a name="l00024"></a><span class="lineno">   24</span>&#160;<span class="comment"> * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR</span></div><div class="line"><a name="l00025"></a><span class="lineno">   25</span>&#160;<span class="comment"> * OTHER DEALINGS IN THE SOFTWARE.</span></div><div class="line"><a name="l00026"></a><span class="lineno">   26</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00027"></a><span class="lineno">   27</span>&#160;<span class="comment"> * Except as contained in this notice, the name of Maxim Integrated</span></div><div class="line"><a name="l00028"></a><span class="lineno">   28</span>&#160;<span class="comment"> * Products, Inc. shall not be used except as stated in the Maxim Integrated</span></div><div class="line"><a name="l00029"></a><span class="lineno">   29</span>&#160;<span class="comment"> * Products, Inc. Branding Policy.</span></div><div class="line"><a name="l00030"></a><span class="lineno">   30</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00031"></a><span class="lineno">   31</span>&#160;<span class="comment"> * The mere transfer of this software does not imply any licenses</span></div><div class="line"><a name="l00032"></a><span class="lineno">   32</span>&#160;<span class="comment"> * of trade secrets, proprietary technology, copyrights, patents,</span></div><div class="line"><a name="l00033"></a><span class="lineno">   33</span>&#160;<span class="comment"> * trademarks, maskwork rights, or any other form of intellectual</span></div><div class="line"><a name="l00034"></a><span class="lineno">   34</span>&#160;<span class="comment"> * property whatsoever. Maxim Integrated Products, Inc. retains all</span></div><div class="line"><a name="l00035"></a><span class="lineno">   35</span>&#160;<span class="comment"> * ownership rights.</span></div><div class="line"><a name="l00036"></a><span class="lineno">   36</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00037"></a><span class="lineno">   37</span>&#160;<span class="comment"> *</span></div><div class="line"><a name="l00038"></a><span class="lineno">   38</span>&#160;<span class="comment"> *************************************************************************** */</span></div><div class="line"><a name="l00039"></a><span class="lineno">   39</span>&#160;</div><div class="line"><a name="l00040"></a><span class="lineno">   40</span>&#160;<span class="preprocessor">#ifndef _UART_REGS_H_</span></div><div class="line"><a name="l00041"></a><span class="lineno">   41</span>&#160;<span class="preprocessor">#define _UART_REGS_H_</span></div><div class="line"><a name="l00042"></a><span class="lineno">   42</span>&#160;</div><div class="line"><a name="l00043"></a><span class="lineno">   43</span>&#160;<span class="comment">/* **** Includes **** */</span></div><div class="line"><a name="l00044"></a><span class="lineno">   44</span>&#160;<span class="preprocessor">#include &lt;stdint.h&gt;</span></div><div class="line"><a name="l00045"></a><span class="lineno">   45</span>&#160;</div><div class="line"><a name="l00046"></a><span class="lineno">   46</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00047"></a><span class="lineno">   47</span>&#160;<span class="keyword">extern</span> <span class="stringliteral">&quot;C&quot;</span> {</div><div class="line"><a name="l00048"></a><span class="lineno">   48</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00049"></a><span class="lineno">   49</span>&#160; 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MXC_F_UART_CTRL_ENABLE_POS)) </span></div><div class="line"><a name="l00129"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga4082d26275162ff2d280bda901e30741">  129</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY_EN_POS                  1 </span></div><div class="line"><a name="l00130"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga02f4af6301212e5d8e9b6ed8c7dde9b9">  130</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY_EN                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_PARITY_EN_POS)) </span></div><div class="line"><a name="l00132"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga26b15888eeef7f47e2e7ed0d55294af9">  132</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY_POS                     2 </span></div><div class="line"><a name="l00133"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga1747cd4aff4032a793585954accdaae8">  133</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARITY                         ((uint32_t)(0x3UL &lt;&lt; MXC_F_UART_CTRL_PARITY_POS)) </span></div><div class="line"><a name="l00134"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga711c48c5e4a3f2608c23b92a1ba23164">  134</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_EVEN                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00135"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga2a7828fbbbd1f112c34c6c0a475ef617">  135</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_EVEN                    (MXC_V_UART_CTRL_PARITY_EVEN &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00136"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gae6a6dfb0f632419b007cc50acde0bfe9">  136</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_ODD                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00137"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga18eab6b837ed20e7de88f7197666b489">  137</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_ODD                     (MXC_V_UART_CTRL_PARITY_ODD &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00138"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gac444c23a278a6aafc5bf44cf04a7e1fa">  138</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_MARK                    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00139"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gadaf4027fe0ab4bb48c72855ccb33f932">  139</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_MARK                    (MXC_V_UART_CTRL_PARITY_MARK &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00140"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gae6a74b198e7612963a46b49a1b7a641e">  140</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_PARITY_SPACE                   ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00141"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga935715a96e0954cf1b628565f9b37f81">  141</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_PARITY_SPACE                   (MXC_V_UART_CTRL_PARITY_SPACE &lt;&lt; MXC_F_UART_CTRL_PARITY_POS) </span></div><div class="line"><a name="l00143"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga7b6bda9e8bffe28c3234ada305e5f3e9">  143</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARMD_POS                      4 </span></div><div class="line"><a name="l00144"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga8b8907499e05d62c8b85ecbdfa6f2f42">  144</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_PARMD                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_PARMD_POS)) </span></div><div class="line"><a name="l00146"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaa258ffd300e3885d28d44c5071c825a7">  146</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_TX_FLUSH_POS                   5 </span></div><div class="line"><a name="l00147"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gab13812e9325ed3c975155683f4686bb4">  147</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_TX_FLUSH                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_TX_FLUSH_POS)) </span></div><div class="line"><a name="l00149"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gad5ffbfe195a47654daab94d6bed98339">  149</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_FLUSH_POS                   6 </span></div><div class="line"><a name="l00150"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga2c03ca3405dfb54b6e48ee1821b6be10">  150</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_FLUSH                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_RX_FLUSH_POS)) </span></div><div class="line"><a name="l00152"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga79f5d1b77808472a9be4bd2d492421ad">  152</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BITACC_POS                     7 </span></div><div class="line"><a name="l00153"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaddcab42fd77602664796e03695f93815">  153</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BITACC                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_BITACC_POS)) </span></div><div class="line"><a name="l00155"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga1c09238a1318f0eb0649dfb400adf566">  155</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CHAR_SIZE_POS                  8 </span></div><div class="line"><a name="l00156"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaf1bd2dfb833f344d0b3b94fbda78499b">  156</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CHAR_SIZE                      ((uint32_t)(0x3UL &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS)) </span></div><div class="line"><a name="l00157"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaf76d42569176fa1b84ed8670747faa3e">  157</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_5                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00158"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga91bdab569b26937a1acef5c409a917b6">  158</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_5                    (MXC_V_UART_CTRL_CHAR_SIZE_5 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00159"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gabf31f6eac5d5a28ee9a3df8de3f9c03c">  159</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_6                    ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00160"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga39a47340f9b5cc0cc1ae83ac760d2151">  160</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_6                    (MXC_V_UART_CTRL_CHAR_SIZE_6 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00161"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaa2f5789016cec430027f883bbd712ba2">  161</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_7                    ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00162"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaae55160878331b04f53c9ee72bc95421">  162</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_7                    (MXC_V_UART_CTRL_CHAR_SIZE_7 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00163"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga7e1df3e533686b075e8149b0e5d96dfd">  163</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_CTRL_CHAR_SIZE_8                    ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00164"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gab465b46e44c6448d8109482fedb41eee">  164</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_CTRL_CHAR_SIZE_8                    (MXC_V_UART_CTRL_CHAR_SIZE_8 &lt;&lt; MXC_F_UART_CTRL_CHAR_SIZE_POS) </span></div><div class="line"><a name="l00166"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gabd7766119d0feb975e7ddbd74b2050a7">  166</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_STOPBITS_POS                   10 </span></div><div class="line"><a name="l00167"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaa4ee214fdb58673130de839d45697931">  167</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_STOPBITS                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_STOPBITS_POS)) </span></div><div class="line"><a name="l00169"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gab28e00ffd4ccd32acdc7d1781b8cb481">  169</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_CTRL_POS                  11 </span></div><div class="line"><a name="l00170"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga09fc5d412ce0fbdbcd2816203d8b6909">  170</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_CTRL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_FLOW_CTRL_POS)) </span></div><div class="line"><a name="l00172"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gac2b58d0d643321b7234d98e30fefe3e2">  172</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_POL_POS                   12 </span></div><div class="line"><a name="l00173"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga68648c38ee320e22a0c698f626756d0f">  173</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_FLOW_POL                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_FLOW_POL_POS)) </span></div><div class="line"><a name="l00175"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gad75b84da8bd3af91051f922480d8c9c0">  175</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_NULL_MODEM_POS                 13 </span></div><div class="line"><a name="l00176"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaee237e0868929c1ddfe745c560c26fa9">  176</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_NULL_MODEM                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_NULL_MODEM_POS)) </span></div><div class="line"><a name="l00178"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gaabab19d04b4407b09fa473a33c822cfa">  178</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BREAK_POS                      14 </span></div><div class="line"><a name="l00179"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga60928b71b7e752f1ebc03bb26b43d39f">  179</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_BREAK                          ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_BREAK_POS)) </span></div><div class="line"><a name="l00181"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga35c8c02141a960258511775e15d721e3">  181</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CLKSEL_POS                     15 </span></div><div class="line"><a name="l00182"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga4d1b8919bf25658dcfb6f6b41cffa892">  182</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_CLKSEL                         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_CTRL_CLKSEL_POS)) </span></div><div class="line"><a name="l00184"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#ga9795d5baa5a4ad193dfafcbd85d2a97b">  184</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_TO_POS                      16 </span></div><div class="line"><a name="l00185"></a><span class="lineno"><a class="line" href="group__UART__CTRL.html#gae857f800888c75c1ddf246a5b53f96d4">  185</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_CTRL_RX_TO                          ((uint32_t)(0xFFUL &lt;&lt; MXC_F_UART_CTRL_RX_TO_POS)) </span></div><div class="line"><a name="l00195"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#ga9d61418fefb2adaf92605ad995dc382d">  195</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS      0 </span></div><div class="line"><a name="l00196"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#gacaa928252553a81e8649cbd4c8e8b700">  196</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH          ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_THRESH_CTRL_RX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00198"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#ga1b8af94d4c5c4461e29f609644262912">  198</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS      8 </span></div><div class="line"><a name="l00199"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#ga59d030e4e47ddea5342540b32366b7a4">  199</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH          ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_THRESH_CTRL_TX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00201"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#gac2726fd4879697d1e8ea3386593ba94d">  201</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS     16 </span></div><div class="line"><a name="l00202"></a><span class="lineno"><a class="line" href="group__UART__THRESH__CTRL.html#gad89a46d7b694e4bbf1ba638216fad23f">  202</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH         ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_THRESH_CTRL_RTS_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00212"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga83593b5f2c92e49483b51569b464d766">  212</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_BUSY_POS                  0 </span></div><div class="line"><a name="l00213"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga8cc2eed60ed7624934d4b66f2fefae9d">  213</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_BUSY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_TX_BUSY_POS)) </span></div><div class="line"><a name="l00215"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gae93d3edd20f8a24eaee4a61b79ce8601">  215</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_BUSY_POS                  1 </span></div><div class="line"><a name="l00216"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga27da1282ba12a6a13d984e30650360f1">  216</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_BUSY                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_BUSY_POS)) </span></div><div class="line"><a name="l00218"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gafa95389bb3928632741ed28a700d2f5c">  218</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_PARITY_POS                   2 </span></div><div class="line"><a name="l00219"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga3752f78f7c2e9df0104b6c4f093a9aed">  219</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_PARITY                       ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_PARITY_POS)) </span></div><div class="line"><a name="l00221"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga013ca1be4bfa363fdd9cc9997125d89b">  221</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_BREAK_POS                    3 </span></div><div class="line"><a name="l00222"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gaf0d3550c623dd81db570bd8605030df7">  222</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_BREAK                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_BREAK_POS)) </span></div><div class="line"><a name="l00224"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga81bbda5993a9bca73acd93a0f8e414b7">  224</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_EMPTY_POS                 4 </span></div><div class="line"><a name="l00225"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga8885509d7b7db7272c4d71cef613e490">  225</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_EMPTY                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_EMPTY_POS)) </span></div><div class="line"><a name="l00227"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga9eb77b73836f713eb8a49ec055652e21">  227</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FULL_POS                  5 </span></div><div class="line"><a name="l00228"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga919e76985c9ea024988bac9f9afabf90">  228</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FULL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_FULL_POS)) </span></div><div class="line"><a name="l00230"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gacf6ef413e5c55958b76460180b26477b">  230</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_EMPTY_POS                 6 </span></div><div class="line"><a name="l00231"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gae98eedaceea22e182a02e5b34c3438b9">  231</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_EMPTY                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_TX_EMPTY_POS)) </span></div><div class="line"><a name="l00233"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga85d3afe938ec1f376737c8ab316432ab">  233</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FULL_POS                  7 </span></div><div class="line"><a name="l00234"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga57bb5519616b26db1343818ac1d5dd2d">  234</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FULL                      ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_TX_FULL_POS)) </span></div><div class="line"><a name="l00236"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga73871110f934990531377f0425abe0fc">  236</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FIFO_CNT_POS              8 </span></div><div class="line"><a name="l00237"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga73ece69c53dc19412c995a37126e9186">  237</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_FIFO_CNT                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_STATUS_RX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00239"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gae81453de93965234b8a0e8e00058bd8e">  239</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FIFO_CNT_POS              16 </span></div><div class="line"><a name="l00240"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gad88895a51f3f9c21053f8647d602555f">  240</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_TX_FIFO_CNT                  ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_STATUS_TX_FIFO_CNT_POS)) </span></div><div class="line"><a name="l00242"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#ga44c2ed658a865a5e6b389b384bd6e322">  242</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_TO_POS                    24 </span></div><div class="line"><a name="l00243"></a><span class="lineno"><a class="line" href="group__UART__STATUS.html#gac07d6d7729484b30e01bb318694318a4">  243</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_STATUS_RX_TO                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_STATUS_RX_TO_POS)) </span></div><div class="line"><a name="l00253"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga10bc37740966726bb28bd08ba49347f8">  253</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS           0 </span></div><div class="line"><a name="l00254"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga4d91f98a13e7a4ea1025c4fbf7d85e3f">  254</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FRAME_ERROR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_FRAME_ERROR_POS)) </span></div><div class="line"><a name="l00256"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gad96696b3bc6f03dac8037d08d4ee6bc9">  256</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS          1 </span></div><div class="line"><a name="l00257"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga558c501711ca6637859c13fccc348aa6">  257</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_PARITY_ERROR              ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_PARITY_ERROR_POS)) </span></div><div class="line"><a name="l00259"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga2af68525b76cafc9d7efbe048e53cb6e">  259</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_CTS_CHANGE_POS               2 </span></div><div class="line"><a name="l00260"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga3496d76e7678c94f6f26df5c6d773324">  260</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_CTS_CHANGE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_CTS_CHANGE_POS)) </span></div><div class="line"><a name="l00262"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga45b4aa40bd72f85d10d934159f154a79">  262</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_OVERRUN_POS               3 </span></div><div class="line"><a name="l00263"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga3aef5c7f31afdd01e6c616a5ff448fd4">  263</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_OVERRUN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_OVERRUN_POS)) </span></div><div class="line"><a name="l00265"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga3036730c439dbea0d8d7fef38c785b4a">  265</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS           4 </span></div><div class="line"><a name="l00266"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga9542b8f06f6dd4b04ffdee6ec6aac66d">  266</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00268"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gace43800e2e7baa961c56f93d67d627b3">  268</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS     5 </span></div><div class="line"><a name="l00269"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga92edc4747439a6f8643e7a22764a000f">  269</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_TX_FIFO_ALMOST_EMPTY_POS)) </span></div><div class="line"><a name="l00271"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga2303a706fb172d1117de3c045620d9b2">  271</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS           6 </span></div><div class="line"><a name="l00272"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga4a344df2cadd7e5044845788f5e22c35">  272</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_TX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_TX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00274"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gabb7351a3eeddfcb605536a8fa81580de">  274</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_BREAK_POS                    7 </span></div><div class="line"><a name="l00275"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gae8102b6122d177c40deb6b7e7a1cbe7c">  275</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_BREAK                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_BREAK_POS)) </span></div><div class="line"><a name="l00277"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga098abc604ee08a2462d6f55eca948756">  277</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_TIMEOUT_POS               8 </span></div><div class="line"><a name="l00278"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga123f0baa1af6ade5eaff00674a0e51d8">  278</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_RX_TIMEOUT                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_RX_TIMEOUT_POS)) </span></div><div class="line"><a name="l00280"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#gaec95971b9b1ffcfb553bd52f570d6722">  280</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_LAST_BREAK_POS               9 </span></div><div class="line"><a name="l00281"></a><span class="lineno"><a class="line" href="group__UART__INT__EN.html#ga0188244ae78b51a50c8d2e66f09302bd">  281</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_EN_LAST_BREAK                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_EN_LAST_BREAK_POS)) </span></div><div class="line"><a name="l00291"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga0ef9a7350f665bb13d41dc9e94f19f14">  291</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS           0 </span></div><div class="line"><a name="l00292"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga1a90e7f460b986c3117885c4665f52b0">  292</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FRAME_ERROR               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_FRAME_ERROR_POS)) </span></div><div class="line"><a name="l00294"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga470e9215c5ec2615abbdf6ea16b65f60">  294</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS          1 </span></div><div class="line"><a name="l00295"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga2e5b178286e522f9f256ded32518339d">  295</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_PARITY_ERROR              ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_PARITY_ERROR_POS)) </span></div><div class="line"><a name="l00297"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga89b8389e4ea289a35f3ecea6fa925c43">  297</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_CTS_CHANGE_POS               2 </span></div><div class="line"><a name="l00298"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga368fcf1876edf37e85407ecee7336990">  298</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_CTS_CHANGE                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_CTS_CHANGE_POS)) </span></div><div class="line"><a name="l00300"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga63084779427149fabc3b258f0024a79e">  300</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_OVERRUN_POS               3 </span></div><div class="line"><a name="l00301"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gae86085eaf55374c22681d49171e4c268">  301</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_OVERRUN                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_OVERRUN_POS)) </span></div><div class="line"><a name="l00303"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gabb43b97f4791a4c7c43a3eb52f330ba3">  303</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS           4 </span></div><div class="line"><a name="l00304"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gaa66bf839a8f8f2247881283f02693967">  304</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00306"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gaae8f0e102ebbff8b96f601abf6d340c9">  306</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS     5 </span></div><div class="line"><a name="l00307"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga684c47940ae09668cca8b8c6a9b86d1f">  307</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY         ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_TX_FIFO_ALMOST_EMPTY_POS)) </span></div><div class="line"><a name="l00309"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga1ac961cd3521ff28220dfae542180fe9">  309</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS           6 </span></div><div class="line"><a name="l00310"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga450805b61fc9ca2ae1158f6b4c22209b">  310</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_TX_FIFO_THRESH               ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_TX_FIFO_THRESH_POS)) </span></div><div class="line"><a name="l00312"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga6c7cb6a41c1855f7897d720f37f56e3a">  312</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_BREAK_POS                    7 </span></div><div class="line"><a name="l00313"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga3acf449ed778f492255d42d3c53b1a50">  313</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_BREAK                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_BREAK_POS)) </span></div><div class="line"><a name="l00315"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#gaa34d3345b290f3eb1fcffdd15a3f0ec2">  315</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_TIMEOUT_POS               8 </span></div><div class="line"><a name="l00316"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga85226d808a144ea16f7959fd309f44e9">  316</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_RX_TIMEOUT                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_RX_TIMEOUT_POS)) </span></div><div class="line"><a name="l00318"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga262c37466a5e6d2e5bf82d8145f3af0b">  318</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_LAST_BREAK_POS               9 </span></div><div class="line"><a name="l00319"></a><span class="lineno"><a class="line" href="group__UART__INT__FL.html#ga6322e81603821f38894ea0265edc072e">  319</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_INT_FL_LAST_BREAK                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_INT_FL_LAST_BREAK_POS)) </span></div><div class="line"><a name="l00329"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gace7dc223b33036fd16893ac77a05b263">  329</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_IBAUD_POS                     0 </span></div><div class="line"><a name="l00330"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#ga096a9e851335b9b1c704d44583ba5fad">  330</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_IBAUD                         ((uint32_t)(0xFFFUL &lt;&lt; MXC_F_UART_BAUD0_IBAUD_POS)) </span></div><div class="line"><a name="l00332"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#ga5d0f19c8c9a45e5d0a79f3ecce67cf08">  332</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_FACTOR_POS                    16 </span></div><div class="line"><a name="l00333"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gad9ef6621304a83bc7d7dfec8deb4537d">  333</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD0_FACTOR                        ((uint32_t)(0x3UL &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS)) </span></div><div class="line"><a name="l00334"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#ga7f117abab71faef9628ed3d1aec0d9c4">  334</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_128                    ((uint32_t)0x0UL) </span></div><div class="line"><a name="l00335"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gabbb7dc04e52aac001f3fc3c033c7e06b">  335</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_128                    (MXC_V_UART_BAUD0_FACTOR_128 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00336"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gad8bf13aa6f15dd3764ddddd3ace21e8e">  336</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_64                     ((uint32_t)0x1UL) </span></div><div class="line"><a name="l00337"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gab44699d4723bf00e15a506109fb38104">  337</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_64                     (MXC_V_UART_BAUD0_FACTOR_64 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00338"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gacc2c6dcfafa5b5a36c12bff9262a5d05">  338</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_32                     ((uint32_t)0x2UL) </span></div><div class="line"><a name="l00339"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gaa85451a5dcfeeab5dec3653799f965a1">  339</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_32                     (MXC_V_UART_BAUD0_FACTOR_32 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00340"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gaf9bbef9a6d6c7d56db9ad0ef07119857">  340</a></span>&#160;<span class="preprocessor"> #define MXC_V_UART_BAUD0_FACTOR_16                     ((uint32_t)0x3UL) </span></div><div class="line"><a name="l00341"></a><span class="lineno"><a class="line" href="group__UART__BAUD0.html#gaf7ac099b24090005f6274a329f83a402">  341</a></span>&#160;<span class="preprocessor"> #define MXC_S_UART_BAUD0_FACTOR_16                     (MXC_V_UART_BAUD0_FACTOR_16 &lt;&lt; MXC_F_UART_BAUD0_FACTOR_POS) </span></div><div class="line"><a name="l00351"></a><span class="lineno"><a class="line" href="group__UART__BAUD1.html#ga864987b16ec670142872e42587e07c8c">  351</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD1_DBAUD_POS                     0 </span></div><div class="line"><a name="l00352"></a><span class="lineno"><a class="line" href="group__UART__BAUD1.html#ga75f253137e900b9c5902a384ad004410">  352</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_BAUD1_DBAUD                         ((uint32_t)(0xFFFUL &lt;&lt; MXC_F_UART_BAUD1_DBAUD_POS)) </span></div><div class="line"><a name="l00362"></a><span class="lineno"><a class="line" href="group__UART__FIFO.html#gac32f8db97fecb7931ab0241d767f7796">  362</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_FIFO_FIFO_POS                       0 </span></div><div class="line"><a name="l00363"></a><span class="lineno"><a class="line" href="group__UART__FIFO.html#ga393a38e4a9a75c0fcfbc96d1bb790d8f">  363</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_FIFO_FIFO                           ((uint32_t)(0xFFUL &lt;&lt; MXC_F_UART_FIFO_FIFO_POS)) </span></div><div class="line"><a name="l00373"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gae641dd039384fe57e34c4bd47a72895a">  373</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TXDMA_EN_POS                    0 </span></div><div class="line"><a name="l00374"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gae80f906d46e20cf77586834fda24b5a8">  374</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TXDMA_EN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_TXDMA_EN_POS)) </span></div><div class="line"><a name="l00376"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gaa04a7beef7f509b5fab449818e62e5dc">  376</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_EN_POS                    1 </span></div><div class="line"><a name="l00377"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gac96cf5a87e82fc202dd6e0007150ff4e">  377</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_EN                        ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_RXDMA_EN_POS)) </span></div><div class="line"><a name="l00379"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gab7f87e3f7bed3b1cbe8ddf237fc45fe6">  379</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_START_POS                 3 </span></div><div class="line"><a name="l00380"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga26fd201c29b8ab6aabed050ad4e6c4ea">  380</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_START                     ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_RXDMA_START_POS)) </span></div><div class="line"><a name="l00382"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga16f66d46a24c45c8f69f4de32aedf27b">  382</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_AUTO_TO_POS               5 </span></div><div class="line"><a name="l00383"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gae2eac669d530adaaff606c0e5b7b1c52">  383</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_AUTO_TO                   ((uint32_t)(0x1UL &lt;&lt; MXC_F_UART_DMA_RXDMA_AUTO_TO_POS)) </span></div><div class="line"><a name="l00385"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#gae752540ed4cfe99f7ea8ab1c9b3d6f05">  385</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TXDMA_LEVEL_POS                 8 </span></div><div class="line"><a name="l00386"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga1fa761deacc326a55af7438669b01b21">  386</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_TXDMA_LEVEL                     ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_DMA_TXDMA_LEVEL_POS)) </span></div><div class="line"><a name="l00388"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga324fd0547f84fa0bc10517d662f0837a">  388</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_LEVEL_POS                 16 </span></div><div class="line"><a name="l00389"></a><span class="lineno"><a class="line" href="group__UART__DMA.html#ga3d955f60a334ff70d4ff27fa4fa2e41e">  389</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_DMA_RXDMA_LEVEL                     ((uint32_t)(0x3FUL &lt;&lt; MXC_F_UART_DMA_RXDMA_LEVEL_POS)) </span></div><div class="line"><a name="l00399"></a><span class="lineno"><a class="line" href="group__UART__TX__FIFO.html#ga87ac9140fc8734560ea176bdd6afec8e">  399</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_TX_FIFO_DATA_POS                    0 </span></div><div class="line"><a name="l00400"></a><span class="lineno"><a class="line" href="group__UART__TX__FIFO.html#gae4ef05d4fb99b14b0d9201a048006962">  400</a></span>&#160;<span class="preprocessor"> #define MXC_F_UART_TX_FIFO_DATA                        ((uint32_t)(0x7FUL &lt;&lt; MXC_F_UART_TX_FIFO_DATA_POS)) </span></div><div class="line"><a name="l00404"></a><span class="lineno">  404</span>&#160;<span class="preprocessor">#ifdef __cplusplus</span></div><div class="line"><a name="l00405"></a><span class="lineno">  405</span>&#160;}</div><div class="line"><a name="l00406"></a><span class="lineno">  406</span>&#160;<span class="preprocessor">#endif</span></div><div class="line"><a name="l00407"></a><span class="lineno">  407</span>&#160;</div><div class="line"><a name="l00408"></a><span class="lineno">  408</span>&#160;<span class="preprocessor">#endif </span><span class="comment">/* _UART_REGS_H_ */</span><span class="preprocessor"></span></div><div class="ttc" id="structmxc__uart__regs__t_html_a8d1ee5f15adf137a3e49387428029b92"><div class="ttname"><a href="structmxc__uart__regs__t.html#a8d1ee5f15adf137a3e49387428029b92">mxc_uart_regs_t::baud0</a></div><div class="ttdeci">__IO uint32_t baud0</div><div class="ttdoc">0x14: UART BAUD0 Register </div><div class="ttdef"><b>Definition:</b> uart_regs.h:94</div></div>
 <div class="ttc" id="structmxc__uart__regs__t_html_ac5e0e67d1af815c24d1fa602727e7811"><div class="ttname"><a href="structmxc__uart__regs__t.html#ac5e0e67d1af815c24d1fa602727e7811">mxc_uart_regs_t::baud1</a></div><div class="ttdeci">__IO uint32_t baud1</div><div class="ttdoc">0x18: UART BAUD1 Register </div><div class="ttdef"><b>Definition:</b> uart_regs.h:95</div></div>
 <div class="ttc" id="structmxc__uart__regs__t_html_aca2dbb139bffbd1e52cfacd02c38eb46"><div class="ttname"><a href="structmxc__uart__regs__t.html#aca2dbb139bffbd1e52cfacd02c38eb46">mxc_uart_regs_t::int_fl</a></div><div class="ttdeci">__IO uint32_t int_fl</div><div class="ttdoc">0x10: UART INT_FL Register </div><div class="ttdef"><b>Definition:</b> uart_regs.h:93</div></div>
 <div class="ttc" id="structmxc__uart__regs__t_html_a0472317b1fc5e3022c2f7d3489a91524"><div class="ttname"><a href="structmxc__uart__regs__t.html#a0472317b1fc5e3022c2f7d3489a91524">mxc_uart_regs_t::int_en</a></div><div class="ttdeci">__IO uint32_t int_en</div><div class="ttdoc">0x0C: UART INT_EN Register </div><div class="ttdef"><b>Definition:</b> uart_regs.h:92</div></div>