From beab46e59ce00ed424eaf441bd686540146b40d6 Mon Sep 17 00:00:00 2001
From: schneider <schneider@blinkenlichts.net>
Date: Sat, 17 Oct 2020 02:08:41 +0200
Subject: [PATCH] change(startup): Move stack sizes to linker scripts
---
.../Maxim/MAX32665/Source/GCC/max32665.ld | 17 ++++++-----------
.../Maxim/MAX32665/Source/GCC/max32665_boot.ld | 17 ++++++-----------
.../Maxim/MAX32665/Source/GCC/max32665_core0.ld | 17 ++++++-----------
.../Maxim/MAX32665/Source/GCC/max32665_core1.ld | 17 ++++++-----------
.../MAX32665/Source/GCC/startup_max32665.S | 6 +++++-
5 files changed, 29 insertions(+), 45 deletions(-)
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld
index 3058bb8ec..ec9d87ecf 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld
@@ -57,6 +57,8 @@ SRAM_ADDR = DEFINED(ARM_SRAM_START) ? ARM_SRAM_START : (SDMA_CODE_ADDR + SDMA_CO
/* SRAM_SIZE must be defined */
SRAM_LEN = SRAM_SIZE + SRAM_ORIGIN - SRAM_ADDR;
+STACK_SIZE = 0x1000;
+
/* SPID and SPIX Sections here are maximum possible sizes */
/* If used, they should be adjusted for the external Flash/RAM size */
MEMORY {
@@ -191,18 +193,11 @@ SECTIONS {
_ebss = ALIGN(., 4);
} > SRAM
- /* Setup the stack for Core 1, it will only be used if the user code
- * includes a definition of Stack_Size_Core1, which defines the space
- * reserved above the main core's stack for core 1's stack */
-
- __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1;
-
- /* Set stack top to end of RAM, and stack limit move down by Stack_Size.
- * If core 1 is used, set the stack to the bottom of Core 1's stack region */
- __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit = __StackTop - Stack_Size;
+ /* Set stack top to end of RAM, and stack limit move down by Stack_Size. */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ /*__StackLimit = __StackTop - Stack_Size; */
+ __StackLimit = __StackTop - STACK_SIZE;
.heap (COPY):
{
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_boot.ld b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_boot.ld
index 30b2d30fc..8868c6910 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_boot.ld
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_boot.ld
@@ -34,6 +34,8 @@
*
******************************************************************************/
+STACK_SIZE = 0x1000;
+
/* SPID and SPIX Sections here are maximum possible sizes */
/* If used, they should be adjusted for the external Flash/RAM size */
MEMORY {
@@ -120,18 +122,11 @@ SECTIONS {
_ebss = ALIGN(., 4);
} > SRAM
- /* Setup the stack for Core 1, it will only be used if the user code
- * includes a definition of Stack_Size_Core1, which defines the space
- * reserved above the main core's stack for core 1's stack */
-
- __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1;
-
- /* Set stack top to end of RAM, and stack limit move down by Stack_Size.
- * If core 1 is used, set the stack to the bottom of Core 1's stack region */
- __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit = __StackTop - Stack_Size;
+ /* Set stack top to end of RAM, and stack limit move down by Stack_Size. */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ /*__StackLimit = __StackTop - Stack_Size; */
+ __StackLimit = __StackTop - STACK_SIZE;
.heap (COPY):
{
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core0.ld b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core0.ld
index 9895c9a37..2c2e94e19 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core0.ld
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core0.ld
@@ -34,6 +34,8 @@
*
******************************************************************************/
+STACK_SIZE = 0x1000;
+
/* SPID and SPIX Sections here are maximum possible sizes */
/* If used, they should be adjusted for the external Flash/RAM size */
MEMORY {
@@ -120,18 +122,11 @@ SECTIONS {
_ebss = ALIGN(., 4);
} > SRAM
- /* Setup the stack for Core 1, it will only be used if the user code
- * includes a definition of Stack_Size_Core1, which defines the space
- * reserved above the main core's stack for core 1's stack */
-
- __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1;
-
- /* Set stack top to end of RAM, and stack limit move down by Stack_Size.
- * If core 1 is used, set the stack to the bottom of Core 1's stack region */
- __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit = __StackTop - Stack_Size;
+ /* Set stack top to end of RAM, and stack limit move down by Stack_Size. */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ /*__StackLimit = __StackTop - Stack_Size; */
+ __StackLimit = __StackTop - STACK_SIZE;
.heap (COPY):
{
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core1.ld b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core1.ld
index 7612a2589..2dedc3ddf 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core1.ld
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665_core1.ld
@@ -34,6 +34,8 @@
*
******************************************************************************/
+STACK_SIZE = 0x2000;
+
/* SPID and SPIX Sections here are maximum possible sizes */
/* If used, they should be adjusted for the external Flash/RAM size */
MEMORY {
@@ -120,18 +122,11 @@ SECTIONS {
_ebss = ALIGN(., 4);
} > SRAM
- /* Setup the stack for Core 1, it will only be used if the user code
- * includes a definition of Stack_Size_Core1, which defines the space
- * reserved above the main core's stack for core 1's stack */
-
- __StackTop_Core1 = ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit_Core1 = DEFINED(Stack_Size_Core1) ? __StackTop_Core1 - Stack_Size_Core1 : __StackTop_Core1;
-
- /* Set stack top to end of RAM, and stack limit move down by Stack_Size.
- * If core 1 is used, set the stack to the bottom of Core 1's stack region */
- __StackTop = DEFINED(Stack_Size_Core1) ? __StackLimit_Core1 : ORIGIN(SRAM) + LENGTH(SRAM);
- __StackLimit = __StackTop - Stack_Size;
+ /* Set stack top to end of RAM, and stack limit move down by Stack_Size. */
+ __StackTop = ORIGIN(SRAM) + LENGTH(SRAM);
+ /*__StackLimit = __StackTop - Stack_Size; */
+ __StackLimit = __StackTop - STACK_SIZE;
.heap (COPY):
{
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
index 8022b65fe..99f0c24e0 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
@@ -63,12 +63,16 @@
.equ ARM_SRAM_START, __ARM_SRAM_START
#endif
+/*
+ XXX: card10: Stack size moved to linker scripts.
+
.globl Stack_Size
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x00001000
#endif
+
.globl __StackTop
.globl __StackLimit
__StackLimit:
@@ -76,7 +80,7 @@ __StackLimit:
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
-
+*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
--
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