diff --git a/epicardium/modules/hardware.c b/epicardium/modules/hardware.c
index 92dff16eadfdeea87f65fd47c956d1d67057ab44..013df5a4334726f3d40666ff242df06c49461414 100644
--- a/epicardium/modules/hardware.c
+++ b/epicardium/modules/hardware.c
@@ -88,7 +88,6 @@ int hardware_early_init(void)
MXC_RTC,
SQUARE_WAVE_ENABLED,
F_32KHZ,
- NOISE_IMMUNE_MODE,
NULL) == E_BUSY
)
;
diff --git a/lib/card10/card10.c b/lib/card10/card10.c
index 51ac0429390159c97bd787bc1b59fd3654ad7c8d..ef1b0f71c6b9ff699acfacad3b8b39873d44a3ee 100644
--- a/lib/card10/card10.c
+++ b/lib/card10/card10.c
@@ -64,7 +64,6 @@ void card10_init(void)
MXC_RTC,
SQUARE_WAVE_ENABLED,
F_32KHZ,
- NOISE_IMMUNE_MODE,
NULL) == E_BUSY
)
;
diff --git a/lib/sdk/Libraries/Boards/EvKit_V1/Source/board.c b/lib/sdk/Libraries/Boards/EvKit_V1/Source/board.c
index 647c579d9659f23e4946447eed05c5cdc2aa60f2..4833d5ac4b530addb20748f9b8c37e2143c2956b 100644
--- a/lib/sdk/Libraries/Boards/EvKit_V1/Source/board.c
+++ b/lib/sdk/Libraries/Boards/EvKit_V1/Source/board.c
@@ -140,6 +140,12 @@ int Console_Shutdown(void)
return E_NO_ERROR;
}
+/******************************************************************************/
+int Console_PrepForSleep(void)
+{
+ return UART_PrepForSleep(ConsoleUart);
+}
+
/******************************************************************************/
void NMI_Handler(void)
{
diff --git a/lib/sdk/Libraries/Boards/EvKit_V1/examples.txt b/lib/sdk/Libraries/Boards/EvKit_V1/examples.txt
index 559344b42ccd2dad47cb6907b8726fea6617099d..b53d8eaded8e8451d1724a88a1e4f4f5749c8c53 100644
--- a/lib/sdk/Libraries/Boards/EvKit_V1/examples.txt
+++ b/lib/sdk/Libraries/Boards/EvKit_V1/examples.txt
@@ -4,7 +4,10 @@ BLE_beacon
BLE_datc
BLE_dats
BLE_fit
+BLE_fit_ds
+BLE_hci_uart
BLE_scanner
+Bootloader
CRC
DES
DMA
@@ -21,6 +24,7 @@ LP
MAA
OWM
Pulse_Train
+RPU
RTC
SDHC_FAT
SDHC_Raw
@@ -28,6 +32,7 @@ Semaphore
SPI
SPIXF
SPIXR
+SPI_DMA
TMR
TRNG
UART
@@ -35,4 +40,5 @@ USB_CDCACM
USB_CompositeDevice
USB_HIDKeyboard
USB_MassStorage
+USB_MassStorage_SDHC
Watchdog
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h
index 86f31accafbb0670e8e157418bef2e52b8bce8b9..f0309eb6abf89478dc657f25e118de20d7d69603 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h
@@ -262,12 +262,12 @@ typedef struct {
#define MXC_F_DMA_CFG_REQSEL ((uint32_t)(0x3FUL << MXC_F_DMA_CFG_REQSEL_POS)) /**< CFG_REQSEL Mask */
#define MXC_V_DMA_CFG_REQSEL_MEMTOMEM ((uint32_t)0x0UL) /**< CFG_REQSEL_MEMTOMEM Value */
#define MXC_S_DMA_CFG_REQSEL_MEMTOMEM (MXC_V_DMA_CFG_REQSEL_MEMTOMEM << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_MEMTOMEM Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI0RX Value */
- #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI1RX Value */
+ #define MXC_V_DMA_CFG_REQSEL_SPI1RX ((uint32_t)0x1UL) /**< CFG_REQSEL_SPI1RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1RX (MXC_V_DMA_CFG_REQSEL_SPI1RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1RX Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x3UL) /**< CFG_REQSEL_SPI2RX Value */
+ #define MXC_V_DMA_CFG_REQSEL_SPI2RX ((uint32_t)0x2UL) /**< CFG_REQSEL_SPI2RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI2RX (MXC_V_DMA_CFG_REQSEL_SPI2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI2RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI3RX ((uint32_t)0x3UL) /**< CFG_REQSEL_SPI3RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI3RX (MXC_V_DMA_CFG_REQSEL_SPI3RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI3RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0RX ((uint32_t)0x4UL) /**< CFG_REQSEL_UART0RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0RX (MXC_V_DMA_CFG_REQSEL_UART0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1RX ((uint32_t)0x5UL) /**< CFG_REQSEL_UART1RX Value */
@@ -280,8 +280,8 @@ typedef struct {
#define MXC_S_DMA_CFG_REQSEL_ADC (MXC_V_DMA_CFG_REQSEL_ADC << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_ADC Setting */
#define MXC_V_DMA_CFG_REQSEL_UART2RX ((uint32_t)0xEUL) /**< CFG_REQSEL_UART2RX Value */
#define MXC_S_DMA_CFG_REQSEL_UART2RX (MXC_V_DMA_CFG_REQSEL_UART2RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART2RX Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI3RX ((uint32_t)0xFUL) /**< CFG_REQSEL_SPI3RX Value */
- #define MXC_S_DMA_CFG_REQSEL_SPI3RX (MXC_V_DMA_CFG_REQSEL_SPI3RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI3RX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI0RX ((uint32_t)0xFUL) /**< CFG_REQSEL_SPI0RX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI0RX (MXC_V_DMA_CFG_REQSEL_SPI0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX ((uint32_t)0x10UL) /**< CFG_REQSEL_SPI_MSS0RX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI_MSS0RX (MXC_V_DMA_CFG_REQSEL_SPI_MSS0RX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI_MSS0RX Setting */
#define MXC_V_DMA_CFG_REQSEL_USBRXEP1 ((uint32_t)0x11UL) /**< CFG_REQSEL_USBRXEP1 Value */
@@ -306,12 +306,12 @@ typedef struct {
#define MXC_S_DMA_CFG_REQSEL_USBRXEP10 (MXC_V_DMA_CFG_REQSEL_USBRXEP10 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP10 Setting */
#define MXC_V_DMA_CFG_REQSEL_USBRXEP11 ((uint32_t)0x1BUL) /**< CFG_REQSEL_USBRXEP11 Value */
#define MXC_S_DMA_CFG_REQSEL_USBRXEP11 (MXC_V_DMA_CFG_REQSEL_USBRXEP11 << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_USBRXEP11 Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI0TX Value */
- #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI1TX Value */
+ #define MXC_V_DMA_CFG_REQSEL_SPI1TX ((uint32_t)0x21UL) /**< CFG_REQSEL_SPI1TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI1TX (MXC_V_DMA_CFG_REQSEL_SPI1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI1TX Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x23UL) /**< CFG_REQSEL_SPI2TX Value */
+ #define MXC_V_DMA_CFG_REQSEL_SPI2TX ((uint32_t)0x22UL) /**< CFG_REQSEL_SPI2TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI2TX (MXC_V_DMA_CFG_REQSEL_SPI2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI2TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI3TX ((uint32_t)0x23UL) /**< CFG_REQSEL_SPI3TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI3TX (MXC_V_DMA_CFG_REQSEL_SPI3TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI3TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART0TX ((uint32_t)0x24UL) /**< CFG_REQSEL_UART0TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART0TX (MXC_V_DMA_CFG_REQSEL_UART0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART1TX ((uint32_t)0x25UL) /**< CFG_REQSEL_UART1TX Value */
@@ -322,8 +322,8 @@ typedef struct {
#define MXC_S_DMA_CFG_REQSEL_I2C1TX (MXC_V_DMA_CFG_REQSEL_I2C1TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_I2C1TX Setting */
#define MXC_V_DMA_CFG_REQSEL_UART2TX ((uint32_t)0x2EUL) /**< CFG_REQSEL_UART2TX Value */
#define MXC_S_DMA_CFG_REQSEL_UART2TX (MXC_V_DMA_CFG_REQSEL_UART2TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_UART2TX Setting */
- #define MXC_V_DMA_CFG_REQSEL_SPI3TX ((uint32_t)0x2FUL) /**< CFG_REQSEL_SPI3TX Value */
- #define MXC_S_DMA_CFG_REQSEL_SPI3TX (MXC_V_DMA_CFG_REQSEL_SPI3TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI3TX Setting */
+ #define MXC_V_DMA_CFG_REQSEL_SPI0TX ((uint32_t)0x2FUL) /**< CFG_REQSEL_SPI0TX Value */
+ #define MXC_S_DMA_CFG_REQSEL_SPI0TX (MXC_V_DMA_CFG_REQSEL_SPI0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX ((uint32_t)0x30UL) /**< CFG_REQSEL_SPI_MSS0TX Value */
#define MXC_S_DMA_CFG_REQSEL_SPI_MSS0TX (MXC_V_DMA_CFG_REQSEL_SPI_MSS0TX << MXC_F_DMA_CFG_REQSEL_POS) /**< CFG_REQSEL_SPI_MSS0TX Setting */
#define MXC_V_DMA_CFG_REQSEL_USBTXEP1 ((uint32_t)0x31UL) /**< CFG_REQSEL_USBTXEP1 Value */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h
index 5d22591b8c50b62f54c13f57317b889e5f443399..b4dd691ae5068c0d4cddd3f8fc1f25d33d8c8c53 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/fcr_regs.h
@@ -87,9 +87,6 @@ extern "C" {
*/
typedef struct {
__IO uint32_t reg0; /**< <tt>\b 0x00:</tt> FCR REG0 Register */
- __IO uint32_t reg1; /**< <tt>\b 0x04:</tt> FCR REG1 Register */
- __IO uint32_t reg2; /**< <tt>\b 0x08:</tt> FCR REG2 Register */
- __IO uint32_t reg3; /**< <tt>\b 0x0C:</tt> FCR REG3 Register */
} mxc_fcr_regs_t;
/* Register offsets for module FCR */
@@ -100,9 +97,6 @@ typedef struct {
* @{
*/
#define MXC_R_FCR_REG0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: <tt> 0x0000</tt> */
- #define MXC_R_FCR_REG1 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: <tt> 0x0004</tt> */
- #define MXC_R_FCR_REG2 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: <tt> 0x0008</tt> */
- #define MXC_R_FCR_REG3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: <tt> 0x000C</tt> */
/**@} end of group fcr_registers */
/**
@@ -128,60 +122,6 @@ typedef struct {
/**@} end of group FCR_REG0_Register */
-/**
- * @ingroup fcr_registers
- * @defgroup FCR_REG1 FCR_REG1
- * @brief Register 1.
- * @{
- */
- #define MXC_F_FCR_REG1_ACEN_POS 0 /**< REG1_ACEN Position */
- #define MXC_F_FCR_REG1_ACEN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACEN_POS)) /**< REG1_ACEN Mask */
-
- #define MXC_F_FCR_REG1_ACRUN_POS 1 /**< REG1_ACRUN Position */
- #define MXC_F_FCR_REG1_ACRUN ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ACRUN_POS)) /**< REG1_ACRUN Mask */
-
- #define MXC_F_FCR_REG1_LDTRM_POS 2 /**< REG1_LDTRM Position */
- #define MXC_F_FCR_REG1_LDTRM ((uint32_t)(0x1UL << MXC_F_FCR_REG1_LDTRM_POS)) /**< REG1_LDTRM Mask */
-
- #define MXC_F_FCR_REG1_GAININV_POS 3 /**< REG1_GAININV Position */
- #define MXC_F_FCR_REG1_GAININV ((uint32_t)(0x1UL << MXC_F_FCR_REG1_GAININV_POS)) /**< REG1_GAININV Mask */
-
- #define MXC_F_FCR_REG1_ATOMIC_POS 4 /**< REG1_ATOMIC Position */
- #define MXC_F_FCR_REG1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_REG1_ATOMIC_POS)) /**< REG1_ATOMIC Mask */
-
- #define MXC_F_FCR_REG1_MU_POS 8 /**< REG1_MU Position */
- #define MXC_F_FCR_REG1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_REG1_MU_POS)) /**< REG1_MU Mask */
-
-/**@} end of group FCR_REG1_Register */
-
-/**
- * @ingroup fcr_registers
- * @defgroup FCR_REG2 FCR_REG2
- * @brief Register 2.
- * @{
- */
- #define MXC_F_FCR_REG2_INITTRM_POS 0 /**< REG2_INITTRM Position */
- #define MXC_F_FCR_REG2_INITTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_REG2_INITTRM_POS)) /**< REG2_INITTRM Mask */
-
- #define MXC_F_FCR_REG2_MINTRM_POS 10 /**< REG2_MINTRM Position */
- #define MXC_F_FCR_REG2_MINTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_REG2_MINTRM_POS)) /**< REG2_MINTRM Mask */
-
- #define MXC_F_FCR_REG2_MAXTRM_POS 20 /**< REG2_MAXTRM Position */
- #define MXC_F_FCR_REG2_MAXTRM ((uint32_t)(0x1FFUL << MXC_F_FCR_REG2_MAXTRM_POS)) /**< REG2_MAXTRM Mask */
-
-/**@} end of group FCR_REG2_Register */
-
-/**
- * @ingroup fcr_registers
- * @defgroup FCR_REG3 FCR_REG3
- * @brief Register 3.
- * @{
- */
- #define MXC_F_FCR_REG3_DONECNT_POS 0 /**< REG3_DONECNT Position */
- #define MXC_F_FCR_REG3_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_REG3_DONECNT_POS)) /**< REG3_DONECNT Mask */
-
-/**@} end of group FCR_REG3_Register */
-
#ifdef __cplusplus
}
#endif
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h
index a3ca369d1439b576c3c952c3deab4a2405c04590..d8e2846fca49a12d62223bdf9a222411ae911936 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/flc_regs.h
@@ -91,7 +91,8 @@ typedef struct {
__IO uint32_t cn; /**< <tt>\b 0x08:</tt> FLC CN Register */
__R uint32_t rsv_0xc_0x23[6];
__IO uint32_t intr; /**< <tt>\b 0x024:</tt> FLC INTR Register */
- __R uint32_t rsv_0x28_0x2f[2];
+ __I uint32_t ecc_data; /**< <tt>\b 0x28:</tt> FLC ECC_DATA Register */
+ __R uint32_t rsv_0x2c;
__IO uint32_t data[4]; /**< <tt>\b 0x30:</tt> FLC DATA Register */
__O uint32_t acntl; /**< <tt>\b 0x40:</tt> FLC ACNTL Register */
} mxc_flc_regs_t;
@@ -107,6 +108,7 @@ typedef struct {
#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0004</tt> */
#define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0008</tt> */
#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0024</tt> */
+ #define MXC_R_FLC_ECC_DATA ((uint32_t)0x00000028UL) /**< Offset from FLC Base Address: <tt> 0x0028</tt> */
#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0030</tt> */
#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0040</tt> */
/**@} end of group flc_registers */
@@ -167,9 +169,6 @@ typedef struct {
#define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
- #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
- #define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
-
#define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
@@ -199,6 +198,20 @@ typedef struct {
/**@} end of group FLC_INTR_Register */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_ECC_DATA FLC_ECC_DATA
+ * @brief Flash Controller ECC Data Register.
+ * @{
+ */
+ #define MXC_F_FLC_ECC_DATA_ECC_EVEN_POS 0 /**< ECC_DATA_ECC_EVEN Position */
+ #define MXC_F_FLC_ECC_DATA_ECC_EVEN ((uint32_t)(0xFFUL << MXC_F_FLC_ECC_DATA_ECC_EVEN_POS)) /**< ECC_DATA_ECC_EVEN Mask */
+
+ #define MXC_F_FLC_ECC_DATA_ECC_ODD_POS 16 /**< ECC_DATA_ECC_ODD Position */
+ #define MXC_F_FLC_ECC_DATA_ECC_ODD ((uint32_t)(0xFFUL << MXC_F_FLC_ECC_DATA_ECC_ODD_POS)) /**< ECC_DATA_ECC_ODD Mask */
+
+/**@} end of group FLC_ECC_DATA_Register */
+
/**
* @ingroup flc_registers
* @defgroup FLC_DATA FLC_DATA
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h
index 0c2d79cfe93cababc9b295912c9f271ed7e486bd..ab0d15e37ca9185c5e3ddf00b1caffdb01375c51 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h
@@ -108,7 +108,7 @@ typedef struct {
__IO uint32_t syssie; /**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
__R uint32_t rsv_0x58_0x63[3];
__IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */
- __IO uint32_t eccnded; /**< <tt>\b 0x68:</tt> GCR ECCNDED Register */
+ __IO uint32_t ecc_ced; /**< <tt>\b 0x68:</tt> GCR ECC_CED Register */
__IO uint32_t eccirqen; /**< <tt>\b 0x6C:</tt> GCR ECCIRQEN Register */
__IO uint32_t eccerrad; /**< <tt>\b 0x70:</tt> GCR ECCERRAD Register */
__IO uint32_t btleldocn; /**< <tt>\b 0x74:</tt> GCR BTLELDOCN Register */
@@ -143,7 +143,7 @@ typedef struct {
#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
#define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */
- #define MXC_R_GCR_ECCNDED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */
+ #define MXC_R_GCR_ECC_CED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */
#define MXC_R_GCR_ECCIRQEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */
#define MXC_R_GCR_ECCERRAD ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */
#define MXC_R_GCR_BTLELDOCN ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: <tt> 0x0074</tt> */
@@ -177,8 +177,8 @@ typedef struct {
#define MXC_F_GCR_SCON_DCACHE_FLUSH_POS 7 /**< SCON_DCACHE_FLUSH Position */
#define MXC_F_GCR_SCON_DCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_FLUSH_POS)) /**< SCON_DCACHE_FLUSH Mask */
- #define MXC_F_GCR_SCON_DCACHE_DIS_POS 9 /**< SCON_DCACHE_DIS Position */
- #define MXC_F_GCR_SCON_DCACHE_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_DCACHE_DIS_POS)) /**< SCON_DCACHE_DIS Mask */
+ #define MXC_F_GCR_SCON_SRCC_DIS_POS 9 /**< SCON_SRCC_DIS Position */
+ #define MXC_F_GCR_SCON_SRCC_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SCON_SRCC_DIS_POS)) /**< SCON_SRCC_DIS Mask */
#define MXC_F_GCR_SCON_CCHK_POS 13 /**< SCON_CCHK Position */
#define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */
@@ -206,8 +206,8 @@ typedef struct {
#define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
#define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
- #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
- #define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
+ #define MXC_F_GCR_RSTR0_WDT0_POS 1 /**< RSTR0_WDT0 Position */
+ #define MXC_F_GCR_RSTR0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT0_POS)) /**< RSTR0_WDT0 Mask */
#define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
#define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
@@ -239,12 +239,12 @@ typedef struct {
#define MXC_F_GCR_RSTR0_UART1_POS 12 /**< RSTR0_UART1 Position */
#define MXC_F_GCR_RSTR0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS)) /**< RSTR0_UART1 Mask */
- #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
- #define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
-
- #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
+ #define MXC_F_GCR_RSTR0_SPI1_POS 13 /**< RSTR0_SPI1 Position */
#define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
+ #define MXC_F_GCR_RSTR0_SPI2_POS 14 /**< RSTR0_SPI2 Position */
+ #define MXC_F_GCR_RSTR0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI2_POS)) /**< RSTR0_SPI2 Mask */
+
#define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
#define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
@@ -402,6 +402,9 @@ typedef struct {
#define MXC_F_GCR_PM_SDMAWKEN_POS 8 /**< PM_SDMAWKEN Position */
#define MXC_F_GCR_PM_SDMAWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_SDMAWKEN_POS)) /**< PM_SDMAWKEN Mask */
+ #define MXC_F_GCR_PM_COMPWKEN_POS 8 /**< PM_COMPWKEN Position */
+ #define MXC_F_GCR_PM_COMPWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_COMPWKEN_POS)) /**< PM_COMPWKEN Mask */
+
#define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
#define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
@@ -411,6 +414,9 @@ typedef struct {
#define MXC_F_GCR_PM_HIRC8MPD_POS 17 /**< PM_HIRC8MPD Position */
#define MXC_F_GCR_PM_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) /**< PM_HIRC8MPD Mask */
+ #define MXC_F_GCR_PM_XTALPB_POS 20 /**< PM_XTALPB Position */
+ #define MXC_F_GCR_PM_XTALPB ((uint32_t)(0x1UL << MXC_F_GCR_PM_XTALPB_POS)) /**< PM_XTALPB Mask */
+
/**@} end of group GCR_PM_Register */
/**
@@ -471,12 +477,12 @@ typedef struct {
#define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
#define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
- #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
- #define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
-
- #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
+ #define MXC_F_GCR_PERCKCN0_SPI1D_POS 6 /**< PERCKCN0_SPI1D Position */
#define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
+ #define MXC_F_GCR_PERCKCN0_SPI2D_POS 7 /**< PERCKCN0_SPI2D Position */
+ #define MXC_F_GCR_PERCKCN0_SPI2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI2D_POS)) /**< PERCKCN0_SPI2D Mask */
+
#define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
#define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
@@ -489,23 +495,23 @@ typedef struct {
#define MXC_F_GCR_PERCKCN0_CRYPTOD_POS 14 /**< PERCKCN0_CRYPTOD Position */
#define MXC_F_GCR_PERCKCN0_CRYPTOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) /**< PERCKCN0_CRYPTOD Mask */
- #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
- #define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
+ #define MXC_F_GCR_PERCKCN0_TIMER0D_POS 15 /**< PERCKCN0_TIMER0D Position */
+ #define MXC_F_GCR_PERCKCN0_TIMER0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER0D_POS)) /**< PERCKCN0_TIMER0D Mask */
- #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
- #define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
+ #define MXC_F_GCR_PERCKCN0_TIMER1D_POS 16 /**< PERCKCN0_TIMER1D Position */
+ #define MXC_F_GCR_PERCKCN0_TIMER1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER1D_POS)) /**< PERCKCN0_TIMER1D Mask */
- #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
- #define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
+ #define MXC_F_GCR_PERCKCN0_TIMER2D_POS 17 /**< PERCKCN0_TIMER2D Position */
+ #define MXC_F_GCR_PERCKCN0_TIMER2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER2D_POS)) /**< PERCKCN0_TIMER2D Mask */
- #define MXC_F_GCR_PERCKCN0_T3D_POS 18 /**< PERCKCN0_T3D Position */
- #define MXC_F_GCR_PERCKCN0_T3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T3D_POS)) /**< PERCKCN0_T3D Mask */
+ #define MXC_F_GCR_PERCKCN0_TIMER3D_POS 18 /**< PERCKCN0_TIMER3D Position */
+ #define MXC_F_GCR_PERCKCN0_TIMER3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER3D_POS)) /**< PERCKCN0_TIMER3D Mask */
- #define MXC_F_GCR_PERCKCN0_T4D_POS 19 /**< PERCKCN0_T4D Position */
- #define MXC_F_GCR_PERCKCN0_T4D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T4D_POS)) /**< PERCKCN0_T4D Mask */
+ #define MXC_F_GCR_PERCKCN0_TIMER4D_POS 19 /**< PERCKCN0_TIMER4D Position */
+ #define MXC_F_GCR_PERCKCN0_TIMER4D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER4D_POS)) /**< PERCKCN0_TIMER4D Mask */
- #define MXC_F_GCR_PERCKCN0_T5D_POS 20 /**< PERCKCN0_T5D Position */
- #define MXC_F_GCR_PERCKCN0_T5D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T5D_POS)) /**< PERCKCN0_T5D Mask */
+ #define MXC_F_GCR_PERCKCN0_TIMER5D_POS 20 /**< PERCKCN0_TIMER5D Position */
+ #define MXC_F_GCR_PERCKCN0_TIMER5D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_TIMER5D_POS)) /**< PERCKCN0_TIMER5D Mask */
#define MXC_F_GCR_PERCKCN0_ADCD_POS 23 /**< PERCKCN0_ADCD Position */
#define MXC_F_GCR_PERCKCN0_ADCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_ADCD_POS)) /**< PERCKCN0_ADCD Mask */
@@ -659,18 +665,12 @@ typedef struct {
#define MXC_F_GCR_RSTR1_PT_POS 1 /**< RSTR1_PT Position */
#define MXC_F_GCR_RSTR1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PT_POS)) /**< RSTR1_PT Mask */
- #define MXC_F_GCR_RSTR1_PBM_POS 2 /**< RSTR1_PBM Position */
- #define MXC_F_GCR_RSTR1_PBM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PBM_POS)) /**< RSTR1_PBM Mask */
-
#define MXC_F_GCR_RSTR1_SPIXIP_POS 3 /**< RSTR1_SPIXIP Position */
#define MXC_F_GCR_RSTR1_SPIXIP ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXIP_POS)) /**< RSTR1_SPIXIP Mask */
#define MXC_F_GCR_RSTR1_XSPIM_POS 4 /**< RSTR1_XSPIM Position */
#define MXC_F_GCR_RSTR1_XSPIM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_XSPIM_POS)) /**< RSTR1_XSPIM Mask */
- #define MXC_F_GCR_RSTR1_GPIO3_POS 5 /**< RSTR1_GPIO3 Position */
- #define MXC_F_GCR_RSTR1_GPIO3 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_GPIO3_POS)) /**< RSTR1_GPIO3 Mask */
-
#define MXC_F_GCR_RSTR1_SDHC_POS 6 /**< RSTR1_SDHC Position */
#define MXC_F_GCR_RSTR1_SDHC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SDHC_POS)) /**< RSTR1_SDHC Mask */
@@ -680,8 +680,8 @@ typedef struct {
#define MXC_F_GCR_RSTR1_WDT1_POS 8 /**< RSTR1_WDT1 Position */
#define MXC_F_GCR_RSTR1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) /**< RSTR1_WDT1 Mask */
- #define MXC_F_GCR_RSTR1_QSPI0_AHB_POS 9 /**< RSTR1_QSPI0_AHB Position */
- #define MXC_F_GCR_RSTR1_QSPI0_AHB ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_QSPI0_AHB_POS)) /**< RSTR1_QSPI0_AHB Mask */
+ #define MXC_F_GCR_RSTR1_SPI0_POS 9 /**< RSTR1_SPI0 Position */
+ #define MXC_F_GCR_RSTR1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPI0_POS)) /**< RSTR1_SPI0 Mask */
#define MXC_F_GCR_RSTR1_SPIXMEM_POS 15 /**< RSTR1_SPIXMEM Position */
#define MXC_F_GCR_RSTR1_SPIXMEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_SPIXMEM_POS)) /**< RSTR1_SPIXMEM Mask */
@@ -701,6 +701,9 @@ typedef struct {
#define MXC_F_GCR_RSTR1_I2C2_POS 20 /**< RSTR1_I2C2 Position */
#define MXC_F_GCR_RSTR1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_I2C2_POS)) /**< RSTR1_I2C2 Mask */
+ #define MXC_F_GCR_RSTR1_RPU_POS 21 /**< RSTR1_RPU Position */
+ #define MXC_F_GCR_RSTR1_RPU ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_RPU_POS)) /**< RSTR1_RPU Mask */
+
#define MXC_F_GCR_RSTR1_HTMR0_POS 22 /**< RSTR1_HTMR0 Position */
#define MXC_F_GCR_RSTR1_HTMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_HTMR0_POS)) /**< RSTR1_HTMR0 Mask */
@@ -748,8 +751,8 @@ typedef struct {
#define MXC_F_GCR_PERCKCN1_OWIRED_POS 13 /**< PERCKCN1_OWIRED Position */
#define MXC_F_GCR_PERCKCN1_OWIRED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_OWIRED_POS)) /**< PERCKCN1_OWIRED Mask */
- #define MXC_F_GCR_PERCKCN1_SPI3D_POS 14 /**< PERCKCN1_SPI3D Position */
- #define MXC_F_GCR_PERCKCN1_SPI3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPI3D_POS)) /**< PERCKCN1_SPI3D Mask */
+ #define MXC_F_GCR_PERCKCN1_SPI0D_POS 14 /**< PERCKCN1_SPI0D Position */
+ #define MXC_F_GCR_PERCKCN1_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPI0D_POS)) /**< PERCKCN1_SPI0D Mask */
#define MXC_F_GCR_PERCKCN1_SPIXIPDD_POS 20 /**< PERCKCN1_SPIXIPDD Position */
#define MXC_F_GCR_PERCKCN1_SPIXIPDD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_SPIXIPDD_POS)) /**< PERCKCN1_SPIXIPDD Mask */
@@ -792,8 +795,8 @@ typedef struct {
#define MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS 0 /**< EVTEN_CPU0DMAEVENT Position */
#define MXC_F_GCR_EVTEN_CPU0DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS)) /**< EVTEN_CPU0DMAEVENT Mask */
- #define MXC_F_GCR_EVTEN_CPU0RXEVENT_POS 1 /**< EVTEN_CPU0RXEVENT Position */
- #define MXC_F_GCR_EVTEN_CPU0RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0RXEVENT_POS)) /**< EVTEN_CPU0RXEVENT Mask */
+ #define MXC_F_GCR_EVTEN_CPU0DMA1EVENT_POS 1 /**< EVTEN_CPU0DMA1EVENT Position */
+ #define MXC_F_GCR_EVTEN_CPU0DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0DMA1EVENT_POS)) /**< EVTEN_CPU0DMA1EVENT Mask */
#define MXC_F_GCR_EVTEN_CPU0TXEVENT_POS 2 /**< EVTEN_CPU0TXEVENT Position */
#define MXC_F_GCR_EVTEN_CPU0TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0TXEVENT_POS)) /**< EVTEN_CPU0TXEVENT Mask */
@@ -801,8 +804,8 @@ typedef struct {
#define MXC_F_GCR_EVTEN_CPU1DMAEVENT_POS 3 /**< EVTEN_CPU1DMAEVENT Position */
#define MXC_F_GCR_EVTEN_CPU1DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU1DMAEVENT_POS)) /**< EVTEN_CPU1DMAEVENT Mask */
- #define MXC_F_GCR_EVTEN_CPU1RXEVENT_POS 4 /**< EVTEN_CPU1RXEVENT Position */
- #define MXC_F_GCR_EVTEN_CPU1RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU1RXEVENT_POS)) /**< EVTEN_CPU1RXEVENT Mask */
+ #define MXC_F_GCR_EVTEN_CPU1DMA1EVENT_POS 4 /**< EVTEN_CPU1DMA1EVENT Position */
+ #define MXC_F_GCR_EVTEN_CPU1DMA1EVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU1DMA1EVENT_POS)) /**< EVTEN_CPU1DMA1EVENT Mask */
#define MXC_F_GCR_EVTEN_CPU1TXEVENT_POS 5 /**< EVTEN_CPU1TXEVENT Position */
#define MXC_F_GCR_EVTEN_CPU1TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU1TXEVENT_POS)) /**< EVTEN_CPU1TXEVENT Mask */
@@ -883,47 +886,47 @@ typedef struct {
/**
* @ingroup gcr_registers
- * @defgroup GCR_ECCNDED GCR_ECCNDED
+ * @defgroup GCR_ECC_CED GCR_ECC_CED
* @brief ECC Not Double Error Detect Register
* @{
*/
- #define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS 0 /**< ECCNDED_SYSRAM0ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS)) /**< ECCNDED_SYSRAM0ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM0ECC_CED_POS 0 /**< ECC_CED_SYSRAM0ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM0ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM0ECC_CED_POS)) /**< ECC_CED_SYSRAM0ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS 1 /**< ECCNDED_SYSRAM1ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS)) /**< ECCNDED_SYSRAM1ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM1ECC_CED_POS 1 /**< ECC_CED_SYSRAM1ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM1ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM1ECC_CED_POS)) /**< ECC_CED_SYSRAM1ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS 2 /**< ECCNDED_SYSRAM2ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS)) /**< ECCNDED_SYSRAM2ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM2ECC_CED_POS 2 /**< ECC_CED_SYSRAM2ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM2ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM2ECC_CED_POS)) /**< ECC_CED_SYSRAM2ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS 3 /**< ECCNDED_SYSRAM3ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS)) /**< ECCNDED_SYSRAM3ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM3ECC_CED_POS 3 /**< ECC_CED_SYSRAM3ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM3ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM3ECC_CED_POS)) /**< ECC_CED_SYSRAM3ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS 4 /**< ECCNDED_SYSRAM4ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS)) /**< ECCNDED_SYSRAM4ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM4ECC_CED_POS 4 /**< ECC_CED_SYSRAM4ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM4ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM4ECC_CED_POS)) /**< ECC_CED_SYSRAM4ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_SYSRAM5ECCNDED_POS 5 /**< ECCNDED_SYSRAM5ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM5ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM5ECCNDED_POS)) /**< ECCNDED_SYSRAM5ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM5ECC_CED_POS 5 /**< ECC_CED_SYSRAM5ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM5ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM5ECC_CED_POS)) /**< ECC_CED_SYSRAM5ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_SYSRAM6ECCNDED_POS 6 /**< ECCNDED_SYSRAM6ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_SYSRAM6ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM6ECCNDED_POS)) /**< ECCNDED_SYSRAM6ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_SYSRAM6ECC_CED_POS 6 /**< ECC_CED_SYSRAM6ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_SYSRAM6ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_SYSRAM6ECC_CED_POS)) /**< ECC_CED_SYSRAM6ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_IC0ECCNDED_POS 8 /**< ECCNDED_IC0ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_IC0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_IC0ECCNDED_POS)) /**< ECCNDED_IC0ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_IC0ECC_CED_POS 8 /**< ECC_CED_IC0ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_IC0ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_IC0ECC_CED_POS)) /**< ECC_CED_IC0ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_IC1ECCNDED_POS 9 /**< ECCNDED_IC1ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_IC1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_IC1ECCNDED_POS)) /**< ECCNDED_IC1ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_IC1ECC_CED_POS 9 /**< ECC_CED_IC1ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_IC1ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_IC1ECC_CED_POS)) /**< ECC_CED_IC1ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_ICXIPECCNDED_POS 10 /**< ECCNDED_ICXIPECCNDED Position */
- #define MXC_F_GCR_ECCNDED_ICXIPECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_ICXIPECCNDED_POS)) /**< ECCNDED_ICXIPECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_ICXIPECC_CED_POS 10 /**< ECC_CED_ICXIPECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_ICXIPECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_ICXIPECC_CED_POS)) /**< ECC_CED_ICXIPECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_FL0ECCNDED_POS 11 /**< ECCNDED_FL0ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_FL0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_FL0ECCNDED_POS)) /**< ECCNDED_FL0ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_FL0ECC_CED_POS 11 /**< ECC_CED_FL0ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_FL0ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_FL0ECC_CED_POS)) /**< ECC_CED_FL0ECC_CED Mask */
- #define MXC_F_GCR_ECCNDED_FL1ECCNDED_POS 12 /**< ECCNDED_FL1ECCNDED Position */
- #define MXC_F_GCR_ECCNDED_FL1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_FL1ECCNDED_POS)) /**< ECCNDED_FL1ECCNDED Mask */
+ #define MXC_F_GCR_ECC_CED_FL1ECC_CED_POS 12 /**< ECC_CED_FL1ECC_CED Position */
+ #define MXC_F_GCR_ECC_CED_FL1ECC_CED ((uint32_t)(0x1UL << MXC_F_GCR_ECC_CED_FL1ECC_CED_POS)) /**< ECC_CED_FL1ECC_CED Mask */
-/**@} end of group GCR_ECCNDED_Register */
+/**@} end of group GCR_ECC_CED_Register */
/**
* @ingroup gcr_registers
@@ -1041,6 +1044,12 @@ typedef struct {
#define MXC_F_GCR_BTLELDOCN_LDOWDISCH_POS 9 /**< BTLELDOCN_LDOWDISCH Position */
#define MXC_F_GCR_BTLELDOCN_LDOWDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCN_LDOWDISCH_POS)) /**< BTLELDOCN_LDOWDISCH Mask */
+ #define MXC_F_GCR_BTLELDOCN_LDOWOBYP_POS 10 /**< BTLELDOCN_LDOWOBYP Position */
+ #define MXC_F_GCR_BTLELDOCN_LDOWOBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCN_LDOWOBYP_POS)) /**< BTLELDOCN_LDOWOBYP Mask */
+
+ #define MXC_F_GCR_BTLELDOCN_LDOWODISCH_POS 11 /**< BTLELDOCN_LDOWODISCH Position */
+ #define MXC_F_GCR_BTLELDOCN_LDOWODISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCN_LDOWODISCH_POS)) /**< BTLELDOCN_LDOWODISCH Mask */
+
#define MXC_F_GCR_BTLELDOCN_LDOWOENDLY_POS 12 /**< BTLELDOCN_LDOWOENDLY Position */
#define MXC_F_GCR_BTLELDOCN_LDOWOENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCN_LDOWOENDLY_POS)) /**< BTLELDOCN_LDOWOENDLY Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h
index d25878b4288bd8d6a7cc9fc2c3b4390051c62e2e..13a1df9d3b063f42c61ab4d47ecbc16db45cd3e8 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gpio_regs.h
@@ -98,7 +98,7 @@ typedef struct {
__I uint32_t in; /**< <tt>\b 0x24:</tt> GPIO IN Register */
__IO uint32_t int_mod; /**< <tt>\b 0x28:</tt> GPIO INT_MOD Register */
__IO uint32_t int_pol; /**< <tt>\b 0x2C:</tt> GPIO INT_POL Register */
- __R uint32_t rsv_0x30;
+ __IO uint32_t in_en; /**< <tt>\b 0x30:</tt> GPIO IN_EN Register */
__IO uint32_t int_en; /**< <tt>\b 0x34:</tt> GPIO INT_EN Register */
__IO uint32_t int_en_set; /**< <tt>\b 0x38:</tt> GPIO INT_EN_SET Register */
__IO uint32_t int_en_clr; /**< <tt>\b 0x3C:</tt> GPIO INT_EN_CLR Register */
@@ -147,6 +147,7 @@ typedef struct {
#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: <tt> 0x0024</tt> */
#define MXC_R_GPIO_INT_MOD ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: <tt> 0x0028</tt> */
#define MXC_R_GPIO_INT_POL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: <tt> 0x002C</tt> */
+ #define MXC_R_GPIO_IN_EN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: <tt> 0x0030</tt> */
#define MXC_R_GPIO_INT_EN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: <tt> 0x0034</tt> */
#define MXC_R_GPIO_INT_EN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: <tt> 0x0038</tt> */
#define MXC_R_GPIO_INT_EN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: <tt> 0x003C</tt> */
@@ -347,6 +348,21 @@ typedef struct {
/**@} end of group GPIO_INT_POL_Register */
+/**
+ * @ingroup gpio_registers
+ * @defgroup GPIO_IN_EN GPIO_IN_EN
+ * @brief GPIO Port Input Enable.
+ * @{
+ */
+ #define MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS 0 /**< IN_EN_GPIO_IN_EN Position */
+ #define MXC_F_GPIO_IN_EN_GPIO_IN_EN ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS)) /**< IN_EN_GPIO_IN_EN Mask */
+ #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS ((uint32_t)0x0UL) /**< IN_EN_GPIO_IN_EN_DIS Value */
+ #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_DIS (MXC_V_GPIO_IN_EN_GPIO_IN_EN_DIS << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_DIS Setting */
+ #define MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN ((uint32_t)0x1UL) /**< IN_EN_GPIO_IN_EN_EN Value */
+ #define MXC_S_GPIO_IN_EN_GPIO_IN_EN_EN (MXC_V_GPIO_IN_EN_GPIO_IN_EN_EN << MXC_F_GPIO_IN_EN_GPIO_IN_EN_POS) /**< IN_EN_GPIO_IN_EN_EN Setting */
+
+/**@} end of group GPIO_IN_EN_Register */
+
/**
* @ingroup gpio_registers
* @defgroup GPIO_INT_EN GPIO_INT_EN
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h
index 0e8d72d51a4703fda6fa22b6bb605c09eb54d3bf..4fb371a56884845becb492e05a6a3714c0ba0f46 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/htmr_regs.h
@@ -107,6 +107,18 @@ typedef struct {
#define MXC_R_HTMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from HTMR Base Address: <tt> 0x0010</tt> */
/**@} end of group htmr_registers */
+/**
+ * @ingroup htmr_registers
+ * @defgroup HTMR_SEC HTMR_SEC
+ * @brief HTimer Long-Interval Counter. This register contains the 32 most significant
+ * bits of the counter.
+ * @{
+ */
+ #define MXC_F_HTMR_SEC_RTS_POS 0 /**< SEC_RTS Position */
+ #define MXC_F_HTMR_SEC_RTS ((uint32_t)(0x7FFFFFFFUL << MXC_F_HTMR_SEC_RTS_POS)) /**< SEC_RTS Mask */
+
+/**@} end of group HTMR_SEC_Register */
+
/**
* @ingroup htmr_registers
* @defgroup HTMR_SSEC HTMR_SSEC
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h
index 7202c881d6bfb415797d7ecc90e623c387ca49f7..3e0a3d87ae5fbf7248a01134a4d07b0c2c102eb7 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/i2c_regs.h
@@ -210,39 +210,6 @@ typedef struct {
#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
#define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE Mask */
- #define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
- #define MXC_F_I2C_STATUS_STATUS ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
- #define MXC_V_I2C_STATUS_STATUS_IDLE ((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
- #define MXC_S_I2C_STATUS_STATUS_IDLE (MXC_V_I2C_STATUS_STATUS_IDLE << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
- #define MXC_V_I2C_STATUS_STATUS_MTX_ADDR ((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
- #define MXC_S_I2C_STATUS_STATUS_MTX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting */
- #define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK ((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
- #define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK Setting */
- #define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR ((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
- #define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR Setting */
- #define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR ((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
- #define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR Setting */
- #define MXC_V_I2C_STATUS_STATUS_SRX_ADDR ((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
- #define MXC_S_I2C_STATUS_STATUS_SRX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting */
- #define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK ((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
- #define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK Setting */
- #define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR ((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
- #define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR (MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR Setting */
- #define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK ((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
- #define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK Setting */
- #define MXC_V_I2C_STATUS_STATUS_TX ((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
- #define MXC_S_I2C_STATUS_STATUS_TX (MXC_V_I2C_STATUS_STATUS_TX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
- #define MXC_V_I2C_STATUS_STATUS_RX_ACK ((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
- #define MXC_S_I2C_STATUS_STATUS_RX_ACK (MXC_V_I2C_STATUS_STATUS_RX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
- #define MXC_V_I2C_STATUS_STATUS_RX ((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
- #define MXC_S_I2C_STATUS_STATUS_RX (MXC_V_I2C_STATUS_STATUS_RX << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
- #define MXC_V_I2C_STATUS_STATUS_TX_ACK ((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
- #define MXC_S_I2C_STATUS_STATUS_TX_ACK (MXC_V_I2C_STATUS_STATUS_TX_ACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
- #define MXC_V_I2C_STATUS_STATUS_NACK ((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
- #define MXC_S_I2C_STATUS_STATUS_NACK (MXC_V_I2C_STATUS_STATUS_NACK << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
- #define MXC_V_I2C_STATUS_STATUS_BY_ST ((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
- #define MXC_S_I2C_STATUS_STATUS_BY_ST (MXC_V_I2C_STATUS_STATUS_BY_ST << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
-
/**@} end of group I2C_STATUS_Register */
/**
@@ -299,6 +266,12 @@ typedef struct {
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 /**< INT_FL0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**< INT_FL0_TX_LOCK_OUT Mask */
+ #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS 22 /**< INT_FL0_RD_ADDR_MATCH Position */
+ #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS)) /**< INT_FL0_RD_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS 23 /**< INT_FL0_WR_ADDR_MATCH Position */
+ #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS)) /**< INT_FL0_WR_ADDR_MATCH Mask */
+
/**@} end of group I2C_INT_FL0_Register */
/**
@@ -355,6 +328,12 @@ typedef struct {
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 /**< INT_EN0_TX_LOCK_OUT Position */
#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**< INT_EN0_TX_LOCK_OUT Mask */
+ #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS 22 /**< INT_EN0_RD_ADDR_MATCH Position */
+ #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS)) /**< INT_EN0_RD_ADDR_MATCH Mask */
+
+ #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS 23 /**< INT_EN0_WR_ADDR_MATCH Position */
+ #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS)) /**< INT_EN0_WR_ADDR_MATCH Mask */
+
/**@} end of group I2C_INT_EN0_Register */
/**
@@ -369,6 +348,9 @@ typedef struct {
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 /**< INT_FL1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**< INT_FL1_TX_UNDERFLOW Mask */
+ #define MXC_F_I2C_INT_FL1_START_POS 2 /**< INT_FL1_START Position */
+ #define MXC_F_I2C_INT_FL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS)) /**< INT_FL1_START Mask */
+
/**@} end of group I2C_INT_FL1_Register */
/**
@@ -383,6 +365,9 @@ typedef struct {
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 /**< INT_EN1_TX_UNDERFLOW Position */
#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**< INT_EN1_TX_UNDERFLOW Mask */
+ #define MXC_F_I2C_INT_EN1_START_POS 2 /**< INT_EN1_START Position */
+ #define MXC_F_I2C_INT_EN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_START_POS)) /**< INT_EN1_START Mask */
+
/**@} end of group I2C_INT_EN1_Register */
/**
@@ -442,6 +427,18 @@ typedef struct {
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 /**< TX_CTRL0_TX_READY_MODE Position */
#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**< TX_CTRL0_TX_READY_MODE Mask */
+ #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS 2 /**< TX_CTRL0_TX_AMGC_AFD Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS)) /**< TX_CTRL0_TX_AMGC_AFD Mask */
+
+ #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS 3 /**< TX_CTRL0_TX_AMW_AFD Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS)) /**< TX_CTRL0_TX_AMW_AFD Mask */
+
+ #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS 4 /**< TX_CTRL0_TX_AMR_AFD Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS)) /**< TX_CTRL0_TX_AMR_AFD Mask */
+
+ #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS 5 /**< TX_CTRL0_TX_NACK_AFD Position */
+ #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS)) /**< TX_CTRL0_TX_NACK_AFD Mask */
+
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
#define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH Mask */
@@ -574,12 +571,6 @@ typedef struct {
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**< SLAVE_ADDR_SLAVE_ADDR Mask */
- #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS 10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
- #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_DIS Mask */
-
- #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS 11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
- #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX ((uint32_t)(0xFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**< SLAVE_ADDR_SLAVE_ADDR_IDX Mask */
-
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 /**< SLAVE_ADDR_EX_ADDR Position */
#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h
index d6ce94c482f92c64954133495c7e9c51433c7be5..116435d7e451e3f1463461ee540426953465af64 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h
@@ -172,7 +172,7 @@ typedef enum {
ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
DVS_IRQn, /* 0x63 0x018C 99: DVS Controller */
SIMO_IRQn, /* 0x64 0x0190 100: SIMO Controller */
- RPU_IRQn, /* 0x65 0x0194 101: RPU */
+ SCA_IRQn, /* 0x65 0x0194 101: SCA */
AUDIO_IRQn, /* 0x66 0x0198 102: Audio subsystem */
FLC1_IRQn, /* 0x67 0x019C 103: Flash Control 1 */
UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
@@ -513,13 +513,13 @@ typedef enum {
(p) == MXC_ICC1 ? 1 : -1)
/******************************************************************************/
/* Instruction Cache XIP */
-#define MXC_BASE_ICX ((uint32_t)0x4002F000UL)
-#define MXC_ICX ((mxc_icc_regs_t*)MXC_BASE_ICX)
+#define MXC_BASE_SFCC ((uint32_t)0x4002F000UL)
+#define MXC_SFCC ((mxc_icc_regs_t*)MXC_BASE_SFCC)
/******************************************************************************/
/* Data Cache */
-#define MXC_BASE_EMCC ((uint32_t)0x40033000UL)
-#define MXC_EMCC ((mxc_emcc_regs_t*)MXC_BASE_EMCC)
+#define MXC_BASE_SRCC ((uint32_t)0x40033000UL)
+#define MXC_SRCC ((mxc_srcc_regs_t*)MXC_BASE_SRCC)
/******************************************************************************/
/* ADC */
@@ -810,7 +810,7 @@ typedef enum {
/******************************************************************************/
/* RPU */
-#define MXC_BASE_RPU ((uint32_t)0x40002300UL)
+#define MXC_BASE_RPU ((uint32_t)0x40002000UL)
#define MXC_RPU ((mxc_rpu_regs_t*)MXC_BASE_RPU)
#define MXC_RPU_NUM_BUS_MASTERS 9
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd
index 712d5e796f430da1a5833c743310040aa777d687..97bad21031827b2b176ff379fb993f2b535c7825 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd
@@ -576,19 +576,6 @@
</field>
</fields>
</register>
- <register>
- <name>HIRC96M</name>
- <description>96MHz Oscillator Trim Register</description>
- <addressOffset>0x04</addressOffset>
- <fields>
- <field>
- <name>HIRC96MTR</name>
- <description>Allows User to Trim 96MHz Oscillator</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
<register>
<name>OUTEN</name>
<description>GPIOOUT_EN Function Enable Register</description>
@@ -837,7 +824,7 @@
</enumeratedValues>
</field>
<field>
- <name>VDDIOH_SEL</name>
+ <name>RSTN_VOLTAGE_SEL</name>
<description>Error! Description not Found!</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
@@ -1484,7 +1471,7 @@
<addressOffset>0x18</addressOffset>
<fields>
<field>
- <name>ADDR</name>
+ <name>COUNT</name>
<description>DMA Byte Address.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
@@ -1854,158 +1841,6 @@
</registers>
</peripheral>
<!--AES_KEY AES Keys.-->
- <peripheral>
- <name>EMCC</name>
- <description>External Memory Cache Controller Registers.</description>
- <baseAddress>0x40033000</baseAddress>
- <addressBlock>
- <offset>0x00</offset>
- <size>0x1000</size>
- <usage>registers</usage>
- </addressBlock>
- <registers>
- <register>
- <name>CACHE_ID</name>
- <description>Cache ID Register.</description>
- <addressOffset>0x0000</addressOffset>
- <access>read-only</access>
- <fields>
- <field>
- <name>RELNUM</name>
- <description>Release Number. Identifies the RTL release version.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- <field>
- <name>PARTNUM</name>
- <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description>
- <bitOffset>6</bitOffset>
- <bitWidth>4</bitWidth>
- </field>
- <field>
- <name>CCHID</name>
- <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description>
- <bitOffset>10</bitOffset>
- <bitWidth>6</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>MEMCFG</name>
- <description>Memory Configuration Register.</description>
- <addressOffset>0x0004</addressOffset>
- <access>read-only</access>
- <resetValue>0x00080008</resetValue>
- <fields>
- <field>
- <name>CCHSZ</name>
- <description>Cache Size. Indicates total size in Kbytes of cache.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- <field>
- <name>MEMSZ</name>
- <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description>
- <bitOffset>16</bitOffset>
- <bitWidth>16</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>CACHE_CTRL</name>
- <description>Cache Control and Status Register.</description>
- <addressOffset>0x0100</addressOffset>
- <fields>
- <field>
- <name>CACHE_EN</name>
- <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Cache Enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>WRITE_ALLOC_EN</name>
- <description>Write Allocate Enable. This bit only writable while the cache is disabled.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Write-no-allocate.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Write-allocate enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CWFST_DIS</name>
- <description>Critical word first and streaming disable. This bit only writeable while the cache is disabled.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Critical word first and streaming disabled.</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Critical word first and streaming enabled.</description>
- <value>0</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>CACHE_RDY</name>
- <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>notReady</name>
- <description>Not Ready.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>ready</name>
- <description>Ready.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- <register>
- <name>INVALIDATE</name>
- <description>Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.</description>
- <addressOffset>0x0700</addressOffset>
- <fields>
- <field>
- <name>IA</name>
- <description>Invalidate all cache contents.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>32</bitWidth>
- </field>
- </fields>
- </register>
- </registers>
- </peripheral>
-<!--EMCC External Memory Cache Controller Registers.-->
<peripheral>
<name>DMA</name>
<description>DMA Controller Fully programmable, chaining capable DMA channels.</description>
@@ -2401,19 +2236,19 @@
<description>Memory To Memory</description>
<value>0x00</value>
</enumeratedValue>
- <enumeratedValue>
- <name>SPI0RX</name>
- <description>SPI0 RX</description>
- <value>0x01</value>
- </enumeratedValue>
<enumeratedValue>
<name>SPI1RX</name>
<description>SPI1 RX</description>
- <value>0x02</value>
+ <value>0x01</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI2RX</name>
<description>SPI2 RX</description>
+ <value>0x02</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SPI3RX</name>
+ <description>SPI3 RX</description>
<value>0x03</value>
</enumeratedValue>
<enumeratedValue>
@@ -2447,8 +2282,8 @@
<value>0x0E</value>
</enumeratedValue>
<enumeratedValue>
- <name>SPI3RX</name>
- <description>SPI3 RX</description>
+ <name>SPI0RX</name>
+ <description>SPI0 RX</description>
<value>0x0F</value>
</enumeratedValue>
<enumeratedValue>
@@ -2511,19 +2346,19 @@
<description>USB Endpoint 11 RX</description>
<value>0x1B</value>
</enumeratedValue>
- <enumeratedValue>
- <name>SPI0TX</name>
- <description>SPI0 TX</description>
- <value>0x21</value>
- </enumeratedValue>
<enumeratedValue>
<name>SPI1TX</name>
<description>SPI1 TX</description>
- <value>0x22</value>
+ <value>0x21</value>
</enumeratedValue>
<enumeratedValue>
<name>SPI2TX</name>
<description>SPI2 TX</description>
+ <value>0x22</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SPI3TX</name>
+ <description>SPI3 TX</description>
<value>0x23</value>
</enumeratedValue>
<enumeratedValue>
@@ -2552,8 +2387,8 @@
<value>0x2E</value>
</enumeratedValue>
<enumeratedValue>
- <name>SPI3TX</name>
- <description>SPI3 TX</description>
+ <name>SPI0TX</name>
+ <description>SPI0 TX</description>
<value>0x2F</value>
</enumeratedValue>
<enumeratedValue>
@@ -3703,24 +3538,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>BRST</name>
- <description>Burst Mode Enable.</description>
- <bitOffset>27</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>disable</name>
- <description>Disable.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>enable</name>
- <description>Enable.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>UNLOCK</name>
<description>Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed.</description>
@@ -3808,6 +3625,26 @@
</field>
</fields>
</register>
+ <register>
+ <name>ECC_DATA</name>
+ <description>Flash Controller ECC Data Register.</description>
+ <addressOffset>0x28</addressOffset>
+ <access>read-only</access>
+ <fields>
+ <field>
+ <name>ECC_EVEN</name>
+ <description>Error Correction Code Even Data.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ <field>
+ <name>ECC_ODD</name>
+ <description>Error Correction Code Odd Data.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>8</bitWidth>
+ </field>
+ </fields>
+ </register>
<register>
<dim>4</dim>
<dimIncrement>4</dimIncrement>
@@ -3948,7 +3785,7 @@
</enumeratedValues>
</field>
<field>
- <name>DCACHE_DIS</name>
+ <name>SRCC_DIS</name>
<description>Data Cache Disable. The system cache(s) will be completely disabled when this bit is set.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
@@ -4052,7 +3889,7 @@
</enumeratedValues>
</field>
<field derivedFrom="DMA">
- <name>WDT</name>
+ <name>WDT0</name>
<description>Watchdog Timer Reset.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
@@ -4118,14 +3955,14 @@
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="DMA">
- <name>SPI0</name>
- <description>SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks.</description>
+ <name>SPI1</name>
+ <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="DMA">
- <name>SPI1</name>
- <description>SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks.</description>
+ <name>SPI2</name>
+ <description>SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
@@ -4550,6 +4387,12 @@
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
+ <field derivedFrom="GPIOWKEN">
+ <name>compwken</name>
+ <description>COMPARATOR Input Wake Up Enable. This bit enables COMP IRQ activity as wakeup source.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
<field>
<name>HIRCPD</name>
<description>HIRC Power Down. This bit selects HIRC power state in DEEPSLEEP mode. </description>
@@ -4580,6 +4423,12 @@
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
+ <field>
+ <name>XTALPB</name>
+ <description>32MHz Bluetooth Oscillator Bypass. </description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
</fields>
</register>
<register>
@@ -4714,14 +4563,14 @@
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>SPI0D</name>
- <description>SPI 0 Disable.</description>
+ <name>SPI1D</name>
+ <description>SPI 1 Disable.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>SPI1D</name>
- <description>SPI 1 Disable.</description>
+ <name>SPI2D</name>
+ <description>SPI 2 Disable.</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
</field>
@@ -4750,37 +4599,37 @@
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>T0D</name>
+ <name>TIMER0D</name>
<description>Timer 0 Disable.</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>T1D</name>
+ <name>TIMER1D</name>
<description>Timer 1 Disable.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>T2D</name>
+ <name>TIMER2D</name>
<description>Timer 2 Disable.</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>T3D</name>
+ <name>TIMER3D</name>
<description>Timer 3 Disable.</description>
<bitOffset>18</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>T4D</name>
+ <name>TIMER4D</name>
<description>Timer 4 Disable.</description>
<bitOffset>19</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="GPIO0D">
- <name>T5D</name>
+ <name>TIMER5D</name>
<description>Timer 5 Disable.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
@@ -5145,12 +4994,6 @@
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
- <field derivedFrom="I2C1">
- <name>PBM</name>
- <description>PBM Reset.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
<field derivedFrom="I2C1">
<name>SPIXIP</name>
<description>SPI XiP Master Reset.</description>
@@ -5163,12 +5006,6 @@
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
- <field derivedFrom="I2C1">
- <name>GPIO3</name>
- <description>GPIO3 Reset.</description>
- <bitOffset>5</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
<field derivedFrom="I2C1">
<name>SDHC</name>
<description>SDHC/SDIO Reset.</description>
@@ -5188,8 +5025,8 @@
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="I2C1">
- <name>QSPI0_AHB</name>
- <description>QSPI0_AHB Reset.</description>
+ <name>SPI0</name>
+ <description>SPI0 Reset.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
@@ -5229,6 +5066,12 @@
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
</field>
+ <field derivedFrom="I2C1">
+ <name>RPU</name>
+ <description>RPU Reset.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
<field derivedFrom="I2C1">
<name>HTMR0</name>
<description>HTMR0 Reset.</description>
@@ -5339,8 +5182,8 @@
<bitWidth>1</bitWidth>
</field>
<field derivedFrom="UART2D">
- <name>SPI3D</name>
- <description>SPI3 Clock Disable.</description>
+ <name>SPI0D</name>
+ <description>SPI0 Clock Disable.</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
</field>
@@ -5418,7 +5261,7 @@
<bitWidth>1</bitWidth>
</field>
<field>
- <name>CPU0RXEVENT</name>
+ <name>CPU0DMA1EVENT</name>
<description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
@@ -5436,7 +5279,7 @@
<bitWidth>1</bitWidth>
</field>
<field>
- <name>CPU1RXEVENT</name>
+ <name>CPU1DMA1EVENT</name>
<description>Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. </description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
@@ -5580,78 +5423,78 @@
</fields>
</register>
<register>
- <name>ECCNDED</name>
+ <name>ECC_CED</name>
<description>ECC Not Double Error Detect Register</description>
<addressOffset>0x68</addressOffset>
<fields>
<field>
- <name>SYSRAM0ECCNDED</name>
+ <name>SYSRAM0ECC_CED</name>
<description>ECC System RAM0 Error Flag. Write 1 to clear.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>SYSRAM1ECCNDED</name>
+ <name>SYSRAM1ECC_CED</name>
<description>ECC System RAM1 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>SYSRAM2ECCNDED</name>
+ <name>SYSRAM2ECC_CED</name>
<description>ECC System RAM2 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>SYSRAM3ECCNDED</name>
+ <name>SYSRAM3ECC_CED</name>
<description>ECC System RAM3 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>SYSRAM4ECCNDED</name>
+ <name>SYSRAM4ECC_CED</name>
<description>ECC System RAM4 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>SYSRAM5ECCNDED</name>
+ <name>SYSRAM5ECC_CED</name>
<description>ECC System RAM5 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>SYSRAM6ECCNDED</name>
+ <name>SYSRAM6ECC_CED</name>
<description>ECC System RAM6 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>IC0ECCNDED</name>
+ <name>IC0ECC_CED</name>
<description>ECC Icache0 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>IC1ECCNDED</name>
+ <name>IC1ECC_CED</name>
<description>ECC Icache1 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>ICXIPECCNDED</name>
+ <name>ICXIPECC_CED</name>
<description>ECC IcacheXIP Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>FL0ECCNDED</name>
+ <name>FL0ECC_CED</name>
<description>ECC Flash0 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
</field>
<field>
- <name>FL1ECCNDED</name>
+ <name>FL1ECC_CED</name>
<description>ECC Flash1 Not Double Error Detect. Write 1 to clear.</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
@@ -5949,6 +5792,42 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>LDOWOBYP</name>
+ <description>LDOWO Bypass Enable</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>LDOWODISCH</name>
+ <description>LDOWO Discharge</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
<field>
<name>LDOWOENDLY</name>
<description>LDOWO Enable Delay Status</description>
@@ -6016,6 +5895,12 @@
<name>GP0</name>
<description>General Purpose Register 0</description>
<addressOffset>0x80</addressOffset>
+ <field>
+ <name>GP0</name>
+ <description>User-defined register RAM.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
</register>
<register>
<name>APBASYNC</name>
@@ -6310,6 +6195,31 @@
</field>
</fields>
</register>
+ <register>
+ <name>IN_EN</name>
+ <description>GPIO Port Input Enable.</description>
+ <addressOffset>0x30</addressOffset>
+ <fields>
+ <field>
+ <name>GPIO_IN_EN</name>
+ <description>Mask of all of the pins on the port.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>GPIO Input Disable</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>GPIO Input Enable</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
<register>
<name>INT_EN</name>
<description>GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port.</description>
@@ -6750,17 +6660,6 @@
</interrupt>
</peripheral>
<!--GPIO1 Individual I/O for each GPIO 1-->
- <peripheral derivedFrom="GPIO0">
- <name>GPIO2</name>
- <description>Individual I/O for each GPIO 2</description>
- <baseAddress>0x4000A000</baseAddress>
- <interrupt>
- <name>GPIO2</name>
- <description>GPIO2 IRQ</description>
- <value>26</value>
- </interrupt>
- </peripheral>
-<!--GPIO2 Individual I/O for each GPIO 2-->
<peripheral>
<name>HTMR</name>
<description>High Speed Timer Module.</description>
@@ -6781,6 +6680,14 @@
<description>HTimer Long-Interval Counter. This register contains the 32 most significant bits of the counter.</description>
<addressOffset>0x00</addressOffset>
<resetMask>0x00000000</resetMask>
+ <fields>
+ <field>
+ <name>RTS</name>
+ <description>HTimer Long Interval Counter.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>31</bitWidth>
+ </field>
+ </fields>
</register>
<register>
<name>SSEC</name>
@@ -7394,88 +7301,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field visable="User">
- <name>STATUS</name>
- <description>Controller Status.</description>
- <bitRange>[11:8]</bitRange>
- <enumeratedValues>
- <enumeratedValue>
- <name>idle</name>
- <description>Controller Idle.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>mtx_addr</name>
- <description>master Transmit address.</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>mrx_addr_ack</name>
- <description>Master Receive address ACK.</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>mtx_ex_addr</name>
- <description>Master Transmit extended address.</description>
- <value>3</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>mrx_ex_addr</name>
- <description>Master Receive extended address ACK.</description>
- <value>4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>srx_addr</name>
- <description>Slave Receive address.</description>
- <value>5</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>stx_addr_ack</name>
- <description>Slave Transmit address ACK.</description>
- <value>6</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>srx_ex_addr</name>
- <description>Slave Receive extended address.</description>
- <value>7</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>stx_ex_addr_ack</name>
- <description>Slave Transmit extended address ACK.</description>
- <value>8</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>tx</name>
- <description>Transmit data (master or slave).</description>
- <value>9</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>rx_ack</name>
- <description>Receive data ACK (master or slave).</description>
- <value>10</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>rx</name>
- <description>Receive data (master or slave).</description>
- <value>11</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>tx_ack</name>
- <description>Transmit data ACK (master or slave).</description>
- <value>12</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>nack</name>
- <description>NACK stage (master or slave).</description>
- <value>13</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>by_st</name>
- <description>Bystander state (ongoing transaction but not participant- another master addressing another slave).</description>
- <value>15</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
</fields>
</register>
<register>
@@ -7744,6 +7569,16 @@
<description>Transmit Lock Out Interrupt.</description>
<bitRange>[15:15]</bitRange>
</field>
+ <field>
+ <name>RD_ADDR_MATCH</name>
+ <description>Slave Read Address Match Interrupt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>WR_ADDR_MATCH</name>
+ <description>Slave Write Address Match Interrupt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
</fields>
</register>
<register>
@@ -8030,6 +7865,16 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>RD_ADDR_MATCH</name>
+ <description>Slave Read Address Match Interrupt.</description>
+ <bitRange>[22:22]</bitRange>
+ </field>
+ <field>
+ <name>WR_ADDR_MATCH</name>
+ <description>Slave Write Address Match Interrupt.</description>
+ <bitRange>[23:23]</bitRange>
+ </field>
</fields>
</register>
<register>
@@ -8071,6 +7916,11 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>START</name>
+ <description>START Condition Interrupt.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
</fields>
</register>
<register>
@@ -8113,6 +7963,11 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>START</name>
+ <description>START Condition Interrupt Enable.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
</fields>
</register>
<register>
@@ -8225,6 +8080,26 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>TX_AMGC_AFD</name>
+ <description>TX FIFO General Call Address Match Auto Flush.</description>
+ <bitRange>[2:2]</bitRange>
+ </field>
+ <field>
+ <name>TX_AMW_AFD</name>
+ <description>TX FIFO Slave Address Match Write Auto Flush.</description>
+ <bitRange>[3:3]</bitRange>
+ </field>
+ <field>
+ <name>TX_AMR_AFD</name>
+ <description>TX FIFO Slave Address Match Read Auto Flush.</description>
+ <bitRange>[4:4]</bitRange>
+ </field>
+ <field>
+ <name>TX_NACK_AFD</name>
+ <description>TX FIFO received NACK Auto Flush.</description>
+ <bitRange>[5:5]</bitRange>
+ </field>
<field>
<name>TX_FLUSH</name>
<description>Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation.</description>
@@ -8462,16 +8337,6 @@
<description>Slave Address.</description>
<bitRange>[9:0]</bitRange>
</field>
- <field>
- <name>SLAVE_ADDR_DIS</name>
- <description>Slave Address DIS.</description>
- <bitRange>[10:10]</bitRange>
- </field>
- <field>
- <name>SLAVE_ADDR_IDX</name>
- <description>Slave Address Index.</description>
- <bitRange>[14:11]</bitRange>
- </field>
<field>
<name>EX_ADDR</name>
<description>Extended Address Select.</description>
@@ -8740,138 +8605,6 @@
</field>
</fields>
</register>
- <register>
- <name>REG1</name>
- <description>Register 1.</description>
- <addressOffset>0x04</addressOffset>
- <access>read-write</access>
- <fields>
- <field>
- <name>ACEN</name>
- <description>Auto-calibration Enable.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ACRUN</name>
- <description>Autocalibration Run.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>not</name>
- <description>Not Running.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>run</name>
- <description>Running.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>LDTRM</name>
- <description>Load Trim.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>GAININV</name>
- <description>Invert Gain.</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>not</name>
- <description>Not Running.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>run</name>
- <description>Running.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>ATOMIC</name>
- <description>Atomic mode.</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>not</name>
- <description>Not Running.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>run</name>
- <description>Running.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>MU</name>
- <description>MU value.</description>
- <bitOffset>8</bitOffset>
- <bitWidth>12</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>REG2</name>
- <description>Register 2.</description>
- <addressOffset>0x08</addressOffset>
- <access>read-write</access>
- <fields>
- <field>
- <name>INITTRM</name>
- <description>Initial Trim Setting.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>MINTRM</name>
- <description>Minimum Trim Setting.</description>
- <bitOffset>10</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- <field>
- <name>MAXTRM</name>
- <description>Maximum Trim Setting.</description>
- <bitOffset>20</bitOffset>
- <bitWidth>9</bitWidth>
- </field>
- </fields>
- </register>
- <register>
- <name>REG3</name>
- <description>Register 3.</description>
- <addressOffset>0x0C</addressOffset>
- <access>read-write</access>
- <fields>
- <field>
- <name>DONECNT</name>
- <description>Auto-callibration Done Counter Setting.</description>
- <bitOffset>0</bitOffset>
- <bitWidth>8</bitWidth>
- </field>
- </fields>
- </register>
</registers>
</peripheral>
<!--FCR Function Control.-->
@@ -8991,6 +8724,12 @@
<bitRange>[3:3]</bitRange>
<access>read-only</access>
</field>
+ <field>
+ <name>od_spec_mode</name>
+ <description>Overdrive Spec Mode.</description>
+ <bitRange>[4:4]</bitRange>
+ <access>read-only</access>
+ </field>
<field>
<name>presence_detect</name>
<description>Presence Pulse Detected.</description>
@@ -10203,29 +9942,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>OVR</name>
- <description>Operating Voltage Range</description>
- <bitOffset>4</bitOffset>
- <bitWidth>2</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>0_9V</name>
- <description>0.9V 24MHz</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1_0V</name>
- <description>1.0V 48MHz</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>1_1V</name>
- <description>1.1V 96MHz</description>
- <value>2</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>BLKDET</name>
<description>Block Auto-Detect</description>
@@ -10244,30 +9960,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>FVDDEN</name>
- <description>Flash VDD Enabled</description>
- <bitOffset>7</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>RREGEN</name>
- <description>Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. </description>
- <bitOffset>8</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>BCKGRND</name>
<description>Background Mode ENable. This bit allows low-power background mode operations, while the CPU is in DeepSleep.</description>
@@ -10323,7 +10015,7 @@
</enumeratedValues>
</field>
<field>
- <name>VDDCMD</name>
+ <name>VCOREMD</name>
<description>VDDC(Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes.</description>
<bitOffset>20</bitOffset>
<bitWidth>1</bitWidth>
@@ -10341,7 +10033,7 @@
</enumeratedValues>
</field>
<field>
- <name>VRTCMD</name>
+ <name>VREGIMD</name>
<description>VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes.</description>
<bitOffset>21</bitOffset>
<bitWidth>1</bitWidth>
@@ -10466,6 +10158,24 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>VRXOUTMD</name>
+ <description>VRXOUT Bluetooth Receiver Supply Power Monitor Disable .</description>
+ <bitOffset>28</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>VTXOUTMD</name>
+ <description>VTXOUT Bluetooth Transmitter Supply Power Monitor Disable .</description>
+ <bitOffset>29</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>PDOWNDSLEN</name>
+ <description>PDOWN DEEPSLEEP Output Enable .</description>
+ <bitOffset>30</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
</fields>
</register>
<register>
@@ -10494,35 +10204,31 @@
</field>
</fields>
</register>
- <register derivedFrom="LPWKST0">
+ <register>
<name>LPWKST1</name>
<description>Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1.</description>
<addressOffset>0x0C</addressOffset>
+ <fields>
+ <field>
+ <name>WAKEST</name>
+ <description>Wakeup IRQ flags (write ones to clear). One or more of these bits will be set when the corresponding dedicated GPIO pin(s) transition(s) from low to high or high to low. If GPIO wakeup source is selected, using PM.GPIOWKEN register, and the corresponding bit is also selected in LPWKEN register, an interrupt will be gnerated to wake up the CPU from a low power mode.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>18</bitWidth>
+ </field>
+ </fields>
</register>
<register derivedFrom="LPWKEN0">
<name>LPWKEN1</name>
<description>Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1.</description>
<addressOffset>0x10</addressOffset>
- </register>
- <register derivedFrom="LPWKST0">
- <name>LPWKST2</name>
- <description>Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2.</description>
- <addressOffset>0x14</addressOffset>
- </register>
- <register derivedFrom="LPWKEN0">
- <name>LPWKEN2</name>
- <description>Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2.</description>
- <addressOffset>0x18</addressOffset>
- </register>
- <register derivedFrom="LPWKST0">
- <name>LPWKST3</name>
- <description>Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3.</description>
- <addressOffset>0x1C</addressOffset>
- </register>
- <register derivedFrom="LPWKEN0">
- <name>LPWKEN3</name>
- <description>Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3.</description>
- <addressOffset>0x20</addressOffset>
+ <fields>
+ <field>
+ <name>WAKEEN</name>
+ <description>Enable wakeup. These bits allow wakeup from the corresponding GPIO pin(s) on transition(s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>31</bitWidth>
+ </field>
+ </fields>
</register>
<register>
<name>LPPWST</name>
@@ -10547,12 +10253,66 @@
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
+ <field>
+ <name>AINCOMP0WKST</name>
+ <description>Analog Input Comparator 0 Wakeup Status Flag.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP1WKST</name>
+ <description>Analog Input Comparator 1 Wakeup Status Flag.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP2WKST</name>
+ <description>Analog Input Comparator 2 Wakeup Status Flag.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP3WKST</name>
+ <description>Analog Input Comparator 3 Wakeup Status Flag.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP0ST</name>
+ <description>Analog Input Comparator 0 Output Status Flag.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP1ST</name>
+ <description>Analog Input Comparator 1 Output Status Flag.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP2ST</name>
+ <description>Analog Input Comparator 2 Output Status Flag.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP3ST</name>
+ <description>Analog Input Comparator 3 Output Status Flag.</description>
+ <bitOffset>11</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
<field>
<name>BBMODEST</name>
<description>Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode.</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
</field>
+ <field>
+ <name>RSTWKST</name>
+ <description>Reset Detect Wakeup Status Flag.</description>
+ <bitOffset>17</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
</fields>
</register>
<register>
@@ -10578,6 +10338,30 @@
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
</field>
+ <field>
+ <name>AINCOMP0WKEN</name>
+ <description>Analog Input Comparator 0 Wakeup Enable.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP1WKEN</name>
+ <description>Analog Input Comparator 1 Wakeup Enable.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP2WKEN</name>
+ <description>Analog Input Comparator 2 Wakeup Enable.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>AINCOMP3WKEN</name>
+ <description>Analog Input Comparator 3 Wakeup Enable.</description>
+ <bitOffset>7</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
</fields>
</register>
<register>
@@ -10693,24 +10477,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>SRAM6SD</name>
- <description>System RAM block 6 Shut Down.</description>
- <bitOffset>6</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>normal</name>
- <description>Normal Operating Mode.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>shutdown</name>
- <description>Shutdown Mode.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>ICACHESD</name>
<description>Instruction Cache RAM Shut Down.</description>
@@ -10748,7 +10514,7 @@
</enumeratedValues>
</field>
<field>
- <name>SCACHESD</name>
+ <name>SRCCSD</name>
<description>System Cache RAM Shut Down.</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
@@ -10973,25 +10739,15 @@
</fields>
</register>
<register>
- <name>GP0</name>
+ <name>BURETVEC</name>
<description>General Purpose Register 0</description>
<addressOffset>0x48</addressOffset>
</register>
<register>
- <name>GP1</name>
+ <name>BUAOD</name>
<description>General Purpose Register 1</description>
<addressOffset>0x4C</addressOffset>
</register>
- <register>
- <name>LPMCSTAT</name>
- <description>Low Power Multi-Core Status</description>
- <addressOffset>0x50</addressOffset>
- </register>
- <register>
- <name>LPMCREQ</name>
- <description>Low Power Multi-Core Request</description>
- <addressOffset>0x54</addressOffset>
- </register>
</registers>
</peripheral>
<!--PWRSEQ Power Sequencer / Low Power Control Register.-->
@@ -11023,7 +10779,7 @@
<resetMask>0x00000000</resetMask>
<fields>
<field>
- <name>RTSS</name>
+ <name>SSEC</name>
<description>RTC Sub-second Counter.</description>
<bitOffset>0</bitOffset>
<bitWidth>8</bitWidth>
@@ -11031,13 +10787,13 @@
</fields>
</register>
<register>
- <name>RAS</name>
+ <name>TODA</name>
<description>Time-of-day Alarm.</description>
<addressOffset>0x08</addressOffset>
<resetMask>0x00000000</resetMask>
<fields>
<field>
- <name>RAS</name>
+ <name>TOD_ALARM</name>
<description>Time-of-day Alarm.</description>
<bitOffset>0</bitOffset>
<bitWidth>20</bitWidth>
@@ -11045,13 +10801,13 @@
</fields>
</register>
<register>
- <name>RSSA</name>
+ <name>SSECA</name>
<description>RTC sub-second alarm. This register contains the reload value for the sub-second alarm.</description>
<addressOffset>0x0C</addressOffset>
<resetMask>0x00000000</resetMask>
<fields>
<field>
- <name>RSSA</name>
+ <name>SSEC_ALARM</name>
<description>This register contains the reload value for the sub-second alarm.</description>
<bitOffset>0</bitOffset>
<bitWidth>32</bitWidth>
@@ -11258,34 +11014,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>X32KMD</name>
- <description>32KHz Oscillator Mode.</description>
- <bitOffset>11</bitOffset>
- <bitWidth>2</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>noiseImmuneMode</name>
- <description>Always operate in Noise Immune Mode. Oscillator warm-up required.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>quietMode</name>
- <description>Always operate in Quiet Mode. No oscillator warm-up required.</description>
- <value>1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>quietInStopWithWarmup</name>
- <description>Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will wait for 32K oscillator warm-up before code execution on Stop Mode exit.</description>
- <value>2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>quietInStopNoWarmup</name>
- <description>Operate in Noise Immune Mode normally, switch to Quiet Mode on Stop Mode entry. Will not wait for 32K oscillator warm-up before code execution on Stop Mode exit.</description>
- <value>3</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>WE</name>
<description>Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits.</description>
@@ -11319,7 +11047,7 @@
<bitWidth>8</bitWidth>
</field>
<field>
- <name>VBATTMR</name>
+ <name>VRTC_TMR</name>
<description>VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds.</description>
<bitOffset>8</bitOffset>
<bitWidth>24</bitWidth>
@@ -11332,42 +11060,6 @@
<addressOffset>0x18</addressOffset>
<resetMask>0x00000000</resetMask>
<fields>
- <field>
- <name>FLITER_EN</name>
- <description>RTC Oscillator Filter Enable</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IBIAS_SEL</name>
- <description>RTC Oscillator 4X Bias Current Select</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>2X</name>
- <description>Selects 2X bias current for RTC oscillator</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>4X</name>
- <description>Selects 4X bias current for RTC oscillator</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>HYST_EN</name>
- <description>RTC Oscillator Hysteresis Buffer Enable</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
- <field>
- <name>IBIAS_EN</name>
- <description>RTC Oscillator Bias Current Enable</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- </field>
<field>
<name>BYPASS</name>
<description>RTC Crystal Bypass</description>
@@ -13790,15 +13482,15 @@
</fields>
</register>
<register>
- <name>BBCR</name>
- <description>BBCR Protection Register</description>
+ <name>MCR</name>
+ <description>MCR Protection Register</description>
<addressOffset>0x006C</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACN</name>
- <description>Allow/Disallow DMA0 access to the BBCR</description>
+ <description>Allow/Disallow DMA0 access to the MCR</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13816,7 +13508,7 @@
</field>
<field>
<name>DMA1ACN</name>
- <description>Allow/Disallow DMA1 access to the BBCR</description>
+ <description>Allow/Disallow DMA1 access to the MCR</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13834,7 +13526,7 @@
</field>
<field>
<name>USBACN</name>
- <description>Allow/Disallow USB access to the BBCR</description>
+ <description>Allow/Disallow USB access to the MCR</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13852,7 +13544,7 @@
</field>
<field>
<name>SYS0ACN</name>
- <description>Allow/Disallow SYS0 access to the BBCR</description>
+ <description>Allow/Disallow SYS0 access to the MCR</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13870,7 +13562,7 @@
</field>
<field>
<name>SYS1ACN</name>
- <description>Allow/Disallow SYS1 access to the BBCR</description>
+ <description>Allow/Disallow SYS1 access to the MCR</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13888,7 +13580,7 @@
</field>
<field>
<name>SDMADACN</name>
- <description>Allow/Disallow SDMA Data access to the BBCR</description>
+ <description>Allow/Disallow SDMA Data access to the MCR</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13906,7 +13598,7 @@
</field>
<field>
<name>SDMAIACN</name>
- <description>Allow/Disallow SDMA Instruction access to the BBCR</description>
+ <description>Allow/Disallow SDMA Instruction access to the MCR</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13924,7 +13616,7 @@
</field>
<field>
<name>CRYPTOACN</name>
- <description>Allow/Disallow CRYPTO access to the BBCR</description>
+ <description>Allow/Disallow CRYPTO access to the MCR</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -13942,7 +13634,7 @@
</field>
<field>
<name>SDIOACN</name>
- <description>Allow/Disallow SDIO access to the BBCR</description>
+ <description>Allow/Disallow SDIO access to the MCR</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -15671,7 +15363,7 @@
</fields>
</register>
<register>
- <name>I2C0</name>
+ <name>I2C0_BUS0</name>
<description>I2C0 Protection Register</description>
<addressOffset>0x01D0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -15842,7 +15534,7 @@
</fields>
</register>
<register>
- <name>I2C1</name>
+ <name>I2C1_BUS0</name>
<description>I2C1 Protection Register</description>
<addressOffset>0x01E0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -16013,7 +15705,7 @@
</fields>
</register>
<register>
- <name>I2C2</name>
+ <name>I2C2_BUS0</name>
<description>I2C2 Protection Register</description>
<addressOffset>0x01F0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -16184,7 +15876,7 @@
</fields>
</register>
<register>
- <name>SPIXIPM</name>
+ <name>SPIXFM</name>
<description>SPI-XIP Master Protection Register</description>
<addressOffset>0x0260</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -16355,7 +16047,7 @@
</fields>
</register>
<register>
- <name>SPIXIPMC</name>
+ <name>SPIXFC</name>
<description>SPI-XIP Master Controller Protection Register</description>
<addressOffset>0x0270</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -17039,7 +16731,7 @@
</fields>
</register>
<register>
- <name>ICACHE0</name>
+ <name>ICC0</name>
<description>Instruction Cache 0 Protection Register</description>
<addressOffset>0x02A0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -17210,7 +16902,7 @@
</fields>
</register>
<register>
- <name>ICACHE1</name>
+ <name>ICC1</name>
<description>Instruction Cache 1 Protection Register</description>
<addressOffset>0x02A4</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -17381,7 +17073,7 @@
</fields>
</register>
<register>
- <name>ICACHEXIP</name>
+ <name>SFCC</name>
<description>Instruction Cache XIP Protection Register</description>
<addressOffset>0x02F0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -17552,7 +17244,7 @@
</fields>
</register>
<register>
- <name>DCACHE</name>
+ <name>SRCC</name>
<description>Data Cache Controller Protection Register</description>
<addressOffset>0x0330</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -18407,7 +18099,7 @@
</fields>
</register>
<register>
- <name>SPID</name>
+ <name>SPIXR</name>
<description>SPI Data Controller Protection Register</description>
<addressOffset>0x03A0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -18578,7 +18270,7 @@
</fields>
</register>
<register>
- <name>PT</name>
+ <name>PTG_BUS0</name>
<description>Pulse Train Protection Register</description>
<addressOffset>0x03C0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -19604,7 +19296,7 @@
</fields>
</register>
<register>
- <name>QSPI1</name>
+ <name>SPI1</name>
<description>QSPI1 Protection Register</description>
<addressOffset>0x0460</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -19775,7 +19467,7 @@
</fields>
</register>
<register>
- <name>QSPI2</name>
+ <name>SPI2</name>
<description>QSPI2 Protection Register</description>
<addressOffset>0x0480</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -21125,7 +20817,7 @@
</fields>
</register>
<register>
- <name>SPIXIPMFIFO</name>
+ <name>SPIXM_FIFO</name>
<description>SPI XIP Master FIFO Protection Register</description>
<addressOffset>0x0BC0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -21458,7 +21150,7 @@
</fields>
</register>
<register>
- <name>QSPI0</name>
+ <name>SPI0</name>
<description>QSPI0 Protection Register</description>
<addressOffset>0x0BE0</addressOffset>
<resetValue>0x00000000</resetValue>
@@ -21791,15 +21483,15 @@
</fields>
</register>
<register>
- <name>SRAM0</name>
- <description>SRAM0 Protection Register</description>
+ <name>SYSRAM0</name>
+ <description>SYSRAM0 Protection Register</description>
<addressOffset>0x0F00</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM0</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM0</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21817,7 +21509,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM0</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM0</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21835,7 +21527,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM0</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM0</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21853,7 +21545,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM0</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM0</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21871,7 +21563,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM0</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM0</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21889,7 +21581,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM0</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM0</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21907,7 +21599,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM0</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM0</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21925,7 +21617,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM0</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM0</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21943,7 +21635,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM0</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM0</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21961,7 +21653,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM0</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM0</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21979,7 +21671,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM0</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM0</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -21997,7 +21689,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM0</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM0</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22015,7 +21707,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM0</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM0</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22033,7 +21725,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM0</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM0</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22051,7 +21743,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM0</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM0</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22069,7 +21761,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM0</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM0</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22087,7 +21779,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM0</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM0</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22105,7 +21797,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM0</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM0</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22124,15 +21816,15 @@
</fields>
</register>
<register>
- <name>SRAM1</name>
- <description>SRAM1 Protection Register</description>
+ <name>SYSRAM1</name>
+ <description>SYSRAM1 Protection Register</description>
<addressOffset>0x0F10</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM1</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM1</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22150,7 +21842,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM1</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM1</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22168,7 +21860,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM1</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM1</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22186,7 +21878,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM1</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM1</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22204,7 +21896,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM1</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM1</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22222,7 +21914,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM1</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM1</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22240,7 +21932,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM1</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM1</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22258,7 +21950,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM1</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM1</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22276,7 +21968,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM1</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM1</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22294,7 +21986,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM1</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM1</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22312,7 +22004,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM1</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM1</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22330,7 +22022,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM1</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM1</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22348,7 +22040,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM1</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM1</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22366,7 +22058,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM1</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM1</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22384,7 +22076,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM1</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM1</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22402,7 +22094,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM1</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM1</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22420,7 +22112,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM1</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM1</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22438,7 +22130,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM1</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM1</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22457,15 +22149,15 @@
</fields>
</register>
<register>
- <name>SRAM2</name>
- <description>SRAM2 Protection Register</description>
+ <name>SYSRAM2</name>
+ <description>SYSRAM2 Protection Register</description>
<addressOffset>0x0F20</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM2</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM2</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22483,7 +22175,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM2</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM2</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22501,7 +22193,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM2</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM2</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22519,7 +22211,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM2</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM2</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22537,7 +22229,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM2</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM2</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22555,7 +22247,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM2</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM2</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22573,7 +22265,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM2</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM2</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22591,7 +22283,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM2</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM2</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22609,7 +22301,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM2</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM2</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22627,7 +22319,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM2</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM2</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22645,7 +22337,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM2</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM2</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22663,7 +22355,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM2</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM2</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22681,7 +22373,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM2</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM2</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22699,7 +22391,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM2</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM2</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22717,7 +22409,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM2</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM2</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22735,7 +22427,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM2</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM2</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22753,7 +22445,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM2</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM2</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22771,7 +22463,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM2</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM2</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22790,15 +22482,15 @@
</fields>
</register>
<register>
- <name>SRAM3</name>
- <description>SRAM3 Protection Register</description>
+ <name>SYSRAM3</name>
+ <description>SYSRAM3 Protection Register</description>
<addressOffset>0x0F30</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM3</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM3</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22816,7 +22508,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM3</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM3</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22834,7 +22526,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM3</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM3</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22852,7 +22544,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM3</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM3</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22870,7 +22562,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM3</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM3</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22888,7 +22580,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM3</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM3</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22906,7 +22598,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM3</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM3</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22924,7 +22616,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM3</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM3</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22942,7 +22634,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM3</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM3</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22960,7 +22652,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM3</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM3</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22978,7 +22670,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM3</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM3</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -22996,7 +22688,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM3</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM3</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23014,7 +22706,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM3</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM3</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23032,7 +22724,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM3</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM3</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23050,7 +22742,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM3</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM3</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23068,7 +22760,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM3</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM3</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23086,7 +22778,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM3</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM3</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23104,7 +22796,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM3</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM3</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23123,15 +22815,15 @@
</fields>
</register>
<register>
- <name>SRAM4</name>
- <description>SRAM4 Protection Register</description>
+ <name>SYSRAM4</name>
+ <description>SYSRAM4 Protection Register</description>
<addressOffset>0x0F40</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM4</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM4</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23149,7 +22841,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM4</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM4</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23167,7 +22859,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM4</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM4</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23185,7 +22877,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM4</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM4</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23203,7 +22895,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM4</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM4</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23221,7 +22913,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM4</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM4</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23239,7 +22931,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM4</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM4</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23257,7 +22949,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM4</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM4</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23275,7 +22967,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM4</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM4</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23293,7 +22985,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM4</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM4</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23311,7 +23003,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM4</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM4</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23329,7 +23021,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM4</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM4</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23347,7 +23039,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM4</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM4</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23365,7 +23057,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM4</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM4</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23383,7 +23075,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM4</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM4</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23401,7 +23093,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM4</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM4</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23419,7 +23111,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM4</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM4</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23437,7 +23129,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM4</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM4</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23456,15 +23148,15 @@
</fields>
</register>
<register>
- <name>SRAM5</name>
- <description>SRAM5 Protection Register</description>
+ <name>SYSRAM5</name>
+ <description>SYSRAM5 Protection Register</description>
<addressOffset>0x0F50</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM5</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM5</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23482,7 +23174,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM5</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM5</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23500,7 +23192,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM5</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM5</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23518,7 +23210,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM5</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM5</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23536,7 +23228,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM5</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM5</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23554,7 +23246,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM5</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM5</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23572,7 +23264,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM5</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM5</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23590,7 +23282,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM5</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM5</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23608,7 +23300,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM5</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM5</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23626,7 +23318,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM5</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM5</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23644,7 +23336,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM5</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM5</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23662,7 +23354,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM5</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM5</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23680,7 +23372,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM5</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM5</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23698,7 +23390,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM5</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM5</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23716,7 +23408,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM5</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM5</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23734,7 +23426,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM5</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM5</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23752,7 +23444,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM5</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM5</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23770,7 +23462,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM5</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM5</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23789,15 +23481,15 @@
</fields>
</register>
<register>
- <name>SRAM6</name>
- <description>SRAM6 Protection Register</description>
+ <name>SYSRAM6</name>
+ <description>SYSRAM6 Protection Register</description>
<addressOffset>0x0F60</addressOffset>
<resetValue>0x00000000</resetValue>
<resetMask>0xFFFFFE00</resetMask>
<fields>
<field>
<name>DMA0ACNR</name>
- <description>Allow/Disallow DMA0 Read access to the SRAM6</description>
+ <description>Allow/Disallow DMA0 Read access to the SYSRAM6</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23815,7 +23507,7 @@
</field>
<field>
<name>DMA0ACNW</name>
- <description>Allow/Disallow DMA0 Write access to the SRAM6</description>
+ <description>Allow/Disallow DMA0 Write access to the SYSRAM6</description>
<bitOffset>1</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23833,7 +23525,7 @@
</field>
<field>
<name>DMA1ACNR</name>
- <description>Allow/Disallow DMA1 Read access to the SRAM6</description>
+ <description>Allow/Disallow DMA1 Read access to the SYSRAM6</description>
<bitOffset>2</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23851,7 +23543,7 @@
</field>
<field>
<name>DMA1ACNW</name>
- <description>Allow/Disallow DMA1 Write access to the SRAM6</description>
+ <description>Allow/Disallow DMA1 Write access to the SYSRAM6</description>
<bitOffset>3</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23869,7 +23561,7 @@
</field>
<field>
<name>USBACNR</name>
- <description>Allow/Disallow USB Read access to the SRAM6</description>
+ <description>Allow/Disallow USB Read access to the SYSRAM6</description>
<bitOffset>4</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23887,7 +23579,7 @@
</field>
<field>
<name>USBACNW</name>
- <description>Allow/Disallow USB Write access to the SRAM6</description>
+ <description>Allow/Disallow USB Write access to the SYSRAM6</description>
<bitOffset>5</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23905,7 +23597,7 @@
</field>
<field>
<name>SYS0ACNR</name>
- <description>Allow/Disallow SYS0 Read access to the SRAM6</description>
+ <description>Allow/Disallow SYS0 Read access to the SYSRAM6</description>
<bitOffset>6</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23923,7 +23615,7 @@
</field>
<field>
<name>SYS0ACNW</name>
- <description>Allow/Disallow SYS0 Write access to the SRAM6</description>
+ <description>Allow/Disallow SYS0 Write access to the SYSRAM6</description>
<bitOffset>7</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23941,7 +23633,7 @@
</field>
<field>
<name>SYS1ACNR</name>
- <description>Allow/Disallow SYS1 Read access to the SRAM6</description>
+ <description>Allow/Disallow SYS1 Read access to the SYSRAM6</description>
<bitOffset>8</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23959,7 +23651,7 @@
</field>
<field>
<name>SYS1ACNW</name>
- <description>Allow/Disallow SYS1 Write access to the SRAM6</description>
+ <description>Allow/Disallow SYS1 Write access to the SYSRAM6</description>
<bitOffset>9</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23977,7 +23669,7 @@
</field>
<field>
<name>SDMADACNR</name>
- <description>Allow/Disallow SDMA Data Read access to the SRAM6</description>
+ <description>Allow/Disallow SDMA Data Read access to the SYSRAM6</description>
<bitOffset>10</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -23995,7 +23687,7 @@
</field>
<field>
<name>SDMADACNW</name>
- <description>Allow/Disallow SDMA Data Write access to the SRAM6</description>
+ <description>Allow/Disallow SDMA Data Write access to the SYSRAM6</description>
<bitOffset>11</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -24013,7 +23705,7 @@
</field>
<field>
<name>SDMAIACNR</name>
- <description>Allow/Disallow SDMA Instruction Read access to the SRAM6</description>
+ <description>Allow/Disallow SDMA Instruction Read access to the SYSRAM6</description>
<bitOffset>12</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -24031,7 +23723,7 @@
</field>
<field>
<name>SDMAIACNW</name>
- <description>Allow/Disallow SDMA Instruction Write access to the SRAM6</description>
+ <description>Allow/Disallow SDMA Instruction Write access to the SYSRAM6</description>
<bitOffset>13</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -24049,7 +23741,7 @@
</field>
<field>
<name>CRYPTOACNR</name>
- <description>Allow/Disallow CRYPTO Read access to the SRAM6</description>
+ <description>Allow/Disallow CRYPTO Read access to the SYSRAM6</description>
<bitOffset>14</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -24067,7 +23759,7 @@
</field>
<field>
<name>CRYPTOACNW</name>
- <description>Allow/Disallow CRYPTO Write access to the SRAM6</description>
+ <description>Allow/Disallow CRYPTO Write access to the SYSRAM6</description>
<bitOffset>15</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -24085,7 +23777,7 @@
</field>
<field>
<name>SDIOACNR</name>
- <description>Allow/Disallow SDIO Read access to the SRAM6</description>
+ <description>Allow/Disallow SDIO Read access to the SYSRAM6</description>
<bitOffset>16</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -24103,7 +23795,7 @@
</field>
<field>
<name>SDIOACNW</name>
- <description>Allow/Disallow SDIO Write access to the SRAM6</description>
+ <description>Allow/Disallow SDIO Write access to the SYSRAM6</description>
<bitOffset>17</bitOffset>
<bitWidth>1</bitWidth>
<enumeratedValues>
@@ -28672,54 +28364,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>SRPOL</name>
- <description>Slave Ready Polarity, each Slave Ready can have unique polarity.</description>
- <bitOffset>24</bitOffset>
- <bitWidth>8</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>SR0_high</name>
- <description>SR0 active high.</description>
- <value>0x1</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR1_high</name>
- <description>SR1 active high.</description>
- <value>0x2</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR2_high</name>
- <description>SR2 active high.</description>
- <value>0x4</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR3_high</name>
- <description>SR3 active high.</description>
- <value>0x8</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR4_high</name>
- <description>SR4 active high.</description>
- <value>0x10</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR5_high</name>
- <description>SR5 active high.</description>
- <value>0x20</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR6_high</name>
- <description>SR6 active high.</description>
- <value>0x40</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>SR7_high</name>
- <description>SR7 active high.</description>
- <value>0x80</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
</fields>
</register>
<register>
@@ -28809,111 +28453,6 @@
</field>
</fields>
</register>
- <register>
- <name>I2S_CTRL</name>
- <description>Register for controlling I2C mode.</description>
- <addressOffset>0x18</addressOffset>
- <access>read-write</access>
- <fields>
- <field>
- <name>I2S_EN</name>
- <description>Low duty cycle control. In timer mode, reload[7:0].</description>
- <bitOffset>0</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>I2C mode is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>I2C mode is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>I2S_MUTE</name>
- <description>I2S Mute.</description>
- <bitOffset>1</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Normal Transmit.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Transmit data is replaced with 0.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>I2S_PAUSE</name>
- <description>I2S Pause.</description>
- <bitOffset>2</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Normal Transmit/Receive.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Halt Transmit and Receive FIFO and DMA accesses, Transmit 0s.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>I2S_MONO</name>
- <description>I2S Monotone.</description>
- <bitOffset>3</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Stereophonic audio format.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Monophonic audio format. Each transmit
- data word is replicated on both left/right
- channels. Receive data is taken from left
- channel, right channel receive data is
- ignored.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>I2S_LJ</name>
- <description>I2S Left Justify.</description>
- <bitOffset>4</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Normal I 2 S audio protocol, audio data
- lags left/right channel signal by one SCLK
- period.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Audio data is synchronized with SSEL
- (left/right channel signal).</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
<register>
<name>DMA</name>
<description>Register for controlling DMA.</description>
@@ -29161,19 +28700,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>TIMEOUT</name>
- <description>Timeout.</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>M_DONE</name>
<description>Master Done, set when SPI Master has completed any transactions.</description>
@@ -29241,110 +28767,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>SR0A</name>
- <description>Slave Ready 0 Asserted.</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR1A</name>
- <description>Slave Ready 1 Asserted.</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR2A</name>
- <description>Slave Ready 2 Asserted.</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR3A</name>
- <description>Slave Ready 3 Asserted.</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR4A</name>
- <description>Slave Ready 4 Asserted.</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR5A</name>
- <description>Slave Ready 5 Asserted.</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR6A</name>
- <description>Slave Ready 6 Asserted.</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR7A</name>
- <description>Slave Ready 7 Asserted.</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>clear</name>
- <description>Flag is set when value read is 1. Write 1 to clear this flag.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
</fields>
</register>
<register>
@@ -29497,24 +28919,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>TIMEOUT</name>
- <description>Timeout interrupt enable.</description>
- <bitOffset>10</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
<field>
<name>M_DONE</name>
<description>Master Done interrupt enable.</description>
@@ -29605,150 +29009,6 @@
</enumeratedValue>
</enumeratedValues>
</field>
- <field>
- <name>SR0A</name>
- <description>Slave Ready 0 Asserted interrupt enable.</description>
- <bitOffset>16</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR1A</name>
- <description>Slave Ready 1 Asserted interrupt enable.</description>
- <bitOffset>17</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR2A</name>
- <description>Slave Ready 2 Asserted interrupt enable.</description>
- <bitOffset>18</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR3A</name>
- <description>Slave Ready 3 Asserted interrupt enable.</description>
- <bitOffset>19</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR4A</name>
- <description>Slave Ready 4 Asserted interrupt enable.</description>
- <bitOffset>20</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR5A</name>
- <description>Slave Ready 5 Asserted interrupt enable.</description>
- <bitOffset>21</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR6A</name>
- <description>Slave Ready 6 Asserted interrupt enable.</description>
- <bitOffset>22</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
- <name>SR7A</name>
- <description>Slave Ready 7 Asserted interrupt enable.</description>
- <bitOffset>23</bitOffset>
- <bitWidth>1</bitWidth>
- <enumeratedValues>
- <enumeratedValue>
- <name>dis</name>
- <description>Interrupt is disabled.</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>en</name>
- <description>Interrupt is enabled.</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
</fields>
</register>
<register>
@@ -30122,6 +29382,12 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>IOSMPL</name>
+ <description>Sample Delay.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
</fields>
</register>
<register>
@@ -30346,6 +29612,54 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>SIMPLE</name>
+ <description>Simple Mode Enable.</description>
+ <bitOffset>20</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Dis</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>En</name>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SIMPLERX</name>
+ <description>Simple Receive Enable.</description>
+ <bitOffset>21</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Dis</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>En</name>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SMPLSS</name>
+ <description>Simple Mode Slave Select.</description>
+ <bitOffset>22</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Dis</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>En</name>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
<field>
<name>SCLK_FB</name>
<description>Enable SCLK Feedback Mode.</description>
@@ -30362,6 +29676,22 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>SCKFBINV</name>
+ <description>SCK Inversion.</description>
+ <bitOffset>25</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Dis</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>En</name>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
</fields>
</register>
<register>
@@ -30400,6 +29730,78 @@
<description>SPIX Controller Special Control Register.</description>
<addressOffset>0x10</addressOffset>
<fields>
+ <field>
+ <name>SAMPL</name>
+ <description>SDIO Sample Mode Enable.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>Dis</name>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>En</name>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SDIOOUT</name>
+ <description>SDIO Output Value Sample Mode.</description>
+ <bitOffset>4</bitOffset>
+ <bitWidth>4</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO0</name>
+ <description>SDIO[0]</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO1</name>
+ <description>SDIO[1]</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO2</name>
+ <description>SDIO[2]</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO3</name>
+ <description>SDIO[3]</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>SDIOOE</name>
+ <description>SDIO Output Enable Sample Mode.</description>
+ <bitOffset>8</bitOffset>
+ <bitWidth>4</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>SDIO0</name>
+ <description>SDIO[0]</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO1</name>
+ <description>SDIO[1]</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO2</name>
+ <description>SDIO[2]</description>
+ <value>2</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>SDIO3</name>
+ <description>SDIO[3]</description>
+ <value>3</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
<field>
<name>SCLKINH3</name>
<description>SCLK Inhibit Mode3. In SPI Mode 3, some SPI flash read timing diagrams show the last SCLK going low prior to de-assertion. The default is to support this additional falling edge of clock. When this bit is set and the device is in SPI Mode 3, the SPI clock is held high while Slave Select is de-asserted. This is to support some SPI flash write timing diagrams.</description>
@@ -30983,6 +30385,12 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>MODE_SEND</name>
+ <description>Mode Send.</description>
+ <bitOffset>9</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
</fields>
</register>
<register>
@@ -31166,6 +30574,37 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>AUTH_DISABLE</name>
+ <description>Integrity Enable.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>Integrity checking disabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>Integrity checking enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>BUS_IDLE</name>
+ <description>SPIXF Bus Idle Detection.</description>
+ <addressOffset>0x24</addressOffset>
+ <fields>
+ <field>
+ <name>BUSIDLE</name>
+ <description>Bus Idle Timer Limit.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
</fields>
</register>
</registers>
@@ -32388,6 +31827,158 @@
</interrupt>
</peripheral>
<!--SPI17Y2 SPI peripheral. 2-->
+ <peripheral>
+ <name>SRCC</name>
+ <description>External Memory Cache Controller Registers.</description>
+ <baseAddress>0x40033000</baseAddress>
+ <addressBlock>
+ <offset>0x00</offset>
+ <size>0x1000</size>
+ <usage>registers</usage>
+ </addressBlock>
+ <registers>
+ <register>
+ <name>CACHE_ID</name>
+ <description>Cache ID Register.</description>
+ <addressOffset>0x0000</addressOffset>
+ <access>read-only</access>
+ <fields>
+ <field>
+ <name>RELNUM</name>
+ <description>Release Number. Identifies the RTL release version.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ <field>
+ <name>PARTNUM</name>
+ <description>Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter.</description>
+ <bitOffset>6</bitOffset>
+ <bitWidth>4</bitWidth>
+ </field>
+ <field>
+ <name>CCHID</name>
+ <description>Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter.</description>
+ <bitOffset>10</bitOffset>
+ <bitWidth>6</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>MEMCFG</name>
+ <description>Memory Configuration Register.</description>
+ <addressOffset>0x0004</addressOffset>
+ <access>read-only</access>
+ <resetValue>0x00080008</resetValue>
+ <fields>
+ <field>
+ <name>CCHSZ</name>
+ <description>Cache Size. Indicates total size in Kbytes of cache.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ <field>
+ <name>MEMSZ</name>
+ <description>Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>16</bitWidth>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>CACHE_CTRL</name>
+ <description>Cache Control and Status Register.</description>
+ <addressOffset>0x0100</addressOffset>
+ <fields>
+ <field>
+ <name>CACHE_EN</name>
+ <description>Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>Cache Enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>WRITE_ALLOC_EN</name>
+ <description>Write Allocate Enable. This bit only writable while the cache is disabled.</description>
+ <bitOffset>1</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>Write-no-allocate.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>Write-allocate enabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CWFST_DIS</name>
+ <description>Critical word first and streaming disable. This bit only writeable while the cache is disabled.</description>
+ <bitOffset>2</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>dis</name>
+ <description>Critical word first and streaming disabled.</description>
+ <value>1</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>en</name>
+ <description>Critical word first and streaming enabled.</description>
+ <value>0</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ <field>
+ <name>CACHE_RDY</name>
+ <description>Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready.</description>
+ <bitOffset>16</bitOffset>
+ <bitWidth>1</bitWidth>
+ <enumeratedValues>
+ <enumeratedValue>
+ <name>notReady</name>
+ <description>Not Ready.</description>
+ <value>0</value>
+ </enumeratedValue>
+ <enumeratedValue>
+ <name>ready</name>
+ <description>Ready.</description>
+ <value>1</value>
+ </enumeratedValue>
+ </enumeratedValues>
+ </field>
+ </fields>
+ </register>
+ <register>
+ <name>INVALIDATE</name>
+ <description>Invalidate All Cache Contents. Any time this register location is written (regardless of the data value), the cache controller immediately begins invalidating the entire contents of the cache memory. The cache will be in bypass mode until the invalidate operation is complete. System software can examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the invalidate operation is complete. Note that it is not necessary to disable the cache controller prior to beginning this operation. Reads from this register always return 0.</description>
+ <addressOffset>0x0700</addressOffset>
+ <fields>
+ <field>
+ <name>IA</name>
+ <description>Invalidate all cache contents.</description>
+ <bitOffset>0</bitOffset>
+ <bitWidth>32</bitWidth>
+ </field>
+ </fields>
+ </register>
+ </registers>
+ </peripheral>
+<!--SRCC External Memory Cache Controller Registers.-->
<peripheral>
<name>TMR0</name>
<description>32-bit reloadable timer that can be used for timing and event counting.</description>
@@ -33539,7 +33130,7 @@
<size>32</size>
<fields>
<field>
- <name>TDMA_EN</name>
+ <name>TXDMA_EN</name>
<description>TX DMA channel enable.</description>
<bitOffset>0</bitOffset>
<bitWidth>1</bitWidth>
@@ -33574,6 +33165,18 @@
</enumeratedValue>
</enumeratedValues>
</field>
+ <field>
+ <name>RXDMA_START</name>
+ <description>RX DMA Start.</description>
+ <bitOffset>3</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
+ <field>
+ <name>RXDMA_AUTO_TO</name>
+ <description>RX DMA Timeout Start.</description>
+ <bitOffset>5</bitOffset>
+ <bitWidth>1</bitWidth>
+ </field>
<field>
<name>TXDMA_LEVEL</name>
<description>TX threshold for DMA transmission.</description>
@@ -35129,7 +34732,7 @@
<size>16</size>
<fields>
<field>
- <name>C_T_HSTRN</name>
+ <name>C_T_HSRTN</name>
<description>High Speed Resume Delay Clock Cycles. This configures the delay from when the RESUME state on the bus ends, the when the USBHS resumes normal operation.</description>
<bitOffset>0</bitOffset>
<bitWidth>16</bitWidth>
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h
index efabd1eea28e17bdf8e64eecff2ee419d78b52e1..4dc8875ae474db35e650a09c085e3354723ce5ff 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/mcr_regs.h
@@ -87,7 +87,7 @@ extern "C" {
*/
typedef struct {
__IO uint32_t eccen; /**< <tt>\b 0x00:</tt> MCR ECCEN Register */
- __IO uint32_t hirc96m; /**< <tt>\b 0x04:</tt> MCR HIRC96M Register */
+ __R uint32_t rsv_0x4;
__IO uint32_t outen; /**< <tt>\b 0x08:</tt> MCR OUTEN Register */
__IO uint32_t aincomp; /**< <tt>\b 0x0C:</tt> MCR AINCOMP Register */
__IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> MCR CTRL Register */
@@ -101,7 +101,6 @@ typedef struct {
* @{
*/
#define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: <tt> 0x0000</tt> */
- #define MXC_R_MCR_HIRC96M ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: <tt> 0x0004</tt> */
#define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: <tt> 0x0008</tt> */
#define MXC_R_MCR_AINCOMP ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: <tt> 0x000C</tt> */
#define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: <tt> 0x0010</tt> */
@@ -148,17 +147,6 @@ typedef struct {
/**@} end of group MCR_ECCEN_Register */
-/**
- * @ingroup mcr_registers
- * @defgroup MCR_HIRC96M MCR_HIRC96M
- * @brief 96MHz Oscillator Trim Register
- * @{
- */
- #define MXC_F_MCR_HIRC96M_HIRC96MTR_POS 0 /**< HIRC96M_HIRC96MTR Position */
- #define MXC_F_MCR_HIRC96M_HIRC96MTR ((uint32_t)(0xFFUL << MXC_F_MCR_HIRC96M_HIRC96MTR_POS)) /**< HIRC96M_HIRC96MTR Mask */
-
-/**@} end of group MCR_HIRC96M_Register */
-
/**
* @ingroup mcr_registers
* @defgroup MCR_OUTEN MCR_OUTEN
@@ -223,8 +211,8 @@ typedef struct {
#define MXC_F_MCR_CTRL_P1M_POS 9 /**< CTRL_P1M Position */
#define MXC_F_MCR_CTRL_P1M ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_P1M_POS)) /**< CTRL_P1M Mask */
- #define MXC_F_MCR_CTRL_VDDIOH_SEL_POS 10 /**< CTRL_VDDIOH_SEL Position */
- #define MXC_F_MCR_CTRL_VDDIOH_SEL ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_VDDIOH_SEL_POS)) /**< CTRL_VDDIOH_SEL Mask */
+ #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS 10 /**< CTRL_RSTN_VOLTAGE_SEL Position */
+ #define MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_RSTN_VOLTAGE_SEL_POS)) /**< CTRL_RSTN_VOLTAGE_SEL Mask */
/**@} end of group MCR_CTRL_Register */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h
index f59c75f9c53872d24af14f43643e1baad7f0c7c4..2455763d0e29059148233cbe1603bc0ccd8223d7 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/owm_regs.h
@@ -170,6 +170,9 @@ typedef struct {
#define MXC_F_OWM_CTRL_STAT_OW_INPUT_POS 3 /**< CTRL_STAT_OW_INPUT Position */
#define MXC_F_OWM_CTRL_STAT_OW_INPUT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OW_INPUT_POS)) /**< CTRL_STAT_OW_INPUT Mask */
+ #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS 4 /**< CTRL_STAT_OD_SPEC_MODE Position */
+ #define MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_OD_SPEC_MODE_POS)) /**< CTRL_STAT_OD_SPEC_MODE Mask */
+
#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS 7 /**< CTRL_STAT_PRESENCE_DETECT Position */
#define MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT ((uint32_t)(0x1UL << MXC_F_OWM_CTRL_STAT_PRESENCE_DETECT_POS)) /**< CTRL_STAT_PRESENCE_DETECT Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h
index cc31a65b3a6e1d79028109fa479d69c6bafac1d1..4a1ea733f930c8d35c24852a2b1307044fbe6dd8 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/pwrseq_regs.h
@@ -91,20 +91,14 @@ typedef struct {
__IO uint32_t lpwken0; /**< <tt>\b 0x08:</tt> PWRSEQ LPWKEN0 Register */
__IO uint32_t lpwkst1; /**< <tt>\b 0x0C:</tt> PWRSEQ LPWKST1 Register */
__IO uint32_t lpwken1; /**< <tt>\b 0x10:</tt> PWRSEQ LPWKEN1 Register */
- __IO uint32_t lpwkst2; /**< <tt>\b 0x14:</tt> PWRSEQ LPWKST2 Register */
- __IO uint32_t lpwken2; /**< <tt>\b 0x18:</tt> PWRSEQ LPWKEN2 Register */
- __IO uint32_t lpwkst3; /**< <tt>\b 0x1C:</tt> PWRSEQ LPWKST3 Register */
- __IO uint32_t lpwken3; /**< <tt>\b 0x20:</tt> PWRSEQ LPWKEN3 Register */
- __R uint32_t rsv_0x24_0x2f[3];
+ __R uint32_t rsv_0x14_0x2f[7];
__IO uint32_t lppwst; /**< <tt>\b 0x30:</tt> PWRSEQ LPPWST Register */
__IO uint32_t lppwen; /**< <tt>\b 0x34:</tt> PWRSEQ LPPWEN Register */
__R uint32_t rsv_0x38_0x3f[2];
__IO uint32_t lpmemsd; /**< <tt>\b 0x40:</tt> PWRSEQ LPMEMSD Register */
__IO uint32_t lpvddpd; /**< <tt>\b 0x44:</tt> PWRSEQ LPVDDPD Register */
- __IO uint32_t gp0; /**< <tt>\b 0x48:</tt> PWRSEQ GP0 Register */
- __IO uint32_t gp1; /**< <tt>\b 0x4C:</tt> PWRSEQ GP1 Register */
- __IO uint32_t lpmcstat; /**< <tt>\b 0x50:</tt> PWRSEQ LPMCSTAT Register */
- __IO uint32_t lpmcreq; /**< <tt>\b 0x54:</tt> PWRSEQ LPMCREQ Register */
+ __IO uint32_t buretvec; /**< <tt>\b 0x48:</tt> PWRSEQ BURETVEC Register */
+ __IO uint32_t buaod; /**< <tt>\b 0x4C:</tt> PWRSEQ BUAOD Register */
} mxc_pwrseq_regs_t;
/* Register offsets for module PWRSEQ */
@@ -119,18 +113,12 @@ typedef struct {
#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0008</tt> */
#define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x000C</tt> */
#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0010</tt> */
- #define MXC_R_PWRSEQ_LPWKST2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0014</tt> */
- #define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0018</tt> */
- #define MXC_R_PWRSEQ_LPWKST3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x001C</tt> */
- #define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0020</tt> */
#define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0030</tt> */
#define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0034</tt> */
#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0040</tt> */
#define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0044</tt> */
- #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */
- #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */
- #define MXC_R_PWRSEQ_LPMCSTAT ((uint32_t)0x00000050UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0050</tt> */
- #define MXC_R_PWRSEQ_LPMCREQ ((uint32_t)0x00000054UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0054</tt> */
+ #define MXC_R_PWRSEQ_BURETVEC ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: <tt> 0x0048</tt> */
+ #define MXC_R_PWRSEQ_BUAOD ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: <tt> 0x004C</tt> */
/**@} end of group pwrseq_registers */
/**
@@ -150,24 +138,9 @@ typedef struct {
#define MXC_V_PWRSEQ_LPCN_RAMRET_EN3 ((uint32_t)0x3UL) /**< LPCN_RAMRET_EN3 Value */
#define MXC_S_PWRSEQ_LPCN_RAMRET_EN3 (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) /**< LPCN_RAMRET_EN3 Setting */
- #define MXC_F_PWRSEQ_LPCN_OVR_POS 4 /**< LPCN_OVR Position */
- #define MXC_F_PWRSEQ_LPCN_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_OVR_POS)) /**< LPCN_OVR Mask */
- #define MXC_V_PWRSEQ_LPCN_OVR_0_9V ((uint32_t)0x0UL) /**< LPCN_OVR_0_9V Value */
- #define MXC_S_PWRSEQ_LPCN_OVR_0_9V (MXC_V_PWRSEQ_LPCN_OVR_0_9V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_0_9V Setting */
- #define MXC_V_PWRSEQ_LPCN_OVR_1_0V ((uint32_t)0x1UL) /**< LPCN_OVR_1_0V Value */
- #define MXC_S_PWRSEQ_LPCN_OVR_1_0V (MXC_V_PWRSEQ_LPCN_OVR_1_0V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_0V Setting */
- #define MXC_V_PWRSEQ_LPCN_OVR_1_1V ((uint32_t)0x2UL) /**< LPCN_OVR_1_1V Value */
- #define MXC_S_PWRSEQ_LPCN_OVR_1_1V (MXC_V_PWRSEQ_LPCN_OVR_1_1V << MXC_F_PWRSEQ_LPCN_OVR_POS) /**< LPCN_OVR_1_1V Setting */
-
#define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6 /**< LPCN_BLKDET Position */
#define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS)) /**< LPCN_BLKDET Mask */
- #define MXC_F_PWRSEQ_LPCN_FVDDEN_POS 7 /**< LPCN_FVDDEN Position */
- #define MXC_F_PWRSEQ_LPCN_FVDDEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FVDDEN_POS)) /**< LPCN_FVDDEN Mask */
-
- #define MXC_F_PWRSEQ_LPCN_RREGEN_POS 8 /**< LPCN_RREGEN Position */
- #define MXC_F_PWRSEQ_LPCN_RREGEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_RREGEN_POS)) /**< LPCN_RREGEN Mask */
-
#define MXC_F_PWRSEQ_LPCN_BCKGRND_POS 9 /**< LPCN_BCKGRND Position */
#define MXC_F_PWRSEQ_LPCN_BCKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) /**< LPCN_BCKGRND Mask */
@@ -177,11 +150,11 @@ typedef struct {
#define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 /**< LPCN_BGOFF Position */
#define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) /**< LPCN_BGOFF Mask */
- #define MXC_F_PWRSEQ_LPCN_VDDCMD_POS 20 /**< LPCN_VDDCMD Position */
- #define MXC_F_PWRSEQ_LPCN_VDDCMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDCMD_POS)) /**< LPCN_VDDCMD Mask */
+ #define MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20 /**< LPCN_VCOREMD Position */
+ #define MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) /**< LPCN_VCOREMD Mask */
- #define MXC_F_PWRSEQ_LPCN_VRTCMD_POS 21 /**< LPCN_VRTCMD Position */
- #define MXC_F_PWRSEQ_LPCN_VRTCMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRTCMD_POS)) /**< LPCN_VRTCMD Mask */
+ #define MXC_F_PWRSEQ_LPCN_VREGIMD_POS 21 /**< LPCN_VREGIMD Position */
+ #define MXC_F_PWRSEQ_LPCN_VREGIMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS)) /**< LPCN_VREGIMD Mask */
#define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22 /**< LPCN_VDDAMD Position */
#define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) /**< LPCN_VDDAMD Mask */
@@ -201,6 +174,15 @@ typedef struct {
#define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27 /**< LPCN_VDDBMD Position */
#define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) /**< LPCN_VDDBMD Mask */
+ #define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS 28 /**< LPCN_VRXOUTMD Position */
+ #define MXC_F_PWRSEQ_LPCN_VRXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS)) /**< LPCN_VRXOUTMD Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS 29 /**< LPCN_VTXOUTMD Position */
+ #define MXC_F_PWRSEQ_LPCN_VTXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS)) /**< LPCN_VTXOUTMD Mask */
+
+ #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS 30 /**< LPCN_PDOWNDSLEN Position */
+ #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS)) /**< LPCN_PDOWNDSLEN Mask */
+
/**@} end of group PWRSEQ_LPCN_Register */
/**
@@ -227,6 +209,30 @@ typedef struct {
/**@} end of group PWRSEQ_LPWKEN0_Register */
+/**
+ * @ingroup pwrseq_registers
+ * @defgroup PWRSEQ_LPWKST1 PWRSEQ_LPWKST1
+ * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power
+ * wakeup status for GPIO1.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS 0 /**< LPWKST1_WAKEST Position */
+ #define MXC_F_PWRSEQ_LPWKST1_WAKEST ((uint32_t)(0x3FFFFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) /**< LPWKST1_WAKEST Mask */
+
+/**@} end of group PWRSEQ_LPWKST1_Register */
+
+/**
+ * @ingroup pwrseq_registers
+ * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1
+ * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup
+ * functionality for GPIO1.
+ * @{
+ */
+ #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS 0 /**< LPWKEN1_WAKEEN Position */
+ #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) /**< LPWKEN1_WAKEEN Mask */
+
+/**@} end of group PWRSEQ_LPWKEN1_Register */
+
/**
* @ingroup pwrseq_registers
* @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST
@@ -242,9 +248,36 @@ typedef struct {
#define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS 3 /**< LPPWST_SDMAWKST Position */
#define MXC_F_PWRSEQ_LPPWST_SDMAWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) /**< LPPWST_SDMAWKST Mask */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS 4 /**< LPPWST_AINCOMP0WKST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS)) /**< LPPWST_AINCOMP0WKST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS 5 /**< LPPWST_AINCOMP1WKST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS)) /**< LPPWST_AINCOMP1WKST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS 6 /**< LPPWST_AINCOMP2WKST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS)) /**< LPPWST_AINCOMP2WKST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS 7 /**< LPPWST_AINCOMP3WKST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS)) /**< LPPWST_AINCOMP3WKST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS 8 /**< LPPWST_AINCOMP0ST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS)) /**< LPPWST_AINCOMP0ST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS 9 /**< LPPWST_AINCOMP1ST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS)) /**< LPPWST_AINCOMP1ST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS 10 /**< LPPWST_AINCOMP2ST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS)) /**< LPPWST_AINCOMP2ST Mask */
+
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS 11 /**< LPPWST_AINCOMP3ST Position */
+ #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS)) /**< LPPWST_AINCOMP3ST Mask */
+
#define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS 16 /**< LPPWST_BBMODEST Position */
#define MXC_F_PWRSEQ_LPPWST_BBMODEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) /**< LPPWST_BBMODEST Mask */
+ #define MXC_F_PWRSEQ_LPPWST_RSTWKST_POS 17 /**< LPPWST_RSTWKST Position */
+ #define MXC_F_PWRSEQ_LPPWST_RSTWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RSTWKST_POS)) /**< LPPWST_RSTWKST Mask */
+
/**@} end of group PWRSEQ_LPPWST_Register */
/**
@@ -262,6 +295,18 @@ typedef struct {
#define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS 3 /**< LPPWEN_SDMAWKEN Position */
#define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) /**< LPPWEN_SDMAWKEN Mask */
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS 4 /**< LPPWEN_AINCOMP0WKEN Position */
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS)) /**< LPPWEN_AINCOMP0WKEN Mask */
+
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS 5 /**< LPPWEN_AINCOMP1WKEN Position */
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS)) /**< LPPWEN_AINCOMP1WKEN Mask */
+
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS 6 /**< LPPWEN_AINCOMP2WKEN Position */
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS)) /**< LPPWEN_AINCOMP2WKEN Mask */
+
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS 7 /**< LPPWEN_AINCOMP3WKEN Position */
+ #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS)) /**< LPPWEN_AINCOMP3WKEN Mask */
+
/**@} end of group PWRSEQ_LPPWEN_Register */
/**
@@ -288,17 +333,14 @@ typedef struct {
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS 5 /**< LPMEMSD_SRAM5SD Position */
#define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) /**< LPMEMSD_SRAM5SD Mask */
- #define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS 6 /**< LPMEMSD_SRAM6SD Position */
- #define MXC_F_PWRSEQ_LPMEMSD_SRAM6SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM6SD_POS)) /**< LPMEMSD_SRAM6SD Mask */
-
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS 7 /**< LPMEMSD_ICACHESD Position */
#define MXC_F_PWRSEQ_LPMEMSD_ICACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) /**< LPMEMSD_ICACHESD Mask */
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS 8 /**< LPMEMSD_ICACHEXIPSD Position */
#define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) /**< LPMEMSD_ICACHEXIPSD Mask */
- #define MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS 9 /**< LPMEMSD_SCACHESD Position */
- #define MXC_F_PWRSEQ_LPMEMSD_SCACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SCACHESD_POS)) /**< LPMEMSD_SCACHESD Mask */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS 9 /**< LPMEMSD_SRCCSD Position */
+ #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS)) /**< LPMEMSD_SRCCSD Mask */
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS 10 /**< LPMEMSD_CRYPTOSD Position */
#define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) /**< LPMEMSD_CRYPTOSD Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h
index bb2fdd2375ca7ecc8a3fdc65c967b1bc2c518d64..bc0edf02a220065629368683dacdaad216ee596d 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rpu_regs.h
@@ -104,7 +104,7 @@ typedef struct {
__IO uint32_t rtc; /**< <tt>\b 0x0060:</tt> RPU RTC Register */
__IO uint32_t wut; /**< <tt>\b 0x0064:</tt> RPU WUT Register */
__IO uint32_t pwrseq; /**< <tt>\b 0x0068:</tt> RPU PWRSEQ Register */
- __IO uint32_t bbcr; /**< <tt>\b 0x006C:</tt> RPU BBCR Register */
+ __IO uint32_t mcr; /**< <tt>\b 0x006C:</tt> RPU MCR Register */
__R uint32_t rsv_0x70_0x7f[4];
__IO uint32_t gpio0; /**< <tt>\b 0x0080:</tt> RPU GPIO0 Register */
__R uint32_t rsv_0x84_0x8f[3];
@@ -126,27 +126,27 @@ typedef struct {
__R uint32_t rsv_0x1b4_0x1bf[3];
__IO uint32_t htimer1; /**< <tt>\b 0x01C0:</tt> RPU HTIMER1 Register */
__R uint32_t rsv_0x1c4_0x1cf[3];
- __IO uint32_t i2c0; /**< <tt>\b 0x01D0:</tt> RPU I2C0 Register */
+ __IO uint32_t i2c0_bus0; /**< <tt>\b 0x01D0:</tt> RPU I2C0_BUS0 Register */
__R uint32_t rsv_0x1d4_0x1df[3];
- __IO uint32_t i2c1; /**< <tt>\b 0x01E0:</tt> RPU I2C1 Register */
+ __IO uint32_t i2c1_bus0; /**< <tt>\b 0x01E0:</tt> RPU I2C1_BUS0 Register */
__R uint32_t rsv_0x1e4_0x1ef[3];
- __IO uint32_t i2c2; /**< <tt>\b 0x01F0:</tt> RPU I2C2 Register */
+ __IO uint32_t i2c2_bus0; /**< <tt>\b 0x01F0:</tt> RPU I2C2_BUS0 Register */
__R uint32_t rsv_0x1f4_0x25f[27];
- __IO uint32_t spixipm; /**< <tt>\b 0x0260:</tt> RPU SPIXIPM Register */
+ __IO uint32_t spixfm; /**< <tt>\b 0x0260:</tt> RPU SPIXFM Register */
__R uint32_t rsv_0x264_0x26f[3];
- __IO uint32_t spixipmc; /**< <tt>\b 0x0270:</tt> RPU SPIXIPMC Register */
+ __IO uint32_t spixfc; /**< <tt>\b 0x0270:</tt> RPU SPIXFC Register */
__R uint32_t rsv_0x274_0x27f[3];
__IO uint32_t dma0; /**< <tt>\b 0x0280:</tt> RPU DMA0 Register */
__R uint32_t rsv_0x284_0x28f[3];
__IO uint32_t flc0; /**< <tt>\b 0x0290:</tt> RPU FLC0 Register */
__IO uint32_t flc1; /**< <tt>\b 0x0294:</tt> RPU FLC1 Register */
__R uint32_t rsv_0x298_0x29f[2];
- __IO uint32_t icache0; /**< <tt>\b 0x02A0:</tt> RPU ICACHE0 Register */
- __IO uint32_t icache1; /**< <tt>\b 0x02A4:</tt> RPU ICACHE1 Register */
+ __IO uint32_t icc0; /**< <tt>\b 0x02A0:</tt> RPU ICC0 Register */
+ __IO uint32_t icc1; /**< <tt>\b 0x02A4:</tt> RPU ICC1 Register */
__R uint32_t rsv_0x2a8_0x2ef[18];
- __IO uint32_t icachexip; /**< <tt>\b 0x02F0:</tt> RPU ICACHEXIP Register */
+ __IO uint32_t sfcc; /**< <tt>\b 0x02F0:</tt> RPU SFCC Register */
__R uint32_t rsv_0x2f4_0x32f[15];
- __IO uint32_t dcache; /**< <tt>\b 0x0330:</tt> RPU DCACHE Register */
+ __IO uint32_t srcc; /**< <tt>\b 0x0330:</tt> RPU SRCC Register */
__R uint32_t rsv_0x334_0x33f[3];
__IO uint32_t adc; /**< <tt>\b 0x0340:</tt> RPU ADC Register */
__R uint32_t rsv_0x344_0x34f[3];
@@ -156,9 +156,9 @@ typedef struct {
__R uint32_t rsv_0x364_0x36f[3];
__IO uint32_t sdhcctrl; /**< <tt>\b 0x0370:</tt> RPU SDHCCTRL Register */
__R uint32_t rsv_0x374_0x39f[11];
- __IO uint32_t spid; /**< <tt>\b 0x03A0:</tt> RPU SPID Register */
+ __IO uint32_t spixr; /**< <tt>\b 0x03A0:</tt> RPU SPIXR Register */
__R uint32_t rsv_0x3a4_0x3bf[7];
- __IO uint32_t pt; /**< <tt>\b 0x03C0:</tt> RPU PT Register */
+ __IO uint32_t ptg_bus0; /**< <tt>\b 0x03C0:</tt> RPU PTG_BUS0 Register */
__R uint32_t rsv_0x3c4_0x3cf[3];
__IO uint32_t owm; /**< <tt>\b 0x03D0:</tt> RPU OWM Register */
__R uint32_t rsv_0x3d4_0x3df[3];
@@ -170,9 +170,9 @@ typedef struct {
__R uint32_t rsv_0x434_0x43f[3];
__IO uint32_t uart2; /**< <tt>\b 0x0440:</tt> RPU UART2 Register */
__R uint32_t rsv_0x444_0x45f[7];
- __IO uint32_t qspi1; /**< <tt>\b 0x0460:</tt> RPU QSPI1 Register */
+ __IO uint32_t spi1; /**< <tt>\b 0x0460:</tt> RPU SPI1 Register */
__R uint32_t rsv_0x464_0x47f[7];
- __IO uint32_t qspi2; /**< <tt>\b 0x0480:</tt> RPU QSPI2 Register */
+ __IO uint32_t spi2; /**< <tt>\b 0x0480:</tt> RPU SPI2 Register */
__R uint32_t rsv_0x484_0x4bf[15];
__IO uint32_t audio; /**< <tt>\b 0x04C0:</tt> RPU AUDIO Register */
__R uint32_t rsv_0x4c4_0x4cf[3];
@@ -184,23 +184,23 @@ typedef struct {
__R uint32_t rsv_0xb14_0xb5f[19];
__IO uint32_t sdio; /**< <tt>\b 0x0B60:</tt> RPU SDIO Register */
__R uint32_t rsv_0xb64_0xbbf[23];
- __IO uint32_t spixipmfifo; /**< <tt>\b 0x0BC0:</tt> RPU SPIXIPMFIFO Register */
+ __IO uint32_t spixm_fifo; /**< <tt>\b 0x0BC0:</tt> RPU SPIXM_FIFO Register */
__R uint32_t rsv_0xbc4_0xbdf[7];
- __IO uint32_t qspi0; /**< <tt>\b 0x0BE0:</tt> RPU QSPI0 Register */
+ __IO uint32_t spi0; /**< <tt>\b 0x0BE0:</tt> RPU SPI0 Register */
__R uint32_t rsv_0xbe4_0xeff[199];
- __IO uint32_t sram0; /**< <tt>\b 0x0F00:</tt> RPU SRAM0 Register */
+ __IO uint32_t sysram0; /**< <tt>\b 0x0F00:</tt> RPU SYSRAM0 Register */
__R uint32_t rsv_0xf04_0xf0f[3];
- __IO uint32_t sram1; /**< <tt>\b 0x0F10:</tt> RPU SRAM1 Register */
+ __IO uint32_t sysram1; /**< <tt>\b 0x0F10:</tt> RPU SYSRAM1 Register */
__R uint32_t rsv_0xf14_0xf1f[3];
- __IO uint32_t sram2; /**< <tt>\b 0x0F20:</tt> RPU SRAM2 Register */
+ __IO uint32_t sysram2; /**< <tt>\b 0x0F20:</tt> RPU SYSRAM2 Register */
__R uint32_t rsv_0xf24_0xf2f[3];
- __IO uint32_t sram3; /**< <tt>\b 0x0F30:</tt> RPU SRAM3 Register */
+ __IO uint32_t sysram3; /**< <tt>\b 0x0F30:</tt> RPU SYSRAM3 Register */
__R uint32_t rsv_0xf34_0xf3f[3];
- __IO uint32_t sram4; /**< <tt>\b 0x0F40:</tt> RPU SRAM4 Register */
+ __IO uint32_t sysram4; /**< <tt>\b 0x0F40:</tt> RPU SYSRAM4 Register */
__R uint32_t rsv_0xf44_0xf4f[3];
- __IO uint32_t sram5; /**< <tt>\b 0x0F50:</tt> RPU SRAM5 Register */
+ __IO uint32_t sysram5; /**< <tt>\b 0x0F50:</tt> RPU SYSRAM5 Register */
__R uint32_t rsv_0xf54_0xf5f[3];
- __IO uint32_t sram6; /**< <tt>\b 0x0F60:</tt> RPU SRAM6 Register */
+ __IO uint32_t sysram6; /**< <tt>\b 0x0F60:</tt> RPU SYSRAM6 Register */
} mxc_rpu_regs_t;
/* Register offsets for module RPU */
@@ -224,7 +224,7 @@ typedef struct {
#define MXC_R_RPU_RTC ((uint32_t)0x00000060UL) /**< Offset from RPU Base Address: <tt> 0x0060</tt> */
#define MXC_R_RPU_WUT ((uint32_t)0x00000064UL) /**< Offset from RPU Base Address: <tt> 0x0064</tt> */
#define MXC_R_RPU_PWRSEQ ((uint32_t)0x00000068UL) /**< Offset from RPU Base Address: <tt> 0x0068</tt> */
- #define MXC_R_RPU_BBCR ((uint32_t)0x0000006CUL) /**< Offset from RPU Base Address: <tt> 0x006C</tt> */
+ #define MXC_R_RPU_MCR ((uint32_t)0x0000006CUL) /**< Offset from RPU Base Address: <tt> 0x006C</tt> */
#define MXC_R_RPU_GPIO0 ((uint32_t)0x00000080UL) /**< Offset from RPU Base Address: <tt> 0x0080</tt> */
#define MXC_R_RPU_GPIO1 ((uint32_t)0x00000090UL) /**< Offset from RPU Base Address: <tt> 0x0090</tt> */
#define MXC_R_RPU_TMR0 ((uint32_t)0x00000100UL) /**< Offset from RPU Base Address: <tt> 0x0100</tt> */
@@ -235,45 +235,45 @@ typedef struct {
#define MXC_R_RPU_TMR5 ((uint32_t)0x00000150UL) /**< Offset from RPU Base Address: <tt> 0x0150</tt> */
#define MXC_R_RPU_HTIMER0 ((uint32_t)0x000001B0UL) /**< Offset from RPU Base Address: <tt> 0x01B0</tt> */
#define MXC_R_RPU_HTIMER1 ((uint32_t)0x000001C0UL) /**< Offset from RPU Base Address: <tt> 0x01C0</tt> */
- #define MXC_R_RPU_I2C0 ((uint32_t)0x000001D0UL) /**< Offset from RPU Base Address: <tt> 0x01D0</tt> */
- #define MXC_R_RPU_I2C1 ((uint32_t)0x000001E0UL) /**< Offset from RPU Base Address: <tt> 0x01E0</tt> */
- #define MXC_R_RPU_I2C2 ((uint32_t)0x000001F0UL) /**< Offset from RPU Base Address: <tt> 0x01F0</tt> */
- #define MXC_R_RPU_SPIXIPM ((uint32_t)0x00000260UL) /**< Offset from RPU Base Address: <tt> 0x0260</tt> */
- #define MXC_R_RPU_SPIXIPMC ((uint32_t)0x00000270UL) /**< Offset from RPU Base Address: <tt> 0x0270</tt> */
+ #define MXC_R_RPU_I2C0_BUS0 ((uint32_t)0x000001D0UL) /**< Offset from RPU Base Address: <tt> 0x01D0</tt> */
+ #define MXC_R_RPU_I2C1_BUS0 ((uint32_t)0x000001E0UL) /**< Offset from RPU Base Address: <tt> 0x01E0</tt> */
+ #define MXC_R_RPU_I2C2_BUS0 ((uint32_t)0x000001F0UL) /**< Offset from RPU Base Address: <tt> 0x01F0</tt> */
+ #define MXC_R_RPU_SPIXFM ((uint32_t)0x00000260UL) /**< Offset from RPU Base Address: <tt> 0x0260</tt> */
+ #define MXC_R_RPU_SPIXFC ((uint32_t)0x00000270UL) /**< Offset from RPU Base Address: <tt> 0x0270</tt> */
#define MXC_R_RPU_DMA0 ((uint32_t)0x00000280UL) /**< Offset from RPU Base Address: <tt> 0x0280</tt> */
#define MXC_R_RPU_FLC0 ((uint32_t)0x00000290UL) /**< Offset from RPU Base Address: <tt> 0x0290</tt> */
#define MXC_R_RPU_FLC1 ((uint32_t)0x00000294UL) /**< Offset from RPU Base Address: <tt> 0x0294</tt> */
- #define MXC_R_RPU_ICACHE0 ((uint32_t)0x000002A0UL) /**< Offset from RPU Base Address: <tt> 0x02A0</tt> */
- #define MXC_R_RPU_ICACHE1 ((uint32_t)0x000002A4UL) /**< Offset from RPU Base Address: <tt> 0x02A4</tt> */
- #define MXC_R_RPU_ICACHEXIP ((uint32_t)0x000002F0UL) /**< Offset from RPU Base Address: <tt> 0x02F0</tt> */
- #define MXC_R_RPU_DCACHE ((uint32_t)0x00000330UL) /**< Offset from RPU Base Address: <tt> 0x0330</tt> */
+ #define MXC_R_RPU_ICC0 ((uint32_t)0x000002A0UL) /**< Offset from RPU Base Address: <tt> 0x02A0</tt> */
+ #define MXC_R_RPU_ICC1 ((uint32_t)0x000002A4UL) /**< Offset from RPU Base Address: <tt> 0x02A4</tt> */
+ #define MXC_R_RPU_SFCC ((uint32_t)0x000002F0UL) /**< Offset from RPU Base Address: <tt> 0x02F0</tt> */
+ #define MXC_R_RPU_SRCC ((uint32_t)0x00000330UL) /**< Offset from RPU Base Address: <tt> 0x0330</tt> */
#define MXC_R_RPU_ADC ((uint32_t)0x00000340UL) /**< Offset from RPU Base Address: <tt> 0x0340</tt> */
#define MXC_R_RPU_DMA1 ((uint32_t)0x00000350UL) /**< Offset from RPU Base Address: <tt> 0x0350</tt> */
#define MXC_R_RPU_SDMA ((uint32_t)0x00000360UL) /**< Offset from RPU Base Address: <tt> 0x0360</tt> */
#define MXC_R_RPU_SDHCCTRL ((uint32_t)0x00000370UL) /**< Offset from RPU Base Address: <tt> 0x0370</tt> */
- #define MXC_R_RPU_SPID ((uint32_t)0x000003A0UL) /**< Offset from RPU Base Address: <tt> 0x03A0</tt> */
- #define MXC_R_RPU_PT ((uint32_t)0x000003C0UL) /**< Offset from RPU Base Address: <tt> 0x03C0</tt> */
+ #define MXC_R_RPU_SPIXR ((uint32_t)0x000003A0UL) /**< Offset from RPU Base Address: <tt> 0x03A0</tt> */
+ #define MXC_R_RPU_PTG_BUS0 ((uint32_t)0x000003C0UL) /**< Offset from RPU Base Address: <tt> 0x03C0</tt> */
#define MXC_R_RPU_OWM ((uint32_t)0x000003D0UL) /**< Offset from RPU Base Address: <tt> 0x03D0</tt> */
#define MXC_R_RPU_SEMA ((uint32_t)0x000003E0UL) /**< Offset from RPU Base Address: <tt> 0x03E0</tt> */
#define MXC_R_RPU_UART0 ((uint32_t)0x00000420UL) /**< Offset from RPU Base Address: <tt> 0x0420</tt> */
#define MXC_R_RPU_UART1 ((uint32_t)0x00000430UL) /**< Offset from RPU Base Address: <tt> 0x0430</tt> */
#define MXC_R_RPU_UART2 ((uint32_t)0x00000440UL) /**< Offset from RPU Base Address: <tt> 0x0440</tt> */
- #define MXC_R_RPU_QSPI1 ((uint32_t)0x00000460UL) /**< Offset from RPU Base Address: <tt> 0x0460</tt> */
- #define MXC_R_RPU_QSPI2 ((uint32_t)0x00000480UL) /**< Offset from RPU Base Address: <tt> 0x0480</tt> */
+ #define MXC_R_RPU_SPI1 ((uint32_t)0x00000460UL) /**< Offset from RPU Base Address: <tt> 0x0460</tt> */
+ #define MXC_R_RPU_SPI2 ((uint32_t)0x00000480UL) /**< Offset from RPU Base Address: <tt> 0x0480</tt> */
#define MXC_R_RPU_AUDIO ((uint32_t)0x000004C0UL) /**< Offset from RPU Base Address: <tt> 0x04C0</tt> */
#define MXC_R_RPU_TRNG ((uint32_t)0x000004D0UL) /**< Offset from RPU Base Address: <tt> 0x04D0</tt> */
#define MXC_R_RPU_BTLE ((uint32_t)0x00000500UL) /**< Offset from RPU Base Address: <tt> 0x0500</tt> */
#define MXC_R_RPU_USBHS ((uint32_t)0x00000B10UL) /**< Offset from RPU Base Address: <tt> 0x0B10</tt> */
#define MXC_R_RPU_SDIO ((uint32_t)0x00000B60UL) /**< Offset from RPU Base Address: <tt> 0x0B60</tt> */
- #define MXC_R_RPU_SPIXIPMFIFO ((uint32_t)0x00000BC0UL) /**< Offset from RPU Base Address: <tt> 0x0BC0</tt> */
- #define MXC_R_RPU_QSPI0 ((uint32_t)0x00000BE0UL) /**< Offset from RPU Base Address: <tt> 0x0BE0</tt> */
- #define MXC_R_RPU_SRAM0 ((uint32_t)0x00000F00UL) /**< Offset from RPU Base Address: <tt> 0x0F00</tt> */
- #define MXC_R_RPU_SRAM1 ((uint32_t)0x00000F10UL) /**< Offset from RPU Base Address: <tt> 0x0F10</tt> */
- #define MXC_R_RPU_SRAM2 ((uint32_t)0x00000F20UL) /**< Offset from RPU Base Address: <tt> 0x0F20</tt> */
- #define MXC_R_RPU_SRAM3 ((uint32_t)0x00000F30UL) /**< Offset from RPU Base Address: <tt> 0x0F30</tt> */
- #define MXC_R_RPU_SRAM4 ((uint32_t)0x00000F40UL) /**< Offset from RPU Base Address: <tt> 0x0F40</tt> */
- #define MXC_R_RPU_SRAM5 ((uint32_t)0x00000F50UL) /**< Offset from RPU Base Address: <tt> 0x0F50</tt> */
- #define MXC_R_RPU_SRAM6 ((uint32_t)0x00000F60UL) /**< Offset from RPU Base Address: <tt> 0x0F60</tt> */
+ #define MXC_R_RPU_SPIXM_FIFO ((uint32_t)0x00000BC0UL) /**< Offset from RPU Base Address: <tt> 0x0BC0</tt> */
+ #define MXC_R_RPU_SPI0 ((uint32_t)0x00000BE0UL) /**< Offset from RPU Base Address: <tt> 0x0BE0</tt> */
+ #define MXC_R_RPU_SYSRAM0 ((uint32_t)0x00000F00UL) /**< Offset from RPU Base Address: <tt> 0x0F00</tt> */
+ #define MXC_R_RPU_SYSRAM1 ((uint32_t)0x00000F10UL) /**< Offset from RPU Base Address: <tt> 0x0F10</tt> */
+ #define MXC_R_RPU_SYSRAM2 ((uint32_t)0x00000F20UL) /**< Offset from RPU Base Address: <tt> 0x0F20</tt> */
+ #define MXC_R_RPU_SYSRAM3 ((uint32_t)0x00000F30UL) /**< Offset from RPU Base Address: <tt> 0x0F30</tt> */
+ #define MXC_R_RPU_SYSRAM4 ((uint32_t)0x00000F40UL) /**< Offset from RPU Base Address: <tt> 0x0F40</tt> */
+ #define MXC_R_RPU_SYSRAM5 ((uint32_t)0x00000F50UL) /**< Offset from RPU Base Address: <tt> 0x0F50</tt> */
+ #define MXC_R_RPU_SYSRAM6 ((uint32_t)0x00000F60UL) /**< Offset from RPU Base Address: <tt> 0x0F60</tt> */
/**@} end of group rpu_registers */
/**
@@ -768,38 +768,38 @@ typedef struct {
/**
* @ingroup rpu_registers
- * @defgroup RPU_BBCR RPU_BBCR
- * @brief BBCR Protection Register
+ * @defgroup RPU_MCR RPU_MCR
+ * @brief MCR Protection Register
* @{
*/
- #define MXC_F_RPU_BBCR_DMA0ACN_POS 0 /**< BBCR_DMA0ACN Position */
- #define MXC_F_RPU_BBCR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_DMA0ACN_POS)) /**< BBCR_DMA0ACN Mask */
+ #define MXC_F_RPU_MCR_DMA0ACN_POS 0 /**< MCR_DMA0ACN Position */
+ #define MXC_F_RPU_MCR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_DMA0ACN_POS)) /**< MCR_DMA0ACN Mask */
- #define MXC_F_RPU_BBCR_DMA1ACN_POS 1 /**< BBCR_DMA1ACN Position */
- #define MXC_F_RPU_BBCR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_DMA1ACN_POS)) /**< BBCR_DMA1ACN Mask */
+ #define MXC_F_RPU_MCR_DMA1ACN_POS 1 /**< MCR_DMA1ACN Position */
+ #define MXC_F_RPU_MCR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_DMA1ACN_POS)) /**< MCR_DMA1ACN Mask */
- #define MXC_F_RPU_BBCR_USBACN_POS 2 /**< BBCR_USBACN Position */
- #define MXC_F_RPU_BBCR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_USBACN_POS)) /**< BBCR_USBACN Mask */
+ #define MXC_F_RPU_MCR_USBACN_POS 2 /**< MCR_USBACN Position */
+ #define MXC_F_RPU_MCR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_USBACN_POS)) /**< MCR_USBACN Mask */
- #define MXC_F_RPU_BBCR_SYS0ACN_POS 3 /**< BBCR_SYS0ACN Position */
- #define MXC_F_RPU_BBCR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_SYS0ACN_POS)) /**< BBCR_SYS0ACN Mask */
+ #define MXC_F_RPU_MCR_SYS0ACN_POS 3 /**< MCR_SYS0ACN Position */
+ #define MXC_F_RPU_MCR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SYS0ACN_POS)) /**< MCR_SYS0ACN Mask */
- #define MXC_F_RPU_BBCR_SYS1ACN_POS 4 /**< BBCR_SYS1ACN Position */
- #define MXC_F_RPU_BBCR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_SYS1ACN_POS)) /**< BBCR_SYS1ACN Mask */
+ #define MXC_F_RPU_MCR_SYS1ACN_POS 4 /**< MCR_SYS1ACN Position */
+ #define MXC_F_RPU_MCR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SYS1ACN_POS)) /**< MCR_SYS1ACN Mask */
- #define MXC_F_RPU_BBCR_SDMADACN_POS 5 /**< BBCR_SDMADACN Position */
- #define MXC_F_RPU_BBCR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_SDMADACN_POS)) /**< BBCR_SDMADACN Mask */
+ #define MXC_F_RPU_MCR_SDMADACN_POS 5 /**< MCR_SDMADACN Position */
+ #define MXC_F_RPU_MCR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SDMADACN_POS)) /**< MCR_SDMADACN Mask */
- #define MXC_F_RPU_BBCR_SDMAIACN_POS 6 /**< BBCR_SDMAIACN Position */
- #define MXC_F_RPU_BBCR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_SDMAIACN_POS)) /**< BBCR_SDMAIACN Mask */
+ #define MXC_F_RPU_MCR_SDMAIACN_POS 6 /**< MCR_SDMAIACN Position */
+ #define MXC_F_RPU_MCR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SDMAIACN_POS)) /**< MCR_SDMAIACN Mask */
- #define MXC_F_RPU_BBCR_CRYPTOACN_POS 7 /**< BBCR_CRYPTOACN Position */
- #define MXC_F_RPU_BBCR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_CRYPTOACN_POS)) /**< BBCR_CRYPTOACN Mask */
+ #define MXC_F_RPU_MCR_CRYPTOACN_POS 7 /**< MCR_CRYPTOACN Position */
+ #define MXC_F_RPU_MCR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_CRYPTOACN_POS)) /**< MCR_CRYPTOACN Mask */
- #define MXC_F_RPU_BBCR_SDIOACN_POS 8 /**< BBCR_SDIOACN Position */
- #define MXC_F_RPU_BBCR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_BBCR_SDIOACN_POS)) /**< BBCR_SDIOACN Mask */
+ #define MXC_F_RPU_MCR_SDIOACN_POS 8 /**< MCR_SDIOACN Position */
+ #define MXC_F_RPU_MCR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_MCR_SDIOACN_POS)) /**< MCR_SDIOACN Mask */
-/**@} end of group RPU_BBCR_Register */
+/**@} end of group RPU_MCR_Register */
/**
* @ingroup rpu_registers
@@ -1153,178 +1153,178 @@ typedef struct {
/**
* @ingroup rpu_registers
- * @defgroup RPU_I2C0 RPU_I2C0
+ * @defgroup RPU_I2C0_BUS0 RPU_I2C0_BUS0
* @brief I2C0 Protection Register
* @{
*/
- #define MXC_F_RPU_I2C0_DMA0ACN_POS 0 /**< I2C0_DMA0ACN Position */
- #define MXC_F_RPU_I2C0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_DMA0ACN_POS)) /**< I2C0_DMA0ACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_DMA0ACN_POS 0 /**< I2C0_BUS0_DMA0ACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_DMA0ACN_POS)) /**< I2C0_BUS0_DMA0ACN Mask */
- #define MXC_F_RPU_I2C0_DMA1ACN_POS 1 /**< I2C0_DMA1ACN Position */
- #define MXC_F_RPU_I2C0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_DMA1ACN_POS)) /**< I2C0_DMA1ACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_DMA1ACN_POS 1 /**< I2C0_BUS0_DMA1ACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_DMA1ACN_POS)) /**< I2C0_BUS0_DMA1ACN Mask */
- #define MXC_F_RPU_I2C0_USBACN_POS 2 /**< I2C0_USBACN Position */
- #define MXC_F_RPU_I2C0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_USBACN_POS)) /**< I2C0_USBACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_USBACN_POS 2 /**< I2C0_BUS0_USBACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_USBACN_POS)) /**< I2C0_BUS0_USBACN Mask */
- #define MXC_F_RPU_I2C0_SYS0ACN_POS 3 /**< I2C0_SYS0ACN Position */
- #define MXC_F_RPU_I2C0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_SYS0ACN_POS)) /**< I2C0_SYS0ACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_SYS0ACN_POS 3 /**< I2C0_BUS0_SYS0ACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SYS0ACN_POS)) /**< I2C0_BUS0_SYS0ACN Mask */
- #define MXC_F_RPU_I2C0_SYS1ACN_POS 4 /**< I2C0_SYS1ACN Position */
- #define MXC_F_RPU_I2C0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_SYS1ACN_POS)) /**< I2C0_SYS1ACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_SYS1ACN_POS 4 /**< I2C0_BUS0_SYS1ACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SYS1ACN_POS)) /**< I2C0_BUS0_SYS1ACN Mask */
- #define MXC_F_RPU_I2C0_SDMADACN_POS 5 /**< I2C0_SDMADACN Position */
- #define MXC_F_RPU_I2C0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_SDMADACN_POS)) /**< I2C0_SDMADACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_SDMADACN_POS 5 /**< I2C0_BUS0_SDMADACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SDMADACN_POS)) /**< I2C0_BUS0_SDMADACN Mask */
- #define MXC_F_RPU_I2C0_SDMAIACN_POS 6 /**< I2C0_SDMAIACN Position */
- #define MXC_F_RPU_I2C0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_SDMAIACN_POS)) /**< I2C0_SDMAIACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_SDMAIACN_POS 6 /**< I2C0_BUS0_SDMAIACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SDMAIACN_POS)) /**< I2C0_BUS0_SDMAIACN Mask */
- #define MXC_F_RPU_I2C0_CRYPTOACN_POS 7 /**< I2C0_CRYPTOACN Position */
- #define MXC_F_RPU_I2C0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_CRYPTOACN_POS)) /**< I2C0_CRYPTOACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_CRYPTOACN_POS 7 /**< I2C0_BUS0_CRYPTOACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_CRYPTOACN_POS)) /**< I2C0_BUS0_CRYPTOACN Mask */
- #define MXC_F_RPU_I2C0_SDIOACN_POS 8 /**< I2C0_SDIOACN Position */
- #define MXC_F_RPU_I2C0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_SDIOACN_POS)) /**< I2C0_SDIOACN Mask */
+ #define MXC_F_RPU_I2C0_BUS0_SDIOACN_POS 8 /**< I2C0_BUS0_SDIOACN Position */
+ #define MXC_F_RPU_I2C0_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C0_BUS0_SDIOACN_POS)) /**< I2C0_BUS0_SDIOACN Mask */
-/**@} end of group RPU_I2C0_Register */
+/**@} end of group RPU_I2C0_BUS0_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_I2C1 RPU_I2C1
+ * @defgroup RPU_I2C1_BUS0 RPU_I2C1_BUS0
* @brief I2C1 Protection Register
* @{
*/
- #define MXC_F_RPU_I2C1_DMA0ACN_POS 0 /**< I2C1_DMA0ACN Position */
- #define MXC_F_RPU_I2C1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_DMA0ACN_POS)) /**< I2C1_DMA0ACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_DMA0ACN_POS 0 /**< I2C1_BUS0_DMA0ACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_DMA0ACN_POS)) /**< I2C1_BUS0_DMA0ACN Mask */
- #define MXC_F_RPU_I2C1_DMA1ACN_POS 1 /**< I2C1_DMA1ACN Position */
- #define MXC_F_RPU_I2C1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_DMA1ACN_POS)) /**< I2C1_DMA1ACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_DMA1ACN_POS 1 /**< I2C1_BUS0_DMA1ACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_DMA1ACN_POS)) /**< I2C1_BUS0_DMA1ACN Mask */
- #define MXC_F_RPU_I2C1_USBACN_POS 2 /**< I2C1_USBACN Position */
- #define MXC_F_RPU_I2C1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_USBACN_POS)) /**< I2C1_USBACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_USBACN_POS 2 /**< I2C1_BUS0_USBACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_USBACN_POS)) /**< I2C1_BUS0_USBACN Mask */
- #define MXC_F_RPU_I2C1_SYS0ACN_POS 3 /**< I2C1_SYS0ACN Position */
- #define MXC_F_RPU_I2C1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_SYS0ACN_POS)) /**< I2C1_SYS0ACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_SYS0ACN_POS 3 /**< I2C1_BUS0_SYS0ACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SYS0ACN_POS)) /**< I2C1_BUS0_SYS0ACN Mask */
- #define MXC_F_RPU_I2C1_SYS1ACN_POS 4 /**< I2C1_SYS1ACN Position */
- #define MXC_F_RPU_I2C1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_SYS1ACN_POS)) /**< I2C1_SYS1ACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_SYS1ACN_POS 4 /**< I2C1_BUS0_SYS1ACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SYS1ACN_POS)) /**< I2C1_BUS0_SYS1ACN Mask */
- #define MXC_F_RPU_I2C1_SDMADACN_POS 5 /**< I2C1_SDMADACN Position */
- #define MXC_F_RPU_I2C1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_SDMADACN_POS)) /**< I2C1_SDMADACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_SDMADACN_POS 5 /**< I2C1_BUS0_SDMADACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SDMADACN_POS)) /**< I2C1_BUS0_SDMADACN Mask */
- #define MXC_F_RPU_I2C1_SDMAIACN_POS 6 /**< I2C1_SDMAIACN Position */
- #define MXC_F_RPU_I2C1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_SDMAIACN_POS)) /**< I2C1_SDMAIACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_SDMAIACN_POS 6 /**< I2C1_BUS0_SDMAIACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SDMAIACN_POS)) /**< I2C1_BUS0_SDMAIACN Mask */
- #define MXC_F_RPU_I2C1_CRYPTOACN_POS 7 /**< I2C1_CRYPTOACN Position */
- #define MXC_F_RPU_I2C1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_CRYPTOACN_POS)) /**< I2C1_CRYPTOACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_CRYPTOACN_POS 7 /**< I2C1_BUS0_CRYPTOACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_CRYPTOACN_POS)) /**< I2C1_BUS0_CRYPTOACN Mask */
- #define MXC_F_RPU_I2C1_SDIOACN_POS 8 /**< I2C1_SDIOACN Position */
- #define MXC_F_RPU_I2C1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_SDIOACN_POS)) /**< I2C1_SDIOACN Mask */
+ #define MXC_F_RPU_I2C1_BUS0_SDIOACN_POS 8 /**< I2C1_BUS0_SDIOACN Position */
+ #define MXC_F_RPU_I2C1_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C1_BUS0_SDIOACN_POS)) /**< I2C1_BUS0_SDIOACN Mask */
-/**@} end of group RPU_I2C1_Register */
+/**@} end of group RPU_I2C1_BUS0_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_I2C2 RPU_I2C2
+ * @defgroup RPU_I2C2_BUS0 RPU_I2C2_BUS0
* @brief I2C2 Protection Register
* @{
*/
- #define MXC_F_RPU_I2C2_DMA0ACN_POS 0 /**< I2C2_DMA0ACN Position */
- #define MXC_F_RPU_I2C2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_DMA0ACN_POS)) /**< I2C2_DMA0ACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_DMA0ACN_POS 0 /**< I2C2_BUS0_DMA0ACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_DMA0ACN_POS)) /**< I2C2_BUS0_DMA0ACN Mask */
- #define MXC_F_RPU_I2C2_DMA1ACN_POS 1 /**< I2C2_DMA1ACN Position */
- #define MXC_F_RPU_I2C2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_DMA1ACN_POS)) /**< I2C2_DMA1ACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_DMA1ACN_POS 1 /**< I2C2_BUS0_DMA1ACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_DMA1ACN_POS)) /**< I2C2_BUS0_DMA1ACN Mask */
- #define MXC_F_RPU_I2C2_USBACN_POS 2 /**< I2C2_USBACN Position */
- #define MXC_F_RPU_I2C2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_USBACN_POS)) /**< I2C2_USBACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_USBACN_POS 2 /**< I2C2_BUS0_USBACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_USBACN_POS)) /**< I2C2_BUS0_USBACN Mask */
- #define MXC_F_RPU_I2C2_SYS0ACN_POS 3 /**< I2C2_SYS0ACN Position */
- #define MXC_F_RPU_I2C2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_SYS0ACN_POS)) /**< I2C2_SYS0ACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_SYS0ACN_POS 3 /**< I2C2_BUS0_SYS0ACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SYS0ACN_POS)) /**< I2C2_BUS0_SYS0ACN Mask */
- #define MXC_F_RPU_I2C2_SYS1ACN_POS 4 /**< I2C2_SYS1ACN Position */
- #define MXC_F_RPU_I2C2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_SYS1ACN_POS)) /**< I2C2_SYS1ACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_SYS1ACN_POS 4 /**< I2C2_BUS0_SYS1ACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SYS1ACN_POS)) /**< I2C2_BUS0_SYS1ACN Mask */
- #define MXC_F_RPU_I2C2_SDMADACN_POS 5 /**< I2C2_SDMADACN Position */
- #define MXC_F_RPU_I2C2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_SDMADACN_POS)) /**< I2C2_SDMADACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_SDMADACN_POS 5 /**< I2C2_BUS0_SDMADACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SDMADACN_POS)) /**< I2C2_BUS0_SDMADACN Mask */
- #define MXC_F_RPU_I2C2_SDMAIACN_POS 6 /**< I2C2_SDMAIACN Position */
- #define MXC_F_RPU_I2C2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_SDMAIACN_POS)) /**< I2C2_SDMAIACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_SDMAIACN_POS 6 /**< I2C2_BUS0_SDMAIACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SDMAIACN_POS)) /**< I2C2_BUS0_SDMAIACN Mask */
- #define MXC_F_RPU_I2C2_CRYPTOACN_POS 7 /**< I2C2_CRYPTOACN Position */
- #define MXC_F_RPU_I2C2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_CRYPTOACN_POS)) /**< I2C2_CRYPTOACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_CRYPTOACN_POS 7 /**< I2C2_BUS0_CRYPTOACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_CRYPTOACN_POS)) /**< I2C2_BUS0_CRYPTOACN Mask */
- #define MXC_F_RPU_I2C2_SDIOACN_POS 8 /**< I2C2_SDIOACN Position */
- #define MXC_F_RPU_I2C2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_SDIOACN_POS)) /**< I2C2_SDIOACN Mask */
+ #define MXC_F_RPU_I2C2_BUS0_SDIOACN_POS 8 /**< I2C2_BUS0_SDIOACN Position */
+ #define MXC_F_RPU_I2C2_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_I2C2_BUS0_SDIOACN_POS)) /**< I2C2_BUS0_SDIOACN Mask */
-/**@} end of group RPU_I2C2_Register */
+/**@} end of group RPU_I2C2_BUS0_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SPIXIPM RPU_SPIXIPM
+ * @defgroup RPU_SPIXFM RPU_SPIXFM
* @brief SPI-XIP Master Protection Register
* @{
*/
- #define MXC_F_RPU_SPIXIPM_DMA0ACN_POS 0 /**< SPIXIPM_DMA0ACN Position */
- #define MXC_F_RPU_SPIXIPM_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_DMA0ACN_POS)) /**< SPIXIPM_DMA0ACN Mask */
+ #define MXC_F_RPU_SPIXFM_DMA0ACN_POS 0 /**< SPIXFM_DMA0ACN Position */
+ #define MXC_F_RPU_SPIXFM_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_DMA0ACN_POS)) /**< SPIXFM_DMA0ACN Mask */
- #define MXC_F_RPU_SPIXIPM_DMA1ACN_POS 1 /**< SPIXIPM_DMA1ACN Position */
- #define MXC_F_RPU_SPIXIPM_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_DMA1ACN_POS)) /**< SPIXIPM_DMA1ACN Mask */
+ #define MXC_F_RPU_SPIXFM_DMA1ACN_POS 1 /**< SPIXFM_DMA1ACN Position */
+ #define MXC_F_RPU_SPIXFM_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_DMA1ACN_POS)) /**< SPIXFM_DMA1ACN Mask */
- #define MXC_F_RPU_SPIXIPM_USBACN_POS 2 /**< SPIXIPM_USBACN Position */
- #define MXC_F_RPU_SPIXIPM_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_USBACN_POS)) /**< SPIXIPM_USBACN Mask */
+ #define MXC_F_RPU_SPIXFM_USBACN_POS 2 /**< SPIXFM_USBACN Position */
+ #define MXC_F_RPU_SPIXFM_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_USBACN_POS)) /**< SPIXFM_USBACN Mask */
- #define MXC_F_RPU_SPIXIPM_SYS0ACN_POS 3 /**< SPIXIPM_SYS0ACN Position */
- #define MXC_F_RPU_SPIXIPM_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_SYS0ACN_POS)) /**< SPIXIPM_SYS0ACN Mask */
+ #define MXC_F_RPU_SPIXFM_SYS0ACN_POS 3 /**< SPIXFM_SYS0ACN Position */
+ #define MXC_F_RPU_SPIXFM_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SYS0ACN_POS)) /**< SPIXFM_SYS0ACN Mask */
- #define MXC_F_RPU_SPIXIPM_SYS1ACN_POS 4 /**< SPIXIPM_SYS1ACN Position */
- #define MXC_F_RPU_SPIXIPM_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_SYS1ACN_POS)) /**< SPIXIPM_SYS1ACN Mask */
+ #define MXC_F_RPU_SPIXFM_SYS1ACN_POS 4 /**< SPIXFM_SYS1ACN Position */
+ #define MXC_F_RPU_SPIXFM_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SYS1ACN_POS)) /**< SPIXFM_SYS1ACN Mask */
- #define MXC_F_RPU_SPIXIPM_SDMADACN_POS 5 /**< SPIXIPM_SDMADACN Position */
- #define MXC_F_RPU_SPIXIPM_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_SDMADACN_POS)) /**< SPIXIPM_SDMADACN Mask */
+ #define MXC_F_RPU_SPIXFM_SDMADACN_POS 5 /**< SPIXFM_SDMADACN Position */
+ #define MXC_F_RPU_SPIXFM_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SDMADACN_POS)) /**< SPIXFM_SDMADACN Mask */
- #define MXC_F_RPU_SPIXIPM_SDMAIACN_POS 6 /**< SPIXIPM_SDMAIACN Position */
- #define MXC_F_RPU_SPIXIPM_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_SDMAIACN_POS)) /**< SPIXIPM_SDMAIACN Mask */
+ #define MXC_F_RPU_SPIXFM_SDMAIACN_POS 6 /**< SPIXFM_SDMAIACN Position */
+ #define MXC_F_RPU_SPIXFM_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SDMAIACN_POS)) /**< SPIXFM_SDMAIACN Mask */
- #define MXC_F_RPU_SPIXIPM_CRYPTOACN_POS 7 /**< SPIXIPM_CRYPTOACN Position */
- #define MXC_F_RPU_SPIXIPM_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_CRYPTOACN_POS)) /**< SPIXIPM_CRYPTOACN Mask */
+ #define MXC_F_RPU_SPIXFM_CRYPTOACN_POS 7 /**< SPIXFM_CRYPTOACN Position */
+ #define MXC_F_RPU_SPIXFM_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_CRYPTOACN_POS)) /**< SPIXFM_CRYPTOACN Mask */
- #define MXC_F_RPU_SPIXIPM_SDIOACN_POS 8 /**< SPIXIPM_SDIOACN Position */
- #define MXC_F_RPU_SPIXIPM_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPM_SDIOACN_POS)) /**< SPIXIPM_SDIOACN Mask */
+ #define MXC_F_RPU_SPIXFM_SDIOACN_POS 8 /**< SPIXFM_SDIOACN Position */
+ #define MXC_F_RPU_SPIXFM_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFM_SDIOACN_POS)) /**< SPIXFM_SDIOACN Mask */
-/**@} end of group RPU_SPIXIPM_Register */
+/**@} end of group RPU_SPIXFM_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SPIXIPMC RPU_SPIXIPMC
+ * @defgroup RPU_SPIXFC RPU_SPIXFC
* @brief SPI-XIP Master Controller Protection Register
* @{
*/
- #define MXC_F_RPU_SPIXIPMC_DMA0ACN_POS 0 /**< SPIXIPMC_DMA0ACN Position */
- #define MXC_F_RPU_SPIXIPMC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_DMA0ACN_POS)) /**< SPIXIPMC_DMA0ACN Mask */
+ #define MXC_F_RPU_SPIXFC_DMA0ACN_POS 0 /**< SPIXFC_DMA0ACN Position */
+ #define MXC_F_RPU_SPIXFC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_DMA0ACN_POS)) /**< SPIXFC_DMA0ACN Mask */
- #define MXC_F_RPU_SPIXIPMC_DMA1ACN_POS 1 /**< SPIXIPMC_DMA1ACN Position */
- #define MXC_F_RPU_SPIXIPMC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_DMA1ACN_POS)) /**< SPIXIPMC_DMA1ACN Mask */
+ #define MXC_F_RPU_SPIXFC_DMA1ACN_POS 1 /**< SPIXFC_DMA1ACN Position */
+ #define MXC_F_RPU_SPIXFC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_DMA1ACN_POS)) /**< SPIXFC_DMA1ACN Mask */
- #define MXC_F_RPU_SPIXIPMC_USBACN_POS 2 /**< SPIXIPMC_USBACN Position */
- #define MXC_F_RPU_SPIXIPMC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_USBACN_POS)) /**< SPIXIPMC_USBACN Mask */
+ #define MXC_F_RPU_SPIXFC_USBACN_POS 2 /**< SPIXFC_USBACN Position */
+ #define MXC_F_RPU_SPIXFC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_USBACN_POS)) /**< SPIXFC_USBACN Mask */
- #define MXC_F_RPU_SPIXIPMC_SYS0ACN_POS 3 /**< SPIXIPMC_SYS0ACN Position */
- #define MXC_F_RPU_SPIXIPMC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SYS0ACN_POS)) /**< SPIXIPMC_SYS0ACN Mask */
+ #define MXC_F_RPU_SPIXFC_SYS0ACN_POS 3 /**< SPIXFC_SYS0ACN Position */
+ #define MXC_F_RPU_SPIXFC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SYS0ACN_POS)) /**< SPIXFC_SYS0ACN Mask */
- #define MXC_F_RPU_SPIXIPMC_SYS1ACN_POS 4 /**< SPIXIPMC_SYS1ACN Position */
- #define MXC_F_RPU_SPIXIPMC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SYS1ACN_POS)) /**< SPIXIPMC_SYS1ACN Mask */
+ #define MXC_F_RPU_SPIXFC_SYS1ACN_POS 4 /**< SPIXFC_SYS1ACN Position */
+ #define MXC_F_RPU_SPIXFC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SYS1ACN_POS)) /**< SPIXFC_SYS1ACN Mask */
- #define MXC_F_RPU_SPIXIPMC_SDMADACN_POS 5 /**< SPIXIPMC_SDMADACN Position */
- #define MXC_F_RPU_SPIXIPMC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDMADACN_POS)) /**< SPIXIPMC_SDMADACN Mask */
+ #define MXC_F_RPU_SPIXFC_SDMADACN_POS 5 /**< SPIXFC_SDMADACN Position */
+ #define MXC_F_RPU_SPIXFC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SDMADACN_POS)) /**< SPIXFC_SDMADACN Mask */
- #define MXC_F_RPU_SPIXIPMC_SDMAIACN_POS 6 /**< SPIXIPMC_SDMAIACN Position */
- #define MXC_F_RPU_SPIXIPMC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDMAIACN_POS)) /**< SPIXIPMC_SDMAIACN Mask */
+ #define MXC_F_RPU_SPIXFC_SDMAIACN_POS 6 /**< SPIXFC_SDMAIACN Position */
+ #define MXC_F_RPU_SPIXFC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SDMAIACN_POS)) /**< SPIXFC_SDMAIACN Mask */
- #define MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS 7 /**< SPIXIPMC_CRYPTOACN Position */
- #define MXC_F_RPU_SPIXIPMC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS)) /**< SPIXIPMC_CRYPTOACN Mask */
+ #define MXC_F_RPU_SPIXFC_CRYPTOACN_POS 7 /**< SPIXFC_CRYPTOACN Position */
+ #define MXC_F_RPU_SPIXFC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_CRYPTOACN_POS)) /**< SPIXFC_CRYPTOACN Mask */
- #define MXC_F_RPU_SPIXIPMC_SDIOACN_POS 8 /**< SPIXIPMC_SDIOACN Position */
- #define MXC_F_RPU_SPIXIPMC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDIOACN_POS)) /**< SPIXIPMC_SDIOACN Mask */
+ #define MXC_F_RPU_SPIXFC_SDIOACN_POS 8 /**< SPIXFC_SDIOACN Position */
+ #define MXC_F_RPU_SPIXFC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXFC_SDIOACN_POS)) /**< SPIXFC_SDIOACN Mask */
-/**@} end of group RPU_SPIXIPMC_Register */
+/**@} end of group RPU_SPIXFC_Register */
/**
* @ingroup rpu_registers
@@ -1433,143 +1433,143 @@ typedef struct {
/**
* @ingroup rpu_registers
- * @defgroup RPU_ICACHE0 RPU_ICACHE0
+ * @defgroup RPU_ICC0 RPU_ICC0
* @brief Instruction Cache 0 Protection Register
* @{
*/
- #define MXC_F_RPU_ICACHE0_DMA0ACN_POS 0 /**< ICACHE0_DMA0ACN Position */
- #define MXC_F_RPU_ICACHE0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_DMA0ACN_POS)) /**< ICACHE0_DMA0ACN Mask */
+ #define MXC_F_RPU_ICC0_DMA0ACN_POS 0 /**< ICC0_DMA0ACN Position */
+ #define MXC_F_RPU_ICC0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_DMA0ACN_POS)) /**< ICC0_DMA0ACN Mask */
- #define MXC_F_RPU_ICACHE0_DMA1ACN_POS 1 /**< ICACHE0_DMA1ACN Position */
- #define MXC_F_RPU_ICACHE0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_DMA1ACN_POS)) /**< ICACHE0_DMA1ACN Mask */
+ #define MXC_F_RPU_ICC0_DMA1ACN_POS 1 /**< ICC0_DMA1ACN Position */
+ #define MXC_F_RPU_ICC0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_DMA1ACN_POS)) /**< ICC0_DMA1ACN Mask */
- #define MXC_F_RPU_ICACHE0_USBACN_POS 2 /**< ICACHE0_USBACN Position */
- #define MXC_F_RPU_ICACHE0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_USBACN_POS)) /**< ICACHE0_USBACN Mask */
+ #define MXC_F_RPU_ICC0_USBACN_POS 2 /**< ICC0_USBACN Position */
+ #define MXC_F_RPU_ICC0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_USBACN_POS)) /**< ICC0_USBACN Mask */
- #define MXC_F_RPU_ICACHE0_SYS0ACN_POS 3 /**< ICACHE0_SYS0ACN Position */
- #define MXC_F_RPU_ICACHE0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SYS0ACN_POS)) /**< ICACHE0_SYS0ACN Mask */
+ #define MXC_F_RPU_ICC0_SYS0ACN_POS 3 /**< ICC0_SYS0ACN Position */
+ #define MXC_F_RPU_ICC0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SYS0ACN_POS)) /**< ICC0_SYS0ACN Mask */
- #define MXC_F_RPU_ICACHE0_SYS1ACN_POS 4 /**< ICACHE0_SYS1ACN Position */
- #define MXC_F_RPU_ICACHE0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SYS1ACN_POS)) /**< ICACHE0_SYS1ACN Mask */
+ #define MXC_F_RPU_ICC0_SYS1ACN_POS 4 /**< ICC0_SYS1ACN Position */
+ #define MXC_F_RPU_ICC0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SYS1ACN_POS)) /**< ICC0_SYS1ACN Mask */
- #define MXC_F_RPU_ICACHE0_SDMADACN_POS 5 /**< ICACHE0_SDMADACN Position */
- #define MXC_F_RPU_ICACHE0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SDMADACN_POS)) /**< ICACHE0_SDMADACN Mask */
+ #define MXC_F_RPU_ICC0_SDMADACN_POS 5 /**< ICC0_SDMADACN Position */
+ #define MXC_F_RPU_ICC0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SDMADACN_POS)) /**< ICC0_SDMADACN Mask */
- #define MXC_F_RPU_ICACHE0_SDMAIACN_POS 6 /**< ICACHE0_SDMAIACN Position */
- #define MXC_F_RPU_ICACHE0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SDMAIACN_POS)) /**< ICACHE0_SDMAIACN Mask */
+ #define MXC_F_RPU_ICC0_SDMAIACN_POS 6 /**< ICC0_SDMAIACN Position */
+ #define MXC_F_RPU_ICC0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SDMAIACN_POS)) /**< ICC0_SDMAIACN Mask */
- #define MXC_F_RPU_ICACHE0_CRYPTOACN_POS 7 /**< ICACHE0_CRYPTOACN Position */
- #define MXC_F_RPU_ICACHE0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_CRYPTOACN_POS)) /**< ICACHE0_CRYPTOACN Mask */
+ #define MXC_F_RPU_ICC0_CRYPTOACN_POS 7 /**< ICC0_CRYPTOACN Position */
+ #define MXC_F_RPU_ICC0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_CRYPTOACN_POS)) /**< ICC0_CRYPTOACN Mask */
- #define MXC_F_RPU_ICACHE0_SDIOACN_POS 8 /**< ICACHE0_SDIOACN Position */
- #define MXC_F_RPU_ICACHE0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE0_SDIOACN_POS)) /**< ICACHE0_SDIOACN Mask */
+ #define MXC_F_RPU_ICC0_SDIOACN_POS 8 /**< ICC0_SDIOACN Position */
+ #define MXC_F_RPU_ICC0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC0_SDIOACN_POS)) /**< ICC0_SDIOACN Mask */
-/**@} end of group RPU_ICACHE0_Register */
+/**@} end of group RPU_ICC0_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_ICACHE1 RPU_ICACHE1
+ * @defgroup RPU_ICC1 RPU_ICC1
* @brief Instruction Cache 1 Protection Register
* @{
*/
- #define MXC_F_RPU_ICACHE1_DMA0ACN_POS 0 /**< ICACHE1_DMA0ACN Position */
- #define MXC_F_RPU_ICACHE1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_DMA0ACN_POS)) /**< ICACHE1_DMA0ACN Mask */
+ #define MXC_F_RPU_ICC1_DMA0ACN_POS 0 /**< ICC1_DMA0ACN Position */
+ #define MXC_F_RPU_ICC1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_DMA0ACN_POS)) /**< ICC1_DMA0ACN Mask */
- #define MXC_F_RPU_ICACHE1_DMA1ACN_POS 1 /**< ICACHE1_DMA1ACN Position */
- #define MXC_F_RPU_ICACHE1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_DMA1ACN_POS)) /**< ICACHE1_DMA1ACN Mask */
+ #define MXC_F_RPU_ICC1_DMA1ACN_POS 1 /**< ICC1_DMA1ACN Position */
+ #define MXC_F_RPU_ICC1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_DMA1ACN_POS)) /**< ICC1_DMA1ACN Mask */
- #define MXC_F_RPU_ICACHE1_USBACN_POS 2 /**< ICACHE1_USBACN Position */
- #define MXC_F_RPU_ICACHE1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_USBACN_POS)) /**< ICACHE1_USBACN Mask */
+ #define MXC_F_RPU_ICC1_USBACN_POS 2 /**< ICC1_USBACN Position */
+ #define MXC_F_RPU_ICC1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_USBACN_POS)) /**< ICC1_USBACN Mask */
- #define MXC_F_RPU_ICACHE1_SYS0ACN_POS 3 /**< ICACHE1_SYS0ACN Position */
- #define MXC_F_RPU_ICACHE1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_SYS0ACN_POS)) /**< ICACHE1_SYS0ACN Mask */
+ #define MXC_F_RPU_ICC1_SYS0ACN_POS 3 /**< ICC1_SYS0ACN Position */
+ #define MXC_F_RPU_ICC1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SYS0ACN_POS)) /**< ICC1_SYS0ACN Mask */
- #define MXC_F_RPU_ICACHE1_SYS1ACN_POS 4 /**< ICACHE1_SYS1ACN Position */
- #define MXC_F_RPU_ICACHE1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_SYS1ACN_POS)) /**< ICACHE1_SYS1ACN Mask */
+ #define MXC_F_RPU_ICC1_SYS1ACN_POS 4 /**< ICC1_SYS1ACN Position */
+ #define MXC_F_RPU_ICC1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SYS1ACN_POS)) /**< ICC1_SYS1ACN Mask */
- #define MXC_F_RPU_ICACHE1_SDMADACN_POS 5 /**< ICACHE1_SDMADACN Position */
- #define MXC_F_RPU_ICACHE1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_SDMADACN_POS)) /**< ICACHE1_SDMADACN Mask */
+ #define MXC_F_RPU_ICC1_SDMADACN_POS 5 /**< ICC1_SDMADACN Position */
+ #define MXC_F_RPU_ICC1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SDMADACN_POS)) /**< ICC1_SDMADACN Mask */
- #define MXC_F_RPU_ICACHE1_SDMAIACN_POS 6 /**< ICACHE1_SDMAIACN Position */
- #define MXC_F_RPU_ICACHE1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_SDMAIACN_POS)) /**< ICACHE1_SDMAIACN Mask */
+ #define MXC_F_RPU_ICC1_SDMAIACN_POS 6 /**< ICC1_SDMAIACN Position */
+ #define MXC_F_RPU_ICC1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SDMAIACN_POS)) /**< ICC1_SDMAIACN Mask */
- #define MXC_F_RPU_ICACHE1_CRYPTOACN_POS 7 /**< ICACHE1_CRYPTOACN Position */
- #define MXC_F_RPU_ICACHE1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_CRYPTOACN_POS)) /**< ICACHE1_CRYPTOACN Mask */
+ #define MXC_F_RPU_ICC1_CRYPTOACN_POS 7 /**< ICC1_CRYPTOACN Position */
+ #define MXC_F_RPU_ICC1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_CRYPTOACN_POS)) /**< ICC1_CRYPTOACN Mask */
- #define MXC_F_RPU_ICACHE1_SDIOACN_POS 8 /**< ICACHE1_SDIOACN Position */
- #define MXC_F_RPU_ICACHE1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHE1_SDIOACN_POS)) /**< ICACHE1_SDIOACN Mask */
+ #define MXC_F_RPU_ICC1_SDIOACN_POS 8 /**< ICC1_SDIOACN Position */
+ #define MXC_F_RPU_ICC1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICC1_SDIOACN_POS)) /**< ICC1_SDIOACN Mask */
-/**@} end of group RPU_ICACHE1_Register */
+/**@} end of group RPU_ICC1_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_ICACHEXIP RPU_ICACHEXIP
+ * @defgroup RPU_SFCC RPU_SFCC
* @brief Instruction Cache XIP Protection Register
* @{
*/
- #define MXC_F_RPU_ICACHEXIP_DMA0ACN_POS 0 /**< ICACHEXIP_DMA0ACN Position */
- #define MXC_F_RPU_ICACHEXIP_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_DMA0ACN_POS)) /**< ICACHEXIP_DMA0ACN Mask */
+ #define MXC_F_RPU_SFCC_DMA0ACN_POS 0 /**< SFCC_DMA0ACN Position */
+ #define MXC_F_RPU_SFCC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_DMA0ACN_POS)) /**< SFCC_DMA0ACN Mask */
- #define MXC_F_RPU_ICACHEXIP_DMA1ACN_POS 1 /**< ICACHEXIP_DMA1ACN Position */
- #define MXC_F_RPU_ICACHEXIP_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_DMA1ACN_POS)) /**< ICACHEXIP_DMA1ACN Mask */
+ #define MXC_F_RPU_SFCC_DMA1ACN_POS 1 /**< SFCC_DMA1ACN Position */
+ #define MXC_F_RPU_SFCC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_DMA1ACN_POS)) /**< SFCC_DMA1ACN Mask */
- #define MXC_F_RPU_ICACHEXIP_USBACN_POS 2 /**< ICACHEXIP_USBACN Position */
- #define MXC_F_RPU_ICACHEXIP_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_USBACN_POS)) /**< ICACHEXIP_USBACN Mask */
+ #define MXC_F_RPU_SFCC_USBACN_POS 2 /**< SFCC_USBACN Position */
+ #define MXC_F_RPU_SFCC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_USBACN_POS)) /**< SFCC_USBACN Mask */
- #define MXC_F_RPU_ICACHEXIP_SYS0ACN_POS 3 /**< ICACHEXIP_SYS0ACN Position */
- #define MXC_F_RPU_ICACHEXIP_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_SYS0ACN_POS)) /**< ICACHEXIP_SYS0ACN Mask */
+ #define MXC_F_RPU_SFCC_SYS0ACN_POS 3 /**< SFCC_SYS0ACN Position */
+ #define MXC_F_RPU_SFCC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SYS0ACN_POS)) /**< SFCC_SYS0ACN Mask */
- #define MXC_F_RPU_ICACHEXIP_SYS1ACN_POS 4 /**< ICACHEXIP_SYS1ACN Position */
- #define MXC_F_RPU_ICACHEXIP_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_SYS1ACN_POS)) /**< ICACHEXIP_SYS1ACN Mask */
+ #define MXC_F_RPU_SFCC_SYS1ACN_POS 4 /**< SFCC_SYS1ACN Position */
+ #define MXC_F_RPU_SFCC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SYS1ACN_POS)) /**< SFCC_SYS1ACN Mask */
- #define MXC_F_RPU_ICACHEXIP_SDMADACN_POS 5 /**< ICACHEXIP_SDMADACN Position */
- #define MXC_F_RPU_ICACHEXIP_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_SDMADACN_POS)) /**< ICACHEXIP_SDMADACN Mask */
+ #define MXC_F_RPU_SFCC_SDMADACN_POS 5 /**< SFCC_SDMADACN Position */
+ #define MXC_F_RPU_SFCC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDMADACN_POS)) /**< SFCC_SDMADACN Mask */
- #define MXC_F_RPU_ICACHEXIP_SDMAIACN_POS 6 /**< ICACHEXIP_SDMAIACN Position */
- #define MXC_F_RPU_ICACHEXIP_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_SDMAIACN_POS)) /**< ICACHEXIP_SDMAIACN Mask */
+ #define MXC_F_RPU_SFCC_SDMAIACN_POS 6 /**< SFCC_SDMAIACN Position */
+ #define MXC_F_RPU_SFCC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDMAIACN_POS)) /**< SFCC_SDMAIACN Mask */
- #define MXC_F_RPU_ICACHEXIP_CRYPTOACN_POS 7 /**< ICACHEXIP_CRYPTOACN Position */
- #define MXC_F_RPU_ICACHEXIP_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_CRYPTOACN_POS)) /**< ICACHEXIP_CRYPTOACN Mask */
+ #define MXC_F_RPU_SFCC_CRYPTOACN_POS 7 /**< SFCC_CRYPTOACN Position */
+ #define MXC_F_RPU_SFCC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_CRYPTOACN_POS)) /**< SFCC_CRYPTOACN Mask */
- #define MXC_F_RPU_ICACHEXIP_SDIOACN_POS 8 /**< ICACHEXIP_SDIOACN Position */
- #define MXC_F_RPU_ICACHEXIP_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_ICACHEXIP_SDIOACN_POS)) /**< ICACHEXIP_SDIOACN Mask */
+ #define MXC_F_RPU_SFCC_SDIOACN_POS 8 /**< SFCC_SDIOACN Position */
+ #define MXC_F_RPU_SFCC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SFCC_SDIOACN_POS)) /**< SFCC_SDIOACN Mask */
-/**@} end of group RPU_ICACHEXIP_Register */
+/**@} end of group RPU_SFCC_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_DCACHE RPU_DCACHE
+ * @defgroup RPU_SRCC RPU_SRCC
* @brief Data Cache Controller Protection Register
* @{
*/
- #define MXC_F_RPU_DCACHE_DMA0ACN_POS 0 /**< DCACHE_DMA0ACN Position */
- #define MXC_F_RPU_DCACHE_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_DMA0ACN_POS)) /**< DCACHE_DMA0ACN Mask */
+ #define MXC_F_RPU_SRCC_DMA0ACN_POS 0 /**< SRCC_DMA0ACN Position */
+ #define MXC_F_RPU_SRCC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_DMA0ACN_POS)) /**< SRCC_DMA0ACN Mask */
- #define MXC_F_RPU_DCACHE_DMA1ACN_POS 1 /**< DCACHE_DMA1ACN Position */
- #define MXC_F_RPU_DCACHE_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_DMA1ACN_POS)) /**< DCACHE_DMA1ACN Mask */
+ #define MXC_F_RPU_SRCC_DMA1ACN_POS 1 /**< SRCC_DMA1ACN Position */
+ #define MXC_F_RPU_SRCC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_DMA1ACN_POS)) /**< SRCC_DMA1ACN Mask */
- #define MXC_F_RPU_DCACHE_USBACN_POS 2 /**< DCACHE_USBACN Position */
- #define MXC_F_RPU_DCACHE_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_USBACN_POS)) /**< DCACHE_USBACN Mask */
+ #define MXC_F_RPU_SRCC_USBACN_POS 2 /**< SRCC_USBACN Position */
+ #define MXC_F_RPU_SRCC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_USBACN_POS)) /**< SRCC_USBACN Mask */
- #define MXC_F_RPU_DCACHE_SYS0ACN_POS 3 /**< DCACHE_SYS0ACN Position */
- #define MXC_F_RPU_DCACHE_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_SYS0ACN_POS)) /**< DCACHE_SYS0ACN Mask */
+ #define MXC_F_RPU_SRCC_SYS0ACN_POS 3 /**< SRCC_SYS0ACN Position */
+ #define MXC_F_RPU_SRCC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SYS0ACN_POS)) /**< SRCC_SYS0ACN Mask */
- #define MXC_F_RPU_DCACHE_SYS1ACN_POS 4 /**< DCACHE_SYS1ACN Position */
- #define MXC_F_RPU_DCACHE_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_SYS1ACN_POS)) /**< DCACHE_SYS1ACN Mask */
+ #define MXC_F_RPU_SRCC_SYS1ACN_POS 4 /**< SRCC_SYS1ACN Position */
+ #define MXC_F_RPU_SRCC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SYS1ACN_POS)) /**< SRCC_SYS1ACN Mask */
- #define MXC_F_RPU_DCACHE_SDMADACN_POS 5 /**< DCACHE_SDMADACN Position */
- #define MXC_F_RPU_DCACHE_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_SDMADACN_POS)) /**< DCACHE_SDMADACN Mask */
+ #define MXC_F_RPU_SRCC_SDMADACN_POS 5 /**< SRCC_SDMADACN Position */
+ #define MXC_F_RPU_SRCC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDMADACN_POS)) /**< SRCC_SDMADACN Mask */
- #define MXC_F_RPU_DCACHE_SDMAIACN_POS 6 /**< DCACHE_SDMAIACN Position */
- #define MXC_F_RPU_DCACHE_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_SDMAIACN_POS)) /**< DCACHE_SDMAIACN Mask */
+ #define MXC_F_RPU_SRCC_SDMAIACN_POS 6 /**< SRCC_SDMAIACN Position */
+ #define MXC_F_RPU_SRCC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDMAIACN_POS)) /**< SRCC_SDMAIACN Mask */
- #define MXC_F_RPU_DCACHE_CRYPTOACN_POS 7 /**< DCACHE_CRYPTOACN Position */
- #define MXC_F_RPU_DCACHE_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_CRYPTOACN_POS)) /**< DCACHE_CRYPTOACN Mask */
+ #define MXC_F_RPU_SRCC_CRYPTOACN_POS 7 /**< SRCC_CRYPTOACN Position */
+ #define MXC_F_RPU_SRCC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_CRYPTOACN_POS)) /**< SRCC_CRYPTOACN Mask */
- #define MXC_F_RPU_DCACHE_SDIOACN_POS 8 /**< DCACHE_SDIOACN Position */
- #define MXC_F_RPU_DCACHE_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_DCACHE_SDIOACN_POS)) /**< DCACHE_SDIOACN Mask */
+ #define MXC_F_RPU_SRCC_SDIOACN_POS 8 /**< SRCC_SDIOACN Position */
+ #define MXC_F_RPU_SRCC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SRCC_SDIOACN_POS)) /**< SRCC_SDIOACN Mask */
-/**@} end of group RPU_DCACHE_Register */
+/**@} end of group RPU_SRCC_Register */
/**
* @ingroup rpu_registers
@@ -1713,73 +1713,73 @@ typedef struct {
/**
* @ingroup rpu_registers
- * @defgroup RPU_SPID RPU_SPID
+ * @defgroup RPU_SPIXR RPU_SPIXR
* @brief SPI Data Controller Protection Register
* @{
*/
- #define MXC_F_RPU_SPID_DMA0ACN_POS 0 /**< SPID_DMA0ACN Position */
- #define MXC_F_RPU_SPID_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_DMA0ACN_POS)) /**< SPID_DMA0ACN Mask */
+ #define MXC_F_RPU_SPIXR_DMA0ACN_POS 0 /**< SPIXR_DMA0ACN Position */
+ #define MXC_F_RPU_SPIXR_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_DMA0ACN_POS)) /**< SPIXR_DMA0ACN Mask */
- #define MXC_F_RPU_SPID_DMA1ACN_POS 1 /**< SPID_DMA1ACN Position */
- #define MXC_F_RPU_SPID_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_DMA1ACN_POS)) /**< SPID_DMA1ACN Mask */
+ #define MXC_F_RPU_SPIXR_DMA1ACN_POS 1 /**< SPIXR_DMA1ACN Position */
+ #define MXC_F_RPU_SPIXR_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_DMA1ACN_POS)) /**< SPIXR_DMA1ACN Mask */
- #define MXC_F_RPU_SPID_USBACN_POS 2 /**< SPID_USBACN Position */
- #define MXC_F_RPU_SPID_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_USBACN_POS)) /**< SPID_USBACN Mask */
+ #define MXC_F_RPU_SPIXR_USBACN_POS 2 /**< SPIXR_USBACN Position */
+ #define MXC_F_RPU_SPIXR_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_USBACN_POS)) /**< SPIXR_USBACN Mask */
- #define MXC_F_RPU_SPID_SYS0ACN_POS 3 /**< SPID_SYS0ACN Position */
- #define MXC_F_RPU_SPID_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_SYS0ACN_POS)) /**< SPID_SYS0ACN Mask */
+ #define MXC_F_RPU_SPIXR_SYS0ACN_POS 3 /**< SPIXR_SYS0ACN Position */
+ #define MXC_F_RPU_SPIXR_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SYS0ACN_POS)) /**< SPIXR_SYS0ACN Mask */
- #define MXC_F_RPU_SPID_SYS1ACN_POS 4 /**< SPID_SYS1ACN Position */
- #define MXC_F_RPU_SPID_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_SYS1ACN_POS)) /**< SPID_SYS1ACN Mask */
+ #define MXC_F_RPU_SPIXR_SYS1ACN_POS 4 /**< SPIXR_SYS1ACN Position */
+ #define MXC_F_RPU_SPIXR_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SYS1ACN_POS)) /**< SPIXR_SYS1ACN Mask */
- #define MXC_F_RPU_SPID_SDMADACN_POS 5 /**< SPID_SDMADACN Position */
- #define MXC_F_RPU_SPID_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_SDMADACN_POS)) /**< SPID_SDMADACN Mask */
+ #define MXC_F_RPU_SPIXR_SDMADACN_POS 5 /**< SPIXR_SDMADACN Position */
+ #define MXC_F_RPU_SPIXR_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SDMADACN_POS)) /**< SPIXR_SDMADACN Mask */
- #define MXC_F_RPU_SPID_SDMAIACN_POS 6 /**< SPID_SDMAIACN Position */
- #define MXC_F_RPU_SPID_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_SDMAIACN_POS)) /**< SPID_SDMAIACN Mask */
+ #define MXC_F_RPU_SPIXR_SDMAIACN_POS 6 /**< SPIXR_SDMAIACN Position */
+ #define MXC_F_RPU_SPIXR_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SDMAIACN_POS)) /**< SPIXR_SDMAIACN Mask */
- #define MXC_F_RPU_SPID_CRYPTOACN_POS 7 /**< SPID_CRYPTOACN Position */
- #define MXC_F_RPU_SPID_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_CRYPTOACN_POS)) /**< SPID_CRYPTOACN Mask */
+ #define MXC_F_RPU_SPIXR_CRYPTOACN_POS 7 /**< SPIXR_CRYPTOACN Position */
+ #define MXC_F_RPU_SPIXR_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_CRYPTOACN_POS)) /**< SPIXR_CRYPTOACN Mask */
- #define MXC_F_RPU_SPID_SDIOACN_POS 8 /**< SPID_SDIOACN Position */
- #define MXC_F_RPU_SPID_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPID_SDIOACN_POS)) /**< SPID_SDIOACN Mask */
+ #define MXC_F_RPU_SPIXR_SDIOACN_POS 8 /**< SPIXR_SDIOACN Position */
+ #define MXC_F_RPU_SPIXR_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXR_SDIOACN_POS)) /**< SPIXR_SDIOACN Mask */
-/**@} end of group RPU_SPID_Register */
+/**@} end of group RPU_SPIXR_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_PT RPU_PT
+ * @defgroup RPU_PTG_BUS0 RPU_PTG_BUS0
* @brief Pulse Train Protection Register
* @{
*/
- #define MXC_F_RPU_PT_DMA0ACN_POS 0 /**< PT_DMA0ACN Position */
- #define MXC_F_RPU_PT_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_DMA0ACN_POS)) /**< PT_DMA0ACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_DMA0ACN_POS 0 /**< PTG_BUS0_DMA0ACN Position */
+ #define MXC_F_RPU_PTG_BUS0_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_DMA0ACN_POS)) /**< PTG_BUS0_DMA0ACN Mask */
- #define MXC_F_RPU_PT_DMA1ACN_POS 1 /**< PT_DMA1ACN Position */
- #define MXC_F_RPU_PT_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_DMA1ACN_POS)) /**< PT_DMA1ACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_DMA1ACN_POS 1 /**< PTG_BUS0_DMA1ACN Position */
+ #define MXC_F_RPU_PTG_BUS0_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_DMA1ACN_POS)) /**< PTG_BUS0_DMA1ACN Mask */
- #define MXC_F_RPU_PT_USBACN_POS 2 /**< PT_USBACN Position */
- #define MXC_F_RPU_PT_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_USBACN_POS)) /**< PT_USBACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_USBACN_POS 2 /**< PTG_BUS0_USBACN Position */
+ #define MXC_F_RPU_PTG_BUS0_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_USBACN_POS)) /**< PTG_BUS0_USBACN Mask */
- #define MXC_F_RPU_PT_SYS0ACN_POS 3 /**< PT_SYS0ACN Position */
- #define MXC_F_RPU_PT_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_SYS0ACN_POS)) /**< PT_SYS0ACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_SYS0ACN_POS 3 /**< PTG_BUS0_SYS0ACN Position */
+ #define MXC_F_RPU_PTG_BUS0_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SYS0ACN_POS)) /**< PTG_BUS0_SYS0ACN Mask */
- #define MXC_F_RPU_PT_SYS1ACN_POS 4 /**< PT_SYS1ACN Position */
- #define MXC_F_RPU_PT_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_SYS1ACN_POS)) /**< PT_SYS1ACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_SYS1ACN_POS 4 /**< PTG_BUS0_SYS1ACN Position */
+ #define MXC_F_RPU_PTG_BUS0_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SYS1ACN_POS)) /**< PTG_BUS0_SYS1ACN Mask */
- #define MXC_F_RPU_PT_SDMADACN_POS 5 /**< PT_SDMADACN Position */
- #define MXC_F_RPU_PT_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_SDMADACN_POS)) /**< PT_SDMADACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_SDMADACN_POS 5 /**< PTG_BUS0_SDMADACN Position */
+ #define MXC_F_RPU_PTG_BUS0_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SDMADACN_POS)) /**< PTG_BUS0_SDMADACN Mask */
- #define MXC_F_RPU_PT_SDMAIACN_POS 6 /**< PT_SDMAIACN Position */
- #define MXC_F_RPU_PT_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_SDMAIACN_POS)) /**< PT_SDMAIACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_SDMAIACN_POS 6 /**< PTG_BUS0_SDMAIACN Position */
+ #define MXC_F_RPU_PTG_BUS0_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SDMAIACN_POS)) /**< PTG_BUS0_SDMAIACN Mask */
- #define MXC_F_RPU_PT_CRYPTOACN_POS 7 /**< PT_CRYPTOACN Position */
- #define MXC_F_RPU_PT_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_CRYPTOACN_POS)) /**< PT_CRYPTOACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_CRYPTOACN_POS 7 /**< PTG_BUS0_CRYPTOACN Position */
+ #define MXC_F_RPU_PTG_BUS0_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_CRYPTOACN_POS)) /**< PTG_BUS0_CRYPTOACN Mask */
- #define MXC_F_RPU_PT_SDIOACN_POS 8 /**< PT_SDIOACN Position */
- #define MXC_F_RPU_PT_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_PT_SDIOACN_POS)) /**< PT_SDIOACN Mask */
+ #define MXC_F_RPU_PTG_BUS0_SDIOACN_POS 8 /**< PTG_BUS0_SDIOACN Position */
+ #define MXC_F_RPU_PTG_BUS0_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_PTG_BUS0_SDIOACN_POS)) /**< PTG_BUS0_SDIOACN Mask */
-/**@} end of group RPU_PT_Register */
+/**@} end of group RPU_PTG_BUS0_Register */
/**
* @ingroup rpu_registers
@@ -1958,73 +1958,73 @@ typedef struct {
/**
* @ingroup rpu_registers
- * @defgroup RPU_QSPI1 RPU_QSPI1
+ * @defgroup RPU_SPI1 RPU_SPI1
* @brief QSPI1 Protection Register
* @{
*/
- #define MXC_F_RPU_QSPI1_DMA0ACN_POS 0 /**< QSPI1_DMA0ACN Position */
- #define MXC_F_RPU_QSPI1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_DMA0ACN_POS)) /**< QSPI1_DMA0ACN Mask */
+ #define MXC_F_RPU_SPI1_DMA0ACN_POS 0 /**< SPI1_DMA0ACN Position */
+ #define MXC_F_RPU_SPI1_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_DMA0ACN_POS)) /**< SPI1_DMA0ACN Mask */
- #define MXC_F_RPU_QSPI1_DMA1ACN_POS 1 /**< QSPI1_DMA1ACN Position */
- #define MXC_F_RPU_QSPI1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_DMA1ACN_POS)) /**< QSPI1_DMA1ACN Mask */
+ #define MXC_F_RPU_SPI1_DMA1ACN_POS 1 /**< SPI1_DMA1ACN Position */
+ #define MXC_F_RPU_SPI1_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_DMA1ACN_POS)) /**< SPI1_DMA1ACN Mask */
- #define MXC_F_RPU_QSPI1_USBACN_POS 2 /**< QSPI1_USBACN Position */
- #define MXC_F_RPU_QSPI1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_USBACN_POS)) /**< QSPI1_USBACN Mask */
+ #define MXC_F_RPU_SPI1_USBACN_POS 2 /**< SPI1_USBACN Position */
+ #define MXC_F_RPU_SPI1_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_USBACN_POS)) /**< SPI1_USBACN Mask */
- #define MXC_F_RPU_QSPI1_SYS0ACN_POS 3 /**< QSPI1_SYS0ACN Position */
- #define MXC_F_RPU_QSPI1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SYS0ACN_POS)) /**< QSPI1_SYS0ACN Mask */
+ #define MXC_F_RPU_SPI1_SYS0ACN_POS 3 /**< SPI1_SYS0ACN Position */
+ #define MXC_F_RPU_SPI1_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SYS0ACN_POS)) /**< SPI1_SYS0ACN Mask */
- #define MXC_F_RPU_QSPI1_SYS1ACN_POS 4 /**< QSPI1_SYS1ACN Position */
- #define MXC_F_RPU_QSPI1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SYS1ACN_POS)) /**< QSPI1_SYS1ACN Mask */
+ #define MXC_F_RPU_SPI1_SYS1ACN_POS 4 /**< SPI1_SYS1ACN Position */
+ #define MXC_F_RPU_SPI1_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SYS1ACN_POS)) /**< SPI1_SYS1ACN Mask */
- #define MXC_F_RPU_QSPI1_SDMADACN_POS 5 /**< QSPI1_SDMADACN Position */
- #define MXC_F_RPU_QSPI1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SDMADACN_POS)) /**< QSPI1_SDMADACN Mask */
+ #define MXC_F_RPU_SPI1_SDMADACN_POS 5 /**< SPI1_SDMADACN Position */
+ #define MXC_F_RPU_SPI1_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SDMADACN_POS)) /**< SPI1_SDMADACN Mask */
- #define MXC_F_RPU_QSPI1_SDMAIACN_POS 6 /**< QSPI1_SDMAIACN Position */
- #define MXC_F_RPU_QSPI1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SDMAIACN_POS)) /**< QSPI1_SDMAIACN Mask */
+ #define MXC_F_RPU_SPI1_SDMAIACN_POS 6 /**< SPI1_SDMAIACN Position */
+ #define MXC_F_RPU_SPI1_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SDMAIACN_POS)) /**< SPI1_SDMAIACN Mask */
- #define MXC_F_RPU_QSPI1_CRYPTOACN_POS 7 /**< QSPI1_CRYPTOACN Position */
- #define MXC_F_RPU_QSPI1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_CRYPTOACN_POS)) /**< QSPI1_CRYPTOACN Mask */
+ #define MXC_F_RPU_SPI1_CRYPTOACN_POS 7 /**< SPI1_CRYPTOACN Position */
+ #define MXC_F_RPU_SPI1_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_CRYPTOACN_POS)) /**< SPI1_CRYPTOACN Mask */
- #define MXC_F_RPU_QSPI1_SDIOACN_POS 8 /**< QSPI1_SDIOACN Position */
- #define MXC_F_RPU_QSPI1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI1_SDIOACN_POS)) /**< QSPI1_SDIOACN Mask */
+ #define MXC_F_RPU_SPI1_SDIOACN_POS 8 /**< SPI1_SDIOACN Position */
+ #define MXC_F_RPU_SPI1_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI1_SDIOACN_POS)) /**< SPI1_SDIOACN Mask */
-/**@} end of group RPU_QSPI1_Register */
+/**@} end of group RPU_SPI1_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_QSPI2 RPU_QSPI2
+ * @defgroup RPU_SPI2 RPU_SPI2
* @brief QSPI2 Protection Register
* @{
*/
- #define MXC_F_RPU_QSPI2_DMA0ACN_POS 0 /**< QSPI2_DMA0ACN Position */
- #define MXC_F_RPU_QSPI2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_DMA0ACN_POS)) /**< QSPI2_DMA0ACN Mask */
+ #define MXC_F_RPU_SPI2_DMA0ACN_POS 0 /**< SPI2_DMA0ACN Position */
+ #define MXC_F_RPU_SPI2_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_DMA0ACN_POS)) /**< SPI2_DMA0ACN Mask */
- #define MXC_F_RPU_QSPI2_DMA1ACN_POS 1 /**< QSPI2_DMA1ACN Position */
- #define MXC_F_RPU_QSPI2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_DMA1ACN_POS)) /**< QSPI2_DMA1ACN Mask */
+ #define MXC_F_RPU_SPI2_DMA1ACN_POS 1 /**< SPI2_DMA1ACN Position */
+ #define MXC_F_RPU_SPI2_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_DMA1ACN_POS)) /**< SPI2_DMA1ACN Mask */
- #define MXC_F_RPU_QSPI2_USBACN_POS 2 /**< QSPI2_USBACN Position */
- #define MXC_F_RPU_QSPI2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_USBACN_POS)) /**< QSPI2_USBACN Mask */
+ #define MXC_F_RPU_SPI2_USBACN_POS 2 /**< SPI2_USBACN Position */
+ #define MXC_F_RPU_SPI2_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_USBACN_POS)) /**< SPI2_USBACN Mask */
- #define MXC_F_RPU_QSPI2_SYS0ACN_POS 3 /**< QSPI2_SYS0ACN Position */
- #define MXC_F_RPU_QSPI2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SYS0ACN_POS)) /**< QSPI2_SYS0ACN Mask */
+ #define MXC_F_RPU_SPI2_SYS0ACN_POS 3 /**< SPI2_SYS0ACN Position */
+ #define MXC_F_RPU_SPI2_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SYS0ACN_POS)) /**< SPI2_SYS0ACN Mask */
- #define MXC_F_RPU_QSPI2_SYS1ACN_POS 4 /**< QSPI2_SYS1ACN Position */
- #define MXC_F_RPU_QSPI2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SYS1ACN_POS)) /**< QSPI2_SYS1ACN Mask */
+ #define MXC_F_RPU_SPI2_SYS1ACN_POS 4 /**< SPI2_SYS1ACN Position */
+ #define MXC_F_RPU_SPI2_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SYS1ACN_POS)) /**< SPI2_SYS1ACN Mask */
- #define MXC_F_RPU_QSPI2_SDMADACN_POS 5 /**< QSPI2_SDMADACN Position */
- #define MXC_F_RPU_QSPI2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SDMADACN_POS)) /**< QSPI2_SDMADACN Mask */
+ #define MXC_F_RPU_SPI2_SDMADACN_POS 5 /**< SPI2_SDMADACN Position */
+ #define MXC_F_RPU_SPI2_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDMADACN_POS)) /**< SPI2_SDMADACN Mask */
- #define MXC_F_RPU_QSPI2_SDMAIACN_POS 6 /**< QSPI2_SDMAIACN Position */
- #define MXC_F_RPU_QSPI2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SDMAIACN_POS)) /**< QSPI2_SDMAIACN Mask */
+ #define MXC_F_RPU_SPI2_SDMAIACN_POS 6 /**< SPI2_SDMAIACN Position */
+ #define MXC_F_RPU_SPI2_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDMAIACN_POS)) /**< SPI2_SDMAIACN Mask */
- #define MXC_F_RPU_QSPI2_CRYPTOACN_POS 7 /**< QSPI2_CRYPTOACN Position */
- #define MXC_F_RPU_QSPI2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_CRYPTOACN_POS)) /**< QSPI2_CRYPTOACN Mask */
+ #define MXC_F_RPU_SPI2_CRYPTOACN_POS 7 /**< SPI2_CRYPTOACN Position */
+ #define MXC_F_RPU_SPI2_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_CRYPTOACN_POS)) /**< SPI2_CRYPTOACN Mask */
- #define MXC_F_RPU_QSPI2_SDIOACN_POS 8 /**< QSPI2_SDIOACN Position */
- #define MXC_F_RPU_QSPI2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_QSPI2_SDIOACN_POS)) /**< QSPI2_SDIOACN Mask */
+ #define MXC_F_RPU_SPI2_SDIOACN_POS 8 /**< SPI2_SDIOACN Position */
+ #define MXC_F_RPU_SPI2_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPI2_SDIOACN_POS)) /**< SPI2_SDIOACN Mask */
-/**@} end of group RPU_QSPI2_Register */
+/**@} end of group RPU_SPI2_Register */
/**
* @ingroup rpu_registers
@@ -2257,561 +2257,561 @@ typedef struct {
/**
* @ingroup rpu_registers
- * @defgroup RPU_SPIXIPMFIFO RPU_SPIXIPMFIFO
+ * @defgroup RPU_SPIXM_FIFO RPU_SPIXM_FIFO
* @brief SPI XIP Master FIFO Protection Register
* @{
*/
- #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNR_POS 0 /**< SPIXIPMFIFO_DMA0ACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_DMA0ACNR_POS)) /**< SPIXIPMFIFO_DMA0ACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS 0 /**< SPIXM_FIFO_DMA0ACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA0ACNR_POS)) /**< SPIXM_FIFO_DMA0ACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNW_POS 1 /**< SPIXIPMFIFO_DMA0ACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_DMA0ACNW_POS)) /**< SPIXIPMFIFO_DMA0ACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS 1 /**< SPIXM_FIFO_DMA0ACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA0ACNW_POS)) /**< SPIXM_FIFO_DMA0ACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNR_POS 2 /**< SPIXIPMFIFO_DMA1ACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_DMA1ACNR_POS)) /**< SPIXIPMFIFO_DMA1ACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS 2 /**< SPIXM_FIFO_DMA1ACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA1ACNR_POS)) /**< SPIXM_FIFO_DMA1ACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNW_POS 3 /**< SPIXIPMFIFO_DMA1ACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_DMA1ACNW_POS)) /**< SPIXIPMFIFO_DMA1ACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS 3 /**< SPIXM_FIFO_DMA1ACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_DMA1ACNW_POS)) /**< SPIXM_FIFO_DMA1ACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_USBACNR_POS 4 /**< SPIXIPMFIFO_USBACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_USBACNR_POS)) /**< SPIXIPMFIFO_USBACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_USBACNR_POS 4 /**< SPIXM_FIFO_USBACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_USBACNR_POS)) /**< SPIXM_FIFO_USBACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_USBACNW_POS 5 /**< SPIXIPMFIFO_USBACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_USBACNW_POS)) /**< SPIXIPMFIFO_USBACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_USBACNW_POS 5 /**< SPIXM_FIFO_USBACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_USBACNW_POS)) /**< SPIXM_FIFO_USBACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNR_POS 6 /**< SPIXIPMFIFO_SYS0ACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SYS0ACNR_POS)) /**< SPIXIPMFIFO_SYS0ACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS 6 /**< SPIXM_FIFO_SYS0ACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS0ACNR_POS)) /**< SPIXM_FIFO_SYS0ACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNW_POS 7 /**< SPIXIPMFIFO_SYS0ACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SYS0ACNW_POS)) /**< SPIXIPMFIFO_SYS0ACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS 7 /**< SPIXM_FIFO_SYS0ACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS0ACNW_POS)) /**< SPIXM_FIFO_SYS0ACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNR_POS 8 /**< SPIXIPMFIFO_SYS1ACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SYS1ACNR_POS)) /**< SPIXIPMFIFO_SYS1ACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS 8 /**< SPIXM_FIFO_SYS1ACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS1ACNR_POS)) /**< SPIXM_FIFO_SYS1ACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNW_POS 9 /**< SPIXIPMFIFO_SYS1ACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SYS1ACNW_POS)) /**< SPIXIPMFIFO_SYS1ACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS 9 /**< SPIXM_FIFO_SYS1ACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SYS1ACNW_POS)) /**< SPIXM_FIFO_SYS1ACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNR_POS 10 /**< SPIXIPMFIFO_SDMADACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SDMADACNR_POS)) /**< SPIXIPMFIFO_SDMADACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS 10 /**< SPIXM_FIFO_SDMADACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMADACNR_POS)) /**< SPIXM_FIFO_SDMADACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNW_POS 11 /**< SPIXIPMFIFO_SDMADACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SDMADACNW_POS)) /**< SPIXIPMFIFO_SDMADACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS 11 /**< SPIXM_FIFO_SDMADACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMADACNW_POS)) /**< SPIXM_FIFO_SDMADACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNR_POS 12 /**< SPIXIPMFIFO_SDMAIACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SDMAIACNR_POS)) /**< SPIXIPMFIFO_SDMAIACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS 12 /**< SPIXM_FIFO_SDMAIACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMAIACNR_POS)) /**< SPIXM_FIFO_SDMAIACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNW_POS 13 /**< SPIXIPMFIFO_SDMAIACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SDMAIACNW_POS)) /**< SPIXIPMFIFO_SDMAIACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS 13 /**< SPIXM_FIFO_SDMAIACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDMAIACNW_POS)) /**< SPIXM_FIFO_SDMAIACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNR_POS 14 /**< SPIXIPMFIFO_CRYPTOACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNR_POS)) /**< SPIXIPMFIFO_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS 14 /**< SPIXM_FIFO_CRYPTOACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_CRYPTOACNR_POS)) /**< SPIXM_FIFO_CRYPTOACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNW_POS 15 /**< SPIXIPMFIFO_CRYPTOACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_CRYPTOACNW_POS)) /**< SPIXIPMFIFO_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS 15 /**< SPIXM_FIFO_CRYPTOACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_CRYPTOACNW_POS)) /**< SPIXM_FIFO_CRYPTOACNW Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNR_POS 16 /**< SPIXIPMFIFO_SDIOACNR Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SDIOACNR_POS)) /**< SPIXIPMFIFO_SDIOACNR Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS 16 /**< SPIXM_FIFO_SDIOACNR Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDIOACNR_POS)) /**< SPIXM_FIFO_SDIOACNR Mask */
- #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNW_POS 17 /**< SPIXIPMFIFO_SDIOACNW Position */
- #define MXC_F_RPU_SPIXIPMFIFO_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMFIFO_SDIOACNW_POS)) /**< SPIXIPMFIFO_SDIOACNW Mask */
+ #define MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS 17 /**< SPIXM_FIFO_SDIOACNW Position */
+ #define MXC_F_RPU_SPIXM_FIFO_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPIXM_FIFO_SDIOACNW_POS)) /**< SPIXM_FIFO_SDIOACNW Mask */
-/**@} end of group RPU_SPIXIPMFIFO_Register */
+/**@} end of group RPU_SPIXM_FIFO_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_QSPI0 RPU_QSPI0
+ * @defgroup RPU_SPI0 RPU_SPI0
* @brief QSPI0 Protection Register
* @{
*/
- #define MXC_F_RPU_QSPI0_DMA0ACNR_POS 0 /**< QSPI0_DMA0ACNR Position */
- #define MXC_F_RPU_QSPI0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_DMA0ACNR_POS)) /**< QSPI0_DMA0ACNR Mask */
+ #define MXC_F_RPU_SPI0_DMA0ACNR_POS 0 /**< SPI0_DMA0ACNR Position */
+ #define MXC_F_RPU_SPI0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNR_POS)) /**< SPI0_DMA0ACNR Mask */
- #define MXC_F_RPU_QSPI0_DMA0ACNW_POS 1 /**< QSPI0_DMA0ACNW Position */
- #define MXC_F_RPU_QSPI0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_DMA0ACNW_POS)) /**< QSPI0_DMA0ACNW Mask */
+ #define MXC_F_RPU_SPI0_DMA0ACNW_POS 1 /**< SPI0_DMA0ACNW Position */
+ #define MXC_F_RPU_SPI0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA0ACNW_POS)) /**< SPI0_DMA0ACNW Mask */
- #define MXC_F_RPU_QSPI0_DMA1ACNR_POS 2 /**< QSPI0_DMA1ACNR Position */
- #define MXC_F_RPU_QSPI0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_DMA1ACNR_POS)) /**< QSPI0_DMA1ACNR Mask */
+ #define MXC_F_RPU_SPI0_DMA1ACNR_POS 2 /**< SPI0_DMA1ACNR Position */
+ #define MXC_F_RPU_SPI0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNR_POS)) /**< SPI0_DMA1ACNR Mask */
- #define MXC_F_RPU_QSPI0_DMA1ACNW_POS 3 /**< QSPI0_DMA1ACNW Position */
- #define MXC_F_RPU_QSPI0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_DMA1ACNW_POS)) /**< QSPI0_DMA1ACNW Mask */
+ #define MXC_F_RPU_SPI0_DMA1ACNW_POS 3 /**< SPI0_DMA1ACNW Position */
+ #define MXC_F_RPU_SPI0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_DMA1ACNW_POS)) /**< SPI0_DMA1ACNW Mask */
- #define MXC_F_RPU_QSPI0_USBACNR_POS 4 /**< QSPI0_USBACNR Position */
- #define MXC_F_RPU_QSPI0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_USBACNR_POS)) /**< QSPI0_USBACNR Mask */
+ #define MXC_F_RPU_SPI0_USBACNR_POS 4 /**< SPI0_USBACNR Position */
+ #define MXC_F_RPU_SPI0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNR_POS)) /**< SPI0_USBACNR Mask */
- #define MXC_F_RPU_QSPI0_USBACNW_POS 5 /**< QSPI0_USBACNW Position */
- #define MXC_F_RPU_QSPI0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_USBACNW_POS)) /**< QSPI0_USBACNW Mask */
+ #define MXC_F_RPU_SPI0_USBACNW_POS 5 /**< SPI0_USBACNW Position */
+ #define MXC_F_RPU_SPI0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_USBACNW_POS)) /**< SPI0_USBACNW Mask */
- #define MXC_F_RPU_QSPI0_SYS0ACNR_POS 6 /**< QSPI0_SYS0ACNR Position */
- #define MXC_F_RPU_QSPI0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SYS0ACNR_POS)) /**< QSPI0_SYS0ACNR Mask */
+ #define MXC_F_RPU_SPI0_SYS0ACNR_POS 6 /**< SPI0_SYS0ACNR Position */
+ #define MXC_F_RPU_SPI0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNR_POS)) /**< SPI0_SYS0ACNR Mask */
- #define MXC_F_RPU_QSPI0_SYS0ACNW_POS 7 /**< QSPI0_SYS0ACNW Position */
- #define MXC_F_RPU_QSPI0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SYS0ACNW_POS)) /**< QSPI0_SYS0ACNW Mask */
+ #define MXC_F_RPU_SPI0_SYS0ACNW_POS 7 /**< SPI0_SYS0ACNW Position */
+ #define MXC_F_RPU_SPI0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS0ACNW_POS)) /**< SPI0_SYS0ACNW Mask */
- #define MXC_F_RPU_QSPI0_SYS1ACNR_POS 8 /**< QSPI0_SYS1ACNR Position */
- #define MXC_F_RPU_QSPI0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SYS1ACNR_POS)) /**< QSPI0_SYS1ACNR Mask */
+ #define MXC_F_RPU_SPI0_SYS1ACNR_POS 8 /**< SPI0_SYS1ACNR Position */
+ #define MXC_F_RPU_SPI0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNR_POS)) /**< SPI0_SYS1ACNR Mask */
- #define MXC_F_RPU_QSPI0_SYS1ACNW_POS 9 /**< QSPI0_SYS1ACNW Position */
- #define MXC_F_RPU_QSPI0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SYS1ACNW_POS)) /**< QSPI0_SYS1ACNW Mask */
+ #define MXC_F_RPU_SPI0_SYS1ACNW_POS 9 /**< SPI0_SYS1ACNW Position */
+ #define MXC_F_RPU_SPI0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SYS1ACNW_POS)) /**< SPI0_SYS1ACNW Mask */
- #define MXC_F_RPU_QSPI0_SDMADACNR_POS 10 /**< QSPI0_SDMADACNR Position */
- #define MXC_F_RPU_QSPI0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SDMADACNR_POS)) /**< QSPI0_SDMADACNR Mask */
+ #define MXC_F_RPU_SPI0_SDMADACNR_POS 10 /**< SPI0_SDMADACNR Position */
+ #define MXC_F_RPU_SPI0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNR_POS)) /**< SPI0_SDMADACNR Mask */
- #define MXC_F_RPU_QSPI0_SDMADACNW_POS 11 /**< QSPI0_SDMADACNW Position */
- #define MXC_F_RPU_QSPI0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SDMADACNW_POS)) /**< QSPI0_SDMADACNW Mask */
+ #define MXC_F_RPU_SPI0_SDMADACNW_POS 11 /**< SPI0_SDMADACNW Position */
+ #define MXC_F_RPU_SPI0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMADACNW_POS)) /**< SPI0_SDMADACNW Mask */
- #define MXC_F_RPU_QSPI0_SDMAIACNR_POS 12 /**< QSPI0_SDMAIACNR Position */
- #define MXC_F_RPU_QSPI0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SDMAIACNR_POS)) /**< QSPI0_SDMAIACNR Mask */
+ #define MXC_F_RPU_SPI0_SDMAIACNR_POS 12 /**< SPI0_SDMAIACNR Position */
+ #define MXC_F_RPU_SPI0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNR_POS)) /**< SPI0_SDMAIACNR Mask */
- #define MXC_F_RPU_QSPI0_SDMAIACNW_POS 13 /**< QSPI0_SDMAIACNW Position */
- #define MXC_F_RPU_QSPI0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SDMAIACNW_POS)) /**< QSPI0_SDMAIACNW Mask */
+ #define MXC_F_RPU_SPI0_SDMAIACNW_POS 13 /**< SPI0_SDMAIACNW Position */
+ #define MXC_F_RPU_SPI0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDMAIACNW_POS)) /**< SPI0_SDMAIACNW Mask */
- #define MXC_F_RPU_QSPI0_CRYPTOACNR_POS 14 /**< QSPI0_CRYPTOACNR Position */
- #define MXC_F_RPU_QSPI0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_CRYPTOACNR_POS)) /**< QSPI0_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SPI0_CRYPTOACNR_POS 14 /**< SPI0_CRYPTOACNR Position */
+ #define MXC_F_RPU_SPI0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNR_POS)) /**< SPI0_CRYPTOACNR Mask */
- #define MXC_F_RPU_QSPI0_CRYPTOACNW_POS 15 /**< QSPI0_CRYPTOACNW Position */
- #define MXC_F_RPU_QSPI0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_CRYPTOACNW_POS)) /**< QSPI0_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SPI0_CRYPTOACNW_POS 15 /**< SPI0_CRYPTOACNW Position */
+ #define MXC_F_RPU_SPI0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_CRYPTOACNW_POS)) /**< SPI0_CRYPTOACNW Mask */
- #define MXC_F_RPU_QSPI0_SDIOACNR_POS 16 /**< QSPI0_SDIOACNR Position */
- #define MXC_F_RPU_QSPI0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SDIOACNR_POS)) /**< QSPI0_SDIOACNR Mask */
+ #define MXC_F_RPU_SPI0_SDIOACNR_POS 16 /**< SPI0_SDIOACNR Position */
+ #define MXC_F_RPU_SPI0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNR_POS)) /**< SPI0_SDIOACNR Mask */
- #define MXC_F_RPU_QSPI0_SDIOACNW_POS 17 /**< QSPI0_SDIOACNW Position */
- #define MXC_F_RPU_QSPI0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_QSPI0_SDIOACNW_POS)) /**< QSPI0_SDIOACNW Mask */
+ #define MXC_F_RPU_SPI0_SDIOACNW_POS 17 /**< SPI0_SDIOACNW Position */
+ #define MXC_F_RPU_SPI0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SPI0_SDIOACNW_POS)) /**< SPI0_SDIOACNW Mask */
-/**@} end of group RPU_QSPI0_Register */
+/**@} end of group RPU_SPI0_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM0 RPU_SRAM0
- * @brief SRAM0 Protection Register
+ * @defgroup RPU_SYSRAM0 RPU_SYSRAM0
+ * @brief SYSRAM0 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM0_DMA0ACNR_POS 0 /**< SRAM0_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA0ACNR_POS)) /**< SRAM0_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_DMA0ACNR_POS 0 /**< SYSRAM0_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM0_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA0ACNR_POS)) /**< SYSRAM0_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM0_DMA0ACNW_POS 1 /**< SRAM0_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA0ACNW_POS)) /**< SRAM0_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_DMA0ACNW_POS 1 /**< SYSRAM0_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM0_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA0ACNW_POS)) /**< SYSRAM0_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM0_DMA1ACNR_POS 2 /**< SRAM0_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA1ACNR_POS)) /**< SRAM0_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_DMA1ACNR_POS 2 /**< SYSRAM0_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM0_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA1ACNR_POS)) /**< SYSRAM0_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM0_DMA1ACNW_POS 3 /**< SRAM0_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_DMA1ACNW_POS)) /**< SRAM0_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_DMA1ACNW_POS 3 /**< SYSRAM0_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM0_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_DMA1ACNW_POS)) /**< SYSRAM0_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM0_USBACNR_POS 4 /**< SRAM0_USBACNR Position */
- #define MXC_F_RPU_SRAM0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_USBACNR_POS)) /**< SRAM0_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_USBACNR_POS 4 /**< SYSRAM0_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM0_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_USBACNR_POS)) /**< SYSRAM0_USBACNR Mask */
- #define MXC_F_RPU_SRAM0_USBACNW_POS 5 /**< SRAM0_USBACNW Position */
- #define MXC_F_RPU_SRAM0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_USBACNW_POS)) /**< SRAM0_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_USBACNW_POS 5 /**< SYSRAM0_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM0_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_USBACNW_POS)) /**< SYSRAM0_USBACNW Mask */
- #define MXC_F_RPU_SRAM0_SYS0ACNR_POS 6 /**< SRAM0_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS0ACNR_POS)) /**< SRAM0_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_SYS0ACNR_POS 6 /**< SYSRAM0_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM0_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS0ACNR_POS)) /**< SYSRAM0_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM0_SYS0ACNW_POS 7 /**< SRAM0_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS0ACNW_POS)) /**< SRAM0_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_SYS0ACNW_POS 7 /**< SYSRAM0_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM0_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS0ACNW_POS)) /**< SYSRAM0_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM0_SYS1ACNR_POS 8 /**< SRAM0_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS1ACNR_POS)) /**< SRAM0_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_SYS1ACNR_POS 8 /**< SYSRAM0_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM0_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS1ACNR_POS)) /**< SYSRAM0_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM0_SYS1ACNW_POS 9 /**< SRAM0_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SYS1ACNW_POS)) /**< SRAM0_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_SYS1ACNW_POS 9 /**< SYSRAM0_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM0_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SYS1ACNW_POS)) /**< SYSRAM0_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM0_SDMADACNR_POS 10 /**< SRAM0_SDMADACNR Position */
- #define MXC_F_RPU_SRAM0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMADACNR_POS)) /**< SRAM0_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_SDMADACNR_POS 10 /**< SYSRAM0_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM0_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMADACNR_POS)) /**< SYSRAM0_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM0_SDMADACNW_POS 11 /**< SRAM0_SDMADACNW Position */
- #define MXC_F_RPU_SRAM0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMADACNW_POS)) /**< SRAM0_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_SDMADACNW_POS 11 /**< SYSRAM0_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM0_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMADACNW_POS)) /**< SYSRAM0_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM0_SDMAIACNR_POS 12 /**< SRAM0_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMAIACNR_POS)) /**< SRAM0_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_SDMAIACNR_POS 12 /**< SYSRAM0_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM0_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMAIACNR_POS)) /**< SYSRAM0_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM0_SDMAIACNW_POS 13 /**< SRAM0_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDMAIACNW_POS)) /**< SRAM0_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_SDMAIACNW_POS 13 /**< SYSRAM0_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM0_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDMAIACNW_POS)) /**< SYSRAM0_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM0_CRYPTOACNR_POS 14 /**< SRAM0_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_CRYPTOACNR_POS)) /**< SRAM0_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_CRYPTOACNR_POS 14 /**< SYSRAM0_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM0_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_CRYPTOACNR_POS)) /**< SYSRAM0_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM0_CRYPTOACNW_POS 15 /**< SRAM0_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_CRYPTOACNW_POS)) /**< SRAM0_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_CRYPTOACNW_POS 15 /**< SYSRAM0_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM0_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_CRYPTOACNW_POS)) /**< SYSRAM0_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM0_SDIOACNR_POS 16 /**< SRAM0_SDIOACNR Position */
- #define MXC_F_RPU_SRAM0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDIOACNR_POS)) /**< SRAM0_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM0_SDIOACNR_POS 16 /**< SYSRAM0_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM0_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDIOACNR_POS)) /**< SYSRAM0_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM0_SDIOACNW_POS 17 /**< SRAM0_SDIOACNW Position */
- #define MXC_F_RPU_SRAM0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM0_SDIOACNW_POS)) /**< SRAM0_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM0_SDIOACNW_POS 17 /**< SYSRAM0_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM0_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM0_SDIOACNW_POS)) /**< SYSRAM0_SDIOACNW Mask */
-/**@} end of group RPU_SRAM0_Register */
+/**@} end of group RPU_SYSRAM0_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM1 RPU_SRAM1
- * @brief SRAM1 Protection Register
+ * @defgroup RPU_SYSRAM1 RPU_SYSRAM1
+ * @brief SYSRAM1 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM1_DMA0ACNR_POS 0 /**< SRAM1_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM1_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_DMA0ACNR_POS)) /**< SRAM1_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_DMA0ACNR_POS 0 /**< SYSRAM1_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM1_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA0ACNR_POS)) /**< SYSRAM1_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM1_DMA0ACNW_POS 1 /**< SRAM1_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM1_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_DMA0ACNW_POS)) /**< SRAM1_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_DMA0ACNW_POS 1 /**< SYSRAM1_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM1_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA0ACNW_POS)) /**< SYSRAM1_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM1_DMA1ACNR_POS 2 /**< SRAM1_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM1_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_DMA1ACNR_POS)) /**< SRAM1_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_DMA1ACNR_POS 2 /**< SYSRAM1_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM1_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA1ACNR_POS)) /**< SYSRAM1_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM1_DMA1ACNW_POS 3 /**< SRAM1_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM1_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_DMA1ACNW_POS)) /**< SRAM1_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_DMA1ACNW_POS 3 /**< SYSRAM1_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM1_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_DMA1ACNW_POS)) /**< SYSRAM1_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM1_USBACNR_POS 4 /**< SRAM1_USBACNR Position */
- #define MXC_F_RPU_SRAM1_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_USBACNR_POS)) /**< SRAM1_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_USBACNR_POS 4 /**< SYSRAM1_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM1_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_USBACNR_POS)) /**< SYSRAM1_USBACNR Mask */
- #define MXC_F_RPU_SRAM1_USBACNW_POS 5 /**< SRAM1_USBACNW Position */
- #define MXC_F_RPU_SRAM1_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_USBACNW_POS)) /**< SRAM1_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_USBACNW_POS 5 /**< SYSRAM1_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM1_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_USBACNW_POS)) /**< SYSRAM1_USBACNW Mask */
- #define MXC_F_RPU_SRAM1_SYS0ACNR_POS 6 /**< SRAM1_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM1_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SYS0ACNR_POS)) /**< SRAM1_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_SYS0ACNR_POS 6 /**< SYSRAM1_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM1_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS0ACNR_POS)) /**< SYSRAM1_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM1_SYS0ACNW_POS 7 /**< SRAM1_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM1_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SYS0ACNW_POS)) /**< SRAM1_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_SYS0ACNW_POS 7 /**< SYSRAM1_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM1_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS0ACNW_POS)) /**< SYSRAM1_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM1_SYS1ACNR_POS 8 /**< SRAM1_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM1_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SYS1ACNR_POS)) /**< SRAM1_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_SYS1ACNR_POS 8 /**< SYSRAM1_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM1_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS1ACNR_POS)) /**< SYSRAM1_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM1_SYS1ACNW_POS 9 /**< SRAM1_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM1_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SYS1ACNW_POS)) /**< SRAM1_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_SYS1ACNW_POS 9 /**< SYSRAM1_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM1_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SYS1ACNW_POS)) /**< SYSRAM1_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM1_SDMADACNR_POS 10 /**< SRAM1_SDMADACNR Position */
- #define MXC_F_RPU_SRAM1_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SDMADACNR_POS)) /**< SRAM1_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_SDMADACNR_POS 10 /**< SYSRAM1_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM1_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMADACNR_POS)) /**< SYSRAM1_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM1_SDMADACNW_POS 11 /**< SRAM1_SDMADACNW Position */
- #define MXC_F_RPU_SRAM1_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SDMADACNW_POS)) /**< SRAM1_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_SDMADACNW_POS 11 /**< SYSRAM1_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM1_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMADACNW_POS)) /**< SYSRAM1_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM1_SDMAIACNR_POS 12 /**< SRAM1_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM1_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SDMAIACNR_POS)) /**< SRAM1_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_SDMAIACNR_POS 12 /**< SYSRAM1_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM1_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMAIACNR_POS)) /**< SYSRAM1_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM1_SDMAIACNW_POS 13 /**< SRAM1_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM1_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SDMAIACNW_POS)) /**< SRAM1_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_SDMAIACNW_POS 13 /**< SYSRAM1_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM1_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDMAIACNW_POS)) /**< SYSRAM1_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM1_CRYPTOACNR_POS 14 /**< SRAM1_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM1_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_CRYPTOACNR_POS)) /**< SRAM1_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_CRYPTOACNR_POS 14 /**< SYSRAM1_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM1_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_CRYPTOACNR_POS)) /**< SYSRAM1_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM1_CRYPTOACNW_POS 15 /**< SRAM1_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM1_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_CRYPTOACNW_POS)) /**< SRAM1_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_CRYPTOACNW_POS 15 /**< SYSRAM1_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM1_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_CRYPTOACNW_POS)) /**< SYSRAM1_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM1_SDIOACNR_POS 16 /**< SRAM1_SDIOACNR Position */
- #define MXC_F_RPU_SRAM1_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SDIOACNR_POS)) /**< SRAM1_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM1_SDIOACNR_POS 16 /**< SYSRAM1_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM1_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDIOACNR_POS)) /**< SYSRAM1_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM1_SDIOACNW_POS 17 /**< SRAM1_SDIOACNW Position */
- #define MXC_F_RPU_SRAM1_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM1_SDIOACNW_POS)) /**< SRAM1_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM1_SDIOACNW_POS 17 /**< SYSRAM1_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM1_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM1_SDIOACNW_POS)) /**< SYSRAM1_SDIOACNW Mask */
-/**@} end of group RPU_SRAM1_Register */
+/**@} end of group RPU_SYSRAM1_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM2 RPU_SRAM2
- * @brief SRAM2 Protection Register
+ * @defgroup RPU_SYSRAM2 RPU_SYSRAM2
+ * @brief SYSRAM2 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM2_DMA0ACNR_POS 0 /**< SRAM2_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM2_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_DMA0ACNR_POS)) /**< SRAM2_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_DMA0ACNR_POS 0 /**< SYSRAM2_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM2_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA0ACNR_POS)) /**< SYSRAM2_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM2_DMA0ACNW_POS 1 /**< SRAM2_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM2_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_DMA0ACNW_POS)) /**< SRAM2_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_DMA0ACNW_POS 1 /**< SYSRAM2_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM2_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA0ACNW_POS)) /**< SYSRAM2_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM2_DMA1ACNR_POS 2 /**< SRAM2_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM2_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_DMA1ACNR_POS)) /**< SRAM2_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_DMA1ACNR_POS 2 /**< SYSRAM2_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM2_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA1ACNR_POS)) /**< SYSRAM2_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM2_DMA1ACNW_POS 3 /**< SRAM2_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM2_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_DMA1ACNW_POS)) /**< SRAM2_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_DMA1ACNW_POS 3 /**< SYSRAM2_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM2_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_DMA1ACNW_POS)) /**< SYSRAM2_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM2_USBACNR_POS 4 /**< SRAM2_USBACNR Position */
- #define MXC_F_RPU_SRAM2_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_USBACNR_POS)) /**< SRAM2_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_USBACNR_POS 4 /**< SYSRAM2_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM2_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_USBACNR_POS)) /**< SYSRAM2_USBACNR Mask */
- #define MXC_F_RPU_SRAM2_USBACNW_POS 5 /**< SRAM2_USBACNW Position */
- #define MXC_F_RPU_SRAM2_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_USBACNW_POS)) /**< SRAM2_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_USBACNW_POS 5 /**< SYSRAM2_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM2_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_USBACNW_POS)) /**< SYSRAM2_USBACNW Mask */
- #define MXC_F_RPU_SRAM2_SYS0ACNR_POS 6 /**< SRAM2_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM2_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SYS0ACNR_POS)) /**< SRAM2_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_SYS0ACNR_POS 6 /**< SYSRAM2_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM2_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS0ACNR_POS)) /**< SYSRAM2_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM2_SYS0ACNW_POS 7 /**< SRAM2_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM2_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SYS0ACNW_POS)) /**< SRAM2_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_SYS0ACNW_POS 7 /**< SYSRAM2_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM2_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS0ACNW_POS)) /**< SYSRAM2_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM2_SYS1ACNR_POS 8 /**< SRAM2_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM2_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SYS1ACNR_POS)) /**< SRAM2_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_SYS1ACNR_POS 8 /**< SYSRAM2_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM2_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS1ACNR_POS)) /**< SYSRAM2_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM2_SYS1ACNW_POS 9 /**< SRAM2_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM2_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SYS1ACNW_POS)) /**< SRAM2_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_SYS1ACNW_POS 9 /**< SYSRAM2_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM2_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SYS1ACNW_POS)) /**< SYSRAM2_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM2_SDMADACNR_POS 10 /**< SRAM2_SDMADACNR Position */
- #define MXC_F_RPU_SRAM2_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SDMADACNR_POS)) /**< SRAM2_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_SDMADACNR_POS 10 /**< SYSRAM2_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM2_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMADACNR_POS)) /**< SYSRAM2_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM2_SDMADACNW_POS 11 /**< SRAM2_SDMADACNW Position */
- #define MXC_F_RPU_SRAM2_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SDMADACNW_POS)) /**< SRAM2_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_SDMADACNW_POS 11 /**< SYSRAM2_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM2_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMADACNW_POS)) /**< SYSRAM2_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM2_SDMAIACNR_POS 12 /**< SRAM2_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM2_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SDMAIACNR_POS)) /**< SRAM2_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_SDMAIACNR_POS 12 /**< SYSRAM2_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM2_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMAIACNR_POS)) /**< SYSRAM2_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM2_SDMAIACNW_POS 13 /**< SRAM2_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM2_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SDMAIACNW_POS)) /**< SRAM2_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_SDMAIACNW_POS 13 /**< SYSRAM2_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM2_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDMAIACNW_POS)) /**< SYSRAM2_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM2_CRYPTOACNR_POS 14 /**< SRAM2_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM2_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_CRYPTOACNR_POS)) /**< SRAM2_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_CRYPTOACNR_POS 14 /**< SYSRAM2_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM2_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_CRYPTOACNR_POS)) /**< SYSRAM2_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM2_CRYPTOACNW_POS 15 /**< SRAM2_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM2_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_CRYPTOACNW_POS)) /**< SRAM2_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_CRYPTOACNW_POS 15 /**< SYSRAM2_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM2_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_CRYPTOACNW_POS)) /**< SYSRAM2_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM2_SDIOACNR_POS 16 /**< SRAM2_SDIOACNR Position */
- #define MXC_F_RPU_SRAM2_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SDIOACNR_POS)) /**< SRAM2_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM2_SDIOACNR_POS 16 /**< SYSRAM2_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM2_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDIOACNR_POS)) /**< SYSRAM2_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM2_SDIOACNW_POS 17 /**< SRAM2_SDIOACNW Position */
- #define MXC_F_RPU_SRAM2_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM2_SDIOACNW_POS)) /**< SRAM2_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM2_SDIOACNW_POS 17 /**< SYSRAM2_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM2_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM2_SDIOACNW_POS)) /**< SYSRAM2_SDIOACNW Mask */
-/**@} end of group RPU_SRAM2_Register */
+/**@} end of group RPU_SYSRAM2_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM3 RPU_SRAM3
- * @brief SRAM3 Protection Register
+ * @defgroup RPU_SYSRAM3 RPU_SYSRAM3
+ * @brief SYSRAM3 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM3_DMA0ACNR_POS 0 /**< SRAM3_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM3_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_DMA0ACNR_POS)) /**< SRAM3_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_DMA0ACNR_POS 0 /**< SYSRAM3_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM3_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA0ACNR_POS)) /**< SYSRAM3_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM3_DMA0ACNW_POS 1 /**< SRAM3_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM3_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_DMA0ACNW_POS)) /**< SRAM3_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_DMA0ACNW_POS 1 /**< SYSRAM3_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM3_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA0ACNW_POS)) /**< SYSRAM3_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM3_DMA1ACNR_POS 2 /**< SRAM3_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM3_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_DMA1ACNR_POS)) /**< SRAM3_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_DMA1ACNR_POS 2 /**< SYSRAM3_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM3_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA1ACNR_POS)) /**< SYSRAM3_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM3_DMA1ACNW_POS 3 /**< SRAM3_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM3_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_DMA1ACNW_POS)) /**< SRAM3_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_DMA1ACNW_POS 3 /**< SYSRAM3_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM3_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_DMA1ACNW_POS)) /**< SYSRAM3_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM3_USBACNR_POS 4 /**< SRAM3_USBACNR Position */
- #define MXC_F_RPU_SRAM3_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_USBACNR_POS)) /**< SRAM3_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_USBACNR_POS 4 /**< SYSRAM3_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM3_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_USBACNR_POS)) /**< SYSRAM3_USBACNR Mask */
- #define MXC_F_RPU_SRAM3_USBACNW_POS 5 /**< SRAM3_USBACNW Position */
- #define MXC_F_RPU_SRAM3_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_USBACNW_POS)) /**< SRAM3_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_USBACNW_POS 5 /**< SYSRAM3_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM3_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_USBACNW_POS)) /**< SYSRAM3_USBACNW Mask */
- #define MXC_F_RPU_SRAM3_SYS0ACNR_POS 6 /**< SRAM3_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM3_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SYS0ACNR_POS)) /**< SRAM3_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_SYS0ACNR_POS 6 /**< SYSRAM3_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM3_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS0ACNR_POS)) /**< SYSRAM3_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM3_SYS0ACNW_POS 7 /**< SRAM3_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM3_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SYS0ACNW_POS)) /**< SRAM3_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_SYS0ACNW_POS 7 /**< SYSRAM3_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM3_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS0ACNW_POS)) /**< SYSRAM3_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM3_SYS1ACNR_POS 8 /**< SRAM3_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM3_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SYS1ACNR_POS)) /**< SRAM3_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_SYS1ACNR_POS 8 /**< SYSRAM3_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM3_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS1ACNR_POS)) /**< SYSRAM3_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM3_SYS1ACNW_POS 9 /**< SRAM3_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM3_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SYS1ACNW_POS)) /**< SRAM3_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_SYS1ACNW_POS 9 /**< SYSRAM3_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM3_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SYS1ACNW_POS)) /**< SYSRAM3_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM3_SDMADACNR_POS 10 /**< SRAM3_SDMADACNR Position */
- #define MXC_F_RPU_SRAM3_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SDMADACNR_POS)) /**< SRAM3_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_SDMADACNR_POS 10 /**< SYSRAM3_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM3_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMADACNR_POS)) /**< SYSRAM3_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM3_SDMADACNW_POS 11 /**< SRAM3_SDMADACNW Position */
- #define MXC_F_RPU_SRAM3_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SDMADACNW_POS)) /**< SRAM3_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_SDMADACNW_POS 11 /**< SYSRAM3_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM3_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMADACNW_POS)) /**< SYSRAM3_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM3_SDMAIACNR_POS 12 /**< SRAM3_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM3_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SDMAIACNR_POS)) /**< SRAM3_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_SDMAIACNR_POS 12 /**< SYSRAM3_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM3_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMAIACNR_POS)) /**< SYSRAM3_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM3_SDMAIACNW_POS 13 /**< SRAM3_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM3_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SDMAIACNW_POS)) /**< SRAM3_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_SDMAIACNW_POS 13 /**< SYSRAM3_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM3_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDMAIACNW_POS)) /**< SYSRAM3_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM3_CRYPTOACNR_POS 14 /**< SRAM3_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM3_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_CRYPTOACNR_POS)) /**< SRAM3_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_CRYPTOACNR_POS 14 /**< SYSRAM3_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM3_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_CRYPTOACNR_POS)) /**< SYSRAM3_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM3_CRYPTOACNW_POS 15 /**< SRAM3_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM3_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_CRYPTOACNW_POS)) /**< SRAM3_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_CRYPTOACNW_POS 15 /**< SYSRAM3_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM3_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_CRYPTOACNW_POS)) /**< SYSRAM3_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM3_SDIOACNR_POS 16 /**< SRAM3_SDIOACNR Position */
- #define MXC_F_RPU_SRAM3_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SDIOACNR_POS)) /**< SRAM3_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM3_SDIOACNR_POS 16 /**< SYSRAM3_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM3_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDIOACNR_POS)) /**< SYSRAM3_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM3_SDIOACNW_POS 17 /**< SRAM3_SDIOACNW Position */
- #define MXC_F_RPU_SRAM3_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM3_SDIOACNW_POS)) /**< SRAM3_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM3_SDIOACNW_POS 17 /**< SYSRAM3_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM3_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM3_SDIOACNW_POS)) /**< SYSRAM3_SDIOACNW Mask */
-/**@} end of group RPU_SRAM3_Register */
+/**@} end of group RPU_SYSRAM3_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM4 RPU_SRAM4
- * @brief SRAM4 Protection Register
+ * @defgroup RPU_SYSRAM4 RPU_SYSRAM4
+ * @brief SYSRAM4 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM4_DMA0ACNR_POS 0 /**< SRAM4_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM4_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_DMA0ACNR_POS)) /**< SRAM4_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_DMA0ACNR_POS 0 /**< SYSRAM4_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM4_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA0ACNR_POS)) /**< SYSRAM4_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM4_DMA0ACNW_POS 1 /**< SRAM4_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM4_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_DMA0ACNW_POS)) /**< SRAM4_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_DMA0ACNW_POS 1 /**< SYSRAM4_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM4_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA0ACNW_POS)) /**< SYSRAM4_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM4_DMA1ACNR_POS 2 /**< SRAM4_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM4_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_DMA1ACNR_POS)) /**< SRAM4_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_DMA1ACNR_POS 2 /**< SYSRAM4_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM4_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA1ACNR_POS)) /**< SYSRAM4_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM4_DMA1ACNW_POS 3 /**< SRAM4_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM4_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_DMA1ACNW_POS)) /**< SRAM4_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_DMA1ACNW_POS 3 /**< SYSRAM4_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM4_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_DMA1ACNW_POS)) /**< SYSRAM4_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM4_USBACNR_POS 4 /**< SRAM4_USBACNR Position */
- #define MXC_F_RPU_SRAM4_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_USBACNR_POS)) /**< SRAM4_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_USBACNR_POS 4 /**< SYSRAM4_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM4_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_USBACNR_POS)) /**< SYSRAM4_USBACNR Mask */
- #define MXC_F_RPU_SRAM4_USBACNW_POS 5 /**< SRAM4_USBACNW Position */
- #define MXC_F_RPU_SRAM4_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_USBACNW_POS)) /**< SRAM4_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_USBACNW_POS 5 /**< SYSRAM4_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM4_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_USBACNW_POS)) /**< SYSRAM4_USBACNW Mask */
- #define MXC_F_RPU_SRAM4_SYS0ACNR_POS 6 /**< SRAM4_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM4_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SYS0ACNR_POS)) /**< SRAM4_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_SYS0ACNR_POS 6 /**< SYSRAM4_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM4_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS0ACNR_POS)) /**< SYSRAM4_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM4_SYS0ACNW_POS 7 /**< SRAM4_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM4_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SYS0ACNW_POS)) /**< SRAM4_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_SYS0ACNW_POS 7 /**< SYSRAM4_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM4_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS0ACNW_POS)) /**< SYSRAM4_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM4_SYS1ACNR_POS 8 /**< SRAM4_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM4_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SYS1ACNR_POS)) /**< SRAM4_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_SYS1ACNR_POS 8 /**< SYSRAM4_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM4_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS1ACNR_POS)) /**< SYSRAM4_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM4_SYS1ACNW_POS 9 /**< SRAM4_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM4_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SYS1ACNW_POS)) /**< SRAM4_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_SYS1ACNW_POS 9 /**< SYSRAM4_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM4_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SYS1ACNW_POS)) /**< SYSRAM4_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM4_SDMADACNR_POS 10 /**< SRAM4_SDMADACNR Position */
- #define MXC_F_RPU_SRAM4_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SDMADACNR_POS)) /**< SRAM4_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_SDMADACNR_POS 10 /**< SYSRAM4_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM4_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMADACNR_POS)) /**< SYSRAM4_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM4_SDMADACNW_POS 11 /**< SRAM4_SDMADACNW Position */
- #define MXC_F_RPU_SRAM4_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SDMADACNW_POS)) /**< SRAM4_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_SDMADACNW_POS 11 /**< SYSRAM4_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM4_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMADACNW_POS)) /**< SYSRAM4_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM4_SDMAIACNR_POS 12 /**< SRAM4_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM4_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SDMAIACNR_POS)) /**< SRAM4_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_SDMAIACNR_POS 12 /**< SYSRAM4_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM4_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMAIACNR_POS)) /**< SYSRAM4_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM4_SDMAIACNW_POS 13 /**< SRAM4_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM4_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SDMAIACNW_POS)) /**< SRAM4_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_SDMAIACNW_POS 13 /**< SYSRAM4_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM4_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDMAIACNW_POS)) /**< SYSRAM4_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM4_CRYPTOACNR_POS 14 /**< SRAM4_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM4_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_CRYPTOACNR_POS)) /**< SRAM4_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_CRYPTOACNR_POS 14 /**< SYSRAM4_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM4_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_CRYPTOACNR_POS)) /**< SYSRAM4_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM4_CRYPTOACNW_POS 15 /**< SRAM4_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM4_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_CRYPTOACNW_POS)) /**< SRAM4_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_CRYPTOACNW_POS 15 /**< SYSRAM4_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM4_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_CRYPTOACNW_POS)) /**< SYSRAM4_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM4_SDIOACNR_POS 16 /**< SRAM4_SDIOACNR Position */
- #define MXC_F_RPU_SRAM4_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SDIOACNR_POS)) /**< SRAM4_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM4_SDIOACNR_POS 16 /**< SYSRAM4_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM4_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDIOACNR_POS)) /**< SYSRAM4_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM4_SDIOACNW_POS 17 /**< SRAM4_SDIOACNW Position */
- #define MXC_F_RPU_SRAM4_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM4_SDIOACNW_POS)) /**< SRAM4_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM4_SDIOACNW_POS 17 /**< SYSRAM4_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM4_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM4_SDIOACNW_POS)) /**< SYSRAM4_SDIOACNW Mask */
-/**@} end of group RPU_SRAM4_Register */
+/**@} end of group RPU_SYSRAM4_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM5 RPU_SRAM5
- * @brief SRAM5 Protection Register
+ * @defgroup RPU_SYSRAM5 RPU_SYSRAM5
+ * @brief SYSRAM5 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM5_DMA0ACNR_POS 0 /**< SRAM5_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM5_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA0ACNR_POS)) /**< SRAM5_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_DMA0ACNR_POS 0 /**< SYSRAM5_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM5_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA0ACNR_POS)) /**< SYSRAM5_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM5_DMA0ACNW_POS 1 /**< SRAM5_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM5_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA0ACNW_POS)) /**< SRAM5_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_DMA0ACNW_POS 1 /**< SYSRAM5_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM5_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA0ACNW_POS)) /**< SYSRAM5_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM5_DMA1ACNR_POS 2 /**< SRAM5_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM5_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA1ACNR_POS)) /**< SRAM5_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_DMA1ACNR_POS 2 /**< SYSRAM5_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM5_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA1ACNR_POS)) /**< SYSRAM5_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM5_DMA1ACNW_POS 3 /**< SRAM5_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM5_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_DMA1ACNW_POS)) /**< SRAM5_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_DMA1ACNW_POS 3 /**< SYSRAM5_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM5_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA1ACNW_POS)) /**< SYSRAM5_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM5_USBACNR_POS 4 /**< SRAM5_USBACNR Position */
- #define MXC_F_RPU_SRAM5_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_USBACNR_POS)) /**< SRAM5_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_USBACNR_POS 4 /**< SYSRAM5_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM5_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_USBACNR_POS)) /**< SYSRAM5_USBACNR Mask */
- #define MXC_F_RPU_SRAM5_USBACNW_POS 5 /**< SRAM5_USBACNW Position */
- #define MXC_F_RPU_SRAM5_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_USBACNW_POS)) /**< SRAM5_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_USBACNW_POS 5 /**< SYSRAM5_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM5_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_USBACNW_POS)) /**< SYSRAM5_USBACNW Mask */
- #define MXC_F_RPU_SRAM5_SYS0ACNR_POS 6 /**< SRAM5_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM5_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS0ACNR_POS)) /**< SRAM5_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_SYS0ACNR_POS 6 /**< SYSRAM5_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM5_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS0ACNR_POS)) /**< SYSRAM5_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM5_SYS0ACNW_POS 7 /**< SRAM5_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM5_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS0ACNW_POS)) /**< SRAM5_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_SYS0ACNW_POS 7 /**< SYSRAM5_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM5_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS0ACNW_POS)) /**< SYSRAM5_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM5_SYS1ACNR_POS 8 /**< SRAM5_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM5_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS1ACNR_POS)) /**< SRAM5_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_SYS1ACNR_POS 8 /**< SYSRAM5_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM5_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS1ACNR_POS)) /**< SYSRAM5_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM5_SYS1ACNW_POS 9 /**< SRAM5_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM5_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SYS1ACNW_POS)) /**< SRAM5_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_SYS1ACNW_POS 9 /**< SYSRAM5_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM5_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SYS1ACNW_POS)) /**< SYSRAM5_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM5_SDMADACNR_POS 10 /**< SRAM5_SDMADACNR Position */
- #define MXC_F_RPU_SRAM5_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMADACNR_POS)) /**< SRAM5_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_SDMADACNR_POS 10 /**< SYSRAM5_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM5_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMADACNR_POS)) /**< SYSRAM5_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM5_SDMADACNW_POS 11 /**< SRAM5_SDMADACNW Position */
- #define MXC_F_RPU_SRAM5_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMADACNW_POS)) /**< SRAM5_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_SDMADACNW_POS 11 /**< SYSRAM5_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM5_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMADACNW_POS)) /**< SYSRAM5_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM5_SDMAIACNR_POS 12 /**< SRAM5_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM5_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMAIACNR_POS)) /**< SRAM5_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_SDMAIACNR_POS 12 /**< SYSRAM5_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM5_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMAIACNR_POS)) /**< SYSRAM5_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM5_SDMAIACNW_POS 13 /**< SRAM5_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM5_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDMAIACNW_POS)) /**< SRAM5_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_SDMAIACNW_POS 13 /**< SYSRAM5_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM5_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMAIACNW_POS)) /**< SYSRAM5_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM5_CRYPTOACNR_POS 14 /**< SRAM5_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM5_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_CRYPTOACNR_POS)) /**< SRAM5_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS 14 /**< SYSRAM5_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM5_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS)) /**< SYSRAM5_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM5_CRYPTOACNW_POS 15 /**< SRAM5_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM5_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_CRYPTOACNW_POS)) /**< SRAM5_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS 15 /**< SYSRAM5_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM5_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS)) /**< SYSRAM5_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM5_SDIOACNR_POS 16 /**< SRAM5_SDIOACNR Position */
- #define MXC_F_RPU_SRAM5_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDIOACNR_POS)) /**< SRAM5_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM5_SDIOACNR_POS 16 /**< SYSRAM5_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM5_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDIOACNR_POS)) /**< SYSRAM5_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM5_SDIOACNW_POS 17 /**< SRAM5_SDIOACNW Position */
- #define MXC_F_RPU_SRAM5_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM5_SDIOACNW_POS)) /**< SRAM5_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM5_SDIOACNW_POS 17 /**< SYSRAM5_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM5_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDIOACNW_POS)) /**< SYSRAM5_SDIOACNW Mask */
-/**@} end of group RPU_SRAM5_Register */
+/**@} end of group RPU_SYSRAM5_Register */
/**
* @ingroup rpu_registers
- * @defgroup RPU_SRAM6 RPU_SRAM6
- * @brief SRAM6 Protection Register
+ * @defgroup RPU_SYSRAM6 RPU_SYSRAM6
+ * @brief SYSRAM6 Protection Register
* @{
*/
- #define MXC_F_RPU_SRAM6_DMA0ACNR_POS 0 /**< SRAM6_DMA0ACNR Position */
- #define MXC_F_RPU_SRAM6_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_DMA0ACNR_POS)) /**< SRAM6_DMA0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_DMA0ACNR_POS 0 /**< SYSRAM6_DMA0ACNR Position */
+ #define MXC_F_RPU_SYSRAM6_DMA0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA0ACNR_POS)) /**< SYSRAM6_DMA0ACNR Mask */
- #define MXC_F_RPU_SRAM6_DMA0ACNW_POS 1 /**< SRAM6_DMA0ACNW Position */
- #define MXC_F_RPU_SRAM6_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_DMA0ACNW_POS)) /**< SRAM6_DMA0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_DMA0ACNW_POS 1 /**< SYSRAM6_DMA0ACNW Position */
+ #define MXC_F_RPU_SYSRAM6_DMA0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA0ACNW_POS)) /**< SYSRAM6_DMA0ACNW Mask */
- #define MXC_F_RPU_SRAM6_DMA1ACNR_POS 2 /**< SRAM6_DMA1ACNR Position */
- #define MXC_F_RPU_SRAM6_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_DMA1ACNR_POS)) /**< SRAM6_DMA1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_DMA1ACNR_POS 2 /**< SYSRAM6_DMA1ACNR Position */
+ #define MXC_F_RPU_SYSRAM6_DMA1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA1ACNR_POS)) /**< SYSRAM6_DMA1ACNR Mask */
- #define MXC_F_RPU_SRAM6_DMA1ACNW_POS 3 /**< SRAM6_DMA1ACNW Position */
- #define MXC_F_RPU_SRAM6_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_DMA1ACNW_POS)) /**< SRAM6_DMA1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_DMA1ACNW_POS 3 /**< SYSRAM6_DMA1ACNW Position */
+ #define MXC_F_RPU_SYSRAM6_DMA1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_DMA1ACNW_POS)) /**< SYSRAM6_DMA1ACNW Mask */
- #define MXC_F_RPU_SRAM6_USBACNR_POS 4 /**< SRAM6_USBACNR Position */
- #define MXC_F_RPU_SRAM6_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_USBACNR_POS)) /**< SRAM6_USBACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_USBACNR_POS 4 /**< SYSRAM6_USBACNR Position */
+ #define MXC_F_RPU_SYSRAM6_USBACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_USBACNR_POS)) /**< SYSRAM6_USBACNR Mask */
- #define MXC_F_RPU_SRAM6_USBACNW_POS 5 /**< SRAM6_USBACNW Position */
- #define MXC_F_RPU_SRAM6_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_USBACNW_POS)) /**< SRAM6_USBACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_USBACNW_POS 5 /**< SYSRAM6_USBACNW Position */
+ #define MXC_F_RPU_SYSRAM6_USBACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_USBACNW_POS)) /**< SYSRAM6_USBACNW Mask */
- #define MXC_F_RPU_SRAM6_SYS0ACNR_POS 6 /**< SRAM6_SYS0ACNR Position */
- #define MXC_F_RPU_SRAM6_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SYS0ACNR_POS)) /**< SRAM6_SYS0ACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_SYS0ACNR_POS 6 /**< SYSRAM6_SYS0ACNR Position */
+ #define MXC_F_RPU_SYSRAM6_SYS0ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS0ACNR_POS)) /**< SYSRAM6_SYS0ACNR Mask */
- #define MXC_F_RPU_SRAM6_SYS0ACNW_POS 7 /**< SRAM6_SYS0ACNW Position */
- #define MXC_F_RPU_SRAM6_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SYS0ACNW_POS)) /**< SRAM6_SYS0ACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_SYS0ACNW_POS 7 /**< SYSRAM6_SYS0ACNW Position */
+ #define MXC_F_RPU_SYSRAM6_SYS0ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS0ACNW_POS)) /**< SYSRAM6_SYS0ACNW Mask */
- #define MXC_F_RPU_SRAM6_SYS1ACNR_POS 8 /**< SRAM6_SYS1ACNR Position */
- #define MXC_F_RPU_SRAM6_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SYS1ACNR_POS)) /**< SRAM6_SYS1ACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_SYS1ACNR_POS 8 /**< SYSRAM6_SYS1ACNR Position */
+ #define MXC_F_RPU_SYSRAM6_SYS1ACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS1ACNR_POS)) /**< SYSRAM6_SYS1ACNR Mask */
- #define MXC_F_RPU_SRAM6_SYS1ACNW_POS 9 /**< SRAM6_SYS1ACNW Position */
- #define MXC_F_RPU_SRAM6_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SYS1ACNW_POS)) /**< SRAM6_SYS1ACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_SYS1ACNW_POS 9 /**< SYSRAM6_SYS1ACNW Position */
+ #define MXC_F_RPU_SYSRAM6_SYS1ACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SYS1ACNW_POS)) /**< SYSRAM6_SYS1ACNW Mask */
- #define MXC_F_RPU_SRAM6_SDMADACNR_POS 10 /**< SRAM6_SDMADACNR Position */
- #define MXC_F_RPU_SRAM6_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SDMADACNR_POS)) /**< SRAM6_SDMADACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_SDMADACNR_POS 10 /**< SYSRAM6_SDMADACNR Position */
+ #define MXC_F_RPU_SYSRAM6_SDMADACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMADACNR_POS)) /**< SYSRAM6_SDMADACNR Mask */
- #define MXC_F_RPU_SRAM6_SDMADACNW_POS 11 /**< SRAM6_SDMADACNW Position */
- #define MXC_F_RPU_SRAM6_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SDMADACNW_POS)) /**< SRAM6_SDMADACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_SDMADACNW_POS 11 /**< SYSRAM6_SDMADACNW Position */
+ #define MXC_F_RPU_SYSRAM6_SDMADACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMADACNW_POS)) /**< SYSRAM6_SDMADACNW Mask */
- #define MXC_F_RPU_SRAM6_SDMAIACNR_POS 12 /**< SRAM6_SDMAIACNR Position */
- #define MXC_F_RPU_SRAM6_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SDMAIACNR_POS)) /**< SRAM6_SDMAIACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_SDMAIACNR_POS 12 /**< SYSRAM6_SDMAIACNR Position */
+ #define MXC_F_RPU_SYSRAM6_SDMAIACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMAIACNR_POS)) /**< SYSRAM6_SDMAIACNR Mask */
- #define MXC_F_RPU_SRAM6_SDMAIACNW_POS 13 /**< SRAM6_SDMAIACNW Position */
- #define MXC_F_RPU_SRAM6_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SDMAIACNW_POS)) /**< SRAM6_SDMAIACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_SDMAIACNW_POS 13 /**< SYSRAM6_SDMAIACNW Position */
+ #define MXC_F_RPU_SYSRAM6_SDMAIACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDMAIACNW_POS)) /**< SYSRAM6_SDMAIACNW Mask */
- #define MXC_F_RPU_SRAM6_CRYPTOACNR_POS 14 /**< SRAM6_CRYPTOACNR Position */
- #define MXC_F_RPU_SRAM6_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_CRYPTOACNR_POS)) /**< SRAM6_CRYPTOACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_CRYPTOACNR_POS 14 /**< SYSRAM6_CRYPTOACNR Position */
+ #define MXC_F_RPU_SYSRAM6_CRYPTOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_CRYPTOACNR_POS)) /**< SYSRAM6_CRYPTOACNR Mask */
- #define MXC_F_RPU_SRAM6_CRYPTOACNW_POS 15 /**< SRAM6_CRYPTOACNW Position */
- #define MXC_F_RPU_SRAM6_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_CRYPTOACNW_POS)) /**< SRAM6_CRYPTOACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_CRYPTOACNW_POS 15 /**< SYSRAM6_CRYPTOACNW Position */
+ #define MXC_F_RPU_SYSRAM6_CRYPTOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_CRYPTOACNW_POS)) /**< SYSRAM6_CRYPTOACNW Mask */
- #define MXC_F_RPU_SRAM6_SDIOACNR_POS 16 /**< SRAM6_SDIOACNR Position */
- #define MXC_F_RPU_SRAM6_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SDIOACNR_POS)) /**< SRAM6_SDIOACNR Mask */
+ #define MXC_F_RPU_SYSRAM6_SDIOACNR_POS 16 /**< SYSRAM6_SDIOACNR Position */
+ #define MXC_F_RPU_SYSRAM6_SDIOACNR ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDIOACNR_POS)) /**< SYSRAM6_SDIOACNR Mask */
- #define MXC_F_RPU_SRAM6_SDIOACNW_POS 17 /**< SRAM6_SDIOACNW Position */
- #define MXC_F_RPU_SRAM6_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SRAM6_SDIOACNW_POS)) /**< SRAM6_SDIOACNW Mask */
+ #define MXC_F_RPU_SYSRAM6_SDIOACNW_POS 17 /**< SYSRAM6_SDIOACNW Position */
+ #define MXC_F_RPU_SYSRAM6_SDIOACNW ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM6_SDIOACNW_POS)) /**< SYSRAM6_SDIOACNW Mask */
-/**@} end of group RPU_SRAM6_Register */
+/**@} end of group RPU_SYSRAM6_Register */
#ifdef __cplusplus
}
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h
index e3b2ae307e95464d2a10dcbe9d137c3b5dea9877..5967da7365c11bed4d209bd2409d57ccf6d7a28b 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/rtc_regs.h
@@ -88,8 +88,8 @@ extern "C" {
typedef struct {
__IO uint32_t sec; /**< <tt>\b 0x00:</tt> RTC SEC Register */
__IO uint32_t ssec; /**< <tt>\b 0x04:</tt> RTC SSEC Register */
- __IO uint32_t ras; /**< <tt>\b 0x08:</tt> RTC RAS Register */
- __IO uint32_t rssa; /**< <tt>\b 0x0C:</tt> RTC RSSA Register */
+ __IO uint32_t toda; /**< <tt>\b 0x08:</tt> RTC TODA Register */
+ __IO uint32_t sseca; /**< <tt>\b 0x0C:</tt> RTC SSECA Register */
__IO uint32_t ctrl; /**< <tt>\b 0x10:</tt> RTC CTRL Register */
__IO uint32_t trim; /**< <tt>\b 0x14:</tt> RTC TRIM Register */
__IO uint32_t oscctrl; /**< <tt>\b 0x18:</tt> RTC OSCCTRL Register */
@@ -104,8 +104,8 @@ typedef struct {
*/
#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: <tt> 0x0000</tt> */
#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: <tt> 0x0004</tt> */
- #define MXC_R_RTC_RAS ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
- #define MXC_R_RTC_RSSA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
+ #define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: <tt> 0x0008</tt> */
+ #define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: <tt> 0x000C</tt> */
#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: <tt> 0x0010</tt> */
#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: <tt> 0x0014</tt> */
#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: <tt> 0x0018</tt> */
@@ -118,33 +118,33 @@ typedef struct {
* when this register rolls over from 0xFF to 0x00.
* @{
*/
- #define MXC_F_RTC_SSEC_RTSS_POS 0 /**< SSEC_RTSS Position */
- #define MXC_F_RTC_SSEC_RTSS ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_RTSS_POS)) /**< SSEC_RTSS Mask */
+ #define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */
+ #define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */
/**@} end of group RTC_SSEC_Register */
/**
* @ingroup rtc_registers
- * @defgroup RTC_RAS RTC_RAS
+ * @defgroup RTC_TODA RTC_TODA
* @brief Time-of-day Alarm.
* @{
*/
- #define MXC_F_RTC_RAS_RAS_POS 0 /**< RAS_RAS Position */
- #define MXC_F_RTC_RAS_RAS ((uint32_t)(0xFFFFFUL << MXC_F_RTC_RAS_RAS_POS)) /**< RAS_RAS Mask */
+ #define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */
+ #define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */
-/**@} end of group RTC_RAS_Register */
+/**@} end of group RTC_TODA_Register */
/**
* @ingroup rtc_registers
- * @defgroup RTC_RSSA RTC_RSSA
+ * @defgroup RTC_SSECA RTC_SSECA
* @brief RTC sub-second alarm. This register contains the reload value for the sub-
* second alarm.
* @{
*/
- #define MXC_F_RTC_RSSA_RSSA_POS 0 /**< RSSA_RSSA Position */
- #define MXC_F_RTC_RSSA_RSSA ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_RSSA_RSSA_POS)) /**< RSSA_RSSA Mask */
+ #define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */
+ #define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */
-/**@} end of group RTC_RSSA_Register */
+/**@} end of group RTC_SSECA_Register */
/**
* @ingroup rtc_registers
@@ -190,17 +190,6 @@ typedef struct {
#define MXC_V_RTC_CTRL_FT_CLKDIV8 ((uint32_t)0x3UL) /**< CTRL_FT_CLKDIV8 Value */
#define MXC_S_RTC_CTRL_FT_CLKDIV8 (MXC_V_RTC_CTRL_FT_CLKDIV8 << MXC_F_RTC_CTRL_FT_POS) /**< CTRL_FT_CLKDIV8 Setting */
- #define MXC_F_RTC_CTRL_X32KMD_POS 11 /**< CTRL_X32KMD Position */
- #define MXC_F_RTC_CTRL_X32KMD ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_X32KMD_POS)) /**< CTRL_X32KMD Mask */
- #define MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE ((uint32_t)0x0UL) /**< CTRL_X32KMD_NOISEIMMUNEMODE Value */
- #define MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE (MXC_V_RTC_CTRL_X32KMD_NOISEIMMUNEMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_NOISEIMMUNEMODE Setting */
- #define MXC_V_RTC_CTRL_X32KMD_QUIETMODE ((uint32_t)0x1UL) /**< CTRL_X32KMD_QUIETMODE Value */
- #define MXC_S_RTC_CTRL_X32KMD_QUIETMODE (MXC_V_RTC_CTRL_X32KMD_QUIETMODE << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETMODE Setting */
- #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP ((uint32_t)0x2UL) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Value */
- #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPWITHWARMUP Setting */
- #define MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP ((uint32_t)0x3UL) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Value */
- #define MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP (MXC_V_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP << MXC_F_RTC_CTRL_X32KMD_POS) /**< CTRL_X32KMD_QUIETINSTOPNOWARMUP Setting */
-
#define MXC_F_RTC_CTRL_WE_POS 15 /**< CTRL_WE Position */
#define MXC_F_RTC_CTRL_WE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WE_POS)) /**< CTRL_WE Mask */
@@ -215,8 +204,8 @@ typedef struct {
#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */
#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */
- #define MXC_F_RTC_TRIM_VBATTMR_POS 8 /**< TRIM_VBATTMR Position */
- #define MXC_F_RTC_TRIM_VBATTMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBATTMR_POS)) /**< TRIM_VBATTMR Mask */
+ #define MXC_F_RTC_TRIM_VRTC_TMR_POS 8 /**< TRIM_VRTC_TMR Position */
+ #define MXC_F_RTC_TRIM_VRTC_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VRTC_TMR_POS)) /**< TRIM_VRTC_TMR Mask */
/**@} end of group RTC_TRIM_Register */
@@ -226,18 +215,6 @@ typedef struct {
* @brief RTC Oscillator Control Register.
* @{
*/
- #define MXC_F_RTC_OSCCTRL_FLITER_EN_POS 0 /**< OSCCTRL_FLITER_EN Position */
- #define MXC_F_RTC_OSCCTRL_FLITER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FLITER_EN_POS)) /**< OSCCTRL_FLITER_EN Mask */
-
- #define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */
- #define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */
-
- #define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */
- #define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */
-
- #define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */
- #define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */
-
#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */
#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixf_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixf_regs.h
index 8e93f9b12a0d53aede8b35fbf686725428c9f38f..63f08b8f269d683e1bb0b0e65dcbf3ae1972ad3a 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixf_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixf_regs.h
@@ -94,6 +94,7 @@ typedef struct {
__R uint32_t rsv_0x14_0x1b[2];
__IO uint32_t io_ctrl; /**< <tt>\b 0x1C:</tt> SPIXF IO_CTRL Register */
__IO uint32_t memseccn; /**< <tt>\b 0x20:</tt> SPIXF MEMSECCN Register */
+ __IO uint32_t bus_idle; /**< <tt>\b 0x24:</tt> SPIXF BUS_IDLE Register */
} mxc_spixf_regs_t;
/* Register offsets for module SPIXF */
@@ -110,6 +111,7 @@ typedef struct {
#define MXC_R_SPIXF_SCLK_FB_CTRL ((uint32_t)0x00000010UL) /**< Offset from SPIXF Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPIXF_IO_CTRL ((uint32_t)0x0000001CUL) /**< Offset from SPIXF Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPIXF_MEMSECCN ((uint32_t)0x00000020UL) /**< Offset from SPIXF Base Address: <tt> 0x0020</tt> */
+ #define MXC_R_SPIXF_BUS_IDLE ((uint32_t)0x00000024UL) /**< Offset from SPIXF Base Address: <tt> 0x0024</tt> */
/**@} end of group spixf_registers */
/**
@@ -220,6 +222,9 @@ typedef struct {
#define MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS 8 /**< MODE_CTRL_NO_CMD Position */
#define MXC_F_SPIXF_MODE_CTRL_NO_CMD ((uint32_t)(0x1UL << MXC_F_SPIXF_MODE_CTRL_NO_CMD_POS)) /**< MODE_CTRL_NO_CMD Mask */
+ #define MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS 9 /**< MODE_CTRL_MODE_SEND Position */
+ #define MXC_F_SPIXF_MODE_CTRL_MODE_SEND ((uint32_t)(0x1UL << MXC_F_SPIXF_MODE_CTRL_MODE_SEND_POS)) /**< MODE_CTRL_MODE_SEND Mask */
+
/**@} end of group SPIXF_MODE_CTRL_Register */
/**
@@ -291,8 +296,22 @@ typedef struct {
#define MXC_F_SPIXF_MEMSECCN_DECEN_POS 0 /**< MEMSECCN_DECEN Position */
#define MXC_F_SPIXF_MEMSECCN_DECEN ((uint32_t)(0x1UL << MXC_F_SPIXF_MEMSECCN_DECEN_POS)) /**< MEMSECCN_DECEN Mask */
+ #define MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS 1 /**< MEMSECCN_AUTH_DISABLE Position */
+ #define MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE ((uint32_t)(0x1UL << MXC_F_SPIXF_MEMSECCN_AUTH_DISABLE_POS)) /**< MEMSECCN_AUTH_DISABLE Mask */
+
/**@} end of group SPIXF_MEMSECCN_Register */
+/**
+ * @ingroup spixf_registers
+ * @defgroup SPIXF_BUS_IDLE SPIXF_BUS_IDLE
+ * @brief SPIXF Bus Idle Detection.
+ * @{
+ */
+ #define MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS 0 /**< BUS_IDLE_BUSIDLE Position */
+ #define MXC_F_SPIXF_BUS_IDLE_BUSIDLE ((uint32_t)(0xFFFFUL << MXC_F_SPIXF_BUS_IDLE_BUSIDLE_POS)) /**< BUS_IDLE_BUSIDLE Mask */
+
+/**@} end of group SPIXF_BUS_IDLE_Register */
+
#ifdef __cplusplus
}
#endif
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h
index 2c1f64c064034041f5fc2a84b4950c707738c98f..e3cc69fd6c6b1b173a255777cbbb9df13cc7713b 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixfc_regs.h
@@ -174,6 +174,9 @@ typedef struct {
#define MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS ((uint32_t)0x3UL) /**< CONFIG_SS_INACT_12_CLKS Value */
#define MXC_S_SPIXFC_CONFIG_SS_INACT_12_CLKS (MXC_V_SPIXFC_CONFIG_SS_INACT_12_CLKS << MXC_F_SPIXFC_CONFIG_SS_INACT_POS) /**< CONFIG_SS_INACT_12_CLKS Setting */
+ #define MXC_F_SPIXFC_CONFIG_IOSMPL_POS 20 /**< CONFIG_IOSMPL Position */
+ #define MXC_F_SPIXFC_CONFIG_IOSMPL ((uint32_t)(0xFUL << MXC_F_SPIXFC_CONFIG_IOSMPL_POS)) /**< CONFIG_IOSMPL Mask */
+
/**@} end of group SPIXFC_CONFIG_Register */
/**
@@ -244,9 +247,21 @@ typedef struct {
#define MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 ((uint32_t)0x3UL) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Value */
#define MXC_S_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 (MXC_V_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_SDIO3 << MXC_F_SPIXFC_GEN_CTRL_BB_DATA_OUT_EN_POS) /**< GEN_CTRL_BB_DATA_OUT_EN_SDIO3 Setting */
+ #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS 20 /**< GEN_CTRL_SIMPLE Position */
+ #define MXC_F_SPIXFC_GEN_CTRL_SIMPLE ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLE_POS)) /**< GEN_CTRL_SIMPLE Mask */
+
+ #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS 21 /**< GEN_CTRL_SIMPLERX Position */
+ #define MXC_F_SPIXFC_GEN_CTRL_SIMPLERX ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SIMPLERX_POS)) /**< GEN_CTRL_SIMPLERX Mask */
+
+ #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS 22 /**< GEN_CTRL_SMPLSS Position */
+ #define MXC_F_SPIXFC_GEN_CTRL_SMPLSS ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SMPLSS_POS)) /**< GEN_CTRL_SMPLSS Mask */
+
#define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS 24 /**< GEN_CTRL_SCLK_FB Position */
#define MXC_F_SPIXFC_GEN_CTRL_SCLK_FB ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCLK_FB_POS)) /**< GEN_CTRL_SCLK_FB Mask */
+ #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS 25 /**< GEN_CTRL_SCKFBINV Position */
+ #define MXC_F_SPIXFC_GEN_CTRL_SCKFBINV ((uint32_t)(0x1UL << MXC_F_SPIXFC_GEN_CTRL_SCKFBINV_POS)) /**< GEN_CTRL_SCKFBINV Mask */
+
/**@} end of group SPIXFC_GEN_CTRL_Register */
/**
@@ -275,6 +290,31 @@ typedef struct {
* @brief SPIX Controller Special Control Register.
* @{
*/
+ #define MXC_F_SPIXFC_SPCTRL_SAMPL_POS 0 /**< SPCTRL_SAMPL Position */
+ #define MXC_F_SPIXFC_SPCTRL_SAMPL ((uint32_t)(0x1UL << MXC_F_SPIXFC_SPCTRL_SAMPL_POS)) /**< SPCTRL_SAMPL Mask */
+
+ #define MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS 4 /**< SPCTRL_SDIOOUT Position */
+ #define MXC_F_SPIXFC_SPCTRL_SDIOOUT ((uint32_t)(0xFUL << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS)) /**< SPCTRL_SDIOOUT Mask */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO0 ((uint32_t)0x0UL) /**< SPCTRL_SDIOOUT_SDIO0 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO0 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO0 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO0 Setting */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO1 ((uint32_t)0x1UL) /**< SPCTRL_SDIOOUT_SDIO1 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO1 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO1 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO1 Setting */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO2 ((uint32_t)0x2UL) /**< SPCTRL_SDIOOUT_SDIO2 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO2 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO2 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO2 Setting */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO3 ((uint32_t)0x3UL) /**< SPCTRL_SDIOOUT_SDIO3 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOUT_SDIO3 (MXC_V_SPIXFC_SPCTRL_SDIOOUT_SDIO3 << MXC_F_SPIXFC_SPCTRL_SDIOOUT_POS) /**< SPCTRL_SDIOOUT_SDIO3 Setting */
+
+ #define MXC_F_SPIXFC_SPCTRL_SDIOOE_POS 8 /**< SPCTRL_SDIOOE Position */
+ #define MXC_F_SPIXFC_SPCTRL_SDIOOE ((uint32_t)(0xFUL << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS)) /**< SPCTRL_SDIOOE Mask */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO0 ((uint32_t)0x0UL) /**< SPCTRL_SDIOOE_SDIO0 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO0 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO0 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO0 Setting */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO1 ((uint32_t)0x1UL) /**< SPCTRL_SDIOOE_SDIO1 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO1 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO1 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO1 Setting */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO2 ((uint32_t)0x2UL) /**< SPCTRL_SDIOOE_SDIO2 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO2 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO2 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO2 Setting */
+ #define MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO3 ((uint32_t)0x3UL) /**< SPCTRL_SDIOOE_SDIO3 Value */
+ #define MXC_S_SPIXFC_SPCTRL_SDIOOE_SDIO3 (MXC_V_SPIXFC_SPCTRL_SDIOOE_SDIO3 << MXC_F_SPIXFC_SPCTRL_SDIOOE_POS) /**< SPCTRL_SDIOOE_SDIO3 Setting */
+
#define MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS 16 /**< SPCTRL_SCLKINH3 Position */
#define MXC_F_SPIXFC_SPCTRL_SCLKINH3 ((uint32_t)(0x1UL << MXC_F_SPIXFC_SPCTRL_SCLKINH3_POS)) /**< SPCTRL_SCLKINH3 Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h
index 275699f7d7a093f6a4363806844479c37bdd7371..1338cb9e6325f12b241a4b3bcea473cd0ad15f26 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/spixr_regs.h
@@ -96,7 +96,7 @@ typedef struct {
__IO uint32_t ctrl3; /**< <tt>\b 0x0C:</tt> SPIXR CTRL3 Register */
__IO uint32_t ctrl4; /**< <tt>\b 0x10:</tt> SPIXR CTRL4 Register */
__IO uint32_t brg_ctrl; /**< <tt>\b 0x14:</tt> SPIXR BRG_CTRL Register */
- __IO uint32_t i2s_ctrl; /**< <tt>\b 0x18:</tt> SPIXR I2S_CTRL Register */
+ __R uint32_t rsv_0x18;
__IO uint32_t dma; /**< <tt>\b 0x1C:</tt> SPIXR DMA Register */
__IO uint32_t irq; /**< <tt>\b 0x20:</tt> SPIXR IRQ Register */
__IO uint32_t irqe; /**< <tt>\b 0x24:</tt> SPIXR IRQE Register */
@@ -121,7 +121,6 @@ typedef struct {
#define MXC_R_SPIXR_CTRL3 ((uint32_t)0x0000000CUL) /**< Offset from SPIXR Base Address: <tt> 0x000C</tt> */
#define MXC_R_SPIXR_CTRL4 ((uint32_t)0x00000010UL) /**< Offset from SPIXR Base Address: <tt> 0x0010</tt> */
#define MXC_R_SPIXR_BRG_CTRL ((uint32_t)0x00000014UL) /**< Offset from SPIXR Base Address: <tt> 0x0014</tt> */
- #define MXC_R_SPIXR_I2S_CTRL ((uint32_t)0x00000018UL) /**< Offset from SPIXR Base Address: <tt> 0x0018</tt> */
#define MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPIXR Base Address: <tt> 0x001C</tt> */
#define MXC_R_SPIXR_IRQ ((uint32_t)0x00000020UL) /**< Offset from SPIXR Base Address: <tt> 0x0020</tt> */
#define MXC_R_SPIXR_IRQE ((uint32_t)0x00000024UL) /**< Offset from SPIXR Base Address: <tt> 0x0024</tt> */
@@ -277,25 +276,6 @@ typedef struct {
#define MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH ((uint32_t)0x80UL) /**< CTRL3_SSPOL_SS7_HIGH Value */
#define MXC_S_SPIXR_CTRL3_SSPOL_SS7_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) /**< CTRL3_SSPOL_SS7_HIGH Setting */
- #define MXC_F_SPIXR_CTRL3_SRPOL_POS 24 /**< CTRL3_SRPOL Position */
- #define MXC_F_SPIXR_CTRL3_SRPOL ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SRPOL_POS)) /**< CTRL3_SRPOL Mask */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR0_HIGH ((uint32_t)0x1UL) /**< CTRL3_SRPOL_SR0_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR0_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR0_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR0_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR1_HIGH ((uint32_t)0x2UL) /**< CTRL3_SRPOL_SR1_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR1_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR1_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR1_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR2_HIGH ((uint32_t)0x4UL) /**< CTRL3_SRPOL_SR2_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR2_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR2_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR2_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR3_HIGH ((uint32_t)0x8UL) /**< CTRL3_SRPOL_SR3_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR3_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR3_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR3_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR4_HIGH ((uint32_t)0x10UL) /**< CTRL3_SRPOL_SR4_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR4_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR4_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR4_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR5_HIGH ((uint32_t)0x20UL) /**< CTRL3_SRPOL_SR5_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR5_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR5_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR5_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR6_HIGH ((uint32_t)0x40UL) /**< CTRL3_SRPOL_SR6_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR6_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR6_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR6_HIGH Setting */
- #define MXC_V_SPIXR_CTRL3_SRPOL_SR7_HIGH ((uint32_t)0x80UL) /**< CTRL3_SRPOL_SR7_HIGH Value */
- #define MXC_S_SPIXR_CTRL3_SRPOL_SR7_HIGH (MXC_V_SPIXR_CTRL3_SRPOL_SR7_HIGH << MXC_F_SPIXR_CTRL3_SRPOL_POS) /**< CTRL3_SRPOL_SR7_HIGH Setting */
-
/**@} end of group SPIXR_CTRL3_Register */
/**
@@ -342,29 +322,6 @@ typedef struct {
/**@} end of group SPIXR_BRG_CTRL_Register */
-/**
- * @ingroup spixr_registers
- * @defgroup SPIXR_I2S_CTRL SPIXR_I2S_CTRL
- * @brief Register for controlling I2C mode.
- * @{
- */
- #define MXC_F_SPIXR_I2S_CTRL_I2S_EN_POS 0 /**< I2S_CTRL_I2S_EN Position */
- #define MXC_F_SPIXR_I2S_CTRL_I2S_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_I2S_CTRL_I2S_EN_POS)) /**< I2S_CTRL_I2S_EN Mask */
-
- #define MXC_F_SPIXR_I2S_CTRL_I2S_MUTE_POS 1 /**< I2S_CTRL_I2S_MUTE Position */
- #define MXC_F_SPIXR_I2S_CTRL_I2S_MUTE ((uint32_t)(0x1UL << MXC_F_SPIXR_I2S_CTRL_I2S_MUTE_POS)) /**< I2S_CTRL_I2S_MUTE Mask */
-
- #define MXC_F_SPIXR_I2S_CTRL_I2S_PAUSE_POS 2 /**< I2S_CTRL_I2S_PAUSE Position */
- #define MXC_F_SPIXR_I2S_CTRL_I2S_PAUSE ((uint32_t)(0x1UL << MXC_F_SPIXR_I2S_CTRL_I2S_PAUSE_POS)) /**< I2S_CTRL_I2S_PAUSE Mask */
-
- #define MXC_F_SPIXR_I2S_CTRL_I2S_MONO_POS 3 /**< I2S_CTRL_I2S_MONO Position */
- #define MXC_F_SPIXR_I2S_CTRL_I2S_MONO ((uint32_t)(0x1UL << MXC_F_SPIXR_I2S_CTRL_I2S_MONO_POS)) /**< I2S_CTRL_I2S_MONO Mask */
-
- #define MXC_F_SPIXR_I2S_CTRL_I2S_LJ_POS 4 /**< I2S_CTRL_I2S_LJ Position */
- #define MXC_F_SPIXR_I2S_CTRL_I2S_LJ ((uint32_t)(0x1UL << MXC_F_SPIXR_I2S_CTRL_I2S_LJ_POS)) /**< I2S_CTRL_I2S_LJ Mask */
-
-/**@} end of group SPIXR_I2S_CTRL_Register */
-
/**
* @ingroup spixr_registers
* @defgroup SPIXR_DMA SPIXR_DMA
@@ -434,9 +391,6 @@ typedef struct {
#define MXC_F_SPIXR_IRQ_ABORT_POS 9 /**< IRQ_ABORT Position */
#define MXC_F_SPIXR_IRQ_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_ABORT_POS)) /**< IRQ_ABORT Mask */
- #define MXC_F_SPIXR_IRQ_TIMEOUT_POS 10 /**< IRQ_TIMEOUT Position */
- #define MXC_F_SPIXR_IRQ_TIMEOUT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TIMEOUT_POS)) /**< IRQ_TIMEOUT Mask */
-
#define MXC_F_SPIXR_IRQ_M_DONE_POS 11 /**< IRQ_M_DONE Position */
#define MXC_F_SPIXR_IRQ_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_M_DONE_POS)) /**< IRQ_M_DONE Mask */
@@ -452,30 +406,6 @@ typedef struct {
#define MXC_F_SPIXR_IRQ_RX_UND_POS 15 /**< IRQ_RX_UND Position */
#define MXC_F_SPIXR_IRQ_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_UND_POS)) /**< IRQ_RX_UND Mask */
- #define MXC_F_SPIXR_IRQ_SR0A_POS 16 /**< IRQ_SR0A Position */
- #define MXC_F_SPIXR_IRQ_SR0A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR0A_POS)) /**< IRQ_SR0A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR1A_POS 17 /**< IRQ_SR1A Position */
- #define MXC_F_SPIXR_IRQ_SR1A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR1A_POS)) /**< IRQ_SR1A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR2A_POS 18 /**< IRQ_SR2A Position */
- #define MXC_F_SPIXR_IRQ_SR2A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR2A_POS)) /**< IRQ_SR2A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR3A_POS 19 /**< IRQ_SR3A Position */
- #define MXC_F_SPIXR_IRQ_SR3A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR3A_POS)) /**< IRQ_SR3A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR4A_POS 20 /**< IRQ_SR4A Position */
- #define MXC_F_SPIXR_IRQ_SR4A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR4A_POS)) /**< IRQ_SR4A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR5A_POS 21 /**< IRQ_SR5A Position */
- #define MXC_F_SPIXR_IRQ_SR5A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR5A_POS)) /**< IRQ_SR5A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR6A_POS 22 /**< IRQ_SR6A Position */
- #define MXC_F_SPIXR_IRQ_SR6A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR6A_POS)) /**< IRQ_SR6A Mask */
-
- #define MXC_F_SPIXR_IRQ_SR7A_POS 23 /**< IRQ_SR7A Position */
- #define MXC_F_SPIXR_IRQ_SR7A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SR7A_POS)) /**< IRQ_SR7A Mask */
-
/**@} end of group SPIXR_IRQ_Register */
/**
@@ -508,9 +438,6 @@ typedef struct {
#define MXC_F_SPIXR_IRQE_ABORT_POS 9 /**< IRQE_ABORT Position */
#define MXC_F_SPIXR_IRQE_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_ABORT_POS)) /**< IRQE_ABORT Mask */
- #define MXC_F_SPIXR_IRQE_TIMEOUT_POS 10 /**< IRQE_TIMEOUT Position */
- #define MXC_F_SPIXR_IRQE_TIMEOUT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TIMEOUT_POS)) /**< IRQE_TIMEOUT Mask */
-
#define MXC_F_SPIXR_IRQE_M_DONE_POS 11 /**< IRQE_M_DONE Position */
#define MXC_F_SPIXR_IRQE_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_M_DONE_POS)) /**< IRQE_M_DONE Mask */
@@ -526,30 +453,6 @@ typedef struct {
#define MXC_F_SPIXR_IRQE_RX_UND_POS 15 /**< IRQE_RX_UND Position */
#define MXC_F_SPIXR_IRQE_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_UND_POS)) /**< IRQE_RX_UND Mask */
- #define MXC_F_SPIXR_IRQE_SR0A_POS 16 /**< IRQE_SR0A Position */
- #define MXC_F_SPIXR_IRQE_SR0A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR0A_POS)) /**< IRQE_SR0A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR1A_POS 17 /**< IRQE_SR1A Position */
- #define MXC_F_SPIXR_IRQE_SR1A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR1A_POS)) /**< IRQE_SR1A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR2A_POS 18 /**< IRQE_SR2A Position */
- #define MXC_F_SPIXR_IRQE_SR2A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR2A_POS)) /**< IRQE_SR2A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR3A_POS 19 /**< IRQE_SR3A Position */
- #define MXC_F_SPIXR_IRQE_SR3A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR3A_POS)) /**< IRQE_SR3A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR4A_POS 20 /**< IRQE_SR4A Position */
- #define MXC_F_SPIXR_IRQE_SR4A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR4A_POS)) /**< IRQE_SR4A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR5A_POS 21 /**< IRQE_SR5A Position */
- #define MXC_F_SPIXR_IRQE_SR5A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR5A_POS)) /**< IRQE_SR5A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR6A_POS 22 /**< IRQE_SR6A Position */
- #define MXC_F_SPIXR_IRQE_SR6A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR6A_POS)) /**< IRQE_SR6A Mask */
-
- #define MXC_F_SPIXR_IRQE_SR7A_POS 23 /**< IRQE_SR7A Position */
- #define MXC_F_SPIXR_IRQE_SR7A ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SR7A_POS)) /**< IRQE_SR7A Mask */
-
/**@} end of group SPIXR_IRQE_Register */
/**
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..48f696670e2e15687ae06340ce0bd93fd3de8c31
--- /dev/null
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/srcc_regs.h
@@ -0,0 +1,183 @@
+/**
+ * @file srcc_regs.h
+ * @brief Registers, Bit Masks and Bit Positions for the SRCC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _SRCC_REGS_H_
+#define _SRCC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+ #pragma system_include
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup srcc
+ * @defgroup srcc_registers SRCC_Registers
+ * @brief Registers, Bit Masks and Bit Positions for the SRCC Peripheral Module.
+ * @details External Memory Cache Controller Registers.
+ */
+
+/**
+ * @ingroup srcc_registers
+ * Structure type to access the SRCC Registers.
+ */
+typedef struct {
+ __I uint32_t cache_id; /**< <tt>\b 0x0000:</tt> SRCC CACHE_ID Register */
+ __I uint32_t memcfg; /**< <tt>\b 0x0004:</tt> SRCC MEMCFG Register */
+ __R uint32_t rsv_0x8_0xff[62];
+ __IO uint32_t cache_ctrl; /**< <tt>\b 0x0100:</tt> SRCC CACHE_CTRL Register */
+ __R uint32_t rsv_0x104_0x6ff[383];
+ __IO uint32_t invalidate; /**< <tt>\b 0x0700:</tt> SRCC INVALIDATE Register */
+} mxc_srcc_regs_t;
+
+/* Register offsets for module SRCC */
+/**
+ * @ingroup srcc_registers
+ * @defgroup SRCC_Register_Offsets Register Offsets
+ * @brief SRCC Peripheral Register Offsets from the SRCC Base Peripheral Address.
+ * @{
+ */
+ #define MXC_R_SRCC_CACHE_ID ((uint32_t)0x00000000UL) /**< Offset from SRCC Base Address: <tt> 0x0000</tt> */
+ #define MXC_R_SRCC_MEMCFG ((uint32_t)0x00000004UL) /**< Offset from SRCC Base Address: <tt> 0x0004</tt> */
+ #define MXC_R_SRCC_CACHE_CTRL ((uint32_t)0x00000100UL) /**< Offset from SRCC Base Address: <tt> 0x0100</tt> */
+ #define MXC_R_SRCC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from SRCC Base Address: <tt> 0x0700</tt> */
+/**@} end of group srcc_registers */
+
+/**
+ * @ingroup srcc_registers
+ * @defgroup SRCC_CACHE_ID SRCC_CACHE_ID
+ * @brief Cache ID Register.
+ * @{
+ */
+ #define MXC_F_SRCC_CACHE_ID_RELNUM_POS 0 /**< CACHE_ID_RELNUM Position */
+ #define MXC_F_SRCC_CACHE_ID_RELNUM ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_RELNUM_POS)) /**< CACHE_ID_RELNUM Mask */
+
+ #define MXC_F_SRCC_CACHE_ID_PARTNUM_POS 6 /**< CACHE_ID_PARTNUM Position */
+ #define MXC_F_SRCC_CACHE_ID_PARTNUM ((uint32_t)(0xFUL << MXC_F_SRCC_CACHE_ID_PARTNUM_POS)) /**< CACHE_ID_PARTNUM Mask */
+
+ #define MXC_F_SRCC_CACHE_ID_CCHID_POS 10 /**< CACHE_ID_CCHID Position */
+ #define MXC_F_SRCC_CACHE_ID_CCHID ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_CCHID_POS)) /**< CACHE_ID_CCHID Mask */
+
+/**@} end of group SRCC_CACHE_ID_Register */
+
+/**
+ * @ingroup srcc_registers
+ * @defgroup SRCC_MEMCFG SRCC_MEMCFG
+ * @brief Memory Configuration Register.
+ * @{
+ */
+ #define MXC_F_SRCC_MEMCFG_CCHSZ_POS 0 /**< MEMCFG_CCHSZ Position */
+ #define MXC_F_SRCC_MEMCFG_CCHSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_CCHSZ_POS)) /**< MEMCFG_CCHSZ Mask */
+
+ #define MXC_F_SRCC_MEMCFG_MEMSZ_POS 16 /**< MEMCFG_MEMSZ Position */
+ #define MXC_F_SRCC_MEMCFG_MEMSZ ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_MEMSZ_POS)) /**< MEMCFG_MEMSZ Mask */
+
+/**@} end of group SRCC_MEMCFG_Register */
+
+/**
+ * @ingroup srcc_registers
+ * @defgroup SRCC_CACHE_CTRL SRCC_CACHE_CTRL
+ * @brief Cache Control and Status Register.
+ * @{
+ */
+ #define MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS 0 /**< CACHE_CTRL_CACHE_EN Position */
+ #define MXC_F_SRCC_CACHE_CTRL_CACHE_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS)) /**< CACHE_CTRL_CACHE_EN Mask */
+
+ #define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN_POS 1 /**< CACHE_CTRL_WRITE_ALLOC_EN Position */
+ #define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN_POS)) /**< CACHE_CTRL_WRITE_ALLOC_EN Mask */
+
+ #define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS 2 /**< CACHE_CTRL_CWFST_DIS Position */
+ #define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS)) /**< CACHE_CTRL_CWFST_DIS Mask */
+
+ #define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS 16 /**< CACHE_CTRL_CACHE_RDY Position */
+ #define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS)) /**< CACHE_CTRL_CACHE_RDY Mask */
+
+/**@} end of group SRCC_CACHE_CTRL_Register */
+
+/**
+ * @ingroup srcc_registers
+ * @defgroup SRCC_INVALIDATE SRCC_INVALIDATE
+ * @brief Invalidate All Cache Contents. Any time this register location is written
+ * (regardless of the data value), the cache controller immediately begins
+ * invalidating the entire contents of the cache memory. The cache will be in
+ * bypass mode until the invalidate operation is complete. System software can
+ * examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the
+ * invalidate operation is complete. Note that it is not necessary to disable the
+ * cache controller prior to beginning this operation. Reads from this register
+ * always return 0.
+ * @{
+ */
+ #define MXC_F_SRCC_INVALIDATE_IA_POS 0 /**< INVALIDATE_IA Position */
+ #define MXC_F_SRCC_INVALIDATE_IA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_IA_POS)) /**< INVALIDATE_IA Mask */
+
+/**@} end of group SRCC_INVALIDATE_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SRCC_REGS_H_ */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h
index 85424dd8d3a5ce8f46f28ea73d513c5d5102d728..952fc7aa89bf57cbacca4d9119a40ca1cb5d56fc 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/tpu_regs.h
@@ -349,8 +349,8 @@ typedef struct {
* @brief Crypto DMA Byte Count.
* @{
*/
- #define MXC_F_TPU_DMA_CNT_ADDR_POS 0 /**< DMA_CNT_ADDR Position */
- #define MXC_F_TPU_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */
+ #define MXC_F_TPU_DMA_CNT_COUNT_POS 0 /**< DMA_CNT_COUNT Position */
+ #define MXC_F_TPU_DMA_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_COUNT_POS)) /**< DMA_CNT_COUNT Mask */
/**@} end of group TPU_DMA_CNT_Register */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h
index 59fac235e8607607ed75646369b6f888519614f2..33f3e2973d58d48ee43f6755ab3024000ce4f954 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/uart_regs.h
@@ -370,12 +370,18 @@ typedef struct {
* @brief DMA Configuration.
* @{
*/
- #define MXC_F_UART_DMA_TDMA_EN_POS 0 /**< DMA_TDMA_EN Position */
- #define MXC_F_UART_DMA_TDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TDMA_EN_POS)) /**< DMA_TDMA_EN Mask */
+ #define MXC_F_UART_DMA_TXDMA_EN_POS 0 /**< DMA_TXDMA_EN Position */
+ #define MXC_F_UART_DMA_TXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TXDMA_EN_POS)) /**< DMA_TXDMA_EN Mask */
#define MXC_F_UART_DMA_RXDMA_EN_POS 1 /**< DMA_RXDMA_EN Position */
#define MXC_F_UART_DMA_RXDMA_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_EN_POS)) /**< DMA_RXDMA_EN Mask */
+ #define MXC_F_UART_DMA_RXDMA_START_POS 3 /**< DMA_RXDMA_START Position */
+ #define MXC_F_UART_DMA_RXDMA_START ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_START_POS)) /**< DMA_RXDMA_START Mask */
+
+ #define MXC_F_UART_DMA_RXDMA_AUTO_TO_POS 5 /**< DMA_RXDMA_AUTO_TO Position */
+ #define MXC_F_UART_DMA_RXDMA_AUTO_TO ((uint32_t)(0x1UL << MXC_F_UART_DMA_RXDMA_AUTO_TO_POS)) /**< DMA_RXDMA_AUTO_TO Mask */
+
#define MXC_F_UART_DMA_TXDMA_LEVEL_POS 8 /**< DMA_TXDMA_LEVEL Position */
#define MXC_F_UART_DMA_TXDMA_LEVEL ((uint32_t)(0x3FUL << MXC_F_UART_DMA_TXDMA_LEVEL_POS)) /**< DMA_TXDMA_LEVEL Mask */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h
index 1844cc2a245b65369c6f905c2d954cdc462ac5ca..5255bd0c98b358fc9c2d1b74768d7d5bdb3c4890 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Include/usbhs_regs.h
@@ -1037,8 +1037,8 @@ typedef struct {
* @brief Sets delay between HS resume to UTM normal operating mode.
* @{
*/
- #define MXC_F_USBHS_CTHSRTN_C_T_HSTRN_POS 0 /**< CTHSRTN_C_T_HSTRN Position */
- #define MXC_F_USBHS_CTHSRTN_C_T_HSTRN ((uint16_t)(0xFFFFUL << MXC_F_USBHS_CTHSRTN_C_T_HSTRN_POS)) /**< CTHSRTN_C_T_HSTRN Mask */
+ #define MXC_F_USBHS_CTHSRTN_C_T_HSRTN_POS 0 /**< CTHSRTN_C_T_HSRTN Position */
+ #define MXC_F_USBHS_CTHSRTN_C_T_HSRTN ((uint16_t)(0xFFFFUL << MXC_F_USBHS_CTHSRTN_C_T_HSRTN_POS)) /**< CTHSRTN_C_T_HSRTN Mask */
/**@} end of group USBHS_CTHSRTN_Register */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/gcc.mk b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/gcc.mk
index 18ae0f5e0abc398e07c30dcdff6f30131f3fefdf..53313a6737b94278d0a9721ee071a084d447fa76 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/gcc.mk
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/gcc.mk
@@ -41,7 +41,9 @@ endif
# Create output object file names
SRCS_NOPATH := $(foreach NAME,$(SRCS),$(basename $(notdir $(NAME))).c)
+BINS_NOPATH := $(foreach NAME,$(BINS),$(basename $(notdir $(NAME))).bin)
OBJS_NOPATH := $(SRCS_NOPATH:.c=.o)
+OBJS_NOPATH += $(BINS_NOPATH:.bin=.o)
OBJS := $(OBJS_NOPATH:%.o=$(BUILD_DIR)/%.o)
################################################################################
@@ -188,6 +190,9 @@ LD=${PREFIX}-gcc
# the command for striping objects.
STRIP=$(PREFIX)-strip
+# the utility to fix debug info file paths in finished executables.
+FIXDBGPATHS=$(wildcard $(shell which fixdbgpaths))
+
# The flags passed to the linker.
LDFLAGS=-mthumb \
-mcpu=cortex-m4 \
@@ -220,6 +225,17 @@ else
fixpath=$(1)
endif
+# Determine whether to include stripping of
+# debug symbols from generated archive files.
+gcc_strip_libraries=
+ifeq ($(STRIP_LIBRARIES),0)
+else
+ifneq ($(STRIP_LIBRARIES),)
+gcc_strip_libraries=1
+else
+endif
+endif
+
# Add the include file paths to AFLAGS and CFLAGS.
AFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
CFLAGS+=${patsubst %,-I%,$(call fixpath,$(IPATH))}
@@ -241,6 +257,32 @@ ${BUILD_DIR}/%.o: %.c
echo " CC ${<}"; \
fi
@${CC} ${CFLAGS} -o $(call fixpath,${@}) $(call fixpath,${<})
+ifneq ($(FIXDBGPATHS),)
+ifneq ($(FIXDBGPATHS_MATCH)$(FIXDBGPATHS_REPLACE),)
+ @if [ ! -e $(call fixpath,${@}) ]; \
+ then \
+ false; \
+ elif [ 'x${ECLIPSE}' != x ]; \
+ then \
+ echo $(FIXDBGPATHS) -f $(call fixpath,${@}) \
+ -m '$(FIXDBGPATHS_MATCH)' \
+ -r '$(FIXDBGPATHS_REPLACE)'; \
+ elif [ 'x${VERBOSE}' != x ]; \
+ then \
+ echo $(FIXDBGPATHS) -f $(call fixpath,${@}) \
+ -m '$(FIXDBGPATHS_MATCH)' \
+ -r '$(FIXDBGPATHS_REPLACE)'; \
+ elif [ 'x${QUIET}' != x ]; \
+ then \
+ :; \
+ else \
+ echo " FIXDBGPATHS ${@}"; \
+ fi
+ @$(FIXDBGPATHS) -f $(call fixpath,${@}) \
+ -m '$(FIXDBGPATHS_MATCH)' \
+ -r '$(FIXDBGPATHS_REPLACE)'
+endif
+endif
ifeq "$(CYGWIN)" "True"
@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
endif
@@ -280,6 +322,28 @@ ifeq "$(CYGWIN)" "True"
@sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
endif
+# The rule for building the object file from binary source file.
+# Resulting object will have the following symbols
+# _binary_<file_name>_bin_start
+# _binary_<file_name>_bin_end
+# _binary_<file_name>_bin_size
+${BUILD_DIR}/%.o: %.bin
+ @if [ 'x${VERBOSE}' = x ]; \
+ then \
+ echo " CP ${<}"; \
+ elif [ 'x${QUIET}' != x ]; \
+ then \
+ :; \
+ else \
+ echo ${OBJCOPY} -I binary -B arm -O elf32-littlearm --rename-section \
+ .data=.text $(call fixpath,${<}) $(call fixpath,${@}); \
+ fi
+ @${OBJCOPY} -I binary -B arm -O elf32-littlearm --rename-section \
+ .data=.text $(call fixpath,${<}) $(call fixpath,${@})
+ifeq "$(CYGWIN)" "True"
+ @sed -i -r -e 's/([A-Na-n]):/\/cygdrive\/\L\1/g' -e 's/\\([A-Za-z])/\/\1/g' ${@:.o=.d}
+endif
+
# The rule for creating an object library.
${BUILD_DIR}/%.a:
@if [ 'x${VERBOSE}' = x ]; \
@@ -292,7 +356,7 @@ ${BUILD_DIR}/%.a:
echo ${AR} -cr $(call fixpath,${@}) $(call fixpath,${^}); \
fi
@${AR} -cr $(call fixpath,${@}) $(call fixpath,${^})
-ifneq ($(STRIP_LIBRARIES),)
+ifneq ($(gcc_strip_libraries),)
ifneq ($(STRIP),)
@if [ 'x${ECLIPSE}' != x ]; \
then \
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld
index 65eb1c59991e5816ba3ae49f76648d714fc61637..51e3599b55dbdb4b2267b58493c4003239d908b0 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/max32665.ld
@@ -37,15 +37,18 @@
/* Allocate space if SDMA_SIZE is defined at the start of SRAM*/
SRAM_ORIGIN = 0x20000000;
-SDMA_LEN = DEFINED(SDMA_SIZE) ? SDMA_SIZE : 0;
-OTP_LEN = DEFINED(SDMA_SIZE) ? 0x40 : 0;
-SHARED_LEN = DEFINED(SDMA_SIZE) ? 1k : 0;
+SDMA_CODE_LEN = DEFINED(SDMA_CODE_SIZE) ? SDMA_CODE_SIZE : 0;
+SDMA_DATA_LEN = DEFINED(SDMA_DATA_SIZE) ? SDMA_DATA_SIZE : 0;
+SDMA_LEN = SDMA_CODE_LEN + SDMA_DATA_LEN;
+OTP_LEN = DEFINED(SDMA_CODE_SIZE) ? 0x40 : 0;
+SHARED_LEN = DEFINED(SDMA_CODE_SIZE) ? 1k : 0;
SHARED_LEN_HALF = SHARED_LEN / 2;
OTP_ADDR = SRAM_ORIGIN;
SHARED_ADDR = OTP_ADDR + OTP_LEN;
-SDMA_ADDR = SHARED_ADDR + SHARED_LEN;
-SRAM_ADDR = SDMA_ADDR + SDMA_LEN;
+SDMA_DATA_ADDR = SHARED_ADDR + SHARED_LEN;
+SDMA_CODE_ADDR = SDMA_DATA_ADDR + SDMA_DATA_LEN;
+SRAM_ADDR = SDMA_CODE_ADDR + SDMA_CODE_LEN;
/* Give leftover SRAM to the SRAM memory region */
/* SRAM_SIZE must be defined */
@@ -60,7 +63,8 @@ MEMORY {
OTP (rwx) : ORIGIN = OTP_ADDR, LENGTH = OTP_LEN
ARM_SHARED(rwx) : ORIGIN = SHARED_ADDR, LENGTH = SHARED_LEN_HALF
SDMA_SHARED(rwx): ORIGIN = SHARED_ADDR + SHARED_LEN_HALF, LENGTH = SHARED_LEN_HALF
- SDMA (rwx) : ORIGIN = SDMA_ADDR, LENGTH = SDMA_LEN
+ SDMA_DATA (rwx) : ORIGIN = SDMA_DATA_ADDR, LENGTH = SDMA_DATA_LEN
+ SDMA_CODE (rwx) : ORIGIN = SDMA_CODE_ADDR, LENGTH = SDMA_CODE_LEN
SRAM (rwx) : ORIGIN = SRAM_ADDR, LENGTH = SRAM_LEN
SPID (rw) : ORIGIN = 0x80000000, LENGTH = 512M
@@ -158,14 +162,23 @@ SECTIONS {
_esdma_shared = ALIGN(., 4);
} > SDMA_SHARED
- .sdma :
+ .sdma_code :
{
- _sdma = ALIGN(., 4);
+ _sdma_code = ALIGN(., 4);
*(.sdma_code*) /*SDMA Code*/
- _esdma = ALIGN(., 4);
- } > SDMA AT>FLASH
- __load_sdma = LOADADDR(.sdma);
+ _esdma_code = ALIGN(., 4);
+ } > SDMA_CODE AT>FLASH
+ __load_sdma_code = LOADADDR(.sdma_code);
+
+ .sdma_data :
+ {
+ _sdma_data = ALIGN(., 4);
+ *(.sdma_data*) /*SDMA Data*/
+
+ _esdma_data = ALIGN(., 4);
+ } > SDMA_DATA AT>FLASH
+ __load_sdma_data = LOADADDR(.sdma_data);
.bss :
{
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
index ecfdb306a81c119548333884d31bdba3fbe305b9..115b857be8e1cb352d1af01c04e0873e29254a06 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/GCC/startup_max32665.S
@@ -50,9 +50,13 @@
#endif
/* Define SDMA_SIZE to enable the loading of the SDMA image */
-#ifdef __SDMA_SIZE
- .global SDMA_SIZE
- .equ SDMA_SIZE, __SDMA_SIZE
+#ifdef __SDMA_CODE_SIZE
+ .global SDMA_CODE_SIZE
+ .equ SDMA_CODE_SIZE, __SDMA_CODE_SIZE
+#endif
+#ifdef __SDMA_DATA_SIZE
+ .global SDMA_DATA_SIZE
+ .equ SDMA_DATA_SIZE, __SDMA_DATA_SIZE
#endif
.globl Stack_Size
@@ -194,7 +198,7 @@ __isr_vector:
.long ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */
.long DVS_IRQHandler /* 0x63 0x018C 99: DVS Controller */
.long SIMO_IRQHandler /* 0x64 0x0190 100: SIMO Controller */
- .long RPU_IRQHandler /* 0x65 0x0194 101: RPU */ /* @TODO: Is this correct? */
+ .long SCA_IRQHandler /* 0x65 0x0194 101: SCA */
.long AUDIO_IRQHandler /* 0x66 0x0198 102: Audio subsystem */
.long FLC1_IRQHandler /* 0x67 0x019C 103: Flash Control 1 */
.long RSV88_IRQHandler /* 0x68 0x01A0 104: UART 3 */
@@ -280,7 +284,41 @@ ecc_init_exit:
.LC1:
#endif
-#ifdef __SDMA_SIZE
+#ifdef __SDMA_CODE_SIZE
+/* Loop to copy data from read only SDMA memory to RAM. The ranges
+ * of copy from/to are specified by following symbols evaluated in
+ * linker script.
+ * __load_sdma: Where data sections are saved.
+ * _sdma /_esdma: RAM address range that data should be
+ * copied to. Both must be aligned to 4 bytes boundary. */
+
+ ldr r1, =__load_sdma_code
+ ldr r2, =_sdma_code
+ ldr r3, =_esdma_code
+
+#if 0
+/* Here are two copies of loop implemenations. First one favors code size
+ * and the second one favors performance. Default uses the first one.
+ * Change to "#if 0" to use the second one */
+.LC0_sdma_code:
+ cmp r2, r3
+ ittt lt
+ ldrlt r0, [r1], #4
+ strlt r0, [r2], #4
+ blt .LC0_sdma_code
+#else
+ subs r3, r2
+ ble .LC1_sdma_code
+.LC0_sdma_code:
+ subs r3, #4
+ ldr r0, [r1, r3]
+ str r0, [r2, r3]
+ bgt .LC0_sdma_code
+.LC1_sdma_code:
+#endif
+#endif
+
+#ifdef __SDMA_DATA_SIZE
/* Loop to copy data from read only SDMA memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
@@ -288,32 +326,33 @@ ecc_init_exit:
* _sdma /_esdma: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
- ldr r1, =__load_sdma
- ldr r2, =_sdma
- ldr r3, =_esdma
+ ldr r1, =__load_sdma_data
+ ldr r2, =_sdma_data
+ ldr r3, =_esdma_data
#if 0
/* Here are two copies of loop implemenations. First one favors code size
* and the second one favors performance. Default uses the first one.
* Change to "#if 0" to use the second one */
-.LC0_sdma:
+.LC0_sdma_data:
cmp r2, r3
ittt lt
ldrlt r0, [r1], #4
strlt r0, [r2], #4
- blt .LC0_sdma
+ blt .LC0_sdma_data
#else
subs r3, r2
- ble .LC1_sdma
-.LC0_sdma:
+ ble .LC1_sdma_data
+.LC0_sdma_data:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
- bgt .LC0_sdma
-.LC1_sdma:
+ bgt .LC0_sdma_data
+.LC1_sdma_data:
#endif
#endif
+
/*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
@@ -460,7 +499,7 @@ ecc_init_exit:
def_irq_handler ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */
def_irq_handler DVS_IRQHandler /* 0x63 0x018C 99: DVS Controller */
def_irq_handler SIMO_IRQHandler /* 0x64 0x0190 100: SIMO Controller */
- def_irq_handler RPU_IRQHandler /* 0x65 0x0194 101: RPU */ /* @TODO: Is this correct? */
+ def_irq_handler SCA_IRQHandler /* 0x65 0x0194 101: SCA */ /* @TODO: Is this correct? */
def_irq_handler AUDIO_IRQHandler /* 0x66 0x0198 102: Audio subsystem */
def_irq_handler FLC1_IRQHandler /* 0x67 0x019C 103: Flash Control 1 */
def_irq_handler RSV88_IRQHandler /* 0x68 0x01A0 104: UART 3 */
diff --git a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c
index 58025a761482f29de9179252f5faf158c930e91d..4918903a23e3e154093104fc6c92744b4526b21f 100644
--- a/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c
+++ b/lib/sdk/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c
@@ -143,7 +143,7 @@ __weak void SystemInit(void)
__ISB();
// Initialize backup mode entry point to safe default value.
- MXC_PWRSEQ->gp0 = (uint32_t)(Reset_Handler) | 1;
+ MXC_PWRSEQ->buretvec = (uint32_t)(Reset_Handler) | 1;
// FIXME Pre-production parts: Enable TME, disable ICache Read Buffer, disable TME
*(uint32_t *)0x40000c00 = 1;
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/flc.h b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/flc.h
index 5d24185a5b011ddd4bb05d7913ec250af638c69a..6c1108a9a250d89f229179f5602eb1935bd4953e 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/flc.h
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/flc.h
@@ -88,6 +88,14 @@ int FLC_Busy(void);
*/
int FLC_MassErase(void);
+/**
+ * @brief Erases the selected flash array.
+ * @param inst Index of the desired flash array to erase.
+ * @note This function must be executed from RAM.
+ * @return #E_NO_ERROR If function is successful.
+ */
+int FLC_MassEraseInst(int inst);
+
/**
* @brief Erases the page of flash at the specified address.
* @note This function must be executed from RAM.
@@ -181,6 +189,15 @@ int FLC_GetFlags(void);
*/
int FLC_ClearFlags(uint32_t mask);
+/**
+ * @brief Test to see if info block is already unlocked
+ *
+ * @param[in] address The address in the info block
+ *
+ * @return #E_NO_ERROR If unlocked, E_UNINITIALIZED if locked.
+ */
+int FLC_InfoBlockUnlocked(uint32_t address);
+
/**
* @brief Unlock info block
*
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/lp.h b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/lp.h
index a9b23baf855609ed8d9aa8256cd342194829c728..23234192c30623697ea2ddaeff4bbdd7c9e0db94 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/lp.h
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/lp.h
@@ -346,16 +346,6 @@ void LP_FastWakeupEnable(void);
*/
void LP_FastWakeupDisable(void);
-/**
- * @brief Enable Power Fail Monitor
- */
-void LP_PowerFailMonitorEnable(void);
-
-/**
- * @brief Disable Power Fail Monitor
- */
-void LP_PowerFailMonitorDisable(void);
-
/**
* @brief Enables the selected amount of RAM retention in backup mode
* Using any RAM retention removes the ability to shut down VcoreB
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/mxc_sys.h b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/mxc_sys.h
index fb8a2e2acfe5be10a04bbc28eaa9ed7a56aeca85..2cbe11a055e519b4df9aadeaf7d8702bf2d68f13 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/mxc_sys.h
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/mxc_sys.h
@@ -65,7 +65,7 @@ extern "C" {
/** @brief System reset0 and reset1 enumeration. Used in SYS_PeriphReset0 function */
typedef enum {
SYS_RESET_DMA = MXC_F_GCR_RSTR0_DMA_POS, /**< Reset DMA */
- SYS_RESET_WDT = MXC_F_GCR_RSTR0_WDT_POS, /**< Reset WDT */
+ SYS_RESET_WDT = MXC_F_GCR_RSTR0_WDT0_POS, /**< Reset WDT */
SYS_RESET_GPIO0 = MXC_F_GCR_RSTR0_GPIO0_POS, /**< Reset GPIO0 */
SYS_RESET_GPIO1 = MXC_F_GCR_RSTR0_GPIO1_POS, /**< Reset GPIO1 */
SYS_RESET_TIMER0 = MXC_F_GCR_RSTR0_TIMER0_POS, /**< Reset TIMER0 */
@@ -76,8 +76,8 @@ typedef enum {
SYS_RESET_TIMER5 = MXC_F_GCR_RSTR0_TIMER5_POS, /**< Reset TIMER5 */
SYS_RESET_UART0 = MXC_F_GCR_RSTR0_UART0_POS, /**< Reset UART0 */
SYS_RESET_UART1 = MXC_F_GCR_RSTR0_UART1_POS, /**< Reset UART1 */
- SYS_RESET_SPI1 = MXC_F_GCR_RSTR0_SPI0_POS, /**< Reset SPI0 */
- SYS_RESET_SPI2 = MXC_F_GCR_RSTR0_SPI1_POS, /**< Reset SPI1 */
+ SYS_RESET_SPI1 = MXC_F_GCR_RSTR0_SPI1_POS, /**< Reset SPI0 */
+ SYS_RESET_SPI2 = MXC_F_GCR_RSTR0_SPI2_POS, /**< Reset SPI1 */
SYS_RESET_I2C0 = MXC_F_GCR_RSTR0_I2C0_POS, /**< Reset I2C0 */
SYS_RESET_RTC = MXC_F_GCR_RSTR0_RTC_POS, /**< Reset RTC */
SYS_RESET_CRYPTO = MXC_F_GCR_RSTR0_CRYPTO_POS, /**< Reset CRYPTO */
@@ -98,7 +98,7 @@ typedef enum {
SYS_RESET_HTR0 = (MXC_F_GCR_RSTR1_HTMR0_POS + 32), /**< Reset HTMR0 */
SYS_RESET_HTMR1 = (MXC_F_GCR_RSTR1_HTMR1_POS + 32), /**< Reset HTMR1 */
SYS_RESET_WDT1 = (MXC_F_GCR_RSTR1_WDT1_POS + 32), /**< Reset WDT1 */
- SYS_RESET_SPI0 = (MXC_F_GCR_RSTR1_QSPI0_AHB_POS + 32), /**< Reset QSPI0_AHB */
+ SYS_RESET_SPI0 = (MXC_F_GCR_RSTR1_SPI0_POS + 32), /**< Reset QSPI0_AHB */
SYS_RESET_SPIXMEM = (MXC_F_GCR_RSTR1_SPIXMEM_POS + 32), /**< Reset SPIXMEM */
SYS_RESET_SMPHR = (MXC_F_GCR_RSTR1_SMPHR_POS + 32) /**< Reset SMPHR */
} sys_reset_t;
@@ -109,18 +109,18 @@ typedef enum {
SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PERCKCN0_GPIO1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_GPIO1D clock */
SYS_PERIPH_CLOCK_USB = MXC_F_GCR_PERCKCN0_USBD_POS, /**< Disable MXC_F_GCR_PERCKCN0_USBD clock */
SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PERCKCN0_DMAD_POS, /**< Disable MXC_F_GCR_PERCKCN0_DMAD clock */
- SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PERCKCN0_SPI0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
- SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PERCKCN0_SPI1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI2D clock */
+ SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PERCKCN0_SPI1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI1D clock */
+ SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PERCKCN0_SPI2D_POS, /**< Disable MXC_F_GCR_PERCKCN0_SPI2D clock */
SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PERCKCN0_UART0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_UART0D clock */
SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PERCKCN0_UART1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_UART1D clock */
SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PERCKCN0_I2C0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_I2C0D clock */
SYS_PERIPH_CLOCK_TPU = MXC_F_GCR_PERCKCN0_CRYPTOD_POS, /**< Disable MXC_F_GCR_PERCKCN0_CRYPTOD clock */
- SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_T0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
- SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_T1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
- SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_T2D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
- SYS_PERIPH_CLOCK_T3 = MXC_F_GCR_PERCKCN0_T3D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T3D clock */
- SYS_PERIPH_CLOCK_T4 = MXC_F_GCR_PERCKCN0_T4D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T4D clock */
- SYS_PERIPH_CLOCK_T5 = MXC_F_GCR_PERCKCN0_T5D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T5D clock */
+ SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_TIMER0D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T0D clock */
+ SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_TIMER1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T1D clock */
+ SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_TIMER2D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T2D clock */
+ SYS_PERIPH_CLOCK_T3 = MXC_F_GCR_PERCKCN0_TIMER3D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T3D clock */
+ SYS_PERIPH_CLOCK_T4 = MXC_F_GCR_PERCKCN0_TIMER4D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T4D clock */
+ SYS_PERIPH_CLOCK_T5 = MXC_F_GCR_PERCKCN0_TIMER5D_POS, /**< Disable MXC_F_GCR_PERCKCN0_T5D clock */
SYS_PERIPH_CLOCK_ADC = MXC_F_GCR_PERCKCN0_ADCD_POS, /**< Disable MXC_F_GCR_PERCKCN0_ADCD clock */
SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PERCKCN0_I2C1D_POS, /**< Disable MXC_F_GCR_PERCKCN0_I2C1D clock */
SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PERCKCN0_PTD_POS, /**< Disable MXC_F_GCR_PERCKCN0_PTD clock */
@@ -136,7 +136,7 @@ typedef enum {
SYS_PERIPH_CLOCK_SDHC =(MXC_F_GCR_PERCKCN1_SDHCD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_SDHCD clock */
SYS_PERIPH_CLOCK_ICACHEXIP =(MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_ICACHEXIPD clock */
SYS_PERIPH_CLOCK_OWIRE =(MXC_F_GCR_PERCKCN1_OWIRED_POS + 32), /**<Disable MXC_F_GCR_PERCKCN1_OWIRED clock */
- SYS_PERIPH_CLOCK_SPI0 =(MXC_F_GCR_PERCKCN1_SPI3D_POS + 32), /**< Disable QSPI Clock (API Calls QSPI SPI0) */
+ SYS_PERIPH_CLOCK_SPI0 =(MXC_F_GCR_PERCKCN1_SPI0D_POS + 32), /**< Disable QSPI Clock (API Calls QSPI SPI0) */
SYS_PERIPH_CLOCK_SPIXIPD =(MXC_F_GCR_PERCKCN1_SPIXIPDD_POS + 32),
SYS_PERIPH_CLOCK_DMA1 =(MXC_F_GCR_PERCKCN1_DMA1_POS + 32),
SYS_PERIPH_CLOCK_AUDIO =(MXC_F_GCR_PERCKCN1_AUDIO_POS + 32),
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rpu.h b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rpu.h
index a323cedf1b1c7ff7c68910db2a46f7edb8cae24b..0f7259efc357c27a3e6eee6bddd8bae01a1d5f61 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rpu.h
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rpu.h
@@ -90,7 +90,7 @@ typedef enum {
RPU_RTC = MXC_R_RPU_RTC,
RPU_WUT = MXC_R_RPU_WUT,
RPU_PWRSEQ = MXC_R_RPU_PWRSEQ,
- RPU_BBCR = MXC_R_RPU_BBCR,
+ RPU_MCR = MXC_R_RPU_MCR,
RPU_GPIO0 = MXC_R_RPU_GPIO0,
RPU_GPIO1 = MXC_R_RPU_GPIO1,
RPU_TMR0 = MXC_R_RPU_TMR0,
@@ -101,36 +101,36 @@ typedef enum {
RPU_TMR5 = MXC_R_RPU_TMR5,
RPU_HTIMER0 = MXC_R_RPU_HTIMER0,
RPU_HTIMER1 = MXC_R_RPU_HTIMER1,
- RPU_I2C0 = MXC_R_RPU_I2C0,
- RPU_I2C1 = MXC_R_RPU_I2C1,
- RPU_I2C2 = MXC_R_RPU_I2C2,
- RPU_SPIXIPM = MXC_R_RPU_SPIXIPM,
- RPU_SPIXIPMC = MXC_R_RPU_SPIXIPMC,
+ RPU_I2C0_BUS0 = MXC_R_RPU_I2C0_BUS0,
+ RPU_I2C1_BUS0 = MXC_R_RPU_I2C1_BUS0,
+ RPU_I2C2_BUS0 = MXC_R_RPU_I2C2_BUS0,
+ RPU_SPIXFM = MXC_R_RPU_SPIXFM,
+ RPU_SPIXFC = MXC_R_RPU_SPIXFC,
RPU_DMA0 = MXC_R_RPU_DMA0,
RPU_FLC1 = MXC_R_RPU_FLC1,
- RPU_ICACHE0 = MXC_R_RPU_ICACHE0,
- RPU_ICACHE1 = MXC_R_RPU_ICACHE1,
- RPU_ICACHEXIP = MXC_R_RPU_ICACHEXIP,
- RPU_DCACHE = MXC_R_RPU_DCACHE,
+ RPU_ICC0 = MXC_R_RPU_ICC0,
+ RPU_ICC1 = MXC_R_RPU_ICC1,
+ RPU_SFCC = MXC_R_RPU_SFCC,
+ RPU_SRCC = MXC_R_RPU_SRCC,
RPU_ADC = MXC_R_RPU_ADC,
RPU_DMA1 = MXC_R_RPU_DMA1,
RPU_SDMA = MXC_R_RPU_SDMA,
- RPU_SPID = MXC_R_RPU_SPID,
- RPU_PT = MXC_R_RPU_PT,
+ RPU_SPIXR = MXC_R_RPU_SPIXR,
+ RPU_PTG_BUS0 = MXC_R_RPU_PTG_BUS0,
RPU_OWM = MXC_R_RPU_OWM,
RPU_SEMA = MXC_R_RPU_SEMA,
RPU_UART0 = MXC_R_RPU_UART0,
RPU_UART1 = MXC_R_RPU_UART1,
RPU_UART2 = MXC_R_RPU_UART2,
- RPU_QSPI1 = MXC_R_RPU_QSPI1,
- RPU_QSPI2 = MXC_R_RPU_QSPI2,
+ RPU_SPI1 = MXC_R_RPU_SPI1,
+ RPU_SPI2 = MXC_R_RPU_SPI2,
RPU_AUDIO = MXC_R_RPU_AUDIO,
RPU_TRNG = MXC_R_RPU_TRNG,
RPU_BTLE = MXC_R_RPU_BTLE,
RPU_USBHS = MXC_R_RPU_USBHS,
RPU_SDIO = MXC_R_RPU_SDIO,
- RPU_SPIXIPMFIFO = MXC_R_RPU_SPIXIPMFIFO,
- RPU_QSPI0 = MXC_R_RPU_QSPI0
+ RPU_SPIXM_FIFO = MXC_R_RPU_SPIXM_FIFO,
+ RPU_SPI0 = MXC_R_RPU_SPI0
} rpu_device_t;
/* **** Function Prototypes **** */
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rtc.h b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rtc.h
index 0778e5dbc833524aa71f48aab442b667d53c300b..bb1f59a600188823a0924f68ec2959e94414757c 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rtc.h
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/rtc.h
@@ -73,13 +73,6 @@ typedef enum {
F_32KHZ = 32, /**< 32Khz */
} rtc_freq_sel_t;
-typedef enum {
- NOISE_IMMUNE_MODE = MXC_S_RTC_CTRL_X32KMD_NOISEIMMUNEMODE,
- QUIET_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETMODE,
- QUIET_STOP_WARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPWITHWARMUP,
- QUIET_STOP_NOWARMUP_MODE = MXC_S_RTC_CTRL_X32KMD_QUIETINSTOPNOWARMUP,
-} rtc_osc_mode_t;
-
/**
*@brief Enables Time-of-Day's Alarm Interrupt
*@param rtc pointer to the rtc register structure
@@ -175,7 +168,7 @@ int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint16_t ssec, sys_cfg_rtc_t *sy
* @return #E_BUSY If RTC is busy.
*/
int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
- rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg);
+ const sys_cfg_rtc_t* sys_cfg);
/**
*@brief Set Trim register value
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Include/srcc.h b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/srcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..838d0a49985b6d0caca2b724d8621a6b3f8ed9c1
--- /dev/null
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Include/srcc.h
@@ -0,0 +1,149 @@
+/**
+ ******************************************************************************
+ * @file srcc.h
+ * @brief This file contains all functions prototypes and data types for the
+ * External Memory Cache Controller (SRCC) driver
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>©
+ * COPYRIGHT 2017 Maxim Integrated Products, Inc.,
+ * All Rights Reserved.</center></h2>
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Maxim Integrated Products, Inc. retains all
+* ownership rights.
+*
+*
+********************************************************************************
+*/
+/**
+ * @defgroup srcc External Memory Cache Controller (SRCC)
+ * @ingroup periphlibs
+ * @{
+ */
+
+#ifndef _SRCC_H_
+#define _SRCC_H_
+
+/***** Includes *****/
+#include "srcc_regs.h"
+#include "mxc_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***** Definitions *****/
+
+/**
+ * Enumeration type for the SRCC Cache ID Register
+ */
+typedef enum {
+ SRCC_CACHE_ID_RELNUM, // Release Number
+ SRCC_CACHE_ID_PARTNUM, // Part Number
+ SRCC_CACHE_ID_CCHID // Cache ID
+}
+srcc_cache_id_t;
+
+/***** Function Prototypes *****/
+
+/**
+ * @brief Reads the data from the SRCC Cache ID Register
+ * @param id Enumeration type for the SRCC Cache ID Register
+ * @returns The contents of SRCC cache ID Register
+ */
+uint32_t SRCC_ID(srcc_cache_id_t id);
+
+/**
+ * @brief Gets the cache size in Kbytes. The default value is 16KB.
+ * @returns Cache size, in Kbytes
+ */
+uint32_t SRCC_Cache_Size(void);
+
+/**
+ * @brief Gets the main memory size in units of 128KB. The default value is 512MB.
+ * @returns Main memory size, in units of 128KB
+ */
+uint32_t SRCC_Mem_Size(void);
+
+/**
+ * @brief Enables the data cache controller
+ */
+void SRCC_Enable(void);
+
+/**
+ * @brief Disables the data cache controller
+ */
+void SRCC_Disable(void);
+
+/**
+ * @brief Flushes the data cache controller
+ */
+void SRCC_Flush(void);
+
+/**
+ * @brief Enables write-allocate mode with data cache controller
+ */
+void SRCC_Write_Alloc_Enable(void);
+
+/**
+ * @brief Disables write-allocate mode with data cache controller
+ */
+void SRCC_Write_Alloc_Disable(void);
+
+/**
+ * @brief Enables critical-word-first mode with data cache controller
+ */
+void SRCC_Critical_Word_First_Enable(void);
+
+/**
+ * @brief Disables critical-word-first mode with data cache controller
+ */
+void SRCC_Critical_Word_First_Disable(void);
+
+/**
+ * @brief Reads the SRCC Cache ready flag, which is set and cleared by hardware
+ * @returns SRCC Cache ready flag
+ */
+uint32_t SRCC_Ready(void);
+
+/**
+ * @brief Invalidate the entire contents of the data cache.
+ */
+void SRCC_Invalidate_All(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _SRCC_H_*/
+/**
+ * @} end of srcc
+ */
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Makefile b/lib/sdk/Libraries/MAX32665PeriphDriver/Makefile
index 51b33b8062f9df22599bbc562d3acd271e2ab8e0..8189801f152af11dcd07e712310b9c8b7cbcaab9 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Makefile
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Makefile
@@ -68,7 +68,6 @@ SRCS += hash.c
SRCS += crc.c
SRCS += dma.c
SRCS += dvs.c
-SRCS += emcc.c
SRCS += flc.c
SRCS += gpio.c
SRCS += htmr.c
@@ -95,6 +94,7 @@ SRCS += spi.c
SRCS += spixr.c
SRCS += spixf.c
SRCS += spixfc.c
+SRCS += srcc.c
SRCS += tmr.c
SRCS += tmr_utils.c
SRCS += trng.c
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/flc.c b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/flc.c
index f697c2780402234a8887ed07437c2b2e1664f95c..908520a35e2cbfe0098cf97d0bb4c6e6e31f6016 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/flc.c
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/flc.c
@@ -154,37 +154,53 @@ int FLC_Busy(void)
#else
__attribute__((section(".flashprog")))
#endif
-int FLC_MassErase(void)
+int FLC_MassEraseInst(int inst)
{
- int err,i;
+ int err;
mxc_flc_regs_t *flc;
- for (i=0; i<MXC_FLC_INSTANCES; i++) {
- flc = MXC_FLC_GET_FLC(i);
- if ((err = prepare_flc(flc)) != E_NO_ERROR) {
- return err;
- }
-
- /* Write mass erase code */
- flc->cn = (flc->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEALL;
-
- /* Issue mass erase command */
- flc->cn |= MXC_F_FLC_CN_ME;
-
- /* Wait until flash operation is complete */
- while (busy_flc(flc));
- /* Lock flash */
- flc->cn &= ~MXC_F_FLC_CN_UNLOCK;
-
- /* Check access violations */
- if (flc->intr & MXC_F_FLC_INTR_AF) {
- flc->intr &= ~MXC_F_FLC_INTR_AF;
- return E_BAD_STATE;
- }
-
- // Flush cache
- SYS_Flash_Operation();
+ flc = MXC_FLC_GET_FLC(inst);
+ if ((err = prepare_flc(flc)) != E_NO_ERROR) {
+ return err;
}
- return E_NO_ERROR;
+
+ /* Write mass erase code */
+ flc->cn = (flc->cn & ~MXC_F_FLC_CN_ERASE_CODE) | MXC_S_FLC_CN_ERASE_CODE_ERASEALL;
+
+ /* Issue mass erase command */
+ flc->cn |= MXC_F_FLC_CN_ME;
+
+ /* Wait until flash operation is complete */
+ while (busy_flc(flc));
+ /* Lock flash */
+ flc->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+ /* Check access violations */
+ if (flc->intr & MXC_F_FLC_INTR_AF) {
+ flc->intr &= ~MXC_F_FLC_INTR_AF;
+ return E_BAD_STATE;
+ }
+
+ // Flush cache
+ SYS_Flash_Operation();
+ return E_NO_ERROR;
+}
+
+
+//******************************************************************************
+#ifdef __IAR_SYSTEMS_ICC__
+ #pragma section=".flashprog"
+#else
+ __attribute__((section(".flashprog")))
+#endif
+int FLC_MassErase(void)
+{
+ int err;
+
+ if((err = FLC_MassEraseInst(0)) != E_NO_ERROR) {
+ return err;
+ }
+
+ return FLC_MassEraseInst(1);
}
//******************************************************************************
@@ -601,6 +617,19 @@ int FLC_ClearFlags(uint32_t mask)
return E_NO_ERROR;
}
+int FLC_InfoBlockUnlocked(uint32_t address)
+{
+ /* Check to see if info block is unlocked */
+ /* Flash at offset 0x20 will appear erased */
+ uint32_t* infoData = (uint32_t*)(address + 0x20);
+
+ if(*infoData == 0xFFFFFFFF) {
+ return E_NO_ERROR;
+ }
+
+ return E_UNINITIALIZED;
+}
+
int FLC_UnlockInfoBlock(uint32_t address)
{
int err;
@@ -612,9 +641,15 @@ int FLC_UnlockInfoBlock(uint32_t address)
if ((err = SYS_FLC_GetByAddress(&flc, address)) != E_NO_ERROR) {
return err;
}
+ if (FLC_InfoBlockUnlocked(address) == E_NO_ERROR) {
+ return E_NO_ERROR;
+ }
flc->acntl = 0x3a7f5ca3;
flc->acntl = 0xa1e34f20;
flc->acntl = 0x9608b2c1;
+
+ SYS_Flash_Operation();
+
return E_NO_ERROR;
}
@@ -630,6 +665,9 @@ int FLC_LockInfoBlock(uint32_t address)
return err;
}
flc->acntl = 0xDEADBEEF;
+
+ SYS_Flash_Operation();
+
return E_NO_ERROR;
}
/**@} end of group flc */
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/htmr.c b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/htmr.c
index 4d55f00b2f6d3f70ada3cd19cbcfa10cbb22f71f..25a8543fdfbf07da2ee0fa199b3caa28ff9a4f7c 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/htmr.c
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/htmr.c
@@ -250,6 +250,8 @@ int HTMR_CheckBusy(mxc_htmr_regs_t *htmr)
return E_BUSY;
}
}
+ mxc_delay_stop();
+
return E_SUCCESS;
}
@@ -294,4 +296,4 @@ int HTMR_GetLongCount(mxc_htmr_regs_t *htmr)
}
return htmr->sec;
-}
\ No newline at end of file
+}
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/lp.c b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/lp.c
index 43dc7c6c742d2d2fa81ac8fb56e9e5298a42e288..68363a74bd12a9e73acec64386ed81075e5c285a 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/lp.c
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/lp.c
@@ -20,8 +20,6 @@ void LP_ClearWakeStatus(void)
/* Write 1 to clear */
MXC_PWRSEQ->lpwkst0 = 0xFFFFFFFF;
MXC_PWRSEQ->lpwkst1 = 0xFFFFFFFF;
- MXC_PWRSEQ->lpwkst2 = 0xFFFFFFFF;
- MXC_PWRSEQ->lpwkst3 = 0xFFFFFFFF;
MXC_PWRSEQ->lppwst = 0xFFFFFFFF;
}
@@ -230,12 +228,12 @@ void LP_ICache1Wakeup(void)
void LP_SysCacheShutdown(void)
{
- MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SCACHESD;
+ MXC_PWRSEQ->lpmemsd |= MXC_F_PWRSEQ_LPMEMSD_SRCCSD;
}
void LP_SysCacheWakeup(void)
{
- MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SCACHESD;
+ MXC_PWRSEQ->lpmemsd &= ~MXC_F_PWRSEQ_LPMEMSD_SRCCSD;
}
void LP_USBSWLPDisable(void)
@@ -362,11 +360,11 @@ void LP_EnterBackupMode(void* func(void))
{
LP_ClearWakeStatus();
- MXC_PWRSEQ->gp0 = (uint32_t)(&Backup_Handler) | 1;
+ MXC_PWRSEQ->buretvec = (uint32_t)(&Backup_Handler) | 1;
if(func == NULL) {
- MXC_PWRSEQ->gp1 = (uint32_t)(&Reset_Handler) | 1;
+ MXC_PWRSEQ->buaod = (uint32_t)(&Reset_Handler) | 1;
} else {
- MXC_PWRSEQ->gp1 = (uint32_t)(&func) | 1;
+ MXC_PWRSEQ->buaod = (uint32_t)(&func) | 1;
}
// Enable the VDDCSW to ensure we have enough power to start
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/mxc_sys.c b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/mxc_sys.c
index 98fd1b95deff1bf8c74df40c3f99b94dc437b523..e4c5c7d9de6e01182e62b231d99e710d719fdd0c 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/mxc_sys.c
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/mxc_sys.c
@@ -42,6 +42,7 @@
/* **** Includes **** */
#include <stddef.h>
+#include <string.h>
#include "mxc_config.h"
#include "mxc_assert.h"
#include "mxc_sys.h"
@@ -263,6 +264,7 @@ static int SYS_Clock_Timeout(uint32_t ready)
mxc_delay_start(SYS_CLOCK_TIMEOUT);
do {
if (MXC_GCR->clkcn & ready) {
+ mxc_delay_stop();
return E_NO_ERROR;
}
} while (mxc_delay_check() == E_BUSY);
@@ -543,6 +545,11 @@ unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr)
}
/* ************************************************************************** */
+#ifdef __IAR_SYSTEMS_ICC__
+ #pragma section=".flashprog"
+#else
+ __attribute__((section(".flashprog")))
+#endif
void SYS_Flash_Operation(void)
{
/* Flush all instruction caches */
@@ -807,7 +814,7 @@ int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi)
void SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg)
{
GPIO_Config(&gpio_cfg_rtcsqw);
- //mxc_delay(1000);
+ mxc_delay(1000);
MXC_MCR->outen |= MXC_F_MCR_OUTEN_SQWOUT0EN;
}
@@ -933,11 +940,22 @@ int SYS_ADC_Shutdown(void)
}
/* ************************************************************************** */
+#ifdef __IAR_SYSTEMS_ICC__
+ #pragma section=".flashprog"
+#else
+ __attribute__((section(".flashprog")))
+#endif
int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg)
{
return E_NO_ERROR;
}
+/* ************************************************************************** */
+#ifdef __IAR_SYSTEMS_ICC__
+ #pragma section=".flashprog"
+#else
+ __attribute__((section(".flashprog")))
+#endif
int SYS_FLC_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
{
@@ -957,6 +975,13 @@ int SYS_FLC_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr)
}
return E_NO_ERROR;
}
+
+/* ************************************************************************** */
+#ifdef __IAR_SYSTEMS_ICC__
+ #pragma section=".flashprog"
+#else
+ __attribute__((section(".flashprog")))
+#endif
int SYS_FLC_GetPhysicalAddress(uint32_t addr, uint32_t *result)
{
if (addr < MXC_FLASH1_MEM_BASE && addr >= MXC_FLASH0_MEM_BASE) {
@@ -977,6 +1002,12 @@ int SYS_FLC_GetPhysicalAddress(uint32_t addr, uint32_t *result)
return E_NO_ERROR;
}
+/* ************************************************************************** */
+#ifdef __IAR_SYSTEMS_ICC__
+ #pragma section=".flashprog"
+#else
+ __attribute__((section(".flashprog")))
+#endif
/* ************************************************************************** */
int SYS_FLC_Shutdown(void)
{
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/rtc.c b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/rtc.c
index 49bc6b0cdbef12f036cd7ab383125ec856ff470c..8abc77f59a1ed7dbbd55ef555504836f19f70cd3 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/rtc.c
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/rtc.c
@@ -117,7 +117,7 @@ int RTC_SetTimeofdayAlarm(mxc_rtc_regs_t *rtc, uint32_t ras)
return E_BUSY;
}
- rtc->ras = (ras << MXC_F_RTC_RAS_RAS_POS) & MXC_F_RTC_RAS_RAS;
+ rtc->toda = (ras << MXC_F_RTC_TODA_TOD_ALARM_POS) & MXC_F_RTC_TODA_TOD_ALARM;
if(RTC_EnableTimeofdayInterrupt(rtc) == E_BUSY) {
return E_BUSY;
@@ -139,7 +139,7 @@ int RTC_SetSubsecondAlarm(mxc_rtc_regs_t *rtc, uint32_t rssa)
return E_BUSY;
}
- rtc->rssa = (rssa << MXC_F_RTC_RSSA_RSSA_POS) & MXC_F_RTC_RSSA_RSSA;
+ rtc->sseca = (rssa << MXC_F_RTC_SSECA_SSEC_ALARM_POS) & MXC_F_RTC_SSECA_SSEC_ALARM;
if(RTC_EnableSubsecondInterrupt(rtc) == E_BUSY) {
return E_BUSY;
@@ -236,7 +236,7 @@ int RTC_Init(mxc_rtc_regs_t *rtc, uint32_t sec, uint16_t ssec, sys_cfg_rtc_t *sy
// *****************************************************************************
int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
- rtc_osc_mode_t x32kmd, const sys_cfg_rtc_t* sys_cfg)
+ const sys_cfg_rtc_t* sys_cfg)
{
SYS_RTC_SqwavInit(sys_cfg); // Set the Output pins for the squarewave.
@@ -264,11 +264,11 @@ int RTC_SquareWave(mxc_rtc_regs_t *rtc, rtc_sqwave_en_t sqe, rtc_freq_sel_t ft,
if (RTC_CheckBusy()) {
return E_BUSY;
}
- rtc->ctrl &= ~(MXC_F_RTC_CTRL_FT | MXC_F_RTC_CTRL_X32KMD);
+ rtc->ctrl &= ~MXC_F_RTC_CTRL_FT;
if (RTC_CheckBusy()) {
return E_BUSY;
}
- rtc->ctrl |= (MXC_F_RTC_CTRL_SQE | ft | x32kmd); // Enable Sq. wave,
+ rtc->ctrl |= (MXC_F_RTC_CTRL_SQE | ft); // Enable Sq. wave,
}
if (RTC_CheckBusy()) {
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/srcc.c b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/srcc.c
new file mode 100644
index 0000000000000000000000000000000000000000..097245c5a451c7c6cace090142ae674da6645211
--- /dev/null
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/srcc.c
@@ -0,0 +1,141 @@
+/* *****************************************************************************
+ *
+ * Copyright (C) 2017 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ * $Date: 2018-08-28 17:03:02 -0500 (Tue, 28 Aug 2018) $
+ * $Revision: 37424 $
+ *
+ **************************************************************************** */
+
+/* **** Includes **** */
+#include "srcc.h"
+
+/* ************************************************************************** */
+uint32_t SRCC_ID(srcc_cache_id_t id)
+{
+ switch (id) {
+ case SRCC_CACHE_ID_RELNUM:
+ return (((MXC_SRCC->cache_id) & MXC_F_SRCC_CACHE_ID_RELNUM)) >> MXC_F_SRCC_CACHE_ID_RELNUM_POS;
+
+ case SRCC_CACHE_ID_PARTNUM:
+ return (((MXC_SRCC->cache_id) & MXC_F_SRCC_CACHE_ID_PARTNUM)) >> MXC_F_SRCC_CACHE_ID_PARTNUM_POS;
+
+ case SRCC_CACHE_ID_CCHID:
+ default:
+ return (((MXC_SRCC->cache_id) & MXC_F_SRCC_CACHE_ID_CCHID)) >> MXC_F_SRCC_CACHE_ID_CCHID_POS;
+ }
+}
+
+/* ************************************************************************** */
+uint32_t SRCC_Cache_Size(void)
+{
+ return (MXC_SRCC->memcfg & MXC_F_SRCC_MEMCFG_CCHSZ) >> MXC_F_SRCC_MEMCFG_CCHSZ_POS;
+}
+
+/* ************************************************************************** */
+uint32_t SRCC_Mem_Size(void)
+{
+ return (MXC_SRCC->memcfg & MXC_F_SRCC_MEMCFG_MEMSZ) >> MXC_F_SRCC_MEMCFG_MEMSZ_POS;
+}
+
+/* ************************************************************************** */
+void SRCC_Enable(void)
+{
+ MXC_SRCC->cache_ctrl |= MXC_F_SRCC_CACHE_CTRL_CACHE_EN;
+}
+
+/* ************************************************************************** */
+void SRCC_Disable(void)
+{
+ MXC_SRCC->cache_ctrl &= ~MXC_F_SRCC_CACHE_CTRL_CACHE_EN;
+}
+
+/* ************************************************************************** */
+void SRCC_Flush(void)
+{
+ SRCC_Disable();
+ SRCC_Enable();
+}
+
+/* ************************************************************************** */
+void SRCC_Write_Alloc_Enable(void)
+{
+ /* When a cache line is allocated on write operations, this is called
+ "write-allocate". However, there can be performance problems with
+ "write-allocate" because software frequently operates memset() on large
+ portions of memory. This can "pollute" the cache with unwanted cache lines.
+ To avoid this issue, the write-allocate feature is disable by default. The
+ write- allocate enable bit is in CACHE_CTRL[1]. */
+ MXC_SRCC->cache_ctrl |= MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN;
+}
+
+/* ************************************************************************** */
+void SRCC_Write_Alloc_Disable(void)
+{
+ MXC_SRCC->cache_ctrl &= ~MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_EN;
+}
+
+/* ************************************************************************** */
+void SRCC_Critical_Word_First_Enable(void)
+{
+ MXC_SRCC->cache_ctrl &= ~MXC_F_SRCC_CACHE_CTRL_CWFST_DIS;
+}
+
+/* ************************************************************************** */
+void SRCC_Critical_Word_First_Disable(void)
+{
+ MXC_SRCC->cache_ctrl |= MXC_F_SRCC_CACHE_CTRL_CWFST_DIS;
+}
+
+/* ************************************************************************** */
+uint32_t SRCC_Ready(void)
+{
+ /* Cache Ready flag. Cleared by hardware when at any time the cache as a
+ whole is invalidated ( including a system reset). When this bit is 0, the
+ cache is effectively in bypass mode (data fetches will come from main memory
+ or from the line fill buffer). Set by hardware when the invalidate operation
+ is complete and the cache is ready. */
+ return MXC_SRCC->cache_ctrl & MXC_F_SRCC_CACHE_CTRL_CACHE_RDY;
+}
+
+/* ************************************************************************** */
+void SRCC_Invalidate_All(void)
+{
+ /* Invalidate All Cache Contents. Any time this register location is written
+ (regardless of the data value), the cache controller immediately begins
+ invalidating the entire contents of the cache memory. The cache will be in
+ bypass mode until the invalidate operation is complete. System software can
+ examine the Cache Ready bit (CACHE_CTRL.CACHE_RDY) to determine when the
+ invalidate operation is complete. Note that it is not necessary to disable
+ the cache controller prior to beginning this operation. Reads from this
+ register always return 0. */
+ MXC_SRCC->invalidate |= MXC_F_SRCC_INVALIDATE_IA;
+}
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/startup_core1.S b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/startup_core1.S
index 4994235bd3545a98d42c4cb9023fbc0a4e472633..a863c9ec86c5e9fdda1981ccfc9490d1a70d225f 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/Source/startup_core1.S
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/Source/startup_core1.S
@@ -29,7 +29,7 @@ __isr_vector_core1:
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
- .long 0 /* Reserved */ /* @TODO: Is this the Debug Montior Interrupt? */
+ .long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
@@ -120,7 +120,7 @@ __isr_vector_core1:
.long ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */
.long DVS_IRQHandler /* 0x63 0x018C 99: DVS Controller */
.long SIMO_IRQHandler /* 0x64 0x0190 100: SIMO Controller */
- .long RPU_IRQHandler /* 0x65 0x0194 101: RPU */ /* @TODO: Is this correct? */
+ .long SCA_IRQHandler /* 0x65 0x0194 101: SCA */
.long AUDIO_IRQHandler /* 0x66 0x0198 102: Audio subsystem */
.long FLC1_IRQHandler /* 0x67 0x019C 103: Flash Control 1 */
.long RSV88_IRQHandler /* 0x68 0x01A0 104: UART 3 */
@@ -153,4 +153,4 @@ Reset_Handler_Core1:
.SPINC1:
/* spin if main ever returns. */
- bl .SPINC1
\ No newline at end of file
+ bl .SPINC1
diff --git a/lib/sdk/Libraries/MAX32665PeriphDriver/meson.build b/lib/sdk/Libraries/MAX32665PeriphDriver/meson.build
index 6dd4f7284803af04105ff22dc0d1ddea75dfbc80..2195ef7c7dd92f59d08dfaf66294def3dec2f525 100644
--- a/lib/sdk/Libraries/MAX32665PeriphDriver/meson.build
+++ b/lib/sdk/Libraries/MAX32665PeriphDriver/meson.build
@@ -10,7 +10,6 @@ sources = files(
'Source/crc.c',
'Source/dma.c',
'Source/dvs.c',
- 'Source/emcc.c',
'Source/flc.c',
'Source/gpio.c',
'Source/hash.c',
@@ -38,6 +37,7 @@ sources = files(
'Source/spixf.c',
'Source/spixfc.c',
'Source/spixr.c',
+ 'Source/srcc.c',
'Source/startup_core1.S',
'Source/system_core1.c',
'Source/tmr.c',
diff --git a/lib/sdk/Libraries/MAXUSB/Makefile b/lib/sdk/Libraries/MAXUSB/Makefile
index 0e8e68c226f61f56d4130091633b8ab992a70c54..8b59766730a02b08701a1451b4b0af20b6317b00 100644
--- a/lib/sdk/Libraries/MAXUSB/Makefile
+++ b/lib/sdk/Libraries/MAXUSB/Makefile
@@ -84,12 +84,6 @@ endif
ifeq "$(TARGET_UC)" "MAX32656"
TARGET_USB=MUSBHSFC
endif
-ifeq "$(TARGET_UC)" "MAX32570"
-TARGET_USB=MUSBHSFC
-endif
-ifeq "$(TARGET_UC)" "MAX32572"
-TARGET_USB=MUSBHSFC
-endif
# Source files for this test (add path to VPATH below)
SRCS = usb.c
diff --git a/lib/sdk/Libraries/MAXUSB/maxusb.mk b/lib/sdk/Libraries/MAXUSB/maxusb.mk
index 4c273fcabb893f90712bbd5a14d0d293a9bed3bf..31f2b63333a4aba1824d2c4900fcdec368dbeadc 100644
--- a/lib/sdk/Libraries/MAXUSB/maxusb.mk
+++ b/lib/sdk/Libraries/MAXUSB/maxusb.mk
@@ -85,12 +85,6 @@ endif
ifeq "$(TARGET_UC)" "MAX32656"
TARGET_USB=MUSBHSFC
endif
-ifeq "$(TARGET_UC)" "MAX32570"
-TARGET_USB=MUSBHSFC
-endif
-ifeq "$(TARGET_UC)" "MAX32572"
-TARGET_USB=MUSBHSFC
-endif
# Add to include directory list
ifeq "$(TARGET_USB)" "MUSBHSFC"
diff --git a/lib/sdk/Libraries/MAXUSB/src/core/musbhsfc/usb.c b/lib/sdk/Libraries/MAXUSB/src/core/musbhsfc/usb.c
index e510096d3527f533cec9cd4198fea5bc05ffde6c..232e1f01b37f333230c06b64e542e73fdec1265e 100644
--- a/lib/sdk/Libraries/MAXUSB/src/core/musbhsfc/usb.c
+++ b/lib/sdk/Libraries/MAXUSB/src/core/musbhsfc/usb.c
@@ -738,7 +738,7 @@ void usb_irq_handler(maxusb_usbio_events_t *evt)
evt->sudav = 1;
/* Remove this from the IN flags so that it is not erroneously processed as data */
in_flags &= ~MXC_F_USBHS_INTRIN_EP0_IN_INT;
- } else {
+ } else {
/* Otherwise, we are in endpoint 0 data IN/OUT */
/* Fix interrupt flags so that OUTs are processed properly */
if (setup_phase == SETUP_DATA_OUT) {
@@ -983,7 +983,7 @@ int usb_write_endpoint(usb_req_t *req)
/* clear errors */
req->error_code = 0;
- /* Placeholder for DMA code */
+ /* Determine if DMA can be used for this transmit */
armed = 0;
if (!armed) {
@@ -1060,13 +1060,13 @@ int usb_read_endpoint(usb_req_t *req)
/* Select endpoint */
MXC_USBHS->index = ep;
- /* Since the OUT interrupt for EP 0 doesn't really exist, only do this for others */
+ /* Since the OUT interrupt for EP 0 doesn't really exist, only do this logic for other endpoints */
if (ep) {
- /* Placeholder for DMA code */
+
armed = 0;
if (!armed) {
- /* No free DMA channel found, fall back to PIO */
+ /* EP0 or no free DMA channel found, fall back to PIO */
/* See if data already in FIFO for this EP */
if (MXC_USBHS->outcsrl & MXC_F_USBHS_OUTCSRL_OUTPKTRDY) {
@@ -1084,7 +1084,7 @@ int usb_read_endpoint(usb_req_t *req)
if ((req->type == MAXUSB_TYPE_PKT) || (req->actlen == req->reqlen)) {
- /* Done with request, callback fires if configured */
+ /* Done */
MAXUSB_EXIT_CRITICAL();
usb_request[ep] = NULL;
@@ -1092,14 +1092,21 @@ int usb_read_endpoint(usb_req_t *req)
if (req->callback) {
req->callback(req->cbdata);
}
- return 0;
+ return 0;
+
} else {
/* Not done, more data requested */
MXC_USBHS->introuten |= (1 << ep);
+
+ MAXUSB_EXIT_CRITICAL();
+ return 0;
}
} else {
/* No data, will need an interrupt to service later */
MXC_USBHS->introuten |= (1 << ep);
+
+ MAXUSB_EXIT_CRITICAL();
+ return 0;
}
}
}
diff --git a/lib/sdk/Libraries/MAXUSB/src/devclass/cdc_acm.c b/lib/sdk/Libraries/MAXUSB/src/devclass/cdc_acm.c
index ef1769cb48f7a7cd9f694649a685de30b9191f3a..c85ca2b84faa50015cd4ab1019f4d42321074cf1 100644
--- a/lib/sdk/Libraries/MAXUSB/src/devclass/cdc_acm.c
+++ b/lib/sdk/Libraries/MAXUSB/src/devclass/cdc_acm.c
@@ -400,7 +400,7 @@ static void out_callback(void *cbdata)
/******************************************************************************/
static void svc_in_to_host(void *cbdata)
{
- unsigned i;
+ int i;
uint8_t byte;
/* An error will occur when the host has been disconnected.
diff --git a/lib/sdk/Libraries/MAXUSB/src/devclass/hid_kbd.c b/lib/sdk/Libraries/MAXUSB/src/devclass/hid_kbd.c
index ea42305247b97fd5b62acdce82cea952ad6d71ec..1b0af14e0c3643a82c3ca711cf8f775e22eca0d7 100644
--- a/lib/sdk/Libraries/MAXUSB/src/devclass/hid_kbd.c
+++ b/lib/sdk/Libraries/MAXUSB/src/devclass/hid_kbd.c
@@ -71,7 +71,7 @@ static const uint8_t *report_desc;
static int (*chained_func)(usb_setup_pkt *, void *);
static void *chained_cbdata;
-void (*chained_getdesc_func)(usb_setup_pkt *, const uint8_t **, uint16_t *);
+static void (*chained_getdesc_func)(usb_setup_pkt *, const uint8_t **, uint16_t *);
/***** Function Prototypes *****/
static void getdescriptor(usb_setup_pkt *sud, const uint8_t **desc, uint16_t *desclen);
diff --git a/lib/sdk/Libraries/MAXUSB/src/devclass/hid_raw.c b/lib/sdk/Libraries/MAXUSB/src/devclass/hid_raw.c
index f2ec0fa5d2ea8f403c6940bb7641e51bc8967bba..e0275fa1538811b1692d651e72bb01eb082f3448 100644
--- a/lib/sdk/Libraries/MAXUSB/src/devclass/hid_raw.c
+++ b/lib/sdk/Libraries/MAXUSB/src/devclass/hid_raw.c
@@ -81,9 +81,9 @@ static const uint8_t *report_desc;
static int (*callback)(void);
-int (*chained_func)(usb_setup_pkt *, void *);
-void *chained_cbdata;
-void (*chained_getdesc_func)(usb_setup_pkt *, const uint8_t **, uint16_t *);
+static int (*chained_func)(usb_setup_pkt *, void *);
+static void *chained_cbdata;
+static void (*chained_getdesc_func)(usb_setup_pkt *, const uint8_t **, uint16_t *);
/***** Function Prototypes *****/
static void getdescriptor(usb_setup_pkt *sud, const uint8_t **desc, uint16_t *desclen);
@@ -353,7 +353,7 @@ static void out_callback(void *cbdata)
/******************************************************************************/
static void svc_in_to_host(void *cbdata)
{
- unsigned i;
+ int i;
uint8_t byte;
/* An error will occur when the host has been disconnected. */
diff --git a/lib/sdk/Libraries/MAXUSB/src/devclass/msc.c b/lib/sdk/Libraries/MAXUSB/src/devclass/msc.c
index 897cbf33eb12e15abfe154e54fa3bf87a239b332..c6a37f754954dd4b1c293f3dafd128ab0311f228 100644
--- a/lib/sdk/Libraries/MAXUSB/src/devclass/msc.c
+++ b/lib/sdk/Libraries/MAXUSB/src/devclass/msc.c
@@ -118,8 +118,8 @@ static unsigned int ep_to_host;
static uint32_t numBlocks;
static uint32_t blockAddr;
-int (*chained_func)(usb_setup_pkt *, void *);
-void *chained_cbdata;
+static int (*chained_func)(usb_setup_pkt *, void *);
+static void *chained_cbdata;
/***** Function Prototypes *****/
static int msc_classReq(usb_setup_pkt *sud, void *cbdata);
diff --git a/lib/sdk/Libraries/MAXUSB/src/enumerate/enumerate.c b/lib/sdk/Libraries/MAXUSB/src/enumerate/enumerate.c
index 3fcbd48c39a1def8588e0feb875d4a02a540d27e..2ef979951f8a2f917f4245a72621b5a4cb19cb94 100644
--- a/lib/sdk/Libraries/MAXUSB/src/enumerate/enumerate.c
+++ b/lib/sdk/Libraries/MAXUSB/src/enumerate/enumerate.c
@@ -113,9 +113,7 @@ static const usb_req_t enum_req_init = {
0, /* actlen */
0, /* error_code */
status_stage_callback, /* callback */
- &enum_req, /* callback data */
- MAXUSB_TYPE_TRANS, /* type */
- NULL /* driver_xtra */
+ &enum_req /* callback data */
};
/******************************************************************************/
@@ -380,8 +378,7 @@ static int clearfeature(usb_setup_pkt *sud)
if ((sud->bmRequestType & RT_DEV_TO_HOST) ||
(sud->wLength != 0) ||
((sud->wValue == FEAT_ENDPOINT_HALT) && ((sud->bmRequestType & RT_RECIP_MASK) != RT_RECIP_ENDP)) ||
- ((sud->wValue == FEAT_REMOTE_WAKE) && ((sud->bmRequestType & RT_RECIP_MASK) != RT_RECIP_DEVICE)) ||
- ((sud->wValue == FEAT_TEST_MODE) && ((sud->bmRequestType & RT_RECIP_MASK) != RT_RECIP_DEVICE))) {
+ ((sud->wValue == FEAT_REMOTE_WAKE) && ((sud->bmRequestType & RT_RECIP_MASK) != RT_RECIP_DEVICE))) {
return -1;
}
@@ -402,19 +399,9 @@ static int clearfeature(usb_setup_pkt *sud)
} else {
return -1;
}
- } else if ((sud->wValue == FEAT_TEST_MODE)) {
- /* Clear the test mode feature */
- if (callback[ENUM_CLRFEATURE].fnaddr != NULL) {
- result = callback[ENUM_CLRFEATURE].fnaddr(sud, NULL);
- if (result < 0) {
- return result;
- }
- } else {
- return -1;
- }
} else {
/* Per USB 2.0: The Test_Mode feature cannot be cleared by the ClearFeature() request. */
- /* Unsupported */
+ /* Unsupported */
return -1;
}
diff --git a/lib/sdk/Libraries/SDHC/ff13/Source/diskio.c b/lib/sdk/Libraries/SDHC/ff13/Source/diskio.c
index ce97636e45855d04d429aec2253dfb1515eb523e..d04df7967b31ffb0f1da11d217160b5e0b6e37f6 100644
--- a/lib/sdk/Libraries/SDHC/ff13/Source/diskio.c
+++ b/lib/sdk/Libraries/SDHC/ff13/Source/diskio.c
@@ -24,6 +24,9 @@ static DRESULT mmc_get_csd(void *buff);
/* Globals */
unsigned int init_done = 0;
+/* Locals */
+static uint8_t rtc_en;
+
/*-----------------------------------------------------------------------*/
/* Get Drive Status */
/*-----------------------------------------------------------------------*/
diff --git a/lib/sdk/Libraries/SDHC/ff13/Source/diskio.h b/lib/sdk/Libraries/SDHC/ff13/Source/diskio.h
index 13b4024503158b21df0db51feb8752cfad516ef5..a6e4ad2192eec958664a35be1970df7078a8d501 100644
--- a/lib/sdk/Libraries/SDHC/ff13/Source/diskio.h
+++ b/lib/sdk/Libraries/SDHC/ff13/Source/diskio.h
@@ -21,9 +21,6 @@ extern "C" {
/* Status of Disk Functions */
typedef BYTE DSTATUS;
-/*local vaiables*/
-static uint8_t rtc_en;
-
/* Results of Disk Functions */
typedef enum {
RES_OK = 0, /* 0: Successful */