diff --git a/doc/openocd.texi b/doc/openocd.texi
index daa946098720b417d026d4ca3689ed857d3143ce..d41f422bcbb2f10b327d0dd4d722f8dd08c9668b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -66,7 +66,6 @@ Free Documentation License''.
* Running:: Running OpenOCD
* OpenOCD Project Setup:: OpenOCD Project Setup
* Config File Guidelines:: Config File Guidelines
-* Translating Configuration Files:: Translating Configuration Files
* Daemon Configuration:: Daemon Configuration
* Interface - Dongle Configuration:: Interface - Dongle Configuration
* Reset Configuration:: Reset Configuration
@@ -1186,7 +1185,9 @@ handlers too, if just for developer convenience.
Because this is so very board-specific, and chip-specific, no examples
are included here.
Instead, look at the board config files distributed with OpenOCD.
-If you have a boot loader, its source code may also be useful.
+If you have a boot loader, its source code will help; so will
+configuration files for other JTAG tools
+(@pxref{Translating Configuration Files}).
@end quotation
Some of this code could probably be shared between different boards.
@@ -1464,17 +1465,18 @@ Examples:
@item pxa270 - again - CS0 flash - it goes in the board file.
@end itemize
-@node Translating Configuration Files
-@chapter Translating Configuration Files
+@anchor{Translating Configuration Files}
+@section Translating Configuration Files
@cindex translation
-If you have a configuration file for another hardware debugger(Abatron,
-BDI2000, BDI3000, Lauterbach, Segger, MacRaigor, etc.), translating
+If you have a configuration file for another hardware debugger
+or toolset (Abatron, BDI2000, BDI3000, CCS,
+Lauterbach, Segger, Macraigor, etc.), translating
it into OpenOCD syntax is often quite straightforward. The most tricky
part of creating a configuration script is oftentimes the reset init
sequence where e.g. PLLs, DRAM and the like is set up.
One trick that you can use when translating is to write small
-Tcl proc's to translate the syntax into OpenOCD syntax. This
+Tcl procedures to translate the syntax into OpenOCD syntax. This
can avoid manual translation errors and make it easier to
convert other scripts later on.
@@ -1482,23 +1484,22 @@ Example of transforming quirky arguments to a simple search and
replace job:
@example
-# rewrite commands of the form below to arm11 mcr...
-#
# Lauterbach syntax(?)
#
-# Data.Set c15:0x042f %long 0x40000015
+# Data.Set c15:0x042f %long 0x40000015
#
# OpenOCD syntax when using procedure below.
#
-# setc15 0x01 0x00050078
-#
-#
+# setc15 0x01 0x00050078
+
proc setc15 @{regs value@} @{
- global TARGETNAME
+ global TARGETNAME
- echo [format "set p15 0x%04x, 0x%08x" $regs $value]
+ echo [format "set p15 0x%04x, 0x%08x" $regs $value]
- arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value
+ arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
+ [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
+ [expr ($regs>>8)&0x7] $value
@}
@end example
@@ -1563,6 +1564,17 @@ read/write memory on your target, @command{init} must occur before
the memory read/write commands. This includes @command{nand probe}.
@end deffn
+@deffn {Overridable Procedure} jtag_init
+This is invoked at server startup to verify that it can talk
+to the scan chain (list of TAPs) which has been configured.
+
+The default implementation first tries @command{jtag arp_init},
+which uses only a lightweight JTAG reset before examining the
+scan chain.
+If that fails, it tries again, using a harder reset
+from the overridable procedure @command{init_reset}.
+@end deffn
+
@anchor{TCP/IP Ports}
@section TCP/IP Ports
@cindex TCP port
@@ -2192,8 +2204,9 @@ issues (not limited to errata).
For example, certain JTAG commands might need to be issued while
the system as a whole is in a reset state (SRST active)
but the JTAG scan chain is usable (TRST inactive).
-(@xref{JTAG Commands}, where the @command{jtag_reset}
-command is presented.)
+Many systems treat combined assertion of SRST and TRST as a
+trigger for a harder reset than SRST alone.
+Such custom reset handling is discussed later in this chapter.
@end itemize
There can also be other issues.
@@ -2260,7 +2273,7 @@ Possible values are @option{none} (the default), @option{trst_only},
@quotation Tip
If your board provides SRST and/or TRST through the JTAG connector,
-you must declare that or else those signals will not be used.
+you must declare that so those signals can be used.
@end quotation
@item
@@ -2309,6 +2322,82 @@ powerup and pressing a reset button.
@end itemize
@end deffn
+@section Custom Reset Handling
+@cindex events
+
+OpenOCD has several ways to help support the various reset
+mechanisms provided by chip and board vendors.
+The commands shown in the previous section give standard parameters.
+There are also @emph{event handlers} associated with TAPs or Targets.
+Those handlers are Tcl procedures you can provide, which are invoked
+at particular points in the reset sequence.
+
+After configuring those mechanisms, you might still
+find your board doesn't start up or reset correctly.
+For example, maybe it needs a slightly different sequence
+of SRST and/or TRST manipulations, because of quirks that
+the @command{reset_config} mechanism doesn't address;
+or asserting both might trigger a stronger reset, which
+needs special attention.
+
+Experiment with lower level operations, such as @command{jtag_reset}
+and the @command{jtag arp_*} operations shown here,
+to find a sequence of operations that works.
+@xref{JTAG Commands}.
+When you find a working sequence, it can be used to override
+@command{jtag_init}, which fires during OpenOCD startup
+(@pxref{Configuration Stage});
+or @command{init_reset}, which fires during reset processing.
+
+You might also want to provide some project-specific reset
+schemes. For example, on a multi-target board the standard
+@command{reset} command would reset all targets, but you
+may need the ability to reset only one target at time and
+thus want to avoid using the board-wide SRST signal.
+
+@deffn {Overridable Procedure} init_reset mode
+This is invoked near the beginning of the @command{reset} command,
+usually to provide as much of a cold (power-up) reset as practical.
+By default it is also invoked from @command{jtag_init} if
+the scan chain does not respond to pure JTAG operations.
+The @var{mode} parameter is the parameter given to the
+low level reset command (@option{halt},
+@option{init}, or @option{run}), @option{setup},
+or potentially some other value.
+
+The default implementation just invokes @command{jtag arp_init-reset}.
+Replacements will normally build on low level JTAG
+operations such as @command{jtag_reset}.
+Operations here must not address individual TAPs
+(or their associated targets)
+until the JTAG scan chain has first been verified to work.
+
+Implementations must have verified the JTAG scan chain before
+they return.
+This is done by calling @command{jtag arp_init}
+(or @command{jtag arp_init-reset}).
+@end deffn
+
+@deffn Command {jtag arp_init}
+This validates the scan chain using just the four
+standard JTAG signals (TMS, TCK, TDI, TDO).
+It starts by issuing a JTAG-only reset.
+Then it performs checks to verify that the scan chain configuration
+matches the TAPs it can observe.
+Those checks include checking IDCODE values for each active TAP,
+and verifying the length of their instruction registers using
+TAP @code{-ircapture} and @code{-irmask} values.
+If these tests all pass, TAP @code{setup} events are
+issued to all TAPs with handlers for that event.
+@end deffn
+
+@deffn Command {jtag arp_init-reset}
+This uses TRST and SRST to try resetting
+everything on the JTAG scan chain
+(and anything else connected to SRST).
+It then invokes the logic of @command{jtag arp_init}.
+@end deffn
+
@node TAP Declaration
@chapter TAP Declaration
@@ -2540,9 +2629,6 @@ there seems to be no problems with JTAG scan chain operations.
@section Other TAP commands
-@c @deffn Command {jtag arp_init-reset}
-@c ... more or less "toggle TRST ... and SRST too, what the heck"
-
@deffn Command {jtag cget} dotted.name @option{-event} name
@deffnx Command {jtag configure} dotted.name @option{-event} name string
At this writing this TAP attribute
@@ -3218,7 +3304,7 @@ The following target events are defined:
@end ignore
@item @b{reset-assert-pre}
@* Issued as part of @command{reset} processing
-after SRST and/or TRST were activated and deactivated,
+after @command{reset_init} was triggered
but before SRST alone is re-asserted on the tap.
@item @b{reset-assert-post}
@* Issued as part of @command{reset} processing
@@ -3248,10 +3334,11 @@ multiplexing, and so on.
the target clocks are fully set up.)
@item @b{reset-start}
@* Issued as part of @command{reset} processing
-before either SRST or TRST are activated.
+before @command{reset_init} is called.
-This is the most robust place to switch to a low JTAG clock rate, if
-SRST disables PLLs needed to use a fast clock.
+This is the most robust place to use @command{jtag_rclk}
+or @command{jtag_khz} to switch to a low JTAG clock rate,
+when reset disables PLLs needed to use a fast clock.
@ignore
@item @b{reset-wait-pos}
@* Currently not used
@@ -5983,6 +6070,17 @@ The @command{reset_config} command should already have been used
to configure how the board and JTAG adapter treat these two
signals, and to say if either signal is even present.
@xref{Reset Configuration}.
+
+Note that TRST is specially handled.
+It actually signifies JTAG's @sc{reset} state.
+So if the board doesn't support the optional TRST signal,
+or it doesn't support it along with the specified SRST value,
+JTAG reset is triggered with TMS and TCK signals
+instead of the TRST signal.
+And no matter how that JTAG reset is triggered, once
+the scan chain enters @sc{reset} with TRST inactive,
+TAP @code{post-reset} events are delivered to all TAPs
+with handlers for that event.
@end deffn
@deffn Command {runtest} @var{num_cycles}
@@ -6015,7 +6113,7 @@ The @var{tap_state} names used by OpenOCD in the @command{drscan},
and @command{irscan} commands are:
@itemize @bullet
-@item @b{RESET} ... should act as if TRST were active
+@item @b{RESET} ... acts as if TRST were pulsed
@item @b{RUN/IDLE} ... don't assume this always means IDLE
@item @b{DRSELECT}
@item @b{DRCAPTURE}
@@ -6046,7 +6144,7 @@ may not be as expected.
@item @sc{run/idle}, @sc{drpause}, and @sc{irpause} are reasonable
choices after @command{drscan} or @command{irscan} commands,
since they are free of JTAG side effects.
-However, @sc{run/idle} may have side effects that appear at other
+@item @sc{run/idle} may have side effects that appear at non-JTAG
levels, such as advancing the ARM9E-S instruction pipeline.
Consult the documentation for the TAP(s) you are working with.
@end itemize
diff --git a/src/flash/flash.c b/src/flash/flash.c
index 4c123f8fc88f80222364869c828177f9ce6b8db1..d1b023c55b28e11dd369599f553e133510b6842d 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -569,8 +569,8 @@ static int flash_check_sector_parameters(struct command_context_s *cmd_ctx,
}
if (!(last <= (num_sectors - 1))) {
- command_print(cmd_ctx, "ERROR: "
- "last sector must be <= %d", num_sectors - 1);
+ command_print(cmd_ctx, "ERROR: last sector must be <= %d",
+ (int) num_sectors - 1);
return ERROR_FAIL;
}
@@ -616,7 +616,8 @@ static int handle_flash_erase_command(struct command_context_s *cmd_ctx,
return retval;
command_print(cmd_ctx, "erased sectors %i through %i "
"on flash bank %i in %s",
- first, last, bank_nr, duration_text);
+ (int) first, (int) last, (int) bank_nr,
+ duration_text);
free(duration_text);
}
}
@@ -667,8 +668,8 @@ static int handle_flash_protect_command(struct command_context_s *cmd_ctx,
if (retval == ERROR_OK) {
command_print(cmd_ctx, "%s protection for sectors %i "
"through %i on flash bank %i",
- (set) ? "set" : "cleared", first,
- last, bank_nr);
+ (set) ? "set" : "cleared", (int) first,
+ (int) last, (int) bank_nr);
}
}
else
diff --git a/src/flash/lpc2900.c b/src/flash/lpc2900.c
index 26ca67f5fa70ec5175032c394940d8c737293de1..e39c53195d9f588f7ce3591099939050de71094f 100644
--- a/src/flash/lpc2900.c
+++ b/src/flash/lpc2900.c
@@ -444,9 +444,9 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
uint8_t (*page)[FLASH_PAGE_SIZE] )
{
/* Only pages 4...7 are user writable */
- if( (pagenum < 4) || (pagenum > 7) )
+ if ((pagenum < 4) || (pagenum > 7))
{
- LOG_ERROR( "Refuse to burn index sector page %" PRIu32, pagenum );
+ LOG_ERROR("Refuse to burn index sector page %d", pagenum);
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@@ -479,7 +479,7 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
bank->base + pagenum * FLASH_PAGE_SIZE,
4, FLASH_PAGE_SIZE / 4, (uint8_t *)page) != ERROR_OK )
{
- LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
+ LOG_ERROR("Index sector write failed @ page %d", pagenum);
target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
return ERROR_FLASH_OPERATION_FAILED;
@@ -501,10 +501,10 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
/* Wait for the end of the write operation. If it's not over after one
* second, something went dreadfully wrong... :-(
*/
- if( lpc2900_wait_status( bank, INTSRC_END_OF_BURN, 1000 ) != ERROR_OK )
+ if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
{
- LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
- target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
+ LOG_ERROR("Index sector write failed @ page %d", pagenum);
+ target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -796,7 +796,8 @@ static int lpc2900_handle_write_custom_command( struct command_context_s *cmd_ct
if( (image.sections[0].base_address != 0) ||
(image.sections[0].size != ISS_CUSTOMER_SIZE) )
{
- LOG_ERROR("Incorrect image file size. Expected %" PRIu32 ", got %" PRIu32,
+ LOG_ERROR("Incorrect image file size. Expected %d, "
+ "got %" PRIu32,
ISS_CUSTOMER_SIZE, image.sections[0].size);
return ERROR_COMMAND_SYNTAX_ERROR;
}
@@ -1477,12 +1478,13 @@ static int lpc2900_write(struct flash_bank_s *bank, uint8_t *buffer,
}
/* Skip the current sector if it is secured */
- if( bank->sectors[start_sector].is_protected )
+ if (bank->sectors[start_sector].is_protected)
{
- LOG_DEBUG( "Skip secured sector %" PRIu32, start_sector );
+ LOG_DEBUG("Skip secured sector %d",
+ start_sector);
/* Stop if this is the last sector */
- if( start_sector == bank->num_sectors - 1 )
+ if (start_sector == bank->num_sectors - 1)
{
break;
}
@@ -1763,9 +1765,9 @@ static int lpc2900_probe(struct flash_bank_s *bank)
}
/* Show detected device */
- LOG_INFO("Flash bank %" PRIu32
+ LOG_INFO("Flash bank %d"
": Device %s, %" PRIu32
- " KiB in %" PRIu32 " sectors",
+ " KiB in %d sectors",
bank->bank_number,
lpc2900_info->target_name, bank->size / KiB,
bank->num_sectors);
@@ -1805,7 +1807,7 @@ static int lpc2900_probe(struct flash_bank_s *bank)
* that has more than 19 sectors. Politely ask for a fix then.
*/
bank->sectors[i].size = 0;
- LOG_ERROR("Never heard about sector %" PRIu32 " (FIXME please)", i);
+ LOG_ERROR("Never heard about sector %d", i);
}
offset += bank->sectors[i].size;
diff --git a/src/flash/mx3_nand.c b/src/flash/mx3_nand.c
index 20ab91e8110225f862ed1a468d63cfb1932a6913..a5df00338be9f0f3821424bb0cbb7fbf1099d226 100644
--- a/src/flash/mx3_nand.c
+++ b/src/flash/mx3_nand.c
@@ -40,9 +40,9 @@ get_next_halfword_from_sram_buffer() not tested
static const char target_not_halted_err_msg[] =
"target must be halted to use mx3 NAND flash controller";
static const char data_block_size_err_msg[] =
- "minimal granularity is one half-word, %d is incorrect";
+ "minimal granularity is one half-word, %" PRId32 " is incorrect";
static const char sram_buffer_bounds_err_msg[] =
- "trying to access out of SRAM buffer bound (addr=0x%x)";
+ "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
static const char get_status_register_err_msg[] = "can't get NAND status";
static uint32_t in_sram_address;
unsigned char sign_of_sequental_byte_read;
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 1c9d13c94801ef344c5bc6604ab90c9f1a7fac05..564b93f84940d546f35fd00135693467c3978f11 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1167,7 +1167,7 @@ static int jtag_validate_ircapture(void)
(tap->ir_length + 7) / tap->ir_length,
val,
(tap->ir_length + 7) / tap->ir_length,
- tap->ir_capture_value);
+ (unsigned) tap->ir_capture_value);
retval = ERROR_JTAG_INIT_FAILED;
goto done;
@@ -1360,22 +1360,31 @@ int jtag_init_reset(struct command_context_s *cmd_ctx)
if ((retval = jtag_interface_init(cmd_ctx)) != ERROR_OK)
return retval;
- LOG_DEBUG("Trying to bring the JTAG controller to life by asserting TRST / TLR");
+ LOG_DEBUG("Initializing with hard TRST+SRST reset");
- /* Reset can happen after a power cycle.
- *
- * Ideally we would only assert TRST or run TLR before the target reset.
+ /*
+ * This procedure is used by default when OpenOCD triggers a reset.
+ * It's now done through an overridable Tcl "init_reset" wrapper.
*
- * However w/srst_pulls_trst, trst is asserted together with the target
- * reset whether we want it or not.
+ * This started out as a more powerful "get JTAG working" reset than
+ * jtag_init_inner(), applying TRST because some chips won't activate
+ * JTAG without a TRST cycle (presumed to be async, though some of
+ * those chips synchronize JTAG activation using TCK).
*
- * NB! Some targets have JTAG circuitry disabled until a
- * trst & srst has been asserted.
+ * But some chips only activate JTAG as part of an SRST cycle; SRST
+ * got mixed in. So it became a hard reset routine, which got used
+ * in more places, and which coped with JTAG reset being forced as
+ * part of SRST (srst_pulls_trst).
*
- * NB! here we assume nsrst/ntrst delay are sufficient!
+ * And even more corner cases started to surface: TRST and/or SRST
+ * assertion timings matter; some chips need other JTAG operations;
+ * TRST/SRST sequences can need to be different from these, etc.
*
- * NB! order matters!!!! srst *can* disconnect JTAG circuitry
+ * Systems should override that wrapper to support system-specific
+ * requirements that this not-fully-generic code doesn't handle.
*
+ * REVISIT once Tcl code can read the reset_config modes, this won't
+ * need to be a C routine at all...
*/
jtag_add_reset(1, 0); /* TAP_RESET, using TMS+TCK or TRST */
if (jtag_reset_config & RESET_HAS_SRST)
diff --git a/src/target/arm11.c b/src/target/arm11.c
index dc465973bb9acd8539a27cf1bf54b105d45a09ef..588ea3c27598a0f2ce8541ba087b0fbc4d6e3403 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1480,8 +1480,10 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
if (address + size * count != r0)
{
- LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
- address + size * count, r0);
+ LOG_ERROR("Data transfer failed. Expected end "
+ "address 0x%08x, got 0x%08x",
+ (unsigned) (address + size * count),
+ (unsigned) r0);
if (arm11_config_memwrite_burst)
LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
diff --git a/src/target/etm.c b/src/target/etm.c
index 5a774f4d24c364beef75b9acbfcd94431afdbef1..34e2ca8a3c42c93563e13a6224ea71877f0c0a7a 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1497,29 +1497,29 @@ static int handle_etm_info_command(struct command_context_s *cmd_ctx,
command_print(cmd_ctx, "ETM v%d.%d",
etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
command_print(cmd_ctx, "pairs of address comparators: %i",
- (etm->config >> 0) & 0x0f);
+ (int) (etm->config >> 0) & 0x0f);
command_print(cmd_ctx, "data comparators: %i",
- (etm->config >> 4) & 0x0f);
+ (int) (etm->config >> 4) & 0x0f);
command_print(cmd_ctx, "memory map decoders: %i",
- (etm->config >> 8) & 0x1f);
+ (int) (etm->config >> 8) & 0x1f);
command_print(cmd_ctx, "number of counters: %i",
- (etm->config >> 13) & 0x07);
+ (int) (etm->config >> 13) & 0x07);
command_print(cmd_ctx, "sequencer %spresent",
- (etm->config & (1 << 16)) ? "" : "not ");
+ (int) (etm->config & (1 << 16)) ? "" : "not ");
command_print(cmd_ctx, "number of ext. inputs: %i",
- (etm->config >> 17) & 0x07);
+ (int) (etm->config >> 17) & 0x07);
command_print(cmd_ctx, "number of ext. outputs: %i",
- (etm->config >> 20) & 0x07);
+ (int) (etm->config >> 20) & 0x07);
command_print(cmd_ctx, "FIFO full %spresent",
- (etm->config & (1 << 23)) ? "" : "not ");
+ (int) (etm->config & (1 << 23)) ? "" : "not ");
if (etm->bcd_vers < 0x20)
command_print(cmd_ctx, "protocol version: %i",
- (etm->config >> 28) & 0x07);
+ (int) (etm->config >> 28) & 0x07);
else {
command_print(cmd_ctx, "trace start/stop %spresent",
(etm->config & (1 << 26)) ? "" : "not ");
command_print(cmd_ctx, "number of context comparators: %i",
- (etm->config >> 24) & 0x03);
+ (int) (etm->config >> 24) & 0x03);
}
/* SYS_CONFIG isn't present before ETMv1.2 */
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 40126c92837cf746382be1ac4551eef5c1e21956..f245a206aefbbad450d8540df24cdbdb3064c360 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -35,90 +35,41 @@
#include "time_support.h"
#include "image.h"
-/* cli handling */
-int xscale_register_commands(struct command_context_s *cmd_ctx);
-/* forward declarations */
-int xscale_target_create(struct target_s *target, Jim_Interp *interp);
-int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int xscale_quit(void);
-
-int xscale_arch_state(struct target_s *target);
-int xscale_poll(target_t *target);
-int xscale_halt(target_t *target);
-int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
-int xscale_debug_entry(target_t *target);
-int xscale_restore_context(target_t *target);
-
-int xscale_assert_reset(target_t *target);
-int xscale_deassert_reset(target_t *target);
-int xscale_soft_reset_halt(struct target_s *target);
-
-int xscale_set_reg_u32(reg_t *reg, uint32_t value);
-
-int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
-int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
-
-int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
-
-int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-void xscale_enable_watchpoints(struct target_s *target);
-void xscale_enable_breakpoints(struct target_s *target);
-static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
-static int xscale_mmu(struct target_s *target, int *enabled);
-
-int xscale_read_trace(target_t *target);
-
-target_type_t xscale_target =
-{
- .name = "xscale",
-
- .poll = xscale_poll,
- .arch_state = xscale_arch_state,
-
- .target_request_data = NULL,
-
- .halt = xscale_halt,
- .resume = xscale_resume,
- .step = xscale_step,
-
- .assert_reset = xscale_assert_reset,
- .deassert_reset = xscale_deassert_reset,
- .soft_reset_halt = xscale_soft_reset_halt,
-
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
- .read_memory = xscale_read_memory,
- .write_memory = xscale_write_memory,
- .bulk_write_memory = xscale_bulk_write_memory,
- .checksum_memory = arm7_9_checksum_memory,
- .blank_check_memory = arm7_9_blank_check_memory,
-
- .run_algorithm = armv4_5_run_algorithm,
+/*
+ * Important XScale documents available as of October 2009 include:
+ *
+ * Intel XScale® Core Developer’s Manual, January 2004
+ * Order Number: 273473-002
+ * This has a chapter detailing debug facilities, and punts some
+ * details to chip-specific microarchitecture documentats.
+ *
+ * Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
+ * Document Number: 273539-005
+ * Less detailed than the developer's manual, but summarizes those
+ * missing details (for most XScales) and gives LOTS of notes about
+ * debugger/handler interaction issues. Presents a simpler reset
+ * and load-handler sequence than the arch doc. (Note, OpenOCD
+ * doesn't currently support "Hot-Debug" as defined there.)
+ *
+ * Chip-specific microarchitecture documents may also be useful.
+ */
- .add_breakpoint = xscale_add_breakpoint,
- .remove_breakpoint = xscale_remove_breakpoint,
- .add_watchpoint = xscale_add_watchpoint,
- .remove_watchpoint = xscale_remove_watchpoint,
- .register_commands = xscale_register_commands,
- .target_create = xscale_target_create,
- .init_target = xscale_init_target,
- .quit = xscale_quit,
+/* forward declarations */
+static int xscale_resume(struct target_s *, int current,
+ uint32_t address, int handle_breakpoints, int debug_execution);
+static int xscale_debug_entry(target_t *);
+static int xscale_restore_context(target_t *);
+static int xscale_get_reg(reg_t *reg);
+static int xscale_set_reg(reg_t *reg, uint8_t *buf);
+static int xscale_set_breakpoint(struct target_s *, breakpoint_t *);
+static int xscale_set_watchpoint(struct target_s *, watchpoint_t *);
+static int xscale_unset_breakpoint(struct target_s *, breakpoint_t *);
+static int xscale_read_trace(target_t *);
- .virt2phys = xscale_virt2phys,
- .mmu = xscale_mmu
-};
-char* xscale_reg_list[] =
+static char *const xscale_reg_list[] =
{
"XSCALE_MAINID", /* 0 */
"XSCALE_CACHETYPE",
@@ -144,7 +95,7 @@ char* xscale_reg_list[] =
"XSCALE_TXRXCTRL",
};
-xscale_reg_t xscale_reg_arch_info[] =
+static const xscale_reg_t xscale_reg_arch_info[] =
{
{XSCALE_MAINID, NULL},
{XSCALE_CACHETYPE, NULL},
@@ -170,12 +121,21 @@ xscale_reg_t xscale_reg_arch_info[] =
{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
};
-int xscale_reg_arch_type = -1;
+static int xscale_reg_arch_type = -1;
+
+/* convenience wrapper to access XScale specific registers */
+static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
+{
+ uint8_t buf[4];
+
+ buf_set_u32(buf, 0, 32, value);
+
+ return xscale_set_reg(reg, buf);
+}
-int xscale_get_reg(reg_t *reg);
-int xscale_set_reg(reg_t *reg, uint8_t *buf);
-int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
+static int xscale_get_arch_pointers(target_t *target,
+ armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -198,7 +158,7 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc
return ERROR_OK;
}
-int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
+static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
{
if (tap == NULL)
return ERROR_FAIL;
@@ -226,7 +186,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
return ERROR_OK;
}
-int xscale_read_dcsr(target_t *target)
+static int xscale_read_dcsr(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -258,7 +218,6 @@ int xscale_read_dcsr(target_t *target)
fields[1].out_value = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
-
fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
@@ -298,11 +257,11 @@ int xscale_read_dcsr(target_t *target)
static void xscale_getbuf(jtag_callback_data_t arg)
{
- uint8_t *in = (uint8_t *)arg;
+ uint8_t *in = (uint8_t *)arg;
*((uint32_t *)in) = buf_get_u32(in, 0, 32);
}
-int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
+static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
{
if (num_words == 0)
return ERROR_INVALID_ARGUMENTS;
@@ -416,7 +375,7 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
return retval;
}
-int xscale_read_tx(target_t *target, int consume)
+static int xscale_read_tx(target_t *target, int consume)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -458,7 +417,6 @@ int xscale_read_tx(target_t *target, int consume)
fields[1].out_value = NULL;
fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
-
fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = NULL;
@@ -519,7 +477,7 @@ int xscale_read_tx(target_t *target, int consume)
return ERROR_OK;
}
-int xscale_write_rx(target_t *target)
+static int xscale_write_rx(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -550,7 +508,6 @@ int xscale_write_rx(target_t *target)
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
fields[1].in_value = NULL;
-
fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
@@ -608,7 +565,7 @@ int xscale_write_rx(target_t *target)
}
/* send count elements of size byte to the debug handler */
-int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
+static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -675,7 +632,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
return ERROR_OK;
}
-int xscale_send_u32(target_t *target, uint32_t value)
+static int xscale_send_u32(target_t *target, uint32_t value)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -684,7 +641,7 @@ int xscale_send_u32(target_t *target, uint32_t value)
return xscale_write_rx(target);
}
-int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
+static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -722,7 +679,6 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
fields[1].in_value = NULL;
-
fields[2].tap = xscale->jtag_info.tap;
fields[2].num_bits = 1;
fields[2].out_value = &field2;
@@ -747,18 +703,18 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
}
/* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
-unsigned int parity (unsigned int v)
+static unsigned int parity (unsigned int v)
{
- unsigned int ov = v;
+ // unsigned int ov = v;
v ^= v >> 16;
v ^= v >> 8;
v ^= v >> 4;
v &= 0xf;
- LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
+ // LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
return (0x6996 >> v) & 1;
}
-int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
+static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -770,16 +726,15 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
+ /* LDIC into IR */
jtag_set_end_state(TAP_IDLE);
- xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
-
- /* CMD is b010 for Main IC and b011 for Mini IC */
- if (mini)
- buf_set_u32(&cmd, 0, 3, 0x3);
- else
- buf_set_u32(&cmd, 0, 3, 0x2);
+ xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic);
- buf_set_u32(&cmd, 3, 3, 0x0);
+ /* CMD is b011 to load a cacheline into the Mini ICache.
+ * Loading into the main ICache is deprecated, and unused.
+ * It's followed by three zero bits, and 27 address bits.
+ */
+ buf_set_u32(&cmd, 0, 6, 0x3);
/* virtual address of desired cache line */
buf_set_u32(packet, 0, 27, va >> 5);
@@ -787,25 +742,16 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
-
fields[0].in_value = NULL;
-
-
-
-
fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
-
fields[1].in_value = NULL;
-
-
-
-
jtag_add_dr_scan(2, fields, jtag_get_end_state());
+ /* rest of packet is a cacheline: 8 instructions, with parity */
fields[0].num_bits = 32;
fields[0].out_value = packet;
@@ -823,12 +769,10 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
jtag_add_dr_scan(2, fields, jtag_get_end_state());
}
- jtag_execute_queue();
-
- return ERROR_OK;
+ return jtag_execute_queue();
}
-int xscale_invalidate_ic_line(target_t *target, uint32_t va)
+static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -849,29 +793,19 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va)
fields[0].tap = xscale->jtag_info.tap;
fields[0].num_bits = 6;
fields[0].out_value = &cmd;
-
fields[0].in_value = NULL;
-
-
-
-
fields[1].tap = xscale->jtag_info.tap;
fields[1].num_bits = 27;
fields[1].out_value = packet;
-
fields[1].in_value = NULL;
-
-
-
-
jtag_add_dr_scan(2, fields, jtag_get_end_state());
return ERROR_OK;
}
-int xscale_update_vectors(target_t *target)
+static int xscale_update_vectors(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -930,23 +864,23 @@ int xscale_update_vectors(target_t *target)
xscale_invalidate_ic_line(target, 0x0);
xscale_invalidate_ic_line(target, 0xffff0000);
- xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
- xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
+ xscale_load_ic(target, 0x0, xscale->low_vectors);
+ xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
return ERROR_OK;
}
-int xscale_arch_state(struct target_s *target)
+static int xscale_arch_state(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
- char *state[] =
+ static const char *state[] =
{
"disabled", "enabled"
};
- char *arch_dbg_reason[] =
+ static const char *arch_dbg_reason[] =
{
"", "\n(processor reset)", "\n(trace buffer full)"
};
@@ -974,7 +908,7 @@ int xscale_arch_state(struct target_s *target)
return ERROR_OK;
}
-int xscale_poll(target_t *target)
+static int xscale_poll(target_t *target)
{
int retval = ERROR_OK;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1018,7 +952,7 @@ int xscale_poll(target_t *target)
return retval;
}
-int xscale_debug_entry(target_t *target)
+static int xscale_debug_entry(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -1040,8 +974,8 @@ int xscale_debug_entry(target_t *target)
/* move r0 from buffer to register cache */
buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
- armv4_5->core_cache->reg_list[15].dirty = 1;
- armv4_5->core_cache->reg_list[15].valid = 1;
+ armv4_5->core_cache->reg_list[0].dirty = 1;
+ armv4_5->core_cache->reg_list[0].valid = 1;
LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
/* move pc from buffer to register cache */
@@ -1148,7 +1082,7 @@ int xscale_debug_entry(target_t *target)
xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
pc -= 4;
break;
- case 0x7: /* Reserved */
+ case 0x7: /* Reserved (may flag Hot-Debug support) */
default:
LOG_ERROR("Method of Entry is 'Reserved'");
exit(-1);
@@ -1199,7 +1133,7 @@ int xscale_debug_entry(target_t *target)
return ERROR_OK;
}
-int xscale_halt(target_t *target)
+static int xscale_halt(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -1234,7 +1168,7 @@ int xscale_halt(target_t *target)
return ERROR_OK;
}
-int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
+static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale= armv4_5->arch_info;
@@ -1262,7 +1196,7 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
return ERROR_OK;
}
-int xscale_disable_single_step(struct target_s *target)
+static int xscale_disable_single_step(struct target_s *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale= armv4_5->arch_info;
@@ -1275,7 +1209,33 @@ int xscale_disable_single_step(struct target_s *target)
return ERROR_OK;
}
-int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
+static void xscale_enable_watchpoints(struct target_s *target)
+{
+ watchpoint_t *watchpoint = target->watchpoints;
+
+ while (watchpoint)
+ {
+ if (watchpoint->set == 0)
+ xscale_set_watchpoint(target, watchpoint);
+ watchpoint = watchpoint->next;
+ }
+}
+
+static void xscale_enable_breakpoints(struct target_s *target)
+{
+ breakpoint_t *breakpoint = target->breakpoints;
+
+ /* set any pending breakpoints */
+ while (breakpoint)
+ {
+ if (breakpoint->set == 0)
+ xscale_set_breakpoint(target, breakpoint);
+ breakpoint = breakpoint->next;
+ }
+}
+
+static int xscale_resume(struct target_s *target, int current,
+ uint32_t address, int handle_breakpoints, int debug_execution)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale= armv4_5->arch_info;
@@ -1431,7 +1391,8 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha
return ERROR_OK;
}
-static int xscale_step_inner(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+static int xscale_step_inner(struct target_s *target, int current,
+ uint32_t address, int handle_breakpoints)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -1511,7 +1472,8 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr
return ERROR_OK;
}
-int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+static int xscale_step(struct target_s *target, int current,
+ uint32_t address, int handle_breakpoints)
{
armv4_5_common_t *armv4_5 = target->arch_info;
breakpoint_t *breakpoint = target->breakpoints;
@@ -1565,7 +1527,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand
}
-int xscale_assert_reset(target_t *target)
+static int xscale_assert_reset(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -1607,7 +1569,7 @@ int xscale_assert_reset(target_t *target)
return ERROR_OK;
}
-int xscale_deassert_reset(target_t *target)
+static int xscale_deassert_reset(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -1695,23 +1657,23 @@ int xscale_deassert_reset(target_t *target)
cache_line[i / 4] = le_to_h_u32(&buffer[i]);
}
- for (; buf_cnt < 32; buf_cnt += 4)
+ for (; i < 32; i += 4)
{
- cache_line[buf_cnt / 4] = 0xe1a08008;
+ cache_line[i / 4] = 0xe1a08008;
}
/* only load addresses other than the reset vectors */
if ((address % 0x400) != 0x0)
{
- xscale_load_ic(target, 1, address, cache_line);
+ xscale_load_ic(target, address, cache_line);
}
address += buf_cnt;
binary_size -= buf_cnt;
};
- xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
- xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
+ xscale_load_ic(target, 0x0, xscale->low_vectors);
+ xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
@@ -1748,23 +1710,21 @@ int xscale_deassert_reset(target_t *target)
return ERROR_OK;
}
-int xscale_soft_reset_halt(struct target_s *target)
-{
- return ERROR_OK;
-}
-
-int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
+static int xscale_read_core_reg(struct target_s *target, int num,
+ enum armv4_5_mode mode)
{
+ LOG_ERROR("not implemented");
return ERROR_OK;
}
-int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
+static int xscale_write_core_reg(struct target_s *target, int num,
+ enum armv4_5_mode mode, uint32_t value)
{
-
+ LOG_ERROR("not implemented");
return ERROR_OK;
}
-int xscale_full_context(target_t *target)
+static int xscale_full_context(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1840,14 +1800,12 @@ int xscale_full_context(target_t *target)
return ERROR_OK;
}
-int xscale_restore_context(target_t *target)
+static int xscale_restore_context(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
int i, j;
- LOG_DEBUG("-");
-
if (target->state != TARGET_HALTED)
{
LOG_WARNING("target not halted");
@@ -1909,7 +1867,8 @@ int xscale_restore_context(target_t *target)
return ERROR_OK;
}
-int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int xscale_read_memory(struct target_s *target, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -1988,7 +1947,8 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size,
return ERROR_OK;
}
-int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int xscale_write_memory(struct target_s *target, uint32_t address,
+ uint32_t size, uint32_t count, uint8_t *buffer)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2066,12 +2026,13 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size
return ERROR_OK;
}
-int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
+static int xscale_bulk_write_memory(target_t *target, uint32_t address,
+ uint32_t count, uint8_t *buffer)
{
return xscale_write_memory(target, address, 4, count, buffer);
}
-uint32_t xscale_get_ttb(target_t *target)
+static uint32_t xscale_get_ttb(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2083,7 +2044,8 @@ uint32_t xscale_get_ttb(target_t *target)
return ttb;
}
-void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+static void xscale_disable_mmu_caches(target_t *target, int mmu,
+ int d_u_cache, int i_cache)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2122,7 +2084,8 @@ void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c
xscale_send_u32(target, 0x53);
}
-void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+static void xscale_enable_mmu_caches(target_t *target, int mmu,
+ int d_u_cache, int i_cache)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2148,7 +2111,8 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca
xscale_send_u32(target, 0x53);
}
-int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_set_breakpoint(struct target_s *target,
+ breakpoint_t *breakpoint)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2221,7 +2185,8 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_OK;
}
-int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_add_breakpoint(struct target_s *target,
+ breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2252,7 +2217,8 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_OK;
}
-int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_unset_breakpoint(struct target_s *target,
+ breakpoint_t *breakpoint)
{
int retval;
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2307,7 +2273,7 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_OK;
}
-int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2329,7 +2295,8 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
return ERROR_OK;
}
-int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_set_watchpoint(struct target_s *target,
+ watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2385,7 +2352,8 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
return ERROR_OK;
}
-int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_add_watchpoint(struct target_s *target,
+ watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2411,7 +2379,8 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
return ERROR_OK;
}
-int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_unset_watchpoint(struct target_s *target,
+ watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2447,7 +2416,7 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
return ERROR_OK;
}
-int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
xscale_common_t *xscale = armv4_5->arch_info;
@@ -2468,32 +2437,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
return ERROR_OK;
}
-void xscale_enable_watchpoints(struct target_s *target)
-{
- watchpoint_t *watchpoint = target->watchpoints;
-
- while (watchpoint)
- {
- if (watchpoint->set == 0)
- xscale_set_watchpoint(target, watchpoint);
- watchpoint = watchpoint->next;
- }
-}
-
-void xscale_enable_breakpoints(struct target_s *target)
-{
- breakpoint_t *breakpoint = target->breakpoints;
-
- /* set any pending breakpoints */
- while (breakpoint)
- {
- if (breakpoint->set == 0)
- xscale_set_breakpoint(target, breakpoint);
- breakpoint = breakpoint->next;
- }
-}
-
-int xscale_get_reg(reg_t *reg)
+static int xscale_get_reg(reg_t *reg)
{
xscale_reg_t *arch_info = reg->arch_info;
target_t *target = arch_info->target;
@@ -2539,7 +2483,7 @@ int xscale_get_reg(reg_t *reg)
return ERROR_OK;
}
-int xscale_set_reg(reg_t *reg, uint8_t* buf)
+static int xscale_set_reg(reg_t *reg, uint8_t* buf)
{
xscale_reg_t *arch_info = reg->arch_info;
target_t *target = arch_info->target;
@@ -2584,17 +2528,7 @@ int xscale_set_reg(reg_t *reg, uint8_t* buf)
return ERROR_OK;
}
-/* convenience wrapper to access XScale specific registers */
-int xscale_set_reg_u32(reg_t *reg, uint32_t value)
-{
- uint8_t buf[4];
-
- buf_set_u32(buf, 0, 32, value);
-
- return xscale_set_reg(reg, buf);
-}
-
-int xscale_write_dcsr_sw(target_t *target, uint32_t value)
+static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2615,7 +2549,7 @@ int xscale_write_dcsr_sw(target_t *target, uint32_t value)
return ERROR_OK;
}
-int xscale_read_trace(target_t *target)
+static int xscale_read_trace(target_t *target)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2694,7 +2628,8 @@ int xscale_read_trace(target_t *target)
return ERROR_OK;
}
-int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
+static int xscale_read_instruction(target_t *target,
+ arm_instruction_t *instruction)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2760,7 +2695,8 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
return ERROR_OK;
}
-int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *target)
+static int xscale_branch_address(xscale_trace_data_t *trace_data,
+ int i, uint32_t *target)
{
/* if there are less than four entries prior to the indirect branch message
* we can't extract the address */
@@ -2775,7 +2711,7 @@ int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *targ
return 0;
}
-int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
+static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2964,7 +2900,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
return ERROR_OK;
}
-void xscale_build_reg_cache(target_t *target)
+static void xscale_build_reg_cache(target_t *target)
{
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -3009,17 +2945,20 @@ void xscale_build_reg_cache(target_t *target)
xscale->reg_cache = (*cache_p);
}
-int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+static int xscale_init_target(struct command_context_s *cmd_ctx,
+ struct target_s *target)
{
return ERROR_OK;
}
-int xscale_quit(void)
+static int xscale_quit(void)
{
+ jtag_add_runtest(100, TAP_RESET);
return ERROR_OK;
}
-int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
+static int xscale_init_arch_info(target_t *target,
+ xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
{
armv4_5_common_t *armv4_5;
uint32_t high_reset_branch, low_reset_branch;
@@ -3128,7 +3067,7 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t
}
/* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
-int xscale_target_create(struct target_s *target, Jim_Interp *interp)
+static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
{
xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
@@ -3138,7 +3077,9 @@ int xscale_target_create(struct target_s *target, Jim_Interp *interp)
return ERROR_OK;
}
-int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = NULL;
armv4_5_common_t *armv4_5;
@@ -3179,7 +3120,9 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char
return ERROR_OK;
}
-int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = NULL;
armv4_5_common_t *armv4_5;
@@ -3218,7 +3161,9 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
return ERROR_OK;
}
-int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_cache_info_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3232,7 +3177,8 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm
return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
}
-static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
+static int xscale_virt2phys(struct target_s *target,
+ uint32_t virtual, uint32_t *physical)
{
armv4_5_common_t *armv4_5;
xscale_common_t *xscale;
@@ -3269,7 +3215,8 @@ static int xscale_mmu(struct target_s *target, int *enabled)
return ERROR_OK;
}
-int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_mmu_command(command_context_t *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3305,7 +3252,8 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args
return ERROR_OK;
}
-int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_idcache_command(command_context_t *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3359,7 +3307,8 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **
return ERROR_OK;
}
-int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_vector_catch_command(command_context_t *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3387,7 +3336,8 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch
}
-int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_vector_table_command(command_context_t *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3446,7 +3396,9 @@ int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, ch
}
-int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3525,7 +3477,9 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *
return ERROR_OK;
}
-int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_trace_image_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target;
armv4_5_common_t *armv4_5;
@@ -3576,7 +3530,8 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c
return ERROR_OK;
}
-int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3634,7 +3589,9 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm
return ERROR_OK;
}
-int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3650,7 +3607,8 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx
return ERROR_OK;
}
-int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_cp15(command_context_t *cmd_ctx,
+ char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
armv4_5_common_t *armv4_5;
@@ -3739,7 +3697,7 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a
return ERROR_OK;
}
-int xscale_register_commands(struct command_context_s *cmd_ctx)
+static int xscale_register_commands(struct command_context_s *cmd_ctx)
{
command_t *xscale_cmd;
@@ -3769,3 +3727,44 @@ int xscale_register_commands(struct command_context_s *cmd_ctx)
return ERROR_OK;
}
+
+target_type_t xscale_target =
+{
+ .name = "xscale",
+
+ .poll = xscale_poll,
+ .arch_state = xscale_arch_state,
+
+ .target_request_data = NULL,
+
+ .halt = xscale_halt,
+ .resume = xscale_resume,
+ .step = xscale_step,
+
+ .assert_reset = xscale_assert_reset,
+ .deassert_reset = xscale_deassert_reset,
+ .soft_reset_halt = NULL,
+
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+ .read_memory = xscale_read_memory,
+ .write_memory = xscale_write_memory,
+ .bulk_write_memory = xscale_bulk_write_memory,
+ .checksum_memory = arm7_9_checksum_memory,
+ .blank_check_memory = arm7_9_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = xscale_add_breakpoint,
+ .remove_breakpoint = xscale_remove_breakpoint,
+ .add_watchpoint = xscale_add_watchpoint,
+ .remove_watchpoint = xscale_remove_watchpoint,
+
+ .register_commands = xscale_register_commands,
+ .target_create = xscale_target_create,
+ .init_target = xscale_init_target,
+ .quit = xscale_quit,
+
+ .virt2phys = xscale_virt2phys,
+ .mmu = xscale_mmu
+};
diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg
index 81ecac7ec6fc1194c60c5400ca9289f9573d6634..84fc2f77c6039e9e23baae3affd7a0e64d3ea4c4 100644
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -12,14 +12,19 @@ if { [info exists ENDIAN] } {
set _ENDIAN little
}
-#IDs for pxa270. Choose one. Are there others?#
-#set CPUTAPID 0x79265013
-#set CPUTAPID 0x49265013
+#IDs for pxa270. Are there more?
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
+ # set useful default
+ set _CPUTAPID 0x49265013
+}
+
+if { [info exists CPUTAPID2 ] } {
+ set _CPUTAPID2 $CPUTAPID2
+} else {
+ # set useful default
+ set _CPUTAPID2 0x79265013
}
@@ -28,10 +33,10 @@ if { [info exists CPUTAPID ] } {
jtag_nsrst_delay 260
# set the jtag_ntrst_delay to the delay introduced by a reset circuit
# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
+jtag_ntrst_delay 250
set _TARGETNAME $_CHIPNAME.cpu
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
# maps to PXA internal RAM. If you are using a PXA255