From 108028112fdf285cd74eaf50d6a353a09039bb7f Mon Sep 17 00:00:00 2001
From: dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Mon, 21 Sep 2009 00:37:58 +0000
Subject: [PATCH] Ensure that DaVinci chips can't start with a too-fast JTAG
clock. It can be sped up later, once it's known the PLLs are active.
Note that modern tools from TI all use adaptive clocking; and
that if that's done with OpenOCD, "too fast" is also a non-issue.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2740 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
tcl/target/ti_dm355.cfg | 6 ++++++
tcl/target/ti_dm365.cfg | 6 ++++++
tcl/target/ti_dm6446.cfg | 6 ++++++
3 files changed, 18 insertions(+)
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index e5ef8cd2f..abfba1097 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -86,6 +86,12 @@ $_TARGETNAME configure \
-work-area-size 0x4000 \
-work-area-backup 0
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 4f22ea27d..06a52d28f 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -88,6 +88,12 @@ $_TARGETNAME configure \
-work-area-size 0x4000 \
-work-area-backup 0
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index 289518b79..cc23ad440 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -68,6 +68,12 @@ set _TARGETNAME $_CHIPNAME.arm
target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it. OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
arm7_9 fast_memory_access enable
arm7_9 dcc_downloads enable
--
GitLab