diff --git a/src/target/event/pxa255_reset.script b/src/target/event/pxa255_reset.script index a4a971654356836a876dfeb139b47783861a2f33..bc9fa822a9212a4cdb9e1ec81d5f23231de46ead 100644 --- a/src/target/event/pxa255_reset.script +++ b/src/target/event/pxa255_reset.script @@ -1,74 +1,74 @@ -#configuration file for PXA250 Evaluation Board -# ----------------------------------------------------- -# -xscale cp15 15 0x00002001 #Enable CP0 and CP13 access -# -# setup GPIO -# -mww 0x40E00018 0x00008000 #CPSR0 -sleep 20 -mww 0x40E0001C 0x00000002 #GPSR1 -sleep 20 -mww 0x40E00020 0x00000008 #GPSR2 -sleep 20 -mww 0x40E0000C 0x00008000 #GPDR0 -sleep 20 -mww 0x40E00054 0x80000000 #GAFR0_L -sleep 20 -mww 0x40E00058 0x00188010 #GAFR0_H -sleep 20 -mww 0x40E0005C 0x60908018 #GAFR1_L -sleep 20 -mww 0x40E0000C 0x0280E000 #GPDR0 -sleep 20 -mww 0x40E00010 0x821C88B2 #GPDR1 -sleep 20 -mww 0x40E00014 0x000F03DB #GPDR2 -sleep 20 -mww 0x40E00000 0x000F03DB #GPLR0 -sleep 20 - - -mww 0x40F00004 0x00000020 #PSSR -sleep 20 - -# -# setup memory controller -# -mww 0x48000008 0x01111998 #MSC0 -sleep 20 -mww 0x48000010 0x00047ff0 #MSC2 -sleep 20 -mww 0x48000014 0x00000000 #MECR -sleep 20 -mww 0x48000028 0x00010504 #MCMEM0 -sleep 20 -mww 0x4800002C 0x00010504 #MCMEM1 -sleep 20 -mww 0x48000030 0x00010504 #MCATT0 -sleep 20 -mww 0x48000034 0x00010504 #MCATT1 -sleep 20 -mww 0x48000038 0x00004715 #MCIO0 -sleep 20 -mww 0x4800003C 0x00004715 #MCIO1 -sleep 20 -# -mww 0x48000004 0x03CA4018 #MDREF -sleep 20 -mww 0x48000004 0x004B4018 #MDREF -sleep 20 -mww 0x48000004 0x000B4018 #MDREF -sleep 20 -mww 0x48000004 0x000BC018 #MDREF -sleep 20 -mww 0x48000000 0x00001AC8 #MDCNFG -sleep 20 - -sleep 20 - -mww 0x48000000 0x00001AC9 #MDCNFG -sleep 20 -mww 0x48000040 0x00000000 #MDMRS -sleep 20 - +#configuration file for PXA250 Evaluation Board +# ----------------------------------------------------- +# +xscale cp15 15 0x00002001 #Enable CP0 and CP13 access +# +# setup GPIO +# +mww 0x40E00018 0x00008000 #CPSR0 +sleep 20 +mww 0x40E0001C 0x00000002 #GPSR1 +sleep 20 +mww 0x40E00020 0x00000008 #GPSR2 +sleep 20 +mww 0x40E0000C 0x00008000 #GPDR0 +sleep 20 +mww 0x40E00054 0x80000000 #GAFR0_L +sleep 20 +mww 0x40E00058 0x00188010 #GAFR0_H +sleep 20 +mww 0x40E0005C 0x60908018 #GAFR1_L +sleep 20 +mww 0x40E0000C 0x0280E000 #GPDR0 +sleep 20 +mww 0x40E00010 0x821C88B2 #GPDR1 +sleep 20 +mww 0x40E00014 0x000F03DB #GPDR2 +sleep 20 +mww 0x40E00000 0x000F03DB #GPLR0 +sleep 20 + + +mww 0x40F00004 0x00000020 #PSSR +sleep 20 + +# +# setup memory controller +# +mww 0x48000008 0x01111998 #MSC0 +sleep 20 +mww 0x48000010 0x00047ff0 #MSC2 +sleep 20 +mww 0x48000014 0x00000000 #MECR +sleep 20 +mww 0x48000028 0x00010504 #MCMEM0 +sleep 20 +mww 0x4800002C 0x00010504 #MCMEM1 +sleep 20 +mww 0x48000030 0x00010504 #MCATT0 +sleep 20 +mww 0x48000034 0x00010504 #MCATT1 +sleep 20 +mww 0x48000038 0x00004715 #MCIO0 +sleep 20 +mww 0x4800003C 0x00004715 #MCIO1 +sleep 20 +# +mww 0x48000004 0x03CA4018 #MDREF +sleep 20 +mww 0x48000004 0x004B4018 #MDREF +sleep 20 +mww 0x48000004 0x000B4018 #MDREF +sleep 20 +mww 0x48000004 0x000BC018 #MDREF +sleep 20 +mww 0x48000000 0x00001AC8 #MDCNFG +sleep 20 + +sleep 20 + +mww 0x48000000 0x00001AC9 #MDCNFG +sleep 20 +mww 0x48000040 0x00000000 #MDMRS +sleep 20 + diff --git a/src/target/event/str912_reset.script b/src/target/event/str912_reset.script index bbec5976114214ff25d3f165b8f10324d38888fd..c3d6810447aca87cbfe8ad21cc4581bcbec8ceb1 100644 --- a/src/target/event/str912_reset.script +++ b/src/target/event/str912_reset.script @@ -1,22 +1,22 @@ -mww 0xFFFFFD44, 0x00008000 #Disable watchdog -mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator -sleep 20 -mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR -sleep 20 - - -# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, -# when the bank 0 is the boot bank, then enable the Bank 1. */ - -mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB -mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB -mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0 -mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000 -mww 0x54000018, 0x18 #Enable CS on both banks - -# -- Enable 96K RAM */ -mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled -arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register - -str9x flash_config 0 4 2 0 0x80000 -flash protect 0 0 7 off +mww 0xFFFFFD44, 0x00008000 #Disable watchdog +mww 0xFFFFFC20, 0x00000601 #Enable Main oscillator +sleep 20 +mww 0xFFFFFC30, 0x00000001 #Switch master clock to CPU clock, write 1 to PMC_MCKR +sleep 20 + + +# -- Remap Flash Bank 0 at address 0x0 and Bank 1 at address 0x80000, +# when the bank 0 is the boot bank, then enable the Bank 1. */ + +mww 0x54000000, 0x4 #BOOT BANK Size = (2^4) * 32 = 512KB +mww 0x54000004, 0x2 #NON BOOT BANK Size = (2^2) * 8 = 32KB +mww 0x5400000C, 0x0 #BOOT BANK Address = 0x0 +mww 0x54000010, 0x20000 #NON BOOT BANK Address = 0x80000 +mww 0x54000018, 0x18 #Enable CS on both banks + +# -- Enable 96K RAM */ +mww 0x5C002034, 0x0191 # PFQBC enabled / DTCM & AHB wait-states disabled +arm966e cp15 15, 0x60000 #Set bits 17-18 (DTCM/ITCM order bits) of the Core Configuration Control Register + +str9x flash_config 0 4 2 0 0x80000 +flash protect 0 0 7 off diff --git a/src/target/event/wi-9c_reset.script b/src/target/event/wi-9c_reset.script index abb50216628caaf7e90e97cba0a733f6b2253b2e..b648106cafe498f530e135568118fe0e5ce78aae 100644 --- a/src/target/event/wi-9c_reset.script +++ b/src/target/event/wi-9c_reset.script @@ -1,70 +1,70 @@ -mww 0x90600104 0x33313333 -mww 0xA0700000 0x00000001 # Enable the memory controller. -mww 0xA0700024 0x00000006 # Set the refresh counter 6 -mww 0xA0700028 0x00000001 # -mww 0xA0700030 0x00000001 # Set the precharge period -mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles -mww 0xA070003C 0x00000001 # tAPR -mww 0xA0700040 0x00000005 # tDAL -mww 0xA0700044 0x00000001 # tWR -mww 0xA0700048 0x00000006 # tRC 32 clock cycles -mww 0xA070004C 0x00000006 # tRFC 32 clock cycles -mww 0xA0700054 0x00000001 # tRRD -mww 0xA0700058 0x00000001 # tMRD -mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4) -mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5) -mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6) -mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7) -# -mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz -mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz -mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz -mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz -# -mww 0xA0700020 0x00000103 # issue SDRAM PALL command -# -mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible -# -# Add some dummy writes to give the SDRAM time to settle, it needs two -# AHB clock cycles, here we poke in the debugger flag, this lets -# the software know that we are in the debugger -mww 0xA0900000 0x00000002 -mww 0xA0900000 0x00000002 -mww 0xA0900000 0x00000002 -mww 0xA0900000 0x00000002 -mww 0xA0900000 0x00000002 -# -mdw 0xA0900000 -mdw 0xA0900000 -mdw 0xA0900000 -mdw 0xA0900000 -mdw 0xA0900000 -# -mww 0xA0700024 0x00000030 # Set the refresh counter to 30 -mww 0xA0700020 0x00000083 # Issue SDRAM MODE command -# -# Next we perform a read of RAM. -# mw = move word. -mdw 0x00022000 -# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3 -# -mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command -mww 0xA0700100 0x00084280 # Enable buffer access -mww 0xA0700120 0x00084280 # Enable buffer access -mww 0xA0700140 0x00084280 # Enable buffer access -mww 0xA0700160 0x00084280 # Enable buffer access - -#Set byte lane state (static mem 1)" -mww 0xA0700220, 0x00000082 -#Flash Start -mww 0xA09001F8, 0x50000000 -#Flash Mask Reg -mww 0xA09001FC, 0xFF000001 -mww 0xA0700028, 0x00000001 - -# RAMAddr = 0x00020000 -# RAMSize = 0x00004000 - -# Set the processor mode -reg cpsr 0xd3 - +mww 0x90600104 0x33313333 +mww 0xA0700000 0x00000001 # Enable the memory controller. +mww 0xA0700024 0x00000006 # Set the refresh counter 6 +mww 0xA0700028 0x00000001 # +mww 0xA0700030 0x00000001 # Set the precharge period +mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles +mww 0xA070003C 0x00000001 # tAPR +mww 0xA0700040 0x00000005 # tDAL +mww 0xA0700044 0x00000001 # tWR +mww 0xA0700048 0x00000006 # tRC 32 clock cycles +mww 0xA070004C 0x00000006 # tRFC 32 clock cycles +mww 0xA0700054 0x00000001 # tRRD +mww 0xA0700058 0x00000001 # tMRD +mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4) +mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5) +mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6) +mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7) +# +mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz +mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz +mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz +mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz +# +mww 0xA0700020 0x00000103 # issue SDRAM PALL command +# +mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible +# +# Add some dummy writes to give the SDRAM time to settle, it needs two +# AHB clock cycles, here we poke in the debugger flag, this lets +# the software know that we are in the debugger +mww 0xA0900000 0x00000002 +mww 0xA0900000 0x00000002 +mww 0xA0900000 0x00000002 +mww 0xA0900000 0x00000002 +mww 0xA0900000 0x00000002 +# +mdw 0xA0900000 +mdw 0xA0900000 +mdw 0xA0900000 +mdw 0xA0900000 +mdw 0xA0900000 +# +mww 0xA0700024 0x00000030 # Set the refresh counter to 30 +mww 0xA0700020 0x00000083 # Issue SDRAM MODE command +# +# Next we perform a read of RAM. +# mw = move word. +mdw 0x00022000 +# mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3 +# +mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command +mww 0xA0700100 0x00084280 # Enable buffer access +mww 0xA0700120 0x00084280 # Enable buffer access +mww 0xA0700140 0x00084280 # Enable buffer access +mww 0xA0700160 0x00084280 # Enable buffer access + +#Set byte lane state (static mem 1)" +mww 0xA0700220, 0x00000082 +#Flash Start +mww 0xA09001F8, 0x50000000 +#Flash Mask Reg +mww 0xA09001FC, 0xFF000001 +mww 0xA0700028, 0x00000001 + +# RAMAddr = 0x00020000 +# RAMSize = 0x00004000 + +# Set the processor mode +reg cpsr 0xd3 + diff --git a/src/target/event/xba_revA3.script b/src/target/event/xba_revA3.script index 3d0110149c758bd6e2f62b0cc221e4cdb67e2f78..e58185e244abd2e509988ff2a41d5744cb47c7d0 100644 --- a/src/target/event/xba_revA3.script +++ b/src/target/event/xba_revA3.script @@ -1,43 +1,43 @@ -#Written by: Michael Schwingen <rincewind@discworld.dascon.de> -############################################################################# -# setup expansion bus CS, disable external wdt -############################################################################# -mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000 -mww 0xc4000004 0x94d10013 #CS1 -mww 0xc4000008 0x95960003 #CS2 -mww 0xc400000c 0x00000000 #CS3 -mww 0xc4000010 0x80900003 #CS4 -mww 0xc4000014 0x9d520003 #CS5 -mww 0xc4000018 0x81860001 #CS6 -mww 0xc400001c 0x80900003 #CS7 - -############################################################################# -# init SDRAM controller: 16MB, one bank, CL3 -############################################################################# -mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3 -mww 0xCC000004 0 # disable refresh -mww 0xCC000008 3 # NOP -sleep 100 -mww 0xCC000004 2100 # set refresh counter -mww 0xCC000008 2 # Precharge All Banks -sleep 100 -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 4 # Auto Refresh -mww 0xCC000008 1 # Mode Select CL3 - -#mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash -#mirror at 0x00000000 - -#big endian -reg XSCALE_CTRL 0xF8 - -# -# detect flash -# -flash probe 0 +#Written by: Michael Schwingen <rincewind@discworld.dascon.de> +############################################################################# +# setup expansion bus CS, disable external wdt +############################################################################# +mww 0xc4000000 0xbd113842 #CS0 : Flash, write enabled @0x50000000 +mww 0xc4000004 0x94d10013 #CS1 +mww 0xc4000008 0x95960003 #CS2 +mww 0xc400000c 0x00000000 #CS3 +mww 0xc4000010 0x80900003 #CS4 +mww 0xc4000014 0x9d520003 #CS5 +mww 0xc4000018 0x81860001 #CS6 +mww 0xc400001c 0x80900003 #CS7 + +############################################################################# +# init SDRAM controller: 16MB, one bank, CL3 +############################################################################# +mww 0xCC000000 0x2A # SDRAM_CFG: 64MBit, CL3 +mww 0xCC000004 0 # disable refresh +mww 0xCC000008 3 # NOP +sleep 100 +mww 0xCC000004 2100 # set refresh counter +mww 0xCC000008 2 # Precharge All Banks +sleep 100 +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 4 # Auto Refresh +mww 0xCC000008 1 # Mode Select CL3 + +#mww 0xc4000020 0xffffee # CFG0: remove expansion bus boot flash +#mirror at 0x00000000 + +#big endian +reg XSCALE_CTRL 0xF8 + +# +# detect flash +# +flash probe 0 diff --git a/src/target/target/lm3s6965.cfg b/src/target/target/lm3s6965.cfg index 55563f7fc4df2f8e6122a9f9297057bec18029ea..9f6374cd3132079cf2a7b861227d79094ad70af5 100644 --- a/src/target/target/lm3s6965.cfg +++ b/src/target/target/lm3s6965.cfg @@ -1,19 +1,19 @@ -jtag_nsrst_delay 500 -jtag_ntrst_delay 500 - -#LM3S811 Evaluation Board has only srst -reset_config trst_and_srst srst_pulls_trst - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - -target cortex_m3 little run_and_halt 0 - -# 4k working area at base of ram -working_area 0 0x20000000 0x4000 nobackup - -#flash configuration -#flash bank stellaris 0 262144 0 0 0 -flash bank stellaris 0 0 0 0 0 -#flash write_image main.bin 0 bin +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +#LM3S811 Evaluation Board has only srst +reset_config trst_and_srst srst_pulls_trst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +target cortex_m3 little run_and_halt 0 + +# 4k working area at base of ram +working_area 0 0x20000000 0x4000 nobackup + +#flash configuration +#flash bank stellaris 0 262144 0 0 0 +flash bank stellaris 0 0 0 0 0 +#flash write_image main.bin 0 bin diff --git a/src/target/target/readme.txt b/src/target/target/readme.txt index b8bf5dcf88ead2ac5bc5d12fccbcf1f5c53f7a8b..19a7d3a23685659d92f9d6a92b2f54f3128afc0e 100644 --- a/src/target/target/readme.txt +++ b/src/target/target/readme.txt @@ -1,18 +1,18 @@ -Prerequisites: -The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands -do the same thing across all the targets. - -Rules to follow when writing scripts: - -1. The configuration script should be defined such as , for example, the following sequences are working: - reset - flash info <bank> -and - reset - flash erase_address <start> <len> - -In most cases this can be accomplished by specifying the default startup mode as reset_init (target command -in the configuration file). - -2. If the target is correctly configured, flash must be writable without any other helper commands. It is -assumed that all write-protect mechanisms should be disabled. +Prerequisites: +The users of OpenOCD as well as computer programs interacting with OpenOCD are expecting that certain commands +do the same thing across all the targets. + +Rules to follow when writing scripts: + +1. The configuration script should be defined such as , for example, the following sequences are working: + reset + flash info <bank> +and + reset + flash erase_address <start> <len> + +In most cases this can be accomplished by specifying the default startup mode as reset_init (target command +in the configuration file). + +2. If the target is correctly configured, flash must be writable without any other helper commands. It is +assumed that all write-protect mechanisms should be disabled. diff --git a/src/target/target/wi-9c.cfg b/src/target/target/wi-9c.cfg index 2bc7d9369db65439a82f793ac60adedfa0e0bbfa..9c4d565dcc6402c8953261010369f93ff0003398 100644 --- a/src/target/target/wi-9c.cfg +++ b/src/target/target/wi-9c.cfg @@ -1,36 +1,36 @@ -###################################### -# Target: DIGI ConnectCore Wi-9C -###################################### - -reset_config trst_and_srst - -#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction> -jtag_device 4 0x1 0xf 0xe - -jtag_nsrst_delay 200 -jtag_ntrst_delay 0 - -###################### -# Target configuration -###################### - -#target <type> <endianess> <reset mode> <JTAG pos> <variant> -target arm926ejs big reset_init 0 arm926ejs - -target_script 0 reset event/wi-9c_reset.script -run_and_halt_time 0 30 - -#working area <target#> <address> <size> <backup|nobackup> -working_area 0 0x00000000 0x1000 backup - - -##################### -# Flash configuration -##################### - -#M29DW323DB - not working -#flash bank cfi <base> <size> <chip width> <bus width> <target#> -flash bank cfi 0x50000000 0x0400000 2 2 0 - - - +###################################### +# Target: DIGI ConnectCore Wi-9C +###################################### + +reset_config trst_and_srst + +#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction> +jtag_device 4 0x1 0xf 0xe + +jtag_nsrst_delay 200 +jtag_ntrst_delay 0 + +###################### +# Target configuration +###################### + +#target <type> <endianess> <reset mode> <JTAG pos> <variant> +target arm926ejs big reset_init 0 arm926ejs + +target_script 0 reset event/wi-9c_reset.script +run_and_halt_time 0 30 + +#working area <target#> <address> <size> <backup|nobackup> +working_area 0 0x00000000 0x1000 backup + + +##################### +# Flash configuration +##################### + +#M29DW323DB - not working +#flash bank cfi <base> <size> <chip width> <bus width> <target#> +flash bank cfi 0x50000000 0x0400000 2 2 0 + + + diff --git a/src/target/target/xba_revA3.cfg b/src/target/target/xba_revA3.cfg index 2fb837215c87698a8d15715e151a81cd58316ac8..0c73e8c1eff5fc93100117d7893803be32b34b6c 100644 --- a/src/target/target/xba_revA3.cfg +++ b/src/target/target/xba_revA3.cfg @@ -1,28 +1,28 @@ -#Written by: Michael Schwingen <rincewind@discworld.dascon.de> - -reset_config trst_and_srst separate - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE) -jtag_device 7 0x1 0x7f 0x7e - -daemon_startup reset - -#target <type> <endianess> <reset mode> <JTAG pos> <variant> -target xscale big reset_init 0 ixp42x -#target xscale big run_and_halt 0 ixp42x -target_script 0 reset event/xba_revA3.script - -run_and_halt_time 0 100 - -flash bank cfi 0x50000000 0x400000 2 2 0 -working_area 0 0x20010000 0x8000 nobackup - -# halt target -wait_halt - -# set big endian mode -reg XSCALE_CTRL 0xF8 +#Written by: Michael Schwingen <rincewind@discworld.dascon.de> + +reset_config trst_and_srst separate + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE) +jtag_device 7 0x1 0x7f 0x7e + +daemon_startup reset + +#target <type> <endianess> <reset mode> <JTAG pos> <variant> +target xscale big reset_init 0 ixp42x +#target xscale big run_and_halt 0 ixp42x +target_script 0 reset event/xba_revA3.script + +run_and_halt_time 0 100 + +flash bank cfi 0x50000000 0x400000 2 2 0 +working_area 0 0x20010000 0x8000 nobackup + +# halt target +wait_halt + +# set big endian mode +reg XSCALE_CTRL 0xF8