From 33d8d55fc1abdd6b74873ca832b628dff9744edb Mon Sep 17 00:00:00 2001
From: Kevin Gillespie <kgills@gmail.com>
Date: Fri, 14 Dec 2018 15:56:45 -0600
Subject: [PATCH] Working with unencrypted 128-bit writes.
Change-Id: Ia09f0a7302e58dd2836f44c3d7d4862c61cd96a6
---
src/flash/nor/max32xxx.c | 110 ++++++++++++++++++++++++++++-----------
tcl/target/max32xxx.cfg | 12 ++++-
2 files changed, 92 insertions(+), 30 deletions(-)
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 0156d3339..1428b37c6 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -90,6 +90,15 @@
#define WRITE32BIT 0
#define WRITE128BIT 1
+#define OPTIONS_128 0x01 /* Perform 128 bit flash writes */
+#define OPTIONS_ENC 0x02 /* Encrypt the flash contents */
+#define OPTIONS_AUTH 0x04 /* Authenticate the flash contents */
+#define OPTIONS_COUNT 0x08 /* Add counter values to authentication */
+#define OPTIONS_INTER 0x10 /* Interleave the authentication and count values*/
+#define OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */
+#define OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */
+
+
static int max32xxx_mass_erase(struct flash_bank *bank);
struct max32xxx_flash_bank {
@@ -101,11 +110,56 @@ struct max32xxx_flash_bank {
unsigned int clkdiv_value;
unsigned int int_state;
unsigned int burst_size_bits;
+ unsigned int enc_options;
};
/* see contib/loaders/flash/max32xxx/max32xxx.s for src */
static const uint8_t write_code[] = {
-#include "../../contrib/loaders/flash/max32xxx/max32xxx.inc"
+ 0x9b, 0x46, 0x51, 0xf8, 0x84, 0x3c, 0xa1, 0xf5, 0x82, 0x77, 0x02, 0x93, 0x13, 0xf0, 0x02, 0x03, 0x05, 0x93, 0x1e, 0xd0,
+ 0x4f, 0xf0, 0x80, 0x43, 0x9c, 0x68, 0x64, 0x03, 0x5e, 0xbf, 0x9c, 0x68, 0x44, 0xf4, 0x80, 0x24, 0x9c, 0x60, 0x5c, 0x6a,
+ 0x64, 0x04, 0x42, 0xbf, 0x5c, 0x6a, 0x24, 0xf4, 0x80, 0x44, 0x5c, 0x62, 0x01, 0x24, 0x45, 0x4b, 0x1c, 0x60, 0x1c, 0x68,
+ 0x44, 0xf4, 0x80, 0x44, 0x1c, 0x60, 0x1c, 0x68, 0x44, 0xf0, 0x10, 0x04, 0x1c, 0x60, 0x1c, 0x68, 0x44, 0xf0, 0x20, 0x04,
+ 0x1c, 0x60, 0x02, 0x9b, 0x3d, 0x4c, 0x03, 0xf0, 0x01, 0x03, 0x04, 0x93, 0x00, 0xf1, 0x08, 0x03, 0x03, 0x93, 0x3b, 0x4b,
+ 0xa1, 0xf5, 0x80, 0x7a, 0x92, 0xb9, 0x05, 0x9b, 0x7b, 0xb1, 0x4f, 0xf0, 0x80, 0x43, 0x1a, 0x68, 0x42, 0xf4, 0x80, 0x12,
+ 0x1a, 0x60, 0x02, 0x9a, 0x12, 0xf0, 0x40, 0x0f, 0x1a, 0x68, 0x14, 0xbf, 0x42, 0xf4, 0x00, 0x12, 0x22, 0xf4, 0x00, 0x12,
+ 0x1a, 0x60, 0x00, 0xbe, 0x04, 0x9d, 0x00, 0x2d, 0x5e, 0xd1, 0x9d, 0x68, 0xa1, 0xf5, 0x82, 0x7c, 0x45, 0xf0, 0x10, 0x05,
+ 0x9d, 0x60, 0x04, 0x9d, 0xcd, 0xf8, 0x04, 0xb0, 0xae, 0x46, 0xcc, 0xf8, 0x00, 0x50, 0x00, 0x2a, 0x4a, 0xd0, 0xd0, 0xf8,
+ 0x04, 0x80, 0x05, 0x68, 0xa8, 0x45, 0xfa, 0xd0, 0x45, 0x68, 0xd0, 0xf8, 0x04, 0x80, 0x2d, 0x78, 0x08, 0xf1, 0x01, 0x08,
+ 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08,
+ 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x3a, 0x01, 0x96, 0x05, 0xfa, 0x0e, 0xf8, 0xdc, 0xf8,
+ 0x00, 0x50, 0x0e, 0xf1, 0x08, 0x0e, 0x45, 0xea, 0x08, 0x05, 0xbe, 0xf1, 0x20, 0x0f, 0xcc, 0xf8, 0x00, 0x50, 0xd4, 0xd1,
+ 0x9d, 0x68, 0x25, 0xf0, 0x70, 0x45, 0x45, 0xf0, 0x00, 0x55, 0x9d, 0x60, 0xc3, 0xf8, 0x00, 0xb0, 0xdc, 0xf8, 0x00, 0x50,
+ 0x1d, 0x63, 0x9d, 0x68, 0x45, 0xf0, 0x01, 0x05, 0x9d, 0x60, 0x9d, 0x68, 0xed, 0x07, 0xfc, 0xd4, 0x9d, 0x68, 0x25, 0xf0,
+ 0x70, 0x45, 0x9d, 0x60, 0x5d, 0x6a, 0x15, 0xf0, 0x02, 0x0f, 0x04, 0xd0, 0x5d, 0x6a, 0x25, 0xf0, 0x02, 0x05, 0x5d, 0x62,
+ 0x00, 0xbe, 0xdd, 0xf8, 0x04, 0xb0, 0x8f, 0xe7, 0xff, 0x25, 0xce, 0xe7, 0x00, 0x10, 0x00, 0x40, 0x00, 0x90, 0x02, 0x40,
+ 0xa1, 0xf5, 0x84, 0x7e, 0xf4, 0x46, 0xa1, 0xf1, 0xf8, 0x05, 0x06, 0x95, 0xcd, 0xf8, 0x04, 0xb0, 0x00, 0x25, 0x4c, 0xf8,
+ 0x04, 0x5f, 0x00, 0x2a, 0x00, 0xf0, 0xfd, 0x80, 0xd0, 0xf8, 0x04, 0x80, 0x05, 0x68, 0xa8, 0x45, 0xfa, 0xd0, 0x45, 0x68,
+ 0xd0, 0xf8, 0x04, 0x80, 0x2d, 0x78, 0x08, 0xf1, 0x01, 0x08, 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80,
+ 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08, 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80,
+ 0x01, 0x3a, 0x01, 0x96, 0xcc, 0xf8, 0x00, 0x50, 0x00, 0x2a, 0x00, 0xf0, 0xde, 0x80, 0xd0, 0xf8, 0x04, 0x90, 0xd0, 0xf8,
+ 0x00, 0x80, 0xc1, 0x45, 0xf9, 0xd0, 0xd0, 0xf8, 0x04, 0x80, 0x01, 0x3a, 0x98, 0xf8, 0x00, 0x90, 0xd0, 0xf8, 0x04, 0x80,
+ 0x08, 0xf1, 0x01, 0x08, 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf,
+ 0x08, 0xf1, 0x01, 0x08, 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x96, 0x45, 0xea, 0x09, 0x25,
+ 0xcc, 0xf8, 0x00, 0x50, 0x00, 0x2a, 0x00, 0xf0, 0xbb, 0x80, 0xd0, 0xf8, 0x04, 0x90, 0xd0, 0xf8, 0x00, 0x80, 0xc1, 0x45,
+ 0xf9, 0xd0, 0xd0, 0xf8, 0x04, 0x80, 0x01, 0x3a, 0x98, 0xf8, 0x00, 0x90, 0xd0, 0xf8, 0x04, 0x80, 0x08, 0xf1, 0x01, 0x08,
+ 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08,
+ 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x96, 0x45, 0xea, 0x09, 0x45, 0xcc, 0xf8, 0x00, 0x50,
+ 0x00, 0x2a, 0x00, 0xf0, 0x98, 0x80, 0xd0, 0xf8, 0x04, 0x90, 0xd0, 0xf8, 0x00, 0x80, 0xc1, 0x45, 0xf9, 0xd0, 0xd0, 0xf8,
+ 0x04, 0x80, 0x01, 0x3a, 0x98, 0xf8, 0x00, 0x90, 0xd0, 0xf8, 0x04, 0x80, 0x08, 0xf1, 0x01, 0x08, 0x47, 0x45, 0x96, 0xbf,
+ 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08, 0x06, 0xf1, 0x01, 0x06,
+ 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x96, 0x45, 0xea, 0x09, 0x65, 0xcc, 0xf8, 0x00, 0x50, 0x06, 0x9d, 0x65, 0x45,
+ 0x7f, 0xf4, 0x66, 0xaf, 0x05, 0x9d, 0x00, 0x2d, 0x46, 0xd0, 0x02, 0x9d, 0x05, 0xf0, 0x20, 0x05, 0x06, 0x95, 0x2b, 0xf0,
+ 0x7f, 0x45, 0x07, 0x95, 0x06, 0x9e, 0x0e, 0xf5, 0x84, 0x75, 0x0e, 0xf1, 0x04, 0x09, 0xde, 0xf8, 0x04, 0x80, 0x6d, 0x1a,
+ 0x00, 0x2e, 0x5f, 0xd0, 0x07, 0x9e, 0x35, 0x44, 0x85, 0xea, 0x08, 0x05, 0xe1, 0x45, 0xce, 0xf8, 0x04, 0x50, 0xce, 0x46,
+ 0xec, 0xd1, 0x25, 0x68, 0x45, 0xf0, 0x00, 0x65, 0x25, 0x60, 0x00, 0x25, 0x65, 0x60, 0x02, 0x9d, 0x15, 0xf0, 0x40, 0x0f,
+ 0x65, 0x68, 0x14, 0xbf, 0x45, 0xf0, 0x30, 0x05, 0x45, 0xf0, 0x10, 0x05, 0x65, 0x60, 0x65, 0x68, 0x45, 0xf0, 0x0c, 0x05,
+ 0x65, 0x60, 0x3d, 0x68, 0x25, 0x62, 0xda, 0xf8, 0x00, 0x50, 0x65, 0x62, 0x51, 0xf8, 0xfc, 0x5c, 0xa5, 0x62, 0x51, 0xf8,
+ 0xf8, 0x5c, 0xe5, 0x62, 0x25, 0x68, 0x2d, 0x01, 0xfc, 0xd5, 0x25, 0x6b, 0x3d, 0x60, 0x65, 0x6b, 0xca, 0xf8, 0x00, 0x50,
+ 0xa5, 0x6b, 0x41, 0xf8, 0xfc, 0x5c, 0xe5, 0x6b, 0x41, 0xf8, 0xf8, 0x5c, 0x9d, 0x68, 0x25, 0xf0, 0x70, 0x45, 0x45, 0xf0,
+ 0x00, 0x55, 0x9d, 0x60, 0x9d, 0x68, 0x25, 0xf0, 0x10, 0x05, 0x9d, 0x60, 0xc3, 0xf8, 0x00, 0xb0, 0x3d, 0x68, 0x1d, 0x63,
+ 0xda, 0xf8, 0x00, 0x50, 0x5d, 0x63, 0x51, 0xf8, 0xfc, 0x5c, 0x9d, 0x63, 0x51, 0xf8, 0xf8, 0x5c, 0xdd, 0x63, 0x9d, 0x68,
+ 0x45, 0xf0, 0x01, 0x05, 0x9d, 0x60, 0x9d, 0x68, 0xed, 0x07, 0xfc, 0xd4, 0xde, 0xe6, 0xff, 0x25, 0x1c, 0xe7, 0x4f, 0xf0,
+ 0xff, 0x09, 0x3d, 0xe7, 0x4f, 0xf0, 0xff, 0x09, 0x60, 0xe7, 0x4f, 0xf0, 0xff, 0x09, 0x83, 0xe7, 0x5d, 0x44, 0x9f, 0xe7,
};
/* Config Command: flash bank name driver base size chip_width bus_width target [driver_option]
@@ -115,11 +169,8 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
{
struct max32xxx_flash_bank *info;
- if (CMD_ARGC < 9) {
- LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits]");
- return ERROR_FLASH_BANK_INVALID;
- } else if (CMD_ARGC > 10) {
- LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits]");
+ if ((CMD_ARGC < 10) || (CMD_ARGC > 11)) {
+ LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> <burst_bits> [enc_options]");
return ERROR_FLASH_BANK_INVALID;
}
@@ -128,19 +179,23 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->flc_base);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->sector_size);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], info->clkdiv_value);
-
- if (CMD_ARGC == 10)
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->burst_size_bits);
- else {
- /* Default burst size of 32 bits */
- info->burst_size_bits = 32;
- }
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->burst_size_bits);
if ((info->burst_size_bits != 128) && (info->burst_size_bits != 32)) {
LOG_ERROR("Invalid burst size %d, must be 32 or 128", info->burst_size_bits);
return ERROR_FLASH_BANK_INVALID;
}
+ if(CMD_ARGC == 11) {
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[10], info->enc_options);
+ } else {
+ if(info->burst_size_bits == 128) {
+ info->enc_options = OPTIONS_128;
+ } else {
+ info->enc_options = 0x0;
+ }
+ }
+
info->int_state = 0;
bank->driver_priv = info;
return ERROR_OK;
@@ -403,7 +458,8 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct working_area *source;
struct working_area *write_algorithm;
uint32_t address = bank->base + offset;
- struct reg_param reg_params[6];
+ struct reg_param reg_params[5];
+ struct mem_param mem_param[1];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
/* power of two, and multiple of word size */
@@ -448,24 +504,21 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer,
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
- init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
- init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
+ init_reg_param(®_params[4], "sp", 32, PARAM_OUT);
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
- buf_set_u32(reg_params[2].value, 0, 32, address);
- buf_set_u32(reg_params[4].value, 0, 32, info->flc_base);
+ buf_set_u32(reg_params[2].value, 0, 32, wcount*4);
+ buf_set_u32(reg_params[3].value, 0, 32, address);
+ buf_set_u32(reg_params[4].value, 0, 32, source->address + source->size);
- if (info->burst_size_bits == 32) {
- buf_set_u32(reg_params[3].value, 0, 32, wcount);
- buf_set_u32(reg_params[5].value, 0, 32, WRITE32BIT);
- } else {
- buf_set_u32(reg_params[3].value, 0, 32, wcount/4);
- buf_set_u32(reg_params[5].value, 0, 32, WRITE128BIT);
- }
+ /* mem_params for options */
+ init_mem_param(&mem_param[0], source->address + (source->size - 4 - 128), 4, PARAM_OUT);
+ buf_set_u32(mem_param[0].value, 0, 32, info->enc_options);
- retval = target_run_flash_async_algorithm(target, buffer, wcount, 4, 0, NULL,
- 6, reg_params, source->address, source->size, write_algorithm->address, 0, &armv7m_info);
+ /* leave room for stack, 32-bit options and encryption buffer */
+ retval = target_run_flash_async_algorithm(target, buffer, wcount*4, 1, 1, mem_param,
+ 5, reg_params, source->address, (source->size - 4 - 256), write_algorithm->address, 0, &armv7m_info);
if (retval == ERROR_FLASH_OPERATION_FAILED)
LOG_ERROR("error %d executing max32xxx flash write algorithm", retval);
@@ -476,8 +529,7 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer,
destroy_reg_param(®_params[1]);
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
- destroy_reg_param(®_params[4]);
- destroy_reg_param(®_params[5]);
+ destroy_reg_param(®_params[4]);
return retval;
}
diff --git a/tcl/target/max32xxx.cfg b/tcl/target/max32xxx.cfg
index 3fb6e66fd..9039f0d92 100644
--- a/tcl/target/max32xxx.cfg
+++ b/tcl/target/max32xxx.cfg
@@ -83,5 +83,15 @@ if { [info exists FLASH_BITS] } {
set _FLASH_BITS 32
}
+if { [info exists ENC_OPTIONS] } {
+ set _ENC_OPTIONS $ENC_OPTIONS
+} else {
+ if { $FLASH_BITS == 128 } {
+ set _ENC_OPTIONS 1
+ } else {
+ set _ENC_OPTIONS 0
+ }
+}
+
flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
-$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_BITS
+$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_BITS $_ENC_OPTIONS
--
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