diff --git a/contrib/libdcc/dcc_stdio.c b/contrib/libdcc/dcc_stdio.c
index a25e7dd169bc5aa4f3b5443a3d372f3cf2f9023c..08a49abf1b82de1cebecbf9d4a2427b361d84d91 100644
--- a/contrib/libdcc/dcc_stdio.c
+++ b/contrib/libdcc/dcc_stdio.c
@@ -99,7 +99,7 @@ void dbg_write_u16(const unsigned short *val, long len)
while (len > 0)
{
- dcc_data = val[0]
+ dcc_data = val[0]
| ((len > 1) ? val[1] << 16: 0x0000);
dbg_write(dcc_data);
@@ -145,7 +145,7 @@ void dbg_write_str(const char *msg)
| ((len > 2) ? msg[2] << 16 : 0x00)
| ((len > 3) ? msg[3] << 24 : 0x00);
dbg_write(dcc_data);
-
+
msg += 4;
len -= 4;
}
diff --git a/contrib/libdcc/example.c b/contrib/libdcc/example.c
index d456f3955125197db28300c7f5911c7d94883e94..0814c9ce8b0fee5c19ef3722c83d792950616adf 100644
--- a/contrib/libdcc/example.c
+++ b/contrib/libdcc/example.c
@@ -23,11 +23,11 @@
#include "dcc_stdio.h"
/* enable openocd debugmsg at the gdb prompt:
- * monitor target_request debugmsgs enable
- *
+ * monitor target_request debugmsgs enable
+ *
* create a trace point:
* monitor trace point 1
- *
+ *
* to show how often the trace point was hit:
* monitor trace point
*/
diff --git a/ecosflash/flash.c b/ecosflash/flash.c
index 81f7d07dacbc7eeabf53a8488ec52ee56c387c94..c8ac353f4996f4d891da6a2189978c33ce686664 100644
--- a/ecosflash/flash.c
+++ b/ecosflash/flash.c
@@ -53,7 +53,7 @@ int init()
*t=0;
}
return flash_init((_printf *)&myprintf);
-
+
}
@@ -68,15 +68,15 @@ int checkFlash(void *addr, int len)
}
-int erase(void *address, int len)
+int erase(void *address, int len)
{
int retval;
void *failAddress;
-
+
retval=checkFlash(address, len);
if (retval!=0)
return retval;
-
+
retval=init();
if (retval!=0)
return retval;
@@ -88,14 +88,14 @@ int erase(void *address, int len)
extern char _end;
// Data follows immediately after program, long word aligned.
-int program(void *buffer, void *address, int len)
+int program(void *buffer, void *address, int len)
{
int retval;
void *failAddress;
retval=checkFlash(address, len);
if (retval!=0)
return retval;
-
+
retval=init();
if (retval!=0)
return retval;
diff --git a/src/flash/lpc2900.c b/src/flash/lpc2900.c
index e39c53195d9f588f7ce3591099939050de71094f..902180cbe3af8856bad226d9da31577e7af7968c 100644
--- a/src/flash/lpc2900.c
+++ b/src/flash/lpc2900.c
@@ -528,7 +528,7 @@ static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time )
* FPTR.TR = -------------------------------
* 512
*
- * The result is the
+ * The result is the
*/
uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
diff --git a/src/target/arm11.c b/src/target/arm11.c
index c41adfa3bf779df3f6d1e6ec28437072743a9ca5..f46e424b90882d5c282dfbc886888d9d8607eccf 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1203,7 +1203,7 @@ int arm11_assert_reset(target_t *target)
/* FIX! we really should assert srst here, but
* how do we reset the target into the halted state?
- *
+ *
* Also arm11 behaves "funny" when srst is asserted
* (as of writing the rules are not understood).
*/
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 499d592d1e2c95b6973cfa21465ac51a399c4975..1e0e02f189f024fa0e639514de6dc3c32a38f80b 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -176,7 +176,7 @@ reg_t armv7a_gdb_dummy_fp_reg =
void armv7a_show_fault_registers(target_t *target)
{
uint32_t dfsr, ifsr, dfar, ifar;
-
+
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -186,9 +186,9 @@ void armv7a_show_fault_registers(target_t *target)
armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
- LOG_USER("Data fault registers DFSR: %8.8" PRIx32
+ LOG_USER("Data fault registers DFSR: %8.8" PRIx32
", DFAR: %8.8" PRIx32, dfsr, dfar);
- LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+ LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
", IFAR: %8.8" PRIx32, ifsr, ifar);
}
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 846d90c343360367317ed2267c8e1ec42bd4c3f3..025a468a86e610375d1ac9a2b145b267d30cd23f 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -140,13 +140,13 @@ int cortex_a8_init_debug_access(target_t *target)
/* Clear Sticky Power Down status Bit in PRSR to enable access to
the registers in the Core Power Domain */
retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
- /* Enabling of instruction execution in debug mode is done in debug_entry code */
-
+ /* Enabling of instruction execution in debug mode is done in debug_entry code */
+
/* Resync breakpoint registers */
-
+
/* Since this is likley called from init or reset, update targtet state information*/
cortex_a8_poll(target);
-
+
return retval;
}
@@ -254,7 +254,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
-
+
retval = mem_ap_write_u32(swjdp,
armv7a->debug_base + CPUDBG_DTRRX, value);
/* Move DTRRX to r0 */
@@ -331,7 +331,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
+
LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
/* Check that DCCRX is not full */
@@ -343,7 +343,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */
cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
}
-
+
if (Rd > 16)
return retval;
@@ -1237,7 +1237,7 @@ int cortex_a8_assert_reset(target_t *target)
armv4_5_invalidate_core_regs(target);
target->state = TARGET_RESET;
-
+
return ERROR_OK;
}
@@ -1444,7 +1444,7 @@ int cortex_a8_examine(struct target_s *target)
uint32_t didr, ctypr, ttypr, cpuid;
LOG_DEBUG("TODO");
-
+
/* Here we shall insert a proper ROM Table scan */
armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1521,7 +1521,7 @@ int cortex_a8_examine(struct target_s *target)
/* Configure core debug access */
cortex_a8_init_debug_access(target);
-
+
target->type->examined = 1;
return retval;