diff --git a/configure.in b/configure.in index fd2584bbf80bc40d95dd9f911aa22f81c5ab5297..00bdbcdc660b1c90164b6933d85b42f70cf1f3fb 100644 --- a/configure.in +++ b/configure.in @@ -5,6 +5,7 @@ AC_SEARCH_LIBS([ioperm], [ioperm]) AC_CANONICAL_HOST +AC_CHECK_HEADERS(jtag_minidriver.h) AC_CHECK_HEADERS(sys/param.h) AC_CHECK_HEADERS(elf.h) diff --git a/src/target/Makefile.am b/src/target/Makefile.am index f29091d1301bc24997df4e03e92ed1236f120435..64e12753c46374e0c01bd88d8a7b7527c43aed0c 100644 --- a/src/target/Makefile.am +++ b/src/target/Makefile.am @@ -22,6 +22,8 @@ noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7t nobase_dist_pkglib_DATA = xscale/debug_handler.bin event/at91eb40a_reset.script target/at91eb40a.cfg \ event/at91r40008_reset.script event/sam7s256_reset.script event/sam7x256_reset.script \ target/at91r40008.cfg target/lpc2148.cfg target/lpc2294.cfg target/sam7s256.cfg \ - target/sam7x256.cfg target/str710.cfg target/str912.cfg + target/sam7x256.cfg target/str710.cfg target/str912.cfg target/nslu2.cfg target/pxa255_sst.cfg \ + target/pxa255.cfg target/zy1000.cfg event/zy1000_reset.script event/at91sam9260_reset.script target/at91sam9260.cfg + diff --git a/src/target/event/at91sam9260_reset.script b/src/target/event/at91sam9260_reset.script new file mode 100644 index 0000000000000000000000000000000000000000..8390d72c51b371d08fe6ce5fb4028c3f1022318f --- /dev/null +++ b/src/target/event/at91sam9260_reset.script @@ -0,0 +1,58 @@ +mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset +mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog + +mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator +sleep 20 # wait 20 ms +mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator +sleep 10 # wait 10 ms +mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz +sleep 20 # wait 20 ms +mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler +sleep 10 # wait 10 ms +mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected +sleep 10 # wait 10 ms + +jtag_speed 0 # Increase JTAG Speed to 6 MHz +arm7_9 dcc_downloads enable # Enable faster DCC downloads + +mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit +mww 0xffffec04 0x09070806 # SMC_PULSE0 +mww 0xffffec08 0x000d000b # SMC_CYCLE0 +mww 0xffffec0c 0x00001003 # SMC_MODE0 + +flash probe 0 # Identify flash bank 0 + +mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31 +mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31 + +mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM + +#mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks) +mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks) + +mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command +mww 0x20000000 0 +mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command +mww 0x20000000 0 +mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x4 +mww 0x20000000 0 +mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command +mww 0x20000000 0 +mww 0xffffea00 0x0 # SDRAMC_MR : normal mode +mww 0x20000000 0 +mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us + diff --git a/src/target/event/zy1000_reset.script b/src/target/event/zy1000_reset.script new file mode 100644 index 0000000000000000000000000000000000000000..d48eb4022d97b4713910760339791ef7350e8f9f --- /dev/null +++ b/src/target/event/zy1000_reset.script @@ -0,0 +1,18 @@ +reg cpsr 0x000000D3 + +mww 0xFFE00000 0x0100273D +mww 0xFFE00004 0x08002125 +mww 0xFFEe0008 0x02002125 +mww 0xFFE0000c 0x03002125 +mww 0xFFE00010 0x40000000 +mww 0xFFE00014 0x50000000 +mww 0xFFE00018 0x60000000 +mww 0xFFE0001c 0x70000000 +mww 0xFFE00020 0x00000001 +mww 0xFFE00024 0x00000000 + +mww 0xFFFFF124 0xFFFFFFFF +mww 0xffff0010 0x100 +mww 0xffff0034 0x100 + + diff --git a/src/target/target/at91sam9260.cfg b/src/target/target/at91sam9260.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ca5c0e19e568050e5fb6c2f80082ac5ba50d9e2f --- /dev/null +++ b/src/target/target/at91sam9260.cfg @@ -0,0 +1,33 @@ +# Thanks to Pieter Conradie for this script! +# Target: Atmel AT91SAM9260 +###################################### + +reset_config trst_and_srst + +#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction> +jtag_device 4 0x1 0xf 0xe + +jtag_nsrst_delay 200 +jtag_ntrst_delay 0 + +###################### +# Target configuration +###################### + +#target <type> <endianess> <reset mode> <JTAG pos> <variant> +target arm926ejs little reset_init 0 arm926ejs + +target_script 0 reset event/at91sam9260_reset.script +run_and_halt_time 0 30 + +#working area <target#> <address> <size> <backup|nobackup> +working_area 0 0x00300000 0x1000 backup + + +##################### +# Flash configuration +##################### + +#flash bank cfi <base> <size> <chip width> <bus width> <target#> +flash bank cfi 0x10000000 0x01000000 2 2 0 + diff --git a/src/target/target/nslu2.cfg b/src/target/target/nslu2.cfg new file mode 100644 index 0000000000000000000000000000000000000000..ba6a7973af7d343e8e6ab439c53f0241bee05221 --- /dev/null +++ b/src/target/target/nslu2.cfg @@ -0,0 +1,22 @@ +# use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only + +# jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 7 0x1 0x7f 0x7e + +# target configuration +target xscale big reset_init 0 ixp42x +run_and_halt_time 0 30 + +# maps to PXA internal RAM. If you are using a PXA255 +# you must initialize SDRAM or leave this option off +working_area 0 0x00020000 0x10000 nobackup + +# flash bank <driver> <base> <size> <chip_width> <bus_width> +#flash bank cfi 0x50000000 0x1000000 2 4 0 + + + + + diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg new file mode 100644 index 0000000000000000000000000000000000000000..6666309d6bd70a7d9242d7983d35691db7c4e946 --- /dev/null +++ b/src/target/target/pxa255.cfg @@ -0,0 +1,86 @@ +jtag_device 5 0x1 0x1f 0x1e +jtag_nsrst_delay 200 +jtag_ntrst_delay 200 +target xscale little reset_init 0 pxa255 +reset_config trst_and_srst +run_and_halt_time 0 30 + +target_script 0 reset /ram/pxa255.init + +#xscale debug_handler 0 0xFFFF0800 # debug handler base address + +trunc /ram/pxa255.init +append /ram/pxa255.init #configuration file for PXA250 Evaluation Board +append /ram/pxa255.init # ----------------------------------------------------- +append /ram/pxa255.init # +append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access +append /ram/pxa255.init # +append /ram/pxa255.init # setup GPIO +append /ram/pxa255.init # +append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init +append /ram/pxa255.init +append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init +append /ram/pxa255.init # +append /ram/pxa255.init # setup memory controller +append /ram/pxa255.init # +append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1 +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init # +append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init +append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS +append /ram/pxa255.init sleep 20 +append /ram/pxa255.init diff --git a/src/target/target/pxa255_sst.cfg b/src/target/target/pxa255_sst.cfg new file mode 100644 index 0000000000000000000000000000000000000000..79522f2d2a3d6a529c5881d1c9c6338d682195ae --- /dev/null +++ b/src/target/target/pxa255_sst.cfg @@ -0,0 +1,13 @@ +# A PXA255 test board with SST 39LF400A flash +# +# At reset the memory map is as follows. Note that +# the memory map changes later on as the application +# starts... +# +# RAM at 0x40000000 +# Flash at 0x00000000 +# +script /target/pxa255.cfg +# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options] +flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe +working_area 0 0x4000000 0x4000 nobackup 0 diff --git a/src/target/target/zy1000.cfg b/src/target/target/zy1000.cfg new file mode 100644 index 0000000000000000000000000000000000000000..e6929f222fcbc7cf0e657d2cfcf09cbdd5885cf6 --- /dev/null +++ b/src/target/target/zy1000.cfg @@ -0,0 +1,30 @@ +#Script for ZY1000 + +#Atmel ties SRST & TRST together, at which point it makes +#no sense to use TRST, but use TMS instead. +# +#The annoying thing with tying SRST & TRST together is that +#there is no way to halt the CPU *before and during* the +#SRST reset, which means that the CPU will run a number +#of cycles before it can be halted(as much as milliseconds). +reset_config srst_only srst_pulls_trst + +#jtag scan chain +#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) +jtag_device 4 0x1 0xf 0xe + +#target configuration +#target arm7tdmi <endianness> <reset mode> <chainpos> <variant> +target arm7tdmi little reset_init 0 arm7tdmi-s_r4 + +# at CPU CLK <32kHz this must be disabled +arm7 fast_memory_access enable +arm7_9 dcc_downloads enable + + +flash bank ecosflash 0x01000000 0x200000 2 2 0 /rom/at91eb40a.elf +target_script 0 reset event/zy1000_reset.script + +# required for usable performance. Used for lots of +# other things than flash programming. +working_area 0 0x00000000 0x20000 nobackup