diff --git a/src/flash/Makefile.am b/src/flash/Makefile.am
index 0dd1e6a3fa8c9c9676813c8ab05e8bccfdf739c4..418a15c96d696058da0bd397fba33698ebef958f 100644
--- a/src/flash/Makefile.am
+++ b/src/flash/Makefile.am
@@ -4,6 +4,6 @@ METASOURCES = AUTO
noinst_LIBRARIES = libflash.a
libflash_a_SOURCES = flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c str7x.c str9x.c nand.c lpc3180_nand_controller.c \
stellaris.c str9xpec.c stm32x.c tms470.c ecos.c \
- s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c
+ s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c
noinst_HEADERS = flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h str7x.h str9x.h nand.h lpc3180_nand_controller.h \
stellaris.h str9xpec.h stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h
diff --git a/src/flash/flash.c b/src/flash/flash.c
index fda2c91a12e2a025b2a33ced2cbef4a5c47405c2..b9e5a9dc14c3a3ba8bd453f8c2fade76d1e5ce50 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -70,6 +70,7 @@ extern flash_driver_t stm32x_flash;
extern flash_driver_t tms470_flash;
extern flash_driver_t ecosflash_flash;
extern flash_driver_t lpc288x_flash;
+extern flash_driver_t ocl_flash;
flash_driver_t *flash_drivers[] =
{
@@ -84,6 +85,7 @@ flash_driver_t *flash_drivers[] =
&tms470_flash,
&ecosflash_flash,
&lpc288x_flash,
+ &ocl_flash,
NULL,
};
diff --git a/src/flash/ocl.c b/src/flash/ocl.c
new file mode 100644
index 0000000000000000000000000000000000000000..befa4e102ca79186a0bcfecd814eb36451d01a6b
--- /dev/null
+++ b/src/flash/ocl.c
@@ -0,0 +1,402 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "ocl.h"
+
+#include "flash.h"
+#include "target.h"
+#include "log.h"
+#include "binarybuffer.h"
+#include "types.h"
+#include "embeddedice.h"
+#include "arm7_9_common.h"
+
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+int ocl_register_commands(struct command_context_s *cmd_ctx);
+int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
+int ocl_erase(struct flash_bank_s *bank, int first, int last);
+int ocl_protect(struct flash_bank_s *bank, int set, int first, int last);
+int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+int ocl_probe(struct flash_bank_s *bank);
+int ocl_erase_check(struct flash_bank_s *bank);
+int ocl_protect_check(struct flash_bank_s *bank);
+int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size);
+int ocl_auto_probe(struct flash_bank_s *bank);
+
+flash_driver_t ocl_flash =
+{
+ .name = "ocl",
+ .register_commands = ocl_register_commands,
+ .flash_bank_command = ocl_flash_bank_command,
+ .erase = ocl_erase,
+ .protect = ocl_protect,
+ .write = ocl_write,
+ .probe = ocl_probe,
+ .erase_check = ocl_erase_check,
+ .protect_check = ocl_protect_check,
+ .info = ocl_info,
+ .auto_probe = ocl_auto_probe
+};
+
+
+typedef struct ocl_priv_s
+{
+ arm_jtag_t *jtag_info;
+ int buflen;
+ int bufalign;
+} ocl_priv_t;
+
+
+int ocl_register_commands(struct command_context_s *cmd_ctx)
+{
+ return ERROR_OK;
+}
+
+
+int ocl_erase_check(struct flash_bank_s *bank)
+{
+ return ERROR_OK;
+}
+
+
+int ocl_protect_check(struct flash_bank_s *bank)
+{
+ return ERROR_OK;
+}
+
+
+/* flash_bank ocl 0 0 0 0 <target#> */
+int ocl_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+{
+ int retval;
+ armv4_5_common_t *armv4_5;
+ arm7_9_common_t *arm7_9;
+ ocl_priv_t *ocl;
+
+ if (argc < 6)
+ {
+ LOG_WARNING("incomplete flash_bank ocl configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ if ((retval = arm7_9_get_arch_pointers(bank->target, &armv4_5, &arm7_9)) != ERROR_OK)
+ return retval;
+
+ ocl = bank->driver_priv = malloc(sizeof(ocl_priv_t));
+ ocl->jtag_info = &arm7_9->jtag_info;
+ ocl->buflen = 0;
+ ocl->bufalign = 1;
+
+ return ERROR_OK;
+}
+
+
+int ocl_erase(struct flash_bank_s *bank, int first, int last)
+{
+ ocl_priv_t *ocl = bank->driver_priv;
+ int retval;
+ u32 dcc_buffer[3];
+
+ /* check preconditions */
+ if (bank->num_sectors == 0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ if (bank->target->state != TARGET_RUNNING)
+ {
+ LOG_ERROR("target has to be running to communicate with the loader");
+ return ERROR_TARGET_NOT_RUNNING;
+ }
+
+ if ((first == 0) && (last == bank->num_sectors - 1))
+ {
+ dcc_buffer[0] = OCL_ERASE_ALL;
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+ }
+ else
+ {
+ dcc_buffer[0] = OCL_ERASE_BLOCK;
+ dcc_buffer[1] = first;
+ dcc_buffer[2] = last;
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 3) != ERROR_OK))
+ return retval;
+ }
+
+ /* wait for response, fixed timeout of 1 s */
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
+ {
+ if (retval == ERROR_TARGET_TIMEOUT)
+ LOG_ERROR("loader not responding");
+ return retval;
+ }
+
+ /* receive response */
+ if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer+1, 1) != ERROR_OK))
+ return retval;
+
+ if (dcc_buffer[1] != OCL_CMD_DONE)
+ {
+ if (dcc_buffer[0] == OCL_ERASE_ALL)
+ LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08lX", dcc_buffer[1]);
+ else
+ LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08lX", dcc_buffer[1]);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ return ERROR_OK;
+}
+
+
+int ocl_protect(struct flash_bank_s *bank, int set, int first, int last)
+{
+ return ERROR_OK;
+}
+
+
+int ocl_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+ ocl_priv_t *ocl = bank->driver_priv;
+ int retval;
+ u32 *dcc_buffer;
+ u32 *dcc_bufptr;
+ int byteofs;
+ int runlen;
+ u32 chksum;
+
+ int i;
+
+ /* check preconditions */
+ if (ocl->buflen == 0 || ocl->bufalign==0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ if (bank->target->state != TARGET_RUNNING)
+ {
+ LOG_ERROR("target has to be running to communicate with the loader");
+ return ERROR_TARGET_NOT_RUNNING;
+ }
+
+ /* allocate buffer for max. ocl buffer + overhead */
+ dcc_buffer = malloc(sizeof(u32)*(ocl->buflen/4+3));
+
+ while (count)
+ {
+ if (count + (offset % ocl->bufalign) > ocl->buflen)
+ runlen = ocl->buflen - (offset % ocl->bufalign);
+ else
+ runlen = count;
+
+ dcc_buffer[0] = OCL_FLASH_BLOCK | runlen;
+ dcc_buffer[1] = offset;
+ dcc_bufptr = &dcc_buffer[2];
+
+ *dcc_bufptr = 0xffffffff;
+ byteofs = (offset % ocl->bufalign) % 4;
+ chksum = OCL_CHKS_INIT;
+
+ /* copy data to DCC buffer in proper byte order and properly aligned */
+ for (i=0; i<runlen; i++)
+ {
+ switch (byteofs++)
+ {
+ case 0:
+ *dcc_bufptr &= *(buffer++) | 0xffffff00;
+ break;
+ case 1:
+ *dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;
+ break;
+ case 2:
+ *dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;
+ break;
+ case 3:
+ *dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;
+ chksum ^= *(dcc_bufptr++);
+ *dcc_bufptr = 0xffffffff;
+ byteofs = 0;
+ break;
+ }
+ }
+
+ /* add the remaining word to checksum */
+ if (byteofs)
+ chksum ^= *(dcc_bufptr++);
+
+ *(dcc_bufptr++) = chksum;
+
+ /* send the data */
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, dcc_bufptr-dcc_buffer)) != ERROR_OK)
+ {
+ free(dcc_buffer);
+ return retval;
+ }
+
+ /* wait for response, fixed timeout of 1 s */
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
+ {
+ if (retval == ERROR_TARGET_TIMEOUT)
+ LOG_ERROR("loader not responding");
+ free(dcc_buffer);
+ return retval;
+ }
+
+ /* receive response */
+ if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ {
+ free(dcc_buffer);
+ return retval;
+ }
+
+ if (dcc_buffer[0] != OCL_CMD_DONE)
+ {
+ LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08lX", dcc_buffer[0]);
+ free(dcc_buffer);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ count -= runlen;
+ offset += runlen;
+ }
+
+ free(dcc_buffer);
+ return ERROR_OK;
+}
+
+
+int ocl_probe(struct flash_bank_s *bank)
+{
+ ocl_priv_t *ocl = bank->driver_priv;
+ int retval;
+ u32 dcc_buffer[1];
+ int sectsize;
+ int i;
+
+ /* purge pending data in DCC */
+ embeddedice_receive(ocl->jtag_info, dcc_buffer, 1);
+
+ dcc_buffer[0] = OCL_PROBE;
+ if ((retval = embeddedice_send(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+
+ /* wait for response, fixed timeout of 1 s */
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 1000) != ERROR_OK))
+ {
+ if (retval == ERROR_TARGET_TIMEOUT)
+ LOG_ERROR("loader not responding");
+ return retval;
+ }
+
+ /* receive response */
+ if ((retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+
+ if (dcc_buffer[0] != OCL_CMD_DONE)
+ {
+ LOG_ERROR("loader response to OCL_PROBE 0x%08lX", dcc_buffer[0]);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* receive and fill in parameters, detection of loader is important, receive it one by one */
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+ bank->base = dcc_buffer[0];
+
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+ bank->size = dcc_buffer[0];
+
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+ bank->num_sectors = dcc_buffer[0];
+
+ if ((retval = embeddedice_handshake(ocl->jtag_info, EICE_COMM_CTRL_WBIT, 0) != ERROR_OK)
+ || (retval = embeddedice_receive(ocl->jtag_info, dcc_buffer, 1) != ERROR_OK))
+ return retval;
+ ocl->buflen = dcc_buffer[0] & 0xffff;
+ ocl->bufalign = dcc_buffer[0] >> 16;
+
+ bank->sectors = realloc(bank->sectors, sizeof(flash_sector_t)*bank->num_sectors);
+ if (bank->num_sectors == 0)
+ {
+ LOG_ERROR("number of sectors shall be non zero value");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+ if (bank->size % bank->num_sectors) {
+ LOG_ERROR("bank size not divisible by number of sectors");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+ sectsize = bank->size / bank->num_sectors;
+ for (i=0; i<bank->num_sectors; i++)
+ {
+ bank->sectors[i].offset = i * sectsize;
+ bank->sectors[i].size = sectsize;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = -1;
+ }
+
+ if (ocl->bufalign == 0)
+ ocl->bufalign = 1;
+
+ if (ocl->buflen == 0)
+ {
+ LOG_ERROR("buflen shall be non zero value");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ if ((ocl->bufalign > ocl->buflen) || (ocl->buflen % ocl->bufalign))
+ {
+ LOG_ERROR("buflen is not multiple of bufalign");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ if (ocl->buflen % 4)
+ {
+ LOG_ERROR("buflen shall be divisible by 4");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ return ERROR_OK;
+}
+
+
+int ocl_info(struct flash_bank_s *bank, char *buf, int buf_size)
+{
+ return ERROR_OK;
+}
+
+
+int ocl_auto_probe(struct flash_bank_s *bank)
+{
+ ocl_priv_t *ocl = bank->driver_priv;
+
+ if (ocl->buflen == 0 || ocl->bufalign==0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ return ERROR_OK;
+}
diff --git a/src/flash/ocl.h b/src/flash/ocl.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c677b0e012443fb919ac4adc033e8bb065f6d81
--- /dev/null
+++ b/src/flash/ocl.h
@@ -0,0 +1,40 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef OCL_H
+#define OCL_H
+
+/* command/response mask */
+#define OCL_CMD_MASK 0xFFFF0000L
+
+/* commads */
+#define OCL_FLASH_BLOCK 0x0CFB0000L
+#define OCL_ERASE_BLOCK 0x0CEB0000L
+#define OCL_ERASE_ALL 0x0CEA0000L
+#define OCL_PROBE 0x0CBE0000L
+
+/* responses */
+#define OCL_CMD_DONE 0x0ACD0000L
+#define OCL_CMD_ERR 0x0ACE0000L
+#define OCL_CHKS_FAIL 0x0ACF0000L
+#define OCL_BUFF_OVER 0x0AB00000L
+
+#define OCL_CHKS_INIT 0xC100CD0CL
+
+#endif /* OCL_H */
diff --git a/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script b/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script
new file mode 100644
index 0000000000000000000000000000000000000000..dbc40a0c6c4d571dfe35bf22f2715864fe37d960
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/at91sam7x_ocl_flash.script
@@ -0,0 +1,4 @@
+soft_reset_halt
+load_image at91sam7x_ocl.bin 0x200000
+resume 0x200000
+flash probe 0
diff --git a/src/flash/ocl/at91sam7x/at91sam7x_ram.ld b/src/flash/ocl/at91sam7x/at91sam7x_ram.ld
new file mode 100644
index 0000000000000000000000000000000000000000..106d2180437434ff02668dddfc00753de97194be
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/at91sam7x_ram.ld
@@ -0,0 +1,132 @@
+/****************************************************************************
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* SUCH DAMAGE.
+*
+****************************************************************************
+*
+* History:
+*
+* 30.03.06 mifi First Version
+****************************************************************************/
+
+
+ENTRY(ResetHandler)
+SEARCH_DIR(.)
+
+/*
+ * Define stack size here
+ */
+FIQ_STACK_SIZE = 0x0100;
+IRQ_STACK_SIZE = 0x0100;
+ABT_STACK_SIZE = 0x0100;
+UND_STACK_SIZE = 0x0100;
+SVC_STACK_SIZE = 0x0100;
+
+
+MEMORY
+{
+ ram : org = 0x00200000, len = 64k
+}
+
+/*
+ * Do not change the next code
+ */
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors);
+ . = ALIGN(4);
+ *(.init);
+ . = ALIGN(4);
+ *(.text);
+ . = ALIGN(4);
+ *(.rodata);
+ . = ALIGN(4);
+ *(.rodata*);
+ . = ALIGN(4);
+ *(.glue_7t);
+ . = ALIGN(4);
+ *(.glue_7);
+ . = ALIGN(4);
+ etext = .;
+ } > ram
+
+ .data :
+ {
+ PROVIDE (__data_start = .);
+ *(.data)
+ . = ALIGN(4);
+ edata = .;
+ _edata = .;
+ PROVIDE (__data_end = .);
+ } > ram
+
+ .bss :
+ {
+ PROVIDE (__bss_start = .);
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE (__bss_end = .);
+
+ . = ALIGN(256);
+
+ PROVIDE (__stack_start = .);
+
+ PROVIDE (__stack_fiq_start = .);
+ . += FIQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_fiq_end = .);
+
+ PROVIDE (__stack_irq_start = .);
+ . += IRQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_irq_end = .);
+
+ PROVIDE (__stack_abt_start = .);
+ . += ABT_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_abt_end = .);
+
+ PROVIDE (__stack_und_start = .);
+ . += UND_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_und_end = .);
+
+ PROVIDE (__stack_svc_start = .);
+ . += SVC_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_svc_end = .);
+ PROVIDE (__stack_end = .);
+ PROVIDE (__heap_start = .);
+ } > ram
+
+}
+/*** EOF ***/
+
diff --git a/src/flash/ocl/at91sam7x/crt.s b/src/flash/ocl/at91sam7x/crt.s
new file mode 100644
index 0000000000000000000000000000000000000000..9ea8a7fc86e3d36b6098f28cccb33d5f1e536b5c
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/crt.s
@@ -0,0 +1,225 @@
+/****************************************************************************
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* SUCH DAMAGE.
+*
+****************************************************************************
+*
+* History:
+*
+* 18.12.06 mifi First Version
+* The hardware initialization is based on the startup file
+* crtat91sam7x256_rom.S from NutOS 4.2.1.
+* Therefore partial copyright by egnite Software GmbH.
+****************************************************************************/
+
+/*
+ * Some defines for the program status registers
+ */
+ ARM_MODE_USER = 0x10 /* Normal User Mode */
+ ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
+ ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
+ ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
+ ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
+ ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
+ ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
+ ARM_MODE_MASK = 0x1F
+
+ I_BIT = 0x80 /* disable IRQ when I bit is set */
+ F_BIT = 0x40 /* disable IRQ when I bit is set */
+
+/*
+ * Register Base Address
+ */
+ AIC_BASE = 0xFFFFF000
+ AIC_EOICR_OFF = 0x130
+ AIC_IDCR_OFF = 0x124
+
+ RSTC_MR = 0xFFFFFD08
+ RSTC_KEY = 0xA5000000
+ RSTC_URSTEN = 0x00000001
+
+ WDT_BASE = 0xFFFFFD40
+ WDT_MR_OFF = 0x00000004
+ WDT_WDDIS = 0x00008000
+
+ MC_BASE = 0xFFFFFF00
+ MC_FMR_OFF = 0x00000060
+ MC_FWS_1FWS = 0x00480100
+
+ .section .vectors,"ax"
+ .code 32
+
+/****************************************************************************/
+/* Vector table and reset entry */
+/****************************************************************************/
+_vectors:
+ ldr pc, ResetAddr /* Reset */
+ ldr pc, UndefAddr /* Undefined instruction */
+ ldr pc, SWIAddr /* Software interrupt */
+ ldr pc, PAbortAddr /* Prefetch abort */
+ ldr pc, DAbortAddr /* Data abort */
+ ldr pc, ReservedAddr /* Reserved */
+ ldr pc, IRQAddr /* IRQ interrupt */
+ ldr pc, FIQAddr /* FIQ interrupt */
+
+
+ResetAddr: .word ResetHandler
+UndefAddr: .word UndefHandler
+SWIAddr: .word SWIHandler
+PAbortAddr: .word PAbortHandler
+DAbortAddr: .word DAbortHandler
+ReservedAddr: .word 0
+IRQAddr: .word IRQHandler
+FIQAddr: .word FIQHandler
+
+ .ltorg
+
+ .section .init, "ax"
+ .code 32
+
+ .global ResetHandler
+ .global ExitFunction
+ .extern main
+/****************************************************************************/
+/* Reset handler */
+/****************************************************************************/
+ResetHandler:
+ /*
+ * The watchdog is enabled after processor reset. Disable it.
+ */
+ ldr r1, =WDT_BASE
+ ldr r0, =WDT_WDDIS
+ str r0, [r1, #WDT_MR_OFF]
+
+
+ /*
+ * Enable user reset: assertion length programmed to 1ms
+ */
+ ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
+ ldr r1, =RSTC_MR
+ str r0, [r1, #0]
+
+
+ /*
+ * Use 2 cycles for flash access.
+ */
+ ldr r1, =MC_BASE
+ ldr r0, =MC_FWS_1FWS
+ str r0, [r1, #MC_FMR_OFF]
+
+
+ /*
+ * Disable all interrupts. Useful for debugging w/o target reset.
+ */
+ ldr r1, =AIC_BASE
+ mvn r0, #0
+ str r0, [r1, #AIC_EOICR_OFF]
+ str r0, [r1, #AIC_IDCR_OFF]
+
+
+ /*
+ * Setup a stack for each mode
+ */
+ msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
+ ldr sp, =__stack_und_end
+
+ msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
+ ldr sp, =__stack_abt_end
+
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
+ ldr sp, =__stack_fiq_end
+
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
+ ldr sp, =__stack_irq_end
+
+ msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
+ ldr sp, =__stack_svc_end
+
+
+ /*
+ * Clear .bss section
+ */
+ ldr r1, =__bss_start
+ ldr r2, =__bss_end
+ ldr r3, =0
+bss_clear_loop:
+ cmp r1, r2
+ strne r3, [r1], #+4
+ bne bss_clear_loop
+
+
+ /*
+ * Jump to main
+ */
+ mrs r0, cpsr
+ bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
+ msr cpsr, r0
+
+ mov r0, #0 /* No arguments */
+ mov r1, #0 /* No arguments */
+ ldr r2, =main
+ mov lr, pc
+ bx r2 /* And jump... */
+
+ExitFunction:
+ nop
+ nop
+ nop
+ b ExitFunction
+
+
+/****************************************************************************/
+/* Default interrupt handler */
+/****************************************************************************/
+
+UndefHandler:
+ b UndefHandler
+
+SWIHandler:
+ b SWIHandler
+
+PAbortHandler:
+ b PAbortHandler
+
+DAbortHandler:
+ b DAbortHandler
+
+IRQHandler:
+ b IRQHandler
+
+FIQHandler:
+ b FIQHandler
+
+ .weak ExitFunction
+ .weak UndefHandler, PAbortHandler, DAbortHandler
+ .weak IRQHandler, FIQHandler
+
+ .ltorg
+/*** EOF ***/
+
+
Index: src/flash/ocl/at91sam7x/dcc.c
diff --git a/src/flash/ocl/at91sam7x/dcc.c b/src/flash/ocl/at91sam7x/dcc.c
new file mode 100644
index 0000000000000000000000000000000000000000..2c35236961b3ff7e219e1f1b9277507ff6cb2612
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/dcc.c
@@ -0,0 +1,51 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#include "dcc.h"
+
+
+/* debug channel read (debugger->MCU) */
+uint32 dcc_rd(void)
+{
+ volatile uint32 dcc_reg;
+
+ do {
+ asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
+ } while ((dcc_reg&1)==0);
+
+ asm volatile ("mrc p14, 0, %0, C1, C0" : "=r" (dcc_reg) : );
+ return dcc_reg;
+}
+
+
+/* debug channel write (MCU->debugger) */
+int dcc_wr(uint32 data)
+{
+ volatile uint32 dcc_reg;
+
+ do {
+ asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) : );
+ /* operation controled by master, cancel operation
+ upon reception of data for immediate response */
+ if (dcc_reg&1) return -1;
+ } while (dcc_reg&2);
+
+ asm volatile ("mcr p14, 0, %0, C1, C0" : : "r" (data));
+ return 0;
+}
diff --git a/src/flash/ocl/at91sam7x/dcc.h b/src/flash/ocl/at91sam7x/dcc.h
new file mode 100644
index 0000000000000000000000000000000000000000..963df2610ac89a4c48b04d863a107d179681b41e
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/dcc.h
@@ -0,0 +1,31 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef dccH
+#define dccH
+
+#include "platform.h"
+
+/* debug channel read (debugger->MCU) */
+extern uint32 dcc_rd(void);
+
+/* debug channel write (MCU->debugger) */
+extern int dcc_wr(uint32 data);
+
+#endif
diff --git a/src/flash/ocl/at91sam7x/main.c b/src/flash/ocl/at91sam7x/main.c
new file mode 100644
index 0000000000000000000000000000000000000000..c9e93ddbdd503de0cdb97f715573a1b33f6ab503
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/main.c
@@ -0,0 +1,107 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#include "platform.h"
+
+#include "ocl.h"
+#include "dcc.h"
+#include "samflash.h"
+
+
+#define BUFSIZE 1024 /* words, i.e. 4 KiB */
+uint32 buffer[1024];
+
+void cmd_flash(uint32 cmd)
+{
+ unsigned int len;
+ uint32 adr;
+ uint32 chksum;
+ unsigned int bi; /* buffer index */
+ unsigned int bi_start; /* receive start mark */
+ unsigned int bi_end; /* receive end mark */
+ unsigned int ofs;
+ int pagenum;
+ int result;
+
+ adr=dcc_rd();
+ len=cmd&0xffff;
+ ofs=adr%flash_page_size;
+ bi_start=ofs/4;
+ bi_end=(ofs+len+3)/4;
+
+ if (bi_end>BUFSIZE) {
+ dcc_wr(OCL_BUFF_OVER);
+ return;
+ }
+
+ chksum=OCL_CHKS_INIT;
+ for (bi=0; bi<bi_end; bi++) chksum^=buffer[bi]=dcc_rd();
+
+ if (dcc_rd()!=chksum) {
+ dcc_wr(OCL_CHKS_FAIL);
+ return;
+ }
+
+ /* fill in unused positions with unprogrammed values */
+ for (bi=0; bi<bi_start; bi++) buffer[bi]=0xffffffff;
+ for (bi=bi_end; bi%flash_page_size; bi++) buffer[bi]=0xffffffff;
+
+ result=0;
+ pagenum=adr/flash_page_size;
+ for (bi=0; bi<bi_end; bi+=flash_page_size/4) {
+ result=flash_page_program(buffer+bi, pagenum++);
+ if (result) break;
+ }
+
+ /* verify written data */
+ if (!result) result=flash_verify(adr, len, ((uint8 *)buffer)+ofs);
+
+ dcc_wr(OCL_CMD_DONE|result);
+}
+
+
+int main (void)
+{
+ uint32 cmd;
+
+ for (;;) {
+ cmd=dcc_rd();
+ switch (cmd&OCL_CMD_MASK) {
+ case OCL_PROBE:
+ dcc_wr(OCL_CMD_DONE|flash_init());
+ dcc_wr(0x100000); /* base */
+ dcc_wr(flash_page_count*flash_page_size); /* size */
+ dcc_wr(1); /* num_sectors */
+ dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */
+ break;
+ case OCL_ERASE_ALL:
+ dcc_wr(OCL_CMD_DONE|flash_erase_all());
+ break;
+ case OCL_FLASH_BLOCK:
+ cmd_flash(cmd);
+ break;
+ default:
+ /* unknown command */
+ dcc_wr(OCL_CMD_ERR);
+ break;
+ }
+ }
+
+ return(0); /* we shall never get here, just to supress compiler warning */
+}
diff --git a/src/flash/ocl/at91sam7x/makefile b/src/flash/ocl/at91sam7x/makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b48ed70ca826305f15b5e5ecf04680dd126657a0
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/makefile
@@ -0,0 +1,130 @@
+##############################################################################################
+# Start of default section
+#
+
+TRGT = arm-elf-
+CC = $(TRGT)gcc
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+OBJDUMP = $(TRGT)objdump
+
+MCU = arm7tdmi
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################################
+
+##############################################################################################
+# Start of user section
+#
+
+# Define project name here
+PROJECT = at91sam7x_ocl
+
+# Define linker script file here
+LDSCRIPT= at91sam7x_ram.ld
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List C source files here
+SRC = main.c dcc.c samflash.c
+
+# List ASM source files here
+ASRC = crt.s
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+# Define optimisation level here
+OPT = -O2
+
+#
+# End of user defines
+##############################################################################################
+
+
+INCDIR = $(patsubst %,-I%,$(DINCDIR) $(UINCDIR))
+LIBDIR = $(patsubst %,-L%,$(DLIBDIR) $(ULIBDIR))
+DEFS = $(DDEFS) $(UDEFS)
+ADEFS = $(DADEFS) $(UADEFS)
+OBJS = $(ASRC:.s=.o) $(SRC:.c=.o)
+LIBS = $(DLIBS) $(ULIBS)
+MCFLAGS = -mcpu=$(MCU)
+
+ASFLAGS = $(MCFLAGS) -g -gdwarf-2 -Wa,-amhls=$(<:.s=.lst) $(ADEFS)
+CPFLAGS = $(MCFLAGS) $(OPT) -gdwarf-2 -mthumb-interwork -fomit-frame-pointer -Wall -Wstrict-prototypes -fverbose-asm -Wa,-ahlms=$(<:.c=.lst) $(DEFS)
+LDFLAGS = $(MCFLAGS) -nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map,--cref,--no-warn-mismatch $(LIBDIR)
+
+# Generate dependency information
+#CPFLAGS += -MD -MP -MF .dep/$(@F).d
+
+#
+# makefile rules
+#
+
+all: $(OBJS) $(PROJECT).elf $(PROJECT).hex $(PROJECT).bin $(PROJECT).lst
+
+%o : %c
+ $(CC) -c $(CPFLAGS) -I . $(INCDIR) $< -o $@
+
+%o : %s
+ $(AS) -c $(ASFLAGS) $< -o $@
+
+%elf: $(OBJS)
+ $(CC) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
+
+%hex: %elf
+ $(HEX) $< $@
+
+%bin: %elf
+ $(BIN) $< $@
+
+%.lst: %.elf
+ $(OBJDUMP) -h -S $< > $@
+
+clean:
+ -rm -f $(OBJS)
+ -rm -f $(PROJECT).elf
+ -rm -f $(PROJECT).map
+ -rm -f $(PROJECT).hex
+ -rm -f $(PROJECT).bin
+ -rm -f $(PROJECT).lst
+ -rm -f $(SRC:.c=.c.bak)
+ -rm -f $(SRC:.c=.lst)
+ -rm -f $(ASRC:.s=.s.bak)
+ -rm -f $(ASRC:.s=.lst)
+ -rm -fR .dep
+
+#
+# Include the dependency files, should be the last of the makefile
+#
+#-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)
+
+# *** EOF ***
\ No newline at end of file
diff --git a/src/flash/ocl/at91sam7x/ocl.h b/src/flash/ocl/at91sam7x/ocl.h
new file mode 100644
index 0000000000000000000000000000000000000000..8c677b0e012443fb919ac4adc033e8bb065f6d81
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/ocl.h
@@ -0,0 +1,40 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef OCL_H
+#define OCL_H
+
+/* command/response mask */
+#define OCL_CMD_MASK 0xFFFF0000L
+
+/* commads */
+#define OCL_FLASH_BLOCK 0x0CFB0000L
+#define OCL_ERASE_BLOCK 0x0CEB0000L
+#define OCL_ERASE_ALL 0x0CEA0000L
+#define OCL_PROBE 0x0CBE0000L
+
+/* responses */
+#define OCL_CMD_DONE 0x0ACD0000L
+#define OCL_CMD_ERR 0x0ACE0000L
+#define OCL_CHKS_FAIL 0x0ACF0000L
+#define OCL_BUFF_OVER 0x0AB00000L
+
+#define OCL_CHKS_INIT 0xC100CD0CL
+
+#endif /* OCL_H */
diff --git a/src/flash/ocl/at91sam7x/platform.h b/src/flash/ocl/at91sam7x/platform.h
new file mode 100644
index 0000000000000000000000000000000000000000..c73544af4c5fc2a81a7e17e09d85ae5957b8f32d
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/platform.h
@@ -0,0 +1,46 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef platformH
+#define platformH
+
+#include "samregs.h"
+
+
+#define outb(_reg, _val) (*((volatile unsigned char *)(_reg)) = (_val))
+#define outw(_reg, _val) (*((volatile unsigned short *)(_reg)) = (_val))
+#define outr(_reg, _val) (*((volatile unsigned int *)(_reg)) = (_val))
+
+#define inb(_reg) (*((volatile unsigned char *)(_reg)))
+#define inw(_reg) (*((volatile unsigned short *)(_reg)))
+#define inr(_reg) (*((volatile unsigned int *)(_reg)))
+
+#define _BV(bit) (1 << (bit))
+
+
+typedef signed char int8;
+typedef unsigned char uint8;
+
+typedef signed short int16;
+typedef unsigned short uint16;
+
+typedef signed int int32;
+typedef unsigned int uint32;
+
+#endif
diff --git a/src/flash/ocl/at91sam7x/samflash.c b/src/flash/ocl/at91sam7x/samflash.c
new file mode 100644
index 0000000000000000000000000000000000000000..253e410c22bac20d5f2038ebf5ab5c1ff659b382
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/samflash.c
@@ -0,0 +1,196 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#include "samflash.h"
+
+
+unsigned int flash_page_count=1024;
+unsigned int flash_page_size=256;
+
+/* pages per lock bit */
+unsigned int flash_lock_pages=1024/16;
+
+
+/* detect chip and set loader parameters */
+int flash_init(void)
+{
+ unsigned int nvpsiz;
+
+ nvpsiz=(inr(DBGU_CIDR)>>8)&0xf;
+
+ switch (nvpsiz) {
+ case 3:
+ /* AT91SAM7x32 */
+ flash_page_count=256;
+ flash_page_size=128;
+ flash_lock_pages=256/8;
+ break;
+ case 5:
+ /* AT91SAM7x64 */
+ flash_page_count=512;
+ flash_page_size=128;
+ flash_lock_pages=512/16;
+ break;
+ case 7:
+ /* AT91SAM7x128*/
+ flash_page_count=512;
+ flash_page_size=256;
+ flash_lock_pages=512/8;
+ break;
+ case 9:
+ /* AT91SAM7x256 */
+ flash_page_count=1024;
+ flash_page_size=256;
+ flash_lock_pages=1024/16;
+ break;
+ case 10:
+ /* AT91SAM7x512 */
+ flash_page_count=2048;
+ flash_page_size=256;
+ flash_lock_pages=2048/32;
+ break;
+ default:
+ return FLASH_STAT_INITE;
+ }
+ return FLASH_STAT_OK;
+}
+
+
+/* program single flash page */
+int flash_page_program(uint32 *data, int page_num)
+{
+ int i;
+ int efc_ofs;
+
+ uint32 *flash_ptr;
+ uint32 *data_ptr;
+
+ /* select proper controller */
+ if (page_num>=1024) efc_ofs=0x10;
+ else efc_ofs=0;
+
+ /* wait until FLASH is ready, just for sure */
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+
+ /* calculate page address, only lower 8 bits are used to address the latch,
+ but the upper part of address is needed for writing to proper EFC */
+ flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));
+ data_ptr=data;
+
+ /* copy data to latch */
+ for (i=flash_page_size/4; i; i--) {
+ /* we do not use memcpy to be sure that only 32 bit access is used */
+ *(flash_ptr++)=*(data_ptr++);
+ }
+
+ /* page number and page write command to FCR */
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);
+
+ /* wait until it's done */
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+
+ /* check for errors */
+ if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
+ if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
+
+#if 0
+ /* verify written data */
+ flash_ptr=(uint32 *)(FLASH_AREA_ADDR+(page_num*flash_page_size));
+ data_ptr=data;
+
+ for (i=flash_page_size/4; i; i--) {
+ if (*(flash_ptr++)!=*(data_ptr++)) return FLASH_STAT_VERIFE;
+ }
+#endif
+
+ return FLASH_STAT_OK;
+}
+
+
+int flash_erase_plane(int efc_ofs)
+{
+ unsigned int lockbits;
+ int page_num;
+
+ page_num=0;
+ lockbits=inr(MC_FSR+efc_ofs)>>16;
+ while (lockbits) {
+ if (lockbits&1) {
+
+ /* wait until FLASH is ready, just for sure */
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);
+
+ /* wait until it's done */
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+
+ /* check for errors */
+ if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
+ if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
+
+ }
+ if ((page_num+=flash_lock_pages)>flash_page_count) break;
+ lockbits>>=1;
+ }
+
+ /* wait until FLASH is ready, just for sure */
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+
+ /* erase all command to FCR */
+ outr(MC_FCR+efc_ofs, 0x5a000008);
+
+ /* wait until it's done */
+ while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
+
+ /* check for errors */
+ if ((inr(MC_FSR+efc_ofs)&MC_PROGE)) return FLASH_STAT_PROGE;
+ if ((inr(MC_FSR+efc_ofs)&MC_LOCKE)) return FLASH_STAT_LOCKE;
+
+ /* set no erase before programming */
+ outr(MC_FMR+efc_ofs, inr(MC_FMR+efc_ofs)|0x80);
+
+ return FLASH_STAT_OK;
+}
+
+
+/* erase whole chip */
+int flash_erase_all(void)
+{
+ int result;
+
+ if ((result=flash_erase_plane(0))!=FLASH_STAT_OK) return result;
+
+ /* the second flash controller, if any */
+ if (flash_page_count>1024) result=flash_erase_plane(0x10);
+
+ return result;
+}
+
+
+int flash_verify(uint32 adr, unsigned int len, uint8 *src)
+{
+ unsigned char *flash_ptr;
+
+ flash_ptr=(uint8 *)FLASH_AREA_ADDR+adr;
+ for ( ;len; len--) {
+ if (*(flash_ptr++)!=*(src++)) return FLASH_STAT_VERIFE;
+ }
+ return FLASH_STAT_OK;
+}
diff --git a/src/flash/ocl/at91sam7x/samflash.h b/src/flash/ocl/at91sam7x/samflash.h
new file mode 100644
index 0000000000000000000000000000000000000000..c793b9e8d37f44b2c997acdf2977c5836a34fb13
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/samflash.h
@@ -0,0 +1,48 @@
+/***************************************************************************
+ * Copyright (C) 2007 by Pavel Chromy *
+ * chromy@asix.cz *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef samflashH
+#define samflashH
+
+#include "platform.h"
+
+#define FLASH_AREA_ADDR 0x100000
+
+#define FLASH_STAT_OK 0
+#define FLASH_STAT_PROGE 1
+#define FLASH_STAT_LOCKE 2
+#define FLASH_STAT_VERIFE 3
+#define FLASH_STAT_INITE 4
+
+extern unsigned int flash_page_count;
+extern unsigned int flash_page_size; /* words */
+
+/* detect chip and set loader parameters */
+extern int flash_init(void);
+
+/* program single flash page */
+extern int flash_page_program(uint32 *data, int page_num);
+
+/* erase whole chip */
+extern int flash_erase_all(void);
+
+/* verify written data */
+extern int flash_verify(uint32 adr, unsigned int len, uint8 *src);
+
+#endif
diff --git a/src/flash/ocl/at91sam7x/samregs.h b/src/flash/ocl/at91sam7x/samregs.h
new file mode 100644
index 0000000000000000000000000000000000000000..7d3654fe529287ddc64196b81e8ec95dbb424800
--- /dev/null
+++ b/src/flash/ocl/at91sam7x/samregs.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the copyright holders nor the names of
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
+ * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+ * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * For additional information see http://www.ethernut.de/
+ */
+
+
+#ifndef samregsH
+#define samregsH
+
+
+/*
+ * Register definitions below copied from NutOS
+ */
+
+#define DBGU_BASE 0xFFFFF200 /*!< \brief DBGU base address. */
+
+#define DBGU_CIDR_OFF 0x00000040 /*!< \brief DBGU chip ID register offset. */
+#define DBGU_CIDR (DBGU_BASE + DBGU_CIDR_OFF) /*!< \brief DBGU chip ID register. */
+
+
+#define MC_BASE 0xFFFFFF00 /*!< \brief Memory controller base. */
+
+#define MC_FMR_OFF 0x00000060 /*!< \brief MC flash mode register offset. */
+#define MC_FMR (MC_BASE + MC_FMR_OFF) /*!< \brief MC flash mode register address. */
+#define MC_FRDY 0x00000001 /*!< \brief Flash ready. */
+#define MC_LOCKE 0x00000004 /*!< \brief Lock error. */
+#define MC_PROGE 0x00000008 /*!< \brief Programming error. */
+#define MC_NEBP 0x00000080 /*!< \brief No erase before programming. */
+#define MC_FWS_MASK 0x00000300 /*!< \brief Flash wait state mask. */
+#define MC_FWS_1R2W 0x00000000 /*!< \brief 1 cycle for read, 2 for write operations. */
+#define MC_FWS_2R3W 0x00000100 /*!< \brief 2 cycles for read, 3 for write operations. */
+#define MC_FWS_3R4W 0x00000200 /*!< \brief 3 cycles for read, 4 for write operations. */
+#define MC_FWS_4R4W 0x00000300 /*!< \brief 4 cycles for read and write operations. */
+#define MC_FMCN_MASK 0x00FF0000 /*!< \brief Flash microsecond cycle number mask. */
+
+#define MC_FCR_OFF 0x00000064 /*!< \brief MC flash command register offset. */
+#define MC_FCR (MC_BASE + MC_FCR_OFF) /*!< \brief MC flash command register address. */
+#define MC_FCMD_MASK 0x0000000F /*!< \brief Flash command mask. */
+#define MC_FCMD_NOP 0x00000000 /*!< \brief No command. */
+#define MC_FCMD_WP 0x00000001 /*!< \brief Write page. */
+#define MC_FCMD_SLB 0x00000002 /*!< \brief Set lock bit. */
+#define MC_FCMD_WPL 0x00000003 /*!< \brief Write page and lock. */
+#define MC_FCMD_CLB 0x00000004 /*!< \brief Clear lock bit. */
+#define MC_FCMD_EA 0x00000008 /*!< \brief Erase all. */
+#define MC_FCMD_SGPB 0x0000000B /*!< \brief Set general purpose NVM bit. */
+#define MC_FCMD_CGPB 0x0000000D /*!< \brief Clear general purpose NVM bit. */
+#define MC_FCMD_SSB 0x0000000F /*!< \brief Set security bit. */
+#define MC_PAGEN_MASK 0x0003FF00 /*!< \brief Page number mask. */
+#define MC_KEY 0x5A000000 /*!< \brief Writing protect key. */
+
+#define MC_FSR_OFF 0x00000068 /*!< \brief MC flash status register offset. */
+#define MC_FSR (MC_BASE + MC_FSR_OFF) /*!< \brief MC flash status register address. */
+#define MC_SECURITY 0x00000010 /*!< \brief Security bit status. */
+
+
+#endif
diff --git a/src/target/target.h b/src/target/target.h
index fd09df79240fb56a198ae990feeef7274f542ad6..dd70170dd62f4dc49e44d4e6bcfb55d2bb793a28 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -331,5 +331,6 @@ int target_arch_state(struct target_s *target);
#define ERROR_TARGET_DATA_ABORT (-307)
#define ERROR_TARGET_RESOURCE_NOT_AVAILABLE (-308)
#define ERROR_TARGET_TRANSLATION_FAULT (-309)
+#define ERROR_TARGET_NOT_RUNNING (-310)
#endif /* TARGET_H */