From 95c3a1758f78b739aef176d73b376321e5b48b8d Mon Sep 17 00:00:00 2001 From: oharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60> Date: Sun, 2 Nov 2008 18:50:26 +0000 Subject: [PATCH] Rick Altherr <kc8apf@kc8apf.net> - In cortex_m3_resume if debug_execution is non-zero, the PRIMASK and xSPR are modified. The problem is that while the register value is changed, it isn't marked valid or dirty. git-svn-id: svn://svn.berlios.de/openocd/trunk@1119 b42882b7-edfa-0310-969c-e2dbd0fdcd60 --- src/target/cortex_m3.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c index ee9ee2577..d97d912cf 100644 --- a/src/target/cortex_m3.c +++ b/src/target/cortex_m3.c @@ -567,9 +567,14 @@ int cortex_m3_resume(struct target_s *target, int current, u32 address, int hand * This is probably the same inssue as Cortex-M3 Errata 377493: * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; + /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24)); + armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } /* current = 1: continue on current pc, otherwise continue at <address> */ -- GitLab