diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 3275584f9007bfc9b1c411e1f791b90fa19cc336..45394b7e028d3a507a3c6ec4d5fd8a1530b1b5ed 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1391,9 +1391,6 @@ int arm7_9_debug_entry(target_t *target)
LOG_DEBUG("-");
#endif
- if (arm7_9->pre_debug_entry)
- arm7_9->pre_debug_entry(target);
-
/* program EmbeddedICE Debug Control Register to assert DBGACK and INTDIS
* ensure that DBGRQ is cleared
*/
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index b3c3c583366ede154533feb05ba825dbe83d4462..80f8fc74807d10812fed7e4b22dddc8d58b96cec 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -102,7 +102,6 @@ typedef struct arm7_9_common_s
void (*set_special_dbgrq)(target_t *target); /**< Function for setting DBGRQ if the normal way won't work */
- void (*pre_debug_entry)(target_t *target); /**< Callback function called before entering debug mode */
void (*post_debug_entry)(target_t *target); /**< Callback function called after entering debug mode */
void (*pre_restore_context)(target_t *target); /**< Callback function called before restoring the processor context */
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 0e978c24d8810998a1a929c2149344635e122bf0..253bdf08353b7e56abfca57477c64bcdcf6d4e64 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -801,7 +801,6 @@ int arm7tdmi_init_arch_info(target_t *target, arm7tdmi_common_t *arm7tdmi, jtag_
arm7_9->enable_single_step = arm7_9_enable_eice_step;
arm7_9->disable_single_step = arm7_9_disable_eice_step;
- arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL;
arm7_9->pre_restore_context = NULL;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 9c90f002d8ea52ba165ee1fe43b748408e6eeb7a..ac233f6631401a68706550d7e65823085e293361 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -902,7 +902,6 @@ int arm9tdmi_init_arch_info(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_
arm7_9->enable_single_step = arm9tdmi_enable_single_step;
arm7_9->disable_single_step = arm9tdmi_disable_single_step;
- arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL;
arm7_9->pre_restore_context = NULL;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 5814c13decf2e4f184b4f1df3f26d8b89b2ebd03..c5e3257be2f60ad933afd14367a28f0529870c40 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -120,7 +120,6 @@ typedef struct armv7a_common_s
uint32_t CRn, uint32_t CRm, uint32_t value);
int (*examine_debug_reason)(target_t *target);
- void (*pre_debug_entry)(target_t *target);
void (*post_debug_entry)(target_t *target);
void (*pre_restore_context)(target_t *target);
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index f3a74221ce9d3ea06bba73b5a680efbaa218b2ef..2ee92f43bdf666237b7cfca58933ae99b7d4cb6e 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -108,7 +108,6 @@ typedef struct armv7m_common_s
int (*write_core_reg)(struct target_s *target, int num);
int (*examine_debug_reason)(target_t *target);
- void (*pre_debug_entry)(target_t *target);
void (*post_debug_entry)(target_t *target);
void (*pre_restore_context)(target_t *target);
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 025a468a86e610375d1ac9a2b145b267d30cd23f..e716999063748cee01c69bb728287d36f4c5180a 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -637,9 +637,6 @@ int cortex_a8_debug_entry(target_t *target)
cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
- if (armv7a->pre_debug_entry)
- armv7a->pre_debug_entry(target);
-
LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* Enable the ITR execution once we are in debug mode */
@@ -1586,7 +1583,6 @@ LOG_DEBUG(" ");
/* register arch-specific functions */
armv7a->examine_debug_reason = NULL;
- armv7a->pre_debug_entry = NULL;
armv7a->post_debug_entry = cortex_a8_post_debug_entry;
armv7a->pre_restore_context = NULL;
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 1c59f028a29ed76bde858a7b3ad4f81b548d865a..e854f6b6560c174dff1aa227e5f7c9f0e3bc3ff2 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -322,8 +322,6 @@ static int cortex_m3_debug_entry(target_t *target)
swjdp_common_t *swjdp = &armv7m->swjdp_info;
LOG_DEBUG(" ");
- if (armv7m->pre_debug_entry)
- armv7m->pre_debug_entry(target);
cortex_m3_clear_halt(target);
mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -1610,7 +1608,6 @@ static int cortex_m3_init_arch_info(target_t *target,
/* register arch-specific functions */
armv7m->examine_debug_reason = cortex_m3_examine_debug_reason;
- armv7m->pre_debug_entry = NULL;
armv7m->post_debug_entry = NULL;
armv7m->pre_restore_context = NULL;
diff --git a/src/target/fa526.c b/src/target/fa526.c
index eee9e50b9a15901246bc449fa0cc42233aff798c..9cdbf3d4344e204f5e11b9dd064cf9c04b8a1f2d 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -346,7 +346,6 @@ int fa526_init_arch_info_2(target_t *target, arm9tdmi_common_t *arm9tdmi, jtag_t
arm7_9->enable_single_step = arm9tdmi_enable_single_step;
arm7_9->disable_single_step = arm9tdmi_disable_single_step;
- arm7_9->pre_debug_entry = NULL;
arm7_9->post_debug_entry = NULL;
arm7_9->pre_restore_context = NULL;