diff --git a/src/flash/at91sam7.c b/src/flash/at91sam7.c
index 55afb6bf4d92888e0cba52e764bff76ef4d10bef..27779a39a58ef8e2379b4a5767a2231c79d0636e 100644
--- a/src/flash/at91sam7.c
+++ b/src/flash/at91sam7.c
@@ -280,7 +280,7 @@ static int at91sam7_flash_command(struct flash_bank_s *bank, uint8_t cmd, uint16
at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
target_t *target = bank->target;
- fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
+ fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
diff --git a/src/flash/cfi.c b/src/flash/cfi.c
index 774424e097c390dbbf0285fc19c899ee3fc2a30a..4cd5f4dc9eccef2e6a0836d4b5d722a391638114 100644
--- a/src/flash/cfi.c
+++ b/src/flash/cfi.c
@@ -2266,7 +2266,7 @@ static int cfi_probe(struct flash_bank_s *bank)
(1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
(1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
- cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
+ cfi_info->dev_size = 1 << cfi_query_u8(bank, 0, 0x27);
cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
diff --git a/src/flash/non_cfi.c b/src/flash/non_cfi.c
index 3e86e0da30ed80cd9d639d906eb81c7793f2b607..47313672e247945f8c99b392b0f67f05eb77ce01 100644
--- a/src/flash/non_cfi.c
+++ b/src/flash/non_cfi.c
@@ -29,7 +29,7 @@
#define KB 1024
#define MB (1024*1024)
-#define ERASE_REGION(num, size) (((size/256)<<16)|(num-1))
+#define ERASE_REGION(num, size) (((size/256) << 16)|(num-1))
/* non-CFI compatible flashes */
non_cfi_t non_cfi_flashes[] = {
diff --git a/src/flash/ocl.c b/src/flash/ocl.c
index 9997bc0bc458352d12b7993a753dcb926e38505f..a83f5ea838378dcce9171f7b823a4e36cafd02b3 100644
--- a/src/flash/ocl.c
+++ b/src/flash/ocl.c
@@ -208,13 +208,13 @@ static int ocl_write(struct flash_bank_s *bank, uint8_t *buffer, uint32_t offset
*dcc_bufptr &= *(buffer++) | 0xffffff00;
break;
case 1:
- *dcc_bufptr &= ((*(buffer++))<<8) | 0xffff00ff;
+ *dcc_bufptr &= ((*(buffer++)) << 8) | 0xffff00ff;
break;
case 2:
- *dcc_bufptr &= ((*(buffer++))<<16) | 0xff00ffff;
+ *dcc_bufptr &= ((*(buffer++)) << 16) | 0xff00ffff;
break;
case 3:
- *dcc_bufptr &= ((*(buffer++))<<24) | 0x00ffffff;
+ *dcc_bufptr &= ((*(buffer++)) << 24) | 0x00ffffff;
chksum ^= *(dcc_bufptr++);
*dcc_bufptr = 0xffffffff;
byteofs = 0;
diff --git a/src/flash/ocl/at91sam7x/main.c b/src/flash/ocl/at91sam7x/main.c
index 6ecbf35a83aacaf9b415f60954e3c569876c398d..b49a5b894a162869f34fa34855131f027d1feab2 100644
--- a/src/flash/ocl/at91sam7x/main.c
+++ b/src/flash/ocl/at91sam7x/main.c
@@ -88,7 +88,7 @@ int main (void)
dcc_wr(0x100000); /* base */
dcc_wr(flash_page_count*flash_page_size); /* size */
dcc_wr(1); /* num_sectors */
- dcc_wr(4096 | ((unsigned long) flash_page_size<<16)); /* buflen and bufalign */
+ dcc_wr(4096 | ((unsigned long) flash_page_size << 16)); /* buflen and bufalign */
break;
case OCL_ERASE_ALL:
dcc_wr(OCL_CMD_DONE|flash_erase_all());
diff --git a/src/flash/ocl/at91sam7x/samflash.c b/src/flash/ocl/at91sam7x/samflash.c
index b5255191fa86f94320e9902e41c04c9f740b8a89..893b579f422b8e27d7b23422d440f78ea78b13c8 100644
--- a/src/flash/ocl/at91sam7x/samflash.c
+++ b/src/flash/ocl/at91sam7x/samflash.c
@@ -100,7 +100,7 @@ int flash_page_program(uint32 *data, int page_num)
}
/* page number and page write command to FCR */
- outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | MC_KEY | MC_FCMD_WP);
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | MC_KEY | MC_FCMD_WP);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
@@ -136,7 +136,7 @@ int flash_erase_plane(int efc_ofs)
/* wait until FLASH is ready, just for sure */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
- outr(MC_FCR+efc_ofs, ((page_num&0x3ff)<<8) | 0x5a000004);
+ outr(MC_FCR+efc_ofs, ((page_num&0x3ff) << 8) | 0x5a000004);
/* wait until it's done */
while ((inr(MC_FSR+efc_ofs)&MC_FRDY)==0);
diff --git a/src/flash/pic32mx.c b/src/flash/pic32mx.c
index dd24a7dc46c9dc000edb7b6cc392d227c3b28b21..7009995aa737f7e51ce632bb72c19e9462050d40 100644
--- a/src/flash/pic32mx.c
+++ b/src/flash/pic32mx.c
@@ -194,11 +194,11 @@ static int pic32mx_protect_check(struct flash_bank_s *bank)
}
target_read_u32(target, PIC32MX_DEVCFG0, &devcfg0);
- if ((devcfg0 & (1<<28)) == 0) /* code protect bit */
+ if ((devcfg0 & (1 << 28)) == 0) /* code protect bit */
num_pages = 0xffff; /* All pages protected */
else if (bank->base == PIC32MX_KSEG1_BOOT_FLASH)
{
- if (devcfg0 & (1<<24))
+ if (devcfg0 & (1 << 24))
num_pages = 0; /* All pages unprotected */
else
num_pages = 0xffff; /* All pages protected */
diff --git a/src/flash/pic32mx.h b/src/flash/pic32mx.h
index 49c8f5fa69baf19f836a43fe133e7afe80a94510..49a9bb40dc9e724432722e59b894c95ff6d2f2fd 100644
--- a/src/flash/pic32mx.h
+++ b/src/flash/pic32mx.h
@@ -80,11 +80,11 @@ typedef struct pic32mx_flash_bank_s
#define PIC32MX_NVMCONCLR 0xBF80F404
#define PIC32MX_NVMCONSET 0xBF80F408
#define PIC32MX_NVMCONINV 0xBF80F40C
-#define NVMCON_NVMWR (1<<15)
-#define NVMCON_NVMWREN (1<<14)
-#define NVMCON_NVMERR (1<<13)
-#define NVMCON_LVDERR (1<<12)
-#define NVMCON_LVDSTAT (1<<11)
+#define NVMCON_NVMWR (1 << 15)
+#define NVMCON_NVMWREN (1 << 14)
+#define NVMCON_NVMERR (1 << 13)
+#define NVMCON_LVDERR (1 << 12)
+#define NVMCON_LVDSTAT (1 << 11)
#define NVMCON_OP_PFM_ERASE 0x5
#define NVMCON_OP_PAGE_ERASE 0x4
#define NVMCON_OP_ROW_PROG 0x3
diff --git a/src/flash/s3c24xx_regs_nand.h b/src/flash/s3c24xx_regs_nand.h
index 31d9a856e80c186ccd49a1ee37ec1694ea176f41..c8cbe78947028a8b7580032232ac2a85cd681b71 100644
--- a/src/flash/s3c24xx_regs_nand.h
+++ b/src/flash/s3c24xx_regs_nand.h
@@ -59,63 +59,63 @@
#define S3C2412_NFMECC1 S3C2410_NFREG(0x38)
#define S3C2412_NFSECC S3C2410_NFREG(0x3C)
-#define S3C2410_NFCONF_EN (1<<15)
-#define S3C2410_NFCONF_512BYTE (1<<14)
-#define S3C2410_NFCONF_4STEP (1<<13)
-#define S3C2410_NFCONF_INITECC (1<<12)
-#define S3C2410_NFCONF_nFCE (1<<11)
-#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8 (0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16 (1<<0)
-#define S3C2440_NFCONF_ADVFLASH (1<<3)
-#define S3C2440_NFCONF_TACLS(x) ((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x) ((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x) ((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT (1<<13)
-#define S3C2440_NFCONT_SOFTLOCK (1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN (1<<10)
-#define S3C2440_NFCONT_RNBINT_EN (1<<9)
-#define S3C2440_NFCONT_RN_FALLING (1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK (1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK (1<<5)
-#define S3C2440_NFCONT_INITECC (1<<4)
-#define S3C2440_NFCONT_nFCE (1<<1)
-#define S3C2440_NFCONT_ENABLE (1<<0)
-
-#define S3C2440_NFSTAT_READY (1<<0)
-#define S3C2440_NFSTAT_nCE (1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE (1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT (1<<31)
-#define S3C2412_NFCONF_ECCCLKCON (1<<30)
-#define S3C2412_NFCONF_ECC_MLC (1<<24)
-#define S3C2412_NFCONF_TACLS_MASK (7<<12) /* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR (1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT (1<<17)
-#define S3C2412_NFCONT_SOFTLOCK (1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT (1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT (1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK (1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC (1<<5)
-#define S3C2412_NFCONT_nFCE1 (1<<2)
-#define S3C2412_NFCONT_nFCE0 (1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE (1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE (1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE (1<<4)
-#define S3C2412_NFSTAT_nFCE1 (1<<3)
-#define S3C2412_NFSTAT_nFCE0 (1<<2)
-#define S3C2412_NFSTAT_Res1 (1<<1)
-#define S3C2412_NFSTAT_READY (1<<0)
+#define S3C2410_NFCONF_EN (1 << 15)
+#define S3C2410_NFCONF_512BYTE (1 << 14)
+#define S3C2410_NFCONF_4STEP (1 << 13)
+#define S3C2410_NFCONF_INITECC (1 << 12)
+#define S3C2410_NFCONF_nFCE (1 << 11)
+#define S3C2410_NFCONF_TACLS(x) ((x) << 8)
+#define S3C2410_NFCONF_TWRPH0(x) ((x) << 4)
+#define S3C2410_NFCONF_TWRPH1(x) ((x) << 0)
+
+#define S3C2410_NFSTAT_BUSY (1 << 0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8 (0 << 0)
+#define S3C2440_NFCONF_BUSWIDTH_16 (1 << 0)
+#define S3C2440_NFCONF_ADVFLASH (1 << 3)
+#define S3C2440_NFCONF_TACLS(x) ((x) << 12)
+#define S3C2440_NFCONF_TWRPH0(x) ((x) << 8)
+#define S3C2440_NFCONF_TWRPH1(x) ((x) << 4)
+
+#define S3C2440_NFCONT_LOCKTIGHT (1 << 13)
+#define S3C2440_NFCONT_SOFTLOCK (1 << 12)
+#define S3C2440_NFCONT_ILLEGALACC_EN (1 << 10)
+#define S3C2440_NFCONT_RNBINT_EN (1 << 9)
+#define S3C2440_NFCONT_RN_FALLING (1 << 8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK (1 << 6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK (1 << 5)
+#define S3C2440_NFCONT_INITECC (1 << 4)
+#define S3C2440_NFCONT_nFCE (1 << 1)
+#define S3C2440_NFCONT_ENABLE (1 << 0)
+
+#define S3C2440_NFSTAT_READY (1 << 0)
+#define S3C2440_NFSTAT_nCE (1 << 1)
+#define S3C2440_NFSTAT_RnB_CHANGE (1 << 2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS (1 << 3)
+
+#define S3C2412_NFCONF_NANDBOOT (1 << 31)
+#define S3C2412_NFCONF_ECCCLKCON (1 << 30)
+#define S3C2412_NFCONF_ECC_MLC (1 << 24)
+#define S3C2412_NFCONF_TACLS_MASK (7 << 12) /* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR (1 << 18)
+#define S3C2412_NFCONT_LOCKTIGHT (1 << 17)
+#define S3C2412_NFCONT_SOFTLOCK (1 << 16)
+#define S3C2412_NFCONT_ECC4_ENCINT (1 << 13)
+#define S3C2412_NFCONT_ECC4_DECINT (1 << 12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK (1 << 7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC (1 << 5)
+#define S3C2412_NFCONT_nFCE1 (1 << 2)
+#define S3C2412_NFCONT_nFCE0 (1 << 1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE (1 << 7)
+#define S3C2412_NFSTAT_ECC_DECDONE (1 << 6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS (1 << 5)
+#define S3C2412_NFSTAT_RnB_CHANGE (1 << 4)
+#define S3C2412_NFSTAT_nFCE1 (1 << 3)
+#define S3C2412_NFSTAT_nFCE0 (1 << 2)
+#define S3C2412_NFSTAT_Res1 (1 << 1)
+#define S3C2412_NFSTAT_READY (1 << 0)
#define S3C2412_NFECCERR_SERRDATA(x) (((x) >> 21) & 0xf)
#define S3C2412_NFECCERR_SERRBIT(x) (((x) >> 18) & 0x7)
diff --git a/src/flash/stellaris.c b/src/flash/stellaris.c
index 8f5f03a094e4185d053eff83c488f264e0cf8276..09d7f0dd16bb8d2015770fb0c6de4a9b301283c6 100644
--- a/src/flash/stellaris.c
+++ b/src/flash/stellaris.c
@@ -665,9 +665,9 @@ static int stellaris_protect(struct flash_bank_s *bank, int set, int first, int
for (lockregion = first; lockregion <= last; lockregion++)
{
if (set)
- fmppe &= ~(1<<lockregion);
+ fmppe &= ~(1 << lockregion);
else
- fmppe |= (1<<lockregion);
+ fmppe |= (1 << lockregion);
}
/* Clear and disable flash programming interrupts */
diff --git a/src/flash/stellaris.h b/src/flash/stellaris.h
index f2d376055ce2a6e05a496af67a2c08e68538e4c8..18fd3f241500f407b3e9da17c010e2d30c09c975 100644
--- a/src/flash/stellaris.h
+++ b/src/flash/stellaris.h
@@ -82,11 +82,11 @@ typedef struct stellaris_flash_bank_s
#define PMASK 2
/* Flash Controller Command bits */
-#define FMC_WRKEY (0xA442<<16)
-#define FMC_COMT (1<<3)
-#define FMC_MERASE (1<<2)
-#define FMC_ERASE (1<<1)
-#define FMC_WRITE (1<<0)
+#define FMC_WRKEY (0xA442 << 16)
+#define FMC_COMT (1 << 3)
+#define FMC_MERASE (1 << 2)
+#define FMC_ERASE (1 << 1)
+#define FMC_WRITE (1 << 0)
/* STELLARIS constants */
diff --git a/src/flash/stm32x.c b/src/flash/stm32x.c
index 431d3b02c29d6b9dd985e15558360b7b7e84daf9..cc69dd161848cd162ece3e4b4bb600bd83217bf7 100644
--- a/src/flash/stm32x.c
+++ b/src/flash/stm32x.c
@@ -1121,29 +1121,29 @@ static int stm32x_handle_options_write_command(struct command_context_s *cmd_ctx
if (strcmp(args[1], "SWWDG") == 0)
{
- optionbyte |= (1<<0);
+ optionbyte |= (1 << 0);
}
else
{
- optionbyte &= ~(1<<0);
+ optionbyte &= ~(1 << 0);
}
if (strcmp(args[2], "NORSTSTNDBY") == 0)
{
- optionbyte |= (1<<1);
+ optionbyte |= (1 << 1);
}
else
{
- optionbyte &= ~(1<<1);
+ optionbyte &= ~(1 << 1);
}
if (strcmp(args[3], "NORSTSTOP") == 0)
{
- optionbyte |= (1<<2);
+ optionbyte |= (1 << 2);
}
else
{
- optionbyte &= ~(1<<2);
+ optionbyte &= ~(1 << 2);
}
if (stm32x_erase_options(bank) != ERROR_OK)
diff --git a/src/flash/stm32x.h b/src/flash/stm32x.h
index 1b4c2d7d6c1c63d776e8aa1eaaffde04ed13b18a..511146678ce2f8f703dbc736a726509eb086a037 100644
--- a/src/flash/stm32x.h
+++ b/src/flash/stm32x.h
@@ -64,21 +64,21 @@ typedef struct stm32x_flash_bank_s
/* FLASH_CR register bits */
-#define FLASH_PG (1<<0)
-#define FLASH_PER (1<<1)
-#define FLASH_MER (1<<2)
-#define FLASH_OPTPG (1<<4)
-#define FLASH_OPTER (1<<5)
-#define FLASH_STRT (1<<6)
-#define FLASH_LOCK (1<<7)
-#define FLASH_OPTWRE (1<<9)
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER (1 << 2)
+#define FLASH_OPTPG (1 << 4)
+#define FLASH_OPTER (1 << 5)
+#define FLASH_STRT (1 << 6)
+#define FLASH_LOCK (1 << 7)
+#define FLASH_OPTWRE (1 << 9)
/* FLASH_SR register bits */
-#define FLASH_BSY (1<<0)
-#define FLASH_PGERR (1<<2)
-#define FLASH_WRPRTERR (1<<4)
-#define FLASH_EOP (1<<5)
+#define FLASH_BSY (1 << 0)
+#define FLASH_PGERR (1 << 2)
+#define FLASH_WRPRTERR (1 << 4)
+#define FLASH_EOP (1 << 5)
/* STM32_FLASH_OBR bit definitions (reading) */
diff --git a/src/flash/str7x.c b/src/flash/str7x.c
index 13b22be54f1f222861bc70ec6086fc3f487bfe7e..4068ad330bbf2b1e3233492a606e3b6d5198c8fb 100644
--- a/src/flash/str7x.c
+++ b/src/flash/str7x.c
@@ -161,7 +161,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
/* set default bits for str71x flash */
str7x_info->busy_bits = (FLASH_LOCK|FLASH_BSYA1|FLASH_BSYA0);
- str7x_info->disable_bit = (1<<1);
+ str7x_info->disable_bit = (1 << 1);
if (strcmp(args[6], "STR71x") == 0)
{
@@ -175,7 +175,7 @@ static int str7x_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd
else if (strcmp(args[6], "STR75x") == 0)
{
str7x_info->register_base = 0x20100000;
- str7x_info->disable_bit = (1<<0);
+ str7x_info->disable_bit = (1 << 0);
}
else
{
@@ -703,7 +703,7 @@ static int str7x_handle_disable_jtag_command(struct command_context_s *cmd_ctx,
flash_cmd = FLASH_SPR;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_AR), 0x4010DFBC);
- target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1<<(15+ProtectionLevel)));
+ target_write_u32(target, str7x_get_flash_adr(bank, FLASH_DR0), ~(1 << (15+ProtectionLevel)));
flash_cmd = FLASH_SPR | FLASH_WMS;
target_write_u32(target, str7x_get_flash_adr(bank, FLASH_CR0), flash_cmd);
}
diff --git a/src/flash/str9x.c b/src/flash/str9x.c
index 19c0f1eff9cc98ae5208ed440edec05cfa8f8262..2b92d0095c6e1db6a6f66889f86195d147332432 100644
--- a/src/flash/str9x.c
+++ b/src/flash/str9x.c
@@ -132,7 +132,7 @@ static int str9x_build_block_list(struct flash_bank_s *bank)
offset += bank->sectors[i].size;
bank->sectors[num_sectors].is_erased = -1;
bank->sectors[num_sectors].is_protected = 1;
- str9x_info->sector_bits[num_sectors++] = (1<<i);
+ str9x_info->sector_bits[num_sectors++] = (1 << i);
}
for (i = 0; i < b1_sectors; i++)
@@ -143,9 +143,9 @@ static int str9x_build_block_list(struct flash_bank_s *bank)
bank->sectors[num_sectors].is_erased = -1;
bank->sectors[num_sectors].is_protected = 1;
if (str9x_info->variant)
- str9x_info->sector_bits[num_sectors++] = (1<<i);
+ str9x_info->sector_bits[num_sectors++] = (1 << i);
else
- str9x_info->sector_bits[num_sectors++] = (1<<(i+8));
+ str9x_info->sector_bits[num_sectors++] = (1 << (i+8));
}
return ERROR_OK;
diff --git a/src/helper/binarybuffer.h b/src/helper/binarybuffer.h
index 81d3f63ac76942182c0139af00ea37f10757f111..d1fcd8b9c721d47c75513c7e6a43c20727dcbc9d 100644
--- a/src/helper/binarybuffer.h
+++ b/src/helper/binarybuffer.h
@@ -55,7 +55,7 @@ static inline uint32_t buf_get_u32(const uint8_t* buffer, unsigned int first, un
{
if ((num==32) && (first==0))
{
- return (((uint32_t)buffer[3])<<24)|(((uint32_t)buffer[2])<<16)|(((uint32_t)buffer[1])<<8)|(((uint32_t)buffer[0])<<0);
+ return (((uint32_t)buffer[3]) << 24)|(((uint32_t)buffer[2]) << 16)|(((uint32_t)buffer[1]) << 8)|(((uint32_t)buffer[0]) << 0);
} else
{
uint32_t result = 0;
diff --git a/src/helper/jim.c b/src/helper/jim.c
index c0425b98870dca06f445444ab69ad66c051c7689..9c8621503c893b8bd9ba29eadd6a4cb7632dda5a 100644
--- a/src/helper/jim.c
+++ b/src/helper/jim.c
@@ -662,7 +662,7 @@ unsigned int Jim_GenHashFunction(const unsigned char *buf, int len)
{
unsigned int h = 0;
while (len--)
- h += (h<<3)+*buf++;
+ h += (h << 3)+*buf++;
return h;
}
@@ -6957,7 +6957,7 @@ int Jim_EvalExpression(Jim_Interp *interp, Jim_Obj *exprObjPtr,
case JIM_EXPROP_GT: wC = wA>wB; break;
case JIM_EXPROP_LTE: wC = wA <= wB; break;
case JIM_EXPROP_GTE: wC = wA >= wB; break;
- case JIM_EXPROP_LSHIFT: wC = wA<<wB; break;
+ case JIM_EXPROP_LSHIFT: wC = wA << wB; break;
case JIM_EXPROP_RSHIFT: wC = wA >> wB; break;
case JIM_EXPROP_NUMEQ: wC = wA==wB; break;
case JIM_EXPROP_NUMNE: wC = wA != wB; break;
@@ -6996,7 +6996,7 @@ int Jim_EvalExpression(Jim_Interp *interp, Jim_Obj *exprObjPtr,
wC = _rotl(uA,(unsigned long)wB);
#else
const unsigned int S = sizeof(unsigned long) * 8;
- wC = (unsigned long)((uA<<wB)|(uA >> (S-wB)));
+ wC = (unsigned long)((uA << wB)|(uA >> (S-wB)));
#endif
break;
}
@@ -7006,7 +7006,7 @@ int Jim_EvalExpression(Jim_Interp *interp, Jim_Obj *exprObjPtr,
wC = _rotr(uA,(unsigned long)wB);
#else
const unsigned int S = sizeof(unsigned long) * 8;
- wC = (unsigned long)((uA >> wB)|(uA<<(S-wB)));
+ wC = (unsigned long)((uA >> wB)|(uA << (S-wB)));
#endif
break;
}
@@ -8038,7 +8038,7 @@ badfmt:
return JIM_ERR;
}
-#define JIM_MATCHVER_EXACT (1<<JIM_PRIV_FLAG_SHIFT)
+#define JIM_MATCHVER_EXACT (1 << JIM_PRIV_FLAG_SHIFT)
static int JimPackageMatchVersion(int needed, int actual, int flags)
{
if (needed == JIM_PKG_ANY_VERSION) return 1;
diff --git a/src/jtag/arm-jtag-ew.c b/src/jtag/arm-jtag-ew.c
index 0cc30654bb81a971ef0157dd1cb8945da4169725..7616fe703a367274da4285480802cbb65f7d7f5f 100644
--- a/src/jtag/arm-jtag-ew.c
+++ b/src/jtag/arm-jtag-ew.c
@@ -413,8 +413,8 @@ static void armjtagew_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, i
static void armjtagew_reset(int trst, int srst)
{
- const uint8_t trst_mask = (1u<<5);
- const uint8_t srst_mask = (1u<<6);
+ const uint8_t trst_mask = (1u << 5);
+ const uint8_t srst_mask = (1u << 6);
uint8_t val = 0;
uint8_t outp_en = 0;
uint8_t change_mask = 0;
diff --git a/src/jtag/bitbang.c b/src/jtag/bitbang.c
index e3cd63bef2fcdd553879be479fce5ba20e1f5354..dacd65ec23fba079adf457b0707d25557cce25bd 100644
--- a/src/jtag/bitbang.c
+++ b/src/jtag/bitbang.c
@@ -192,7 +192,7 @@ static void bitbang_scan(bool ir_scan, enum scan_type type, uint8_t *buffer, int
int tms=(bit_cnt==scan_size-1) ? 1 : 0;
int tdi;
int bytec=bit_cnt/8;
- int bcval=1<<(bit_cnt % 8);
+ int bcval=1 << (bit_cnt % 8);
/* if we're just reading the scan, but don't care about the output
* default to outputting 'low', this also makes valgrind traces more readable,
diff --git a/src/jtag/dummy.c b/src/jtag/dummy.c
index 6d738ee0dafe8088472e22e4af3069b9efe0e69a..b4aa94154501a080da8b8bd86f375d20250f3148 100644
--- a/src/jtag/dummy.c
+++ b/src/jtag/dummy.c
@@ -77,7 +77,7 @@ static bitbang_interface_t dummy_bitbang =
static int dummy_read(void)
{
int data = 1 & dummy_data;
- dummy_data = (dummy_data >> 1) | (1<<31);
+ dummy_data = (dummy_data >> 1) | (1 << 31);
return data;
}
diff --git a/src/jtag/ft2232.c b/src/jtag/ft2232.c
index 14ee7d142602120730a98614dfbb60bf97f9c123..d4e0fbcbf3261852b1772e3d90b121047930aeff 100644
--- a/src/jtag/ft2232.c
+++ b/src/jtag/ft2232.c
@@ -264,7 +264,7 @@ static void clock_tms(uint8_t mpsse_cmd, int tms_bits, int tms_count, bool tdi_b
bool bit = tms_bits & 1;
if (bit)
- tms_byte |= (1<<tms_ndx);
+ tms_byte |= (1 << tms_ndx);
/* always do state transitions in public view */
tap_set_state(tap_state_transition(tap_get_state(), bit));
@@ -760,7 +760,7 @@ static void ft2232_add_pathmove(tap_state_t* path, int num_states)
if (tap_state_transition(walker, false) == desired_next_state)
; /* bit within tms_bits at index state_ndx is already zero */
else if (tap_state_transition(walker, true) == desired_next_state)
- tms_bits |= (1<<state_ndx);
+ tms_bits |= (1 << state_ndx);
else
{
LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
diff --git a/src/jtag/interface.c b/src/jtag/interface.c
index 6a45d5939b73c497d9a6a2b62da27151aa182e89..e9998011139d720f11f49f15d140da22f3c668b7 100644
--- a/src/jtag/interface.c
+++ b/src/jtag/interface.c
@@ -118,14 +118,14 @@ struct tms_sequences
#define HEX__(n) 0x##n##LU
#define B8__(x) \
- (((x) & 0x0000000FLU)?(1<<0):0) \
- +(((x) & 0x000000F0LU)?(1<<1):0) \
- +(((x) & 0x00000F00LU)?(1<<2):0) \
- +(((x) & 0x0000F000LU)?(1<<3):0) \
- +(((x) & 0x000F0000LU)?(1<<4):0) \
- +(((x) & 0x00F00000LU)?(1<<5):0) \
- +(((x) & 0x0F000000LU)?(1<<6):0) \
- +(((x) & 0xF0000000LU)?(1<<7):0)
+ (((x) & 0x0000000FLU)?(1 << 0):0) \
+ +(((x) & 0x000000F0LU)?(1 << 1):0) \
+ +(((x) & 0x00000F00LU)?(1 << 2):0) \
+ +(((x) & 0x0000F000LU)?(1 << 3):0) \
+ +(((x) & 0x000F0000LU)?(1 << 4):0) \
+ +(((x) & 0x00F00000LU)?(1 << 5):0) \
+ +(((x) & 0x0F000000LU)?(1 << 6):0) \
+ +(((x) & 0xF0000000LU)?(1 << 7):0)
#define B8(bits,count) { ((uint8_t)B8__(HEX__(bits))), (count) }
diff --git a/src/jtag/usbprog.c b/src/jtag/usbprog.c
index ed6472b28bc2bc7ec0bda802ea218f7ec92c07bf..c9ade3d6215b9a6aa5e3f77773368fbe34af0ba1 100644
--- a/src/jtag/usbprog.c
+++ b/src/jtag/usbprog.c
@@ -373,11 +373,11 @@ static void usbprog_write(int tck, int tms, int tdi)
unsigned char output_value=0x00;
if (tms)
- output_value |= (1<<TMS_BIT);
+ output_value |= (1 << TMS_BIT);
if (tdi)
- output_value |= (1<<TDI_BIT);
+ output_value |= (1 << TDI_BIT);
if (tck)
- output_value |= (1<<TCK_BIT);
+ output_value |= (1 << TCK_BIT);
usbprog_jtag_write_slice(usbprog_jtag_handle,output_value);
}
diff --git a/src/jtag/zy1000/jtag_minidriver.h b/src/jtag/zy1000/jtag_minidriver.h
index 0f3e217e6450da615e0c05b5566551f7f77fe285..6b51844b67b2f8d259f30a8acdb7743fb6b3f060 100644
--- a/src/jtag/zy1000/jtag_minidriver.h
+++ b/src/jtag/zy1000/jtag_minidriver.h
@@ -74,7 +74,7 @@ static void setCurrentState(enum tap_state state)
}
waitQueue();
sampleShiftRegister();
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|a);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|a);
}
@@ -106,7 +106,7 @@ static __inline__ void shiftValueInner(const enum tap_state state, const enum ta
}
/* shift out value */
waitIdle();
- ZY1000_POKE(ZY1000_JTAG_BASE+0x28, (((value >> i)&1)<<1)|tms);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x28, (((value >> i)&1) << 1)|tms);
}
waitIdle();
ZY1000_POKE(ZY1000_JTAG_BASE+0x28, 0);
@@ -116,11 +116,11 @@ static __inline__ void shiftValueInner(const enum tap_state state, const enum ta
setCurrentState(endState);
} else
{
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|b);
}
#else
/* fast version */
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|b);
#endif
#else
/* maximum debug version */
@@ -132,15 +132,15 @@ static __inline__ void shiftValueInner(const enum tap_state state, const enum ta
{
sampleShiftRegister();
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value >> i);
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1<<8)|(a<<4)|a);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1 << 8)|(a << 4)|a);
}
sampleShiftRegister();
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value >> (repeat-1));
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1 << 8)|(a << 4)|b);
} else
{
sampleShiftRegister();
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (repeat << 8)|(a << 4)|b);
}
sampleShiftRegister();
#endif
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 4626b7815185e3749cba85122c7223abd2ad36bb..bc9e748a4942edec4d83e31d82fbb1b3e2988e18 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -405,7 +405,7 @@ static void shiftValueInnerFlip(const tap_state_t state, const tap_state_t endSt
a=state;
b=endState;
ZY1000_POKE(ZY1000_JTAG_BASE+0xc, value);
- ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1<<15)|(repeat<<8)|(a<<4)|b);
+ ZY1000_POKE(ZY1000_JTAG_BASE+0x8, (1 << 15)|(repeat << 8)|(a << 4)|b);
VERBOSE(getShiftValueFlip());
}
#endif
@@ -461,7 +461,7 @@ static __inline void scanFields(int num_fields, const scan_field_t *fields, tap_
}
}
/* mask away unused bits for easier debugging */
- value&=~(((uint32_t)0xffffffff)<<k);
+ value&=~(((uint32_t)0xffffffff) << k);
shiftValueInner(shiftState, pause_state, k, value);
@@ -741,7 +741,7 @@ void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int l
for (i = 0; i < count; i++)
{
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 1));
- shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
+ shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1 << 5));
buffer += 4;
}
} else
@@ -750,7 +750,7 @@ void embeddedice_write_dcc(jtag_tap_t *tap, int reg_addr, uint8_t *buffer, int l
for (i = 0; i < count; i++)
{
shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, 0));
- shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1<<5));
+ shiftValueInner(TAP_DRSHIFT, end_state, 6, reg_addr|(1 << 5));
buffer += 4;
}
}
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 3ae0b3108dd37325b3f1c2d485a36ddf59d3bc09..ed0a6a4979913c56b9614730a00ff3c24a9b80e4 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -925,7 +925,7 @@ void gdb_target_to_reg(target_t *target, char *tstr, int str_len, uint8_t *bin)
int i;
for (i = 0; i < str_len; i += 2)
{
- uint8_t t = hextoint(tstr[i])<<4;
+ uint8_t t = hextoint(tstr[i]) << 4;
t |= hextoint(tstr[i+1]);
int j = gdb_reg_pos(target, i/2, str_len/2);
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 146f89f4a3fc6591d8501eea1dc5e073afefdf12..a58c0a7cbf0279ab996e38a73ae3f70790e20833 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -300,7 +300,7 @@ int dap_dp_read_reg(swjdp_common_t *swjdp, uint32_t *value, uint8_t reg_addr)
int dap_ap_select(swjdp_common_t *swjdp,uint8_t apsel)
{
uint32_t select;
- select = (apsel<<24) & 0xFF000000;
+ select = (apsel << 24) & 0xFF000000;
if (select != swjdp->apsel)
{
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 2015c4d3d882b804ea4a5c3222e922f8886e8add..0466ff5b2073a5774da4c6fce78aec1d42d9810f 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -37,15 +37,15 @@
#define DP_SELECT 0x8
#define DP_RDBUFF 0xC
-#define CORUNDETECT (1<<0)
-#define SSTICKYORUN (1<<1)
-#define SSTICKYERR (1<<5)
-#define CDBGRSTREQ (1<<26)
-#define CDBGRSTACK (1<<27)
-#define CDBGPWRUPREQ (1<<28)
-#define CDBGPWRUPACK (1<<29)
-#define CSYSPWRUPREQ (1<<30)
-#define CSYSPWRUPACK (1<<31)
+#define CORUNDETECT (1 << 0)
+#define SSTICKYORUN (1 << 1)
+#define SSTICKYERR (1 << 5)
+#define CDBGRSTREQ (1 << 26)
+#define CDBGRSTACK (1 << 27)
+#define CDBGPWRUPREQ (1 << 28)
+#define CDBGPWRUPACK (1 << 29)
+#define CSYSPWRUPREQ (1 << 30)
+#define CSYSPWRUPACK (1 << 31)
#define AP_REG_CSW 0x00
#define AP_REG_TAR 0x04
@@ -61,13 +61,13 @@
#define CSW_16BIT 1
#define CSW_32BIT 2
-#define CSW_ADDRINC_MASK (3<<4)
+#define CSW_ADDRINC_MASK (3 << 4)
#define CSW_ADDRINC_OFF 0
-#define CSW_ADDRINC_SINGLE (1<<4)
-#define CSW_ADDRINC_PACKED (2<<4)
-#define CSW_HPROT (1<<25)
-#define CSW_MASTER_DEBUG (1<<29)
-#define CSW_DBGSWENABLE (1<<31)
+#define CSW_ADDRINC_SINGLE (1 << 4)
+#define CSW_ADDRINC_PACKED (2 << 4)
+#define CSW_HPROT (1 << 25)
+#define CSW_MASTER_DEBUG (1 << 29)
+#define CSW_DBGSWENABLE (1 << 31)
/* transaction mode */
#define TRANS_MODE_NONE 0
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 90442ea8a96fc667637103ab4ff204103ee2618b..b314e02a19e7a880c2f6edda7fdbfd9c60456cff 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -1330,7 +1330,7 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
if (((opc==0) || (opc==2)) && (offset & 0x00000400))
offset = 0xfffff800 | offset;
- target_address = address + 4 + (offset<<1);
+ target_address = address + 4 + (offset << 1);
switch (opc)
{
@@ -1348,7 +1348,7 @@ int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
case 2:
instruction->type = ARM_UNKNOWN_INSTUCTION;
mnemonic = "prefix";
- target_address = offset<<12;
+ target_address = offset << 12;
break;
/* BL suffix */
case 3:
@@ -1371,8 +1371,8 @@ int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
uint8_t Rm_imm = (opcode >> 6) & 0x7;
- uint32_t opc = opcode & (1<<9);
- uint32_t reg_imm = opcode & (1<<10);
+ uint32_t opc = opcode & (1 << 9);
+ uint32_t reg_imm = opcode & (1 << 10);
char *mnemonic;
if (opc)
@@ -1731,8 +1731,8 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
uint32_t offset = (opcode >> 6) & 0x1f;
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
- uint32_t L = opcode & (1<<11);
- uint32_t B = opcode & (1<<12);
+ uint32_t L = opcode & (1 << 11);
+ uint32_t B = opcode & (1 << 12);
char *mnemonic;
char suffix = ' ';
uint32_t shift = 2;
@@ -1759,13 +1759,13 @@ int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruc
shift = 0;
}
- snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
+ snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
instruction->info.load_store.Rd = Rd;
instruction->info.load_store.Rn = Rn;
instruction->info.load_store.index_mode = 0; /*offset*/
instruction->info.load_store.offset_mode = 0; /*immediate*/
- instruction->info.load_store.offset.offset = offset<<shift;
+ instruction->info.load_store.offset.offset = offset << shift;
return ERROR_OK;
}
@@ -1774,7 +1774,7 @@ int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instr
{
uint32_t offset = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
- uint32_t L = opcode & (1<<11);
+ uint32_t L = opcode & (1 << 11);
char *mnemonic;
if (L)
@@ -1804,7 +1804,7 @@ int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
uint32_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
uint8_t Rn;
- uint32_t SP = opcode & (1<<11);
+ uint32_t SP = opcode & (1 << 11);
char *reg_name;
instruction->type = ARM_ADD;
@@ -1833,7 +1833,7 @@ int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_
int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
{
uint32_t imm = opcode & 0x7f;
- uint8_t opc = opcode & (1<<7);
+ uint8_t opc = opcode & (1 << 7);
char *mnemonic;
@@ -1872,8 +1872,8 @@ int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction
int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
{
uint32_t reg_list = opcode & 0xff;
- uint32_t L = opcode & (1<<11);
- uint32_t R = opcode & (1<<8);
+ uint32_t L = opcode & (1 << 11);
+ uint32_t R = opcode & (1 << 8);
uint8_t Rn = (opcode >> 8) & 7;
uint8_t addr_mode = 0 /* IA */;
char reg_names[40];
@@ -1904,7 +1904,7 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
instruction->type = ARM_LDM;
mnemonic = "POP";
if (R)
- reg_list |= (1<<15) /*PC*/;
+ reg_list |= (1 << 15) /*PC*/;
}
else
{
@@ -1912,14 +1912,14 @@ int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_in
mnemonic = "PUSH";
addr_mode = 3; /*DB*/
if (R)
- reg_list |= (1<<14) /*LR*/;
+ reg_list |= (1 << 14) /*LR*/;
}
}
reg_names_p = reg_names;
for (i = 0; i <= 15; i++)
{
- if (reg_list & (1<<i))
+ if (reg_list & (1 << i))
reg_names_p += snprintf(reg_names_p, (reg_names + 40 - reg_names_p), "r%i, ", i);
}
if (reg_names_p>reg_names)
@@ -1959,7 +1959,7 @@ int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instructio
if (offset & 0x00000080)
offset = 0xffffff00 | offset;
- target_address = address + 4 + (offset<<1);
+ target_address = address + 4 + (offset << 1);
snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
arm_condition_strings[cond], target_address);
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 3d75eed56ddb11f566e51a3b7e81786943b931c4..6c751332b4f1f3cfd5dfcea49849f492b08a858f 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -138,13 +138,13 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
* Rd: destination register
* SYSm: source special register
*/
-#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd<<8) | SYSm) << 16))
+#define ARMV7M_T_MRS(Rd, SYSm) ((0xF3EF) | ((0x8000 | (Rd << 8) | SYSm) << 16))
/* Move from Register from Special Register (Thumb mode) 32 bit Thumb2 instruction
* Rd: source register
* SYSm: destination special register
*/
-#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn<<8 )) | ((0x8800 | SYSm) << 16))
+#define ARMV7M_T_MSR(SYSm, Rn) ((0xF380 | ( Rn << 8 )) | ((0x8800 | SYSm) << 16))
/* Change Processor State. The instruction modifies the PRIMASK and FAULTMASK
* special-purpose register values (Thumb mode) 16 bit Thumb2 instruction
@@ -153,8 +153,8 @@ extern int armv7m_blank_check_memory(struct target_s *target, uint32_t address,
*/
#define I_FLAG 2
#define F_FLAG 1
-#define ARMV7M_T_CPSID(IF) ((0xB660 | (1<<8) | (IF&0x3)) | ((0xB660 | (1<<8) | (IF&0x3)) << 16))
-#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0<<8) | (IF&0x3)) | ((0xB660 | (0<<8) | (IF&0x3)) << 16))
+#define ARMV7M_T_CPSID(IF) ((0xB660 | (1 << 8) | (IF&0x3)) | ((0xB660 | (1 << 8) | (IF&0x3)) << 16))
+#define ARMV7M_T_CPSIE(IF) ((0xB660 | (0 << 8) | (IF&0x3)) | ((0xB660 | (0 << 8) | (IF&0x3)) << 16))
/* Breakpoint (Thumb mode) v5 onwards
* Im: immediate value used by debugger
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 644f68161f9bab4ce0cef33a170e0f874a493113..6079b9ebdeb0f6a920eb9ee2f582512874efd363 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -641,7 +641,7 @@ int cortex_m3_resume(struct target_s *target, int current, uint32_t address, int
/* Make sure we are in Thumb mode */
buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1<<24));
+ buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
}
@@ -1580,7 +1580,7 @@ int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jt
armv7m->swjdp_info.ap_tar_value = -1;
armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
armv7m->swjdp_info.memaccess_tck = 8;
- armv7m->swjdp_info.tar_autoincr_block = (1<<12); /* Cortex-M3 has 4096 bytes autoincrement range */
+ armv7m->swjdp_info.tar_autoincr_block = (1 << 12); /* Cortex-M3 has 4096 bytes autoincrement range */
/* initialize arch-specific breakpoint handling */
diff --git a/src/target/cortex_m3.h b/src/target/cortex_m3.h
index ae772543bff78b223838b6f94e13365fd1672375..70605469e3f2268b16e10019dfe313c447247994 100644
--- a/src/target/cortex_m3.h
+++ b/src/target/cortex_m3.h
@@ -44,7 +44,7 @@ extern char* cortex_m3_state_strings[];
#define DCB_DCRDR 0xE000EDF8
#define DCB_DEMCR 0xE000EDFC
-#define DCRSR_WnR (1<<16)
+#define DCRSR_WnR (1 << 16)
#define DWT_CTRL 0xE0001000
#define DWT_COMP0 0xE0001020
@@ -65,23 +65,23 @@ extern char* cortex_m3_state_strings[];
#define DWT_CTRL 0xE0001000
/* DCB_DHCSR bit and field definitions */
-#define DBGKEY (0xA05F<<16)
-#define C_DEBUGEN (1<<0)
-#define C_HALT (1<<1)
-#define C_STEP (1<<2)
-#define C_MASKINTS (1<<3)
-#define S_REGRDY (1<<16)
-#define S_HALT (1<<17)
-#define S_SLEEP (1<<18)
-#define S_LOCKUP (1<<19)
-#define S_RETIRE_ST (1<<24)
-#define S_RESET_ST (1<<25)
+#define DBGKEY (0xA05F << 16)
+#define C_DEBUGEN (1 << 0)
+#define C_HALT (1 << 1)
+#define C_STEP (1 << 2)
+#define C_MASKINTS (1 << 3)
+#define S_REGRDY (1 << 16)
+#define S_HALT (1 << 17)
+#define S_SLEEP (1 << 18)
+#define S_LOCKUP (1 << 19)
+#define S_RETIRE_ST (1 << 24)
+#define S_RESET_ST (1 << 25)
/* DCB_DEMCR bit and field definitions */
-#define TRCENA (1<<24)
-#define VC_HARDERR (1<<10)
-#define VC_BUSERR (1<<8)
-#define VC_CORERESET (1<<0)
+#define TRCENA (1 << 24)
+#define VC_HARDERR (1 << 10)
+#define VC_BUSERR (1 << 8)
+#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
#define NVIC_ISE0 0xE000E100
@@ -98,12 +98,12 @@ extern char* cortex_m3_state_strings[];
#define NVIC_BFAR 0xE000ED38
/* NVIC_AIRCR bits */
-#define AIRCR_VECTKEY (0x5FA<<16)
-#define AIRCR_SYSRESETREQ (1<<2)
-#define AIRCR_VECTCLRACTIVE (1<<1)
-#define AIRCR_VECTRESET (1<<0)
+#define AIRCR_VECTKEY (0x5FA << 16)
+#define AIRCR_SYSRESETREQ (1 << 2)
+#define AIRCR_VECTCLRACTIVE (1 << 1)
+#define AIRCR_VECTRESET (1 << 0)
/* NVIC_SHCSR bits */
-#define SHCSR_BUSFAULTENA (1<<17)
+#define SHCSR_BUSFAULTENA (1 << 17)
/* NVIC_DFSR bits */
#define DFSR_HALTED 1
#define DFSR_BKPT 2
@@ -112,10 +112,10 @@ extern char* cortex_m3_state_strings[];
#define FPCR_CODE 0
#define FPCR_LITERAL 1
-#define FPCR_REPLACE_REMAP (0<<30)
-#define FPCR_REPLACE_BKPT_LOW (1<<30)
-#define FPCR_REPLACE_BKPT_HIGH (2<<30)
-#define FPCR_REPLACE_BKPT_BOTH (3<<30)
+#define FPCR_REPLACE_REMAP (0 << 30)
+#define FPCR_REPLACE_BKPT_LOW (1 << 30)
+#define FPCR_REPLACE_BKPT_HIGH (2 << 30)
+#define FPCR_REPLACE_BKPT_BOTH (3 << 30)
typedef struct cortex_m3_fp_comparator_s
{
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 6c4bfb9a9d4670654b60e81d6414f5fa7c7ce81f..aa6d921ceb269f22d0c4d47478e330b41fe7537d 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -433,19 +433,19 @@ int mips32_enable_interrupts(struct target_s *target, int enable)
if (enable)
{
- if (!(dcr & (1<<4)))
+ if (!(dcr & (1 << 4)))
{
/* enable interrupts */
- dcr |= (1<<4);
+ dcr |= (1 << 4);
update = 1;
}
}
else
{
- if (dcr & (1<<4))
+ if (dcr & (1 << 4))
{
/* disable interrupts */
- dcr &= ~(1<<4);
+ dcr &= ~(1 << 4);
update = 1;
}
}
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 2d00aa8170cc4e342832465bb17e0a6ec337a7d2..ab47f73104c22e518adba8c31b5a25546cb7816f 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -94,9 +94,9 @@ typedef struct mips32_core_reg_s
#define MIPS32_COP0_MF 0x00
#define MIPS32_COP0_MT 0x04
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|((rd)<<11)| ((shamt)<<6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode)<<26) |((rs)<<21)|((rt)<<16)|(immd))
-#define MIPS32_J_INST(opcode, addr) (((opcode)<<26) |(addr))
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21)|((rt) << 16)|((rd) << 11)| ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21)|((rt) << 16)|(immd))
+#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
#define MIPS32_NOP 0
#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 5985cfd31af777c5ae45eca22bacabcb01fbf08a..7a64bd4d5ddaad08143056be5deafdcef96a9c75 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -285,16 +285,16 @@ int mips_ejtag_init(mips_ejtag_t *ejtag_info)
break;
}
LOG_DEBUG("EJTAG: features:%s%s%s%s%s%s%s",
- ejtag_info->impcode & (1<<28) ? " R3k": " R4k",
- ejtag_info->impcode & (1<<24) ? " DINT": "",
- ejtag_info->impcode & (1<<22) ? " ASID_8": "",
- ejtag_info->impcode & (1<<21) ? " ASID_6": "",
- ejtag_info->impcode & (1<<16) ? " MIPS16": "",
- ejtag_info->impcode & (1<<14) ? " noDMA": " DMA",
- ejtag_info->impcode & (1<<0) ? " MIPS64": " MIPS32"
+ ejtag_info->impcode & (1 << 28) ? " R3k": " R4k",
+ ejtag_info->impcode & (1 << 24) ? " DINT": "",
+ ejtag_info->impcode & (1 << 22) ? " ASID_8": "",
+ ejtag_info->impcode & (1 << 21) ? " ASID_6": "",
+ ejtag_info->impcode & (1 << 16) ? " MIPS16": "",
+ ejtag_info->impcode & (1 << 14) ? " noDMA": " DMA",
+ ejtag_info->impcode & (1 << 0) ? " MIPS64": " MIPS32"
);
- if ((ejtag_info->impcode & (1<<14)) == 0)
+ if ((ejtag_info->impcode & (1 << 14)) == 0)
LOG_DEBUG("EJTAG: DMA Access Mode Support Enabled");
/* set initial state for ejtag control reg */