From c6b24fb4f0e9eb0a2ca3acaff8603e97b7ef0d80 Mon Sep 17 00:00:00 2001
From: dbrownell <dbrownell@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Mon, 5 Oct 2009 08:13:00 +0000
Subject: [PATCH] Get rid of needless OMAP and Davinci target config options so
they provide better examples and are easier to maintain.
git-svn-id: svn://svn.berlios.de/openocd/trunk@2797 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
tcl/target/omap2420.cfg | 7 +------
tcl/target/omap5912.cfg | 9 +--------
tcl/target/ti_dm355.cfg | 15 ++++-----------
tcl/target/ti_dm365.cfg | 9 +++------
tcl/target/ti_dm6446.cfg | 11 ++++-------
5 files changed, 13 insertions(+), 38 deletions(-)
diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 01557491f..866b4a342 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -6,11 +6,6 @@ if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME omap2420
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
@@ -46,7 +41,7 @@ jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JR
# GDB target: the ARM.
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
# scratch: framebuffer, may be initially unavailable in some chips
$_TARGETNAME configure -work-area-phys 0x40210000
diff --git a/tcl/target/omap5912.cfg b/tcl/target/omap5912.cfg
index fa0fc9e07..30650cfbe 100644
--- a/tcl/target/omap5912.cfg
+++ b/tcl/target/omap5912.cfg
@@ -7,13 +7,6 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME omap5912
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a bigendian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -30,7 +23,7 @@ jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
jtag newtap $_CHIPNAME unknown -irlen 8
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
proc omap5912_reset {} {
#
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index 67b3f7a48..b1e19e99d 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -6,11 +6,6 @@ if { [info exists CHIPNAME] } {
} else {
set _CHIPNAME dm355
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
# after JTAG reset until ICEpick is used to route them in.
@@ -33,8 +28,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -44,8 +38,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -55,7 +48,7 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b73b02f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
################
@@ -89,7 +82,7 @@ source [find target/davinci.cfg]
# and the ETB memory (4K) are other options, while trace is unused.
set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
# NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
# and that the work area is used only with a kernel mmu context ...
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti_dm365.cfg
index 06a52d28f..3a17d1a8b 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti_dm365.cfg
@@ -24,8 +24,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -35,8 +34,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x0792602f
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -46,8 +44,7 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b83e02f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
################
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti_dm6446.cfg
index cc23ad440..e96c3e15f 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti_dm6446.cfg
@@ -20,7 +20,7 @@ set EMU01 "-enable"
#set EMU01 "-disable"
# Subsidiary TAP: unknown ... must enable via ICEpick
-jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
+jtag newtap $_CHIPNAME unknown -irlen 8 -disable
jtag configure $_CHIPNAME.unknown -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 3"
@@ -35,8 +35,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
jtag configure $_CHIPNAME.etb -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 1"
@@ -46,8 +45,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07926001
}
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
- -expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
jtag configure $_CHIPNAME.arm -event tap-enable \
"icepick_c_tapenable $_CHIPNAME.jrc 0"
@@ -57,8 +55,7 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x0b70002f
}
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
- -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 8K)
# and the ETB memory (4K) are other options, while trace is unused.
--
GitLab