diff --git a/src/target/board/imx27lnst.cfg b/src/target/board/imx27lnst.cfg
new file mode 100644
index 0000000000000000000000000000000000000000..2ee7f0944b46434ea6e4c153ef989b7c2497f77f
--- /dev/null
+++ b/src/target/board/imx27lnst.cfg
@@ -0,0 +1,59 @@
+# The Linuxstamp-mx27 is board has a single IMX27 chip
+# For further info see http://opencircuits.com/Linuxstamp_mx27#OpenOCD
+source [find target/imx27.cfg]
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { imx27lnst_init }
+
+proc imx27lnst_init { } {
+	# This setup puts RAM at 0xA0000000
+
+	# reset the board correctly
+	jtag_khz 500
+	reset run
+	reset halt
+
+	mww 0x10000000 0x20040304
+	mww 0x10020000 0x00000000
+	mww 0x10000004 0xDFFBFCFB
+	mww 0x10020004 0xFFFFFFFF
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- initial reset
+	# ========================================
+	mww 0xD8001010 0x00000008 
+
+	sleep 100
+
+	# ========================================
+	#  Configure DDR on CSD0 -- wait 5000 cycle 
+	# ========================================
+	mww 0x10027828 0x55555555 
+	mww 0x10027830 0x55555555 
+	mww 0x10027834 0x55555555 
+	mww 0x10027838 0x00005005 
+	mww 0x1002783C 0x15555555 
+
+	mww 0xD8001010 0x00000004 
+
+	mww 0xD8001004 0x00795729 
+
+	#mww 0xD8001000 0x92200000
+	mww 0xD8001000 0x91120000
+	mww 0xA0000F00 0x0
+
+	#mww 0xD8001000 0xA2200000 
+	mww 0xD8001000 0xA1120000
+	mww 0xA0000F00 0x0
+	mww 0xA0000F00 0x0
+
+	#mww 0xD8001000 0xB2200000 
+	mww 0xD8001000 0xB1120000
+	mwb 0xA0000033 0xFF
+	mwb 0xA1000000 0xAA
+
+	#mww 0xD8001000 0x82228085 
+	mww 0xD8001000 0x81128080
+
+}