From d2e9877bc9ad1f40122d1d2e83449dac9e940d15 Mon Sep 17 00:00:00 2001
From: Kevin Gillespie <kgills@gmail.com>
Date: Mon, 17 Dec 2018 09:19:02 -0600
Subject: [PATCH] Removing flash burst bits and adding options.
Change-Id: I2533490869643d283b54437e958dc663df05132e
---
src/flash/nor/max32xxx.c | 46 ++++++++++------------------------------
tcl/target/max32520.cfg | 19 +++++++++++++++++
tcl/target/max32620.cfg | 2 +-
tcl/target/max32625.cfg | 2 +-
tcl/target/max3263x.cfg | 2 +-
tcl/target/max32650.cfg | 3 +--
tcl/target/max32660.cfg | 3 +--
tcl/target/max32665.cfg | 2 +-
tcl/target/max32xxx.cfg | 26 +++++++++++------------
9 files changed, 48 insertions(+), 57 deletions(-)
create mode 100644 tcl/target/max32520.cfg
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 1428b37c6..b4d7bbc86 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -85,10 +85,7 @@
#define ARM_PID_DEFAULT_CM3 0x0000B4C3
#define ARM_PID_DEFAULT_CM4 0x0000B4C4
-#define MAX326XX_ID 0x0000004D
-
-#define WRITE32BIT 0
-#define WRITE128BIT 1
+#define MAX326XX_ID 0x0000004D
#define OPTIONS_128 0x01 /* Perform 128 bit flash writes */
#define OPTIONS_ENC 0x02 /* Encrypt the flash contents */
@@ -98,7 +95,6 @@
#define OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */
#define OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */
-
static int max32xxx_mass_erase(struct flash_bank *bank);
struct max32xxx_flash_bank {
@@ -109,11 +105,9 @@ struct max32xxx_flash_bank {
unsigned int sector_size;
unsigned int clkdiv_value;
unsigned int int_state;
- unsigned int burst_size_bits;
- unsigned int enc_options;
+ unsigned int options;
};
-/* see contib/loaders/flash/max32xxx/max32xxx.s for src */
static const uint8_t write_code[] = {
0x9b, 0x46, 0x51, 0xf8, 0x84, 0x3c, 0xa1, 0xf5, 0x82, 0x77, 0x02, 0x93, 0x13, 0xf0, 0x02, 0x03, 0x05, 0x93, 0x1e, 0xd0,
0x4f, 0xf0, 0x80, 0x43, 0x9c, 0x68, 0x64, 0x03, 0x5e, 0xbf, 0x9c, 0x68, 0x44, 0xf4, 0x80, 0x24, 0x9c, 0x60, 0x5c, 0x6a,
@@ -162,15 +156,12 @@ static const uint8_t write_code[] = {
0xff, 0x09, 0x3d, 0xe7, 0x4f, 0xf0, 0xff, 0x09, 0x60, 0xe7, 0x4f, 0xf0, 0xff, 0x09, 0x83, 0xe7, 0x5d, 0x44, 0x9f, 0xe7,
};
-/* Config Command: flash bank name driver base size chip_width bus_width target [driver_option]
- flash bank max32xxx <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> [burst_bits]
- */
FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
{
struct max32xxx_flash_bank *info;
- if ((CMD_ARGC < 10) || (CMD_ARGC > 11)) {
- LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> <burst_bits> [enc_options]");
+ if ((CMD_ARGC < 10) || (CMD_ARGC > 10)) {
+ LOG_ERROR("incorrect flash bank max32xxx configuration: <base> <size> 0 0 <target> <FLC base> <sector size> <clkdiv> <options>");
return ERROR_FLASH_BANK_INVALID;
}
@@ -179,22 +170,7 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->flc_base);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], info->sector_size);
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], info->clkdiv_value);
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->burst_size_bits);
-
- if ((info->burst_size_bits != 128) && (info->burst_size_bits != 32)) {
- LOG_ERROR("Invalid burst size %d, must be 32 or 128", info->burst_size_bits);
- return ERROR_FLASH_BANK_INVALID;
- }
-
- if(CMD_ARGC == 11) {
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[10], info->enc_options);
- } else {
- if(info->burst_size_bits == 128) {
- info->enc_options = OPTIONS_128;
- } else {
- info->enc_options = 0x0;
- }
- }
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[9], info->options);
info->int_state = 0;
bank->driver_priv = info;
@@ -514,7 +490,7 @@ static int max32xxx_write_block(struct flash_bank *bank, const uint8_t *buffer,
/* mem_params for options */
init_mem_param(&mem_param[0], source->address + (source->size - 4 - 128), 4, PARAM_OUT);
- buf_set_u32(mem_param[0].value, 0, 32, info->enc_options);
+ buf_set_u32(mem_param[0].value, 0, 32, info->options);
/* leave room for stack, 32-bit options and encryption buffer */
retval = target_run_flash_async_algorithm(target, buffer, wcount*4, 1, 1, mem_param,
@@ -556,7 +532,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer,
if (info->probed == 0)
return ERROR_FLASH_BANK_NOT_PROBED;
- if (info->burst_size_bits == 32) {
+ if ((info->options & OPTIONS_128) == 0) {
if (offset & 0x3) {
LOG_ERROR("offset size must be 32-bit aligned");
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
@@ -600,7 +576,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer,
}
}
- if ((info->burst_size_bits == 32) && (remaining >= 4)) {
+ if (((info->options & OPTIONS_128) == 0) && (remaining >= 4)) {
/* write in 32-bit units*/
target_read_u32(target, info->flc_base + FLC_CN, &flash_cn);
flash_cn |= FLC_CN_32BIT;
@@ -629,7 +605,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer,
}
}
- if ((info->burst_size_bits == 128) && (remaining >= 16)) {
+ if ((info->options & OPTIONS_128) && (remaining >= 16)) {
/* write in 128-bit units */
target_read_u32(target, info->flc_base + FLC_CN, &flash_cn);
flash_cn &= ~(FLC_CN_32BIT);
@@ -662,7 +638,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer,
}
}
- if ((info->burst_size_bits == 32) && remaining > 0) {
+ if (((info->options & OPTIONS_128) == 0) && remaining > 0) {
/* write remaining bytes in a 32-bit unit */
target_read_u32(target, info->flc_base + FLC_CN, &flash_cn);
flash_cn |= FLC_CN_32BIT;
@@ -695,7 +671,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer,
}
}
- if ((info->burst_size_bits == 128) && remaining > 0) {
+ if ((info->options & OPTIONS_128) && remaining > 0) {
/* write remaining bytes in a 128-bit unit */
if (target_read_u32(target, info->flc_base + FLC_CN, &flash_cn) != ERROR_OK) {
max32xxx_flash_op_post(bank);
diff --git a/tcl/target/max32520.cfg b/tcl/target/max32520.cfg
new file mode 100644
index 000000000..4e75a99c3
--- /dev/null
+++ b/tcl/target/max32520.cfg
@@ -0,0 +1,19 @@
+# Maxim Integrated MAX32665 OpenOCD target configuration file
+# www.maximintegrated.com
+
+# Set the reset pin configuration
+reset_config srst_only
+adapter_nsrst_delay 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x200000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+
+# Currently set for Emulator
+set FLASH_CLK 40
+
+set FLASH_OPTIONS 0x63
+
+source [find target/max32xxx.cfg]
diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index 1ee892dc6..8aed3a806 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -11,7 +11,7 @@ set FLASH_SIZE 0x200000
set FLC_BASE 0x40002000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
-set FLASH_BITS 32
+set FLASH_OPTIONS 0x00
# Setup the reserved TAP
set RSV_TAP 1
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 44e62f708..f29fabf20 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -11,7 +11,7 @@ set FLASH_SIZE 0x80000
set FLC_BASE 0x40002000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
-set FLASH_BITS 32
+set FLASH_OPTIONS 0x00
# Setup the reserved TAP
set RSV_TAP 1
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index 06565ef6d..2b78df6e3 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -10,7 +10,7 @@ set FLASH_SIZE 0x200000
set FLC_BASE 0x40002000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
-set FLASH_BITS 32
+set FLASH_OPTIONS 0x00
# Setup the reserved TAP
set RSV_TAP 1
diff --git a/tcl/target/max32650.cfg b/tcl/target/max32650.cfg
index 1ae0f6981..e5c28bc93 100644
--- a/tcl/target/max32650.cfg
+++ b/tcl/target/max32650.cfg
@@ -11,7 +11,6 @@ set FLASH_SIZE 0x300000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
-set FLASH_BITS 32
-# set FLASH_BITS 128
+set FLASH_OPTIONS 0x00
source [find target/max32xxx.cfg]
diff --git a/tcl/target/max32660.cfg b/tcl/target/max32660.cfg
index 723d4d5a8..6c6d60179 100644
--- a/tcl/target/max32660.cfg
+++ b/tcl/target/max32660.cfg
@@ -11,7 +11,6 @@ set FLASH_SIZE 0x40000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
-set FLASH_BITS 32
-# set FLASH_BITS 128
+set FLASH_OPTIONS 0x00
source [find target/max32xxx.cfg]
diff --git a/tcl/target/max32665.cfg b/tcl/target/max32665.cfg
index 5d05ee448..893ffa8bb 100644
--- a/tcl/target/max32665.cfg
+++ b/tcl/target/max32665.cfg
@@ -11,6 +11,6 @@ set FLASH_SIZE 0x300000
set FLC_BASE 0x40029000
set FLASH_SECTOR 0x2000
set FLASH_CLK 96
-set FLASH_BITS 128
+set FLASH_OPTIONS 0x01
source [find target/max32xxx.cfg]
diff --git a/tcl/target/max32xxx.cfg b/tcl/target/max32xxx.cfg
index 9039f0d92..9f5b2719e 100644
--- a/tcl/target/max32xxx.cfg
+++ b/tcl/target/max32xxx.cfg
@@ -77,21 +77,19 @@ if { [info exists FLASH_CLK] } {
set _FLASH_CLK 96
}
-if { [info exists FLASH_BITS] } {
- set _FLASH_BITS $FLASH_BITS
+# OPTIONS_128 0x01 /* Perform 128 bit flash writes */
+# OPTIONS_ENC 0x02 /* Encrypt the flash contents */
+# OPTIONS_AUTH 0x04 /* Authenticate the flash contents */
+# OPTIONS_COUNT 0x08 /* Add counter values to authentication */
+# OPTIONS_INTER 0x10 /* Interleave the authentication and count values*/
+# OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */
+# OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */
+
+if { [info exists FLASH_OPTIONS] } {
+ set _FLASH_OPTIONS $FLASH_OPTIONS
} else {
- set _FLASH_BITS 32
-}
-
-if { [info exists ENC_OPTIONS] } {
- set _ENC_OPTIONS $ENC_OPTIONS
-} else {
- if { $FLASH_BITS == 128 } {
- set _ENC_OPTIONS 1
- } else {
- set _ENC_OPTIONS 0
- }
+ set _FLASH_OPTIONS 0
}
flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
-$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_BITS $_ENC_OPTIONS
+$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_OPTIONS
--
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