diff --git a/contrib/loaders/flash/max32xxx/Makefile b/contrib/loaders/flash/max32xxx/Makefile
index 8f3f9242e457acc69c7e54bf43f517a229a68e2f..712b9510e9d44dc559d1de47f7f1d73c0d74d194 100644
--- a/contrib/loaders/flash/max32xxx/Makefile
+++ b/contrib/loaders/flash/max32xxx/Makefile
@@ -1,19 +1,26 @@
+TARGET=max32xxx_write
+ENTRY=algo_write
+
BIN2C = ../../../../src/helper/bin2char.sh
-CROSS_COMPILE ?= arm-none-eabi-
-AS = $(CROSS_COMPILE)as
-OBJCOPY = $(CROSS_COMPILE)objcopy
+all: max32xxx_write.inc
-all: max32xxx.inc
+%.o: %.c
+ arm-none-eabi-gcc -mthumb -mcpu=cortex-m4 -Wa,-mimplicit-it=thumb -Os -Wall -c ${<} -o ${@}
-%.elf: %.s
- $(AS) $< -o $@
+%.elf: %.o
+ arm-none-eabi-ld -nostdlib -nostartfiles --entry $(ENTRY) ${<} -o ${@}
+ arm-none-eabi-size ${@}
%.bin: %.elf
- $(OBJCOPY) -Obinary $< $@
+ arm-none-eabi-objcopy -O binary ${<} ${@}
%.inc: %.bin
$(BIN2C) < $< > $@
+%.dasm: %.o
+ arm-none-eabi-objdump -d -s ${<} > ${TARGET}.dasm
+
clean:
- -rm -f *.elf *.bin *.inc
+ rm -rf $(TARGET).bin $(TARGET).elf $(TARGET).o $(TARGET).dasm $(TARGET).inc
+
diff --git a/contrib/loaders/flash/max32xxx/algo_options.h b/contrib/loaders/flash/max32xxx/algo_options.h
new file mode 100644
index 0000000000000000000000000000000000000000..f85c26a6ba2c32862ffab6af82fa7722c5b16a20
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/algo_options.h
@@ -0,0 +1,7 @@
+#define OPTIONS_128 0x01 /* Perform 128 bit flash writes */
+#define OPTIONS_ENC 0x02 /* Encrypt the flash contents */
+#define OPTIONS_AUTH 0x04 /* Authenticate the flash contents */
+#define OPTIONS_COUNT 0x08 /* Add counter values to authentication */
+#define OPTIONS_INTER 0x10 /* Interleave the authentication and count values*/
+#define OPTIONS_RELATIVE_XOR 0x20 /* Only XOR the offset of the address when encrypting */
+#define OPTIONS_KEYSIZE 0x40 /* Use a 256 bit KEY */
diff --git a/contrib/loaders/flash/max32xxx/flc_regs.h b/contrib/loaders/flash/max32xxx/flc_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..402e7bc3f8508c50416842817ee6801d507de893
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/flc_regs.h
@@ -0,0 +1,261 @@
+/**
+ * @file flc_regs.h
+ * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _FLC_REGS_H_
+#define _FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+ #pragma system_include
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup flc
+ * @defgroup flc_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ * @description Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_registers
+ * Structure type to access the FLC Registers.
+ */
+typedef struct {
+ __IO uint32_t addr; /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
+ __IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
+ __IO uint32_t cn; /**< <tt>\b 0x08:<\tt> FLC CN Register */
+ __R uint32_t rsv_0xc_0x23[6];
+ __IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
+ __R uint32_t rsv_0x28_0x2f[2];
+ __IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
+ __O uint32_t acntl; /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
+} mxc_flc_regs_t;
+
+/* Register offsets for module FLC */
+/**
+ * @ingroup flc_registers
+ * @defgroup FLC_Register_Offsets Register Offsets
+ * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
+ * @{
+ */
+ #define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: <tt> 0x0x000 */
+ #define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0x004 */
+ #define MXC_R_FLC_CN ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: <tt> 0x0x008 */
+ #define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: <tt> 0x0x024 */
+ #define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: <tt> 0x0x030 */
+ #define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: <tt> 0x0x040 */
+/**@} end of group flc_registers */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup ADDR_Register
+ * @brief Flash Write Address.
+ * @{
+ */
+ #define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */
+ #define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group ADDR_Register */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup CLKDIV_Register
+ * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ * MHz clock for Flash controller.
+ * @{
+ */
+ #define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */
+ #define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group CLKDIV_Register */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup CN_Register
+ * @brief Flash Control Register.
+ * @{
+ */
+ #define MXC_F_FLC_CN_WR_POS 0 /**< CN_WR Position */
+ #define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS)) /**< CN_WR Mask */
+ #define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL) /**< CN_WR_COMPLETE Value */
+ #define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
+ #define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL) /**< CN_WR_START Value */
+ #define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS) /**< CN_WR_START Setting */
+
+ #define MXC_F_FLC_CN_ME_POS 1 /**< CN_ME Position */
+ #define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
+
+ #define MXC_F_FLC_CN_PGE_POS 2 /**< CN_PGE Position */
+ #define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
+
+ #define MXC_F_FLC_CN_WDTH_POS 4 /**< CN_WDTH Position */
+ #define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS)) /**< CN_WDTH Mask */
+ #define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL) /**< CN_WDTH_SIZE128 Value */
+ #define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
+ #define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL) /**< CN_WDTH_SIZE32 Value */
+ #define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE32 Setting */
+
+ #define MXC_F_FLC_CN_ERASE_CODE_POS 8 /**< CN_ERASE_CODE Position */
+ #define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
+ #define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CN_ERASE_CODE_NOP Value */
+ #define MXC_S_FLC_CN_ERASE_CODE_NOP (MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
+ #define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CN_ERASE_CODE_ERASEPAGE Value */
+ #define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
+ #define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CN_ERASE_CODE_ERASEALL Value */
+ #define MXC_S_FLC_CN_ERASE_CODE_ERASEALL (MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
+
+ #define MXC_F_FLC_CN_PEND_POS 24 /**< CN_PEND Position */
+ #define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS)) /**< CN_PEND Mask */
+ #define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL) /**< CN_PEND_IDLE Value */
+ #define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
+ #define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL) /**< CN_PEND_BUSY Value */
+ #define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
+
+ #define MXC_F_FLC_CN_LVE_POS 25 /**< CN_LVE Position */
+ #define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS)) /**< CN_LVE Mask */
+ #define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL) /**< CN_LVE_DIS Value */
+ #define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
+ #define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL) /**< CN_LVE_EN Value */
+ #define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_EN Setting */
+
+ #define MXC_F_FLC_CN_BRST_POS 27 /**< CN_BRST Position */
+ #define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS)) /**< CN_BRST Mask */
+ #define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL) /**< CN_BRST_DISABLE Value */
+ #define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
+ #define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL) /**< CN_BRST_ENABLE Value */
+ #define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_ENABLE Setting */
+
+ #define MXC_F_FLC_CN_UNLOCK_POS 28 /**< CN_UNLOCK Position */
+ #define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
+ #define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CN_UNLOCK_UNLOCKED Value */
+ #define MXC_S_FLC_CN_UNLOCK_UNLOCKED (MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
+ #define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CN_UNLOCK_LOCKED Value */
+ #define MXC_S_FLC_CN_UNLOCK_LOCKED (MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
+
+/**@} end of group CN_Register */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup INTR_Register
+ * @brief Flash Interrupt Register.
+ * @{
+ */
+ #define MXC_F_FLC_INTR_DONE_POS 0 /**< INTR_DONE Position */
+ #define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
+ #define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL) /**< INTR_DONE_INACTIVE Value */
+ #define MXC_S_FLC_INTR_DONE_INACTIVE (MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
+ #define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL) /**< INTR_DONE_PENDING Value */
+ #define MXC_S_FLC_INTR_DONE_PENDING (MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
+
+ #define MXC_F_FLC_INTR_AF_POS 1 /**< INTR_AF Position */
+ #define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS)) /**< INTR_AF Mask */
+ #define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL) /**< INTR_AF_NOERROR Value */
+ #define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
+ #define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL) /**< INTR_AF_ERROR Value */
+ #define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_ERROR Setting */
+
+ #define MXC_F_FLC_INTR_DONEIE_POS 8 /**< INTR_DONEIE Position */
+ #define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+ #define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL) /**< INTR_DONEIE_DISABLE Value */
+ #define MXC_S_FLC_INTR_DONEIE_DISABLE (MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
+ #define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL) /**< INTR_DONEIE_ENABLE Value */
+ #define MXC_S_FLC_INTR_DONEIE_ENABLE (MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
+
+ #define MXC_F_FLC_INTR_AFIE_POS 9 /**< INTR_AFIE Position */
+ #define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group INTR_Register */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup DATA_Register
+ * @brief Flash Write Data.
+ * @{
+ */
+ #define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */
+ #define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group DATA_Register */
+
+/**
+ * @ingroup flc_registers
+ * @defgroup ACNTL_Register
+ * @brief Access Control Register. Writing the ACNTL register with the following values in
+ * the order shown, allows read and write access to the system and user Information
+ * block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
+ * 0x9608b2c1. When unlocked, a write of any word will disable access to system and
+ * user information block. Readback of this register is always zero.
+ * @{
+ */
+ #define MXC_F_FLC_ACNTL_ACNTL_POS 0 /**< ACNTL_ACNTL Position */
+ #define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
+
+/**@} end of group ACNTL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REGS_H_ */
diff --git a/contrib/loaders/flash/max32xxx/gcr_regs.h b/contrib/loaders/flash/max32xxx/gcr_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..250050989a17750004c0266f5f416d0f9c3fc9e9
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/gcr_regs.h
@@ -0,0 +1,718 @@
+/**
+ * @file gcr_regs.h
+ * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _GCR_REGS_H_
+#define _GCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+ #pragma system_include
+#endif
+
+#if defined (__CC_ARM)
+ #pragma anon_unions
+#endif
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup gcr
+ * @defgroup gcr_registers GCR_Registers
+ * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ * @details Global Control Registers.
+ */
+
+/**
+ * @ingroup gcr_registers
+ * Structure type to access the GCR Registers.
+ */
+typedef struct {
+ __IO uint32_t scon; /**< <tt>\b 0x00:</tt> GCR SCON Register */
+ __IO uint32_t rstr0; /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */
+ __IO uint32_t clkcn; /**< <tt>\b 0x08:</tt> GCR CLKCN Register */
+ __IO uint32_t pm; /**< <tt>\b 0x0C:</tt> GCR PM Register */
+ __R uint32_t rsv_0x10_0x17[2];
+ __IO uint32_t pckdiv; /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */
+ __R uint32_t rsv_0x1c_0x23[2];
+ __IO uint32_t perckcn0; /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */
+ __IO uint32_t memckcn; /**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */
+ __IO uint32_t memzcn; /**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */
+ __R uint32_t rsv_0x30_0x3f[4];
+ __IO uint32_t sysst; /**< <tt>\b 0x40:</tt> GCR SYSST Register */
+ __IO uint32_t rstr1; /**< <tt>\b 0x44:</tt> GCR RSTR1 Register */
+ __IO uint32_t perckcn1; /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */
+ __IO uint32_t evten; /**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
+ __I uint32_t revision; /**< <tt>\b 0x50:</tt> GCR REVISION Register */
+ __IO uint32_t syssie; /**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
+ __R uint32_t rsv_0x58_0x63[3];
+ __IO uint32_t eccerr; /**< <tt>\b 0x64:</tt> GCR ECCERR Register */
+ __IO uint32_t eccnded; /**< <tt>\b 0x68:</tt> GCR ECCNDED Register */
+ __IO uint32_t eccirqen; /**< <tt>\b 0x6C:</tt> GCR ECCIRQEN Register */
+ __IO uint32_t eccerrad; /**< <tt>\b 0x70:</tt> GCR ECCERRAD Register */
+} mxc_gcr_regs_t;
+
+/* Register offsets for module GCR */
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_Register_Offsets Register Offsets
+ * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
+ * @{
+ */
+ #define MXC_R_GCR_SCON ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: <tt> 0x0000</tt> */
+ #define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: <tt> 0x0004</tt> */
+ #define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: <tt> 0x0008</tt> */
+ #define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: <tt> 0x000C</tt> */
+ #define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: <tt> 0x0018</tt> */
+ #define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: <tt> 0x0024</tt> */
+ #define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: <tt> 0x0028</tt> */
+ #define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: <tt> 0x002C</tt> */
+ #define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: <tt> 0x0040</tt> */
+ #define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: <tt> 0x0044</tt> */
+ #define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: <tt> 0x0048</tt> */
+ #define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: <tt> 0x004C</tt> */
+ #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: <tt> 0x0050</tt> */
+ #define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: <tt> 0x0054</tt> */
+ #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: <tt> 0x0064</tt> */
+ #define MXC_R_GCR_ECCNDED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: <tt> 0x0068</tt> */
+ #define MXC_R_GCR_ECCIRQEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: <tt> 0x006C</tt> */
+ #define MXC_R_GCR_ECCERRAD ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: <tt> 0x0070</tt> */
+/**@} end of group gcr_registers */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_SCON GCR_SCON
+ * @brief System Control.
+ * @{
+ */
+ #define MXC_F_GCR_SCON_BSTAPEN_POS 0 /**< SCON_BSTAPEN Position */
+ #define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) /**< SCON_BSTAPEN Mask */
+ #define MXC_V_GCR_SCON_BSTAPEN_DIS ((uint32_t)0x0UL) /**< SCON_BSTAPEN_DIS Value */
+ #define MXC_S_GCR_SCON_BSTAPEN_DIS (MXC_V_GCR_SCON_BSTAPEN_DIS << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_DIS Setting */
+ #define MXC_V_GCR_SCON_BSTAPEN_EN ((uint32_t)0x1UL) /**< SCON_BSTAPEN_EN Value */
+ #define MXC_S_GCR_SCON_BSTAPEN_EN (MXC_V_GCR_SCON_BSTAPEN_EN << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_EN Setting */
+
+ #define MXC_F_GCR_SCON_SBUSARB_POS 1 /**< SCON_SBUSARB Position */
+ #define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
+ #define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL) /**< SCON_SBUSARB_FIX Value */
+ #define MXC_S_GCR_SCON_SBUSARB_FIX (MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
+ #define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SCON_SBUSARB_ROUND Value */
+ #define MXC_S_GCR_SCON_SBUSARB_ROUND (MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
+
+ #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
+ #define MXC_F_GCR_SCON_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)) /**< SCON_FLASH_PAGE_FLIP Mask */
+ #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
+ #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */
+ #define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
+ #define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED (MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */
+
+ #define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
+ #define MXC_F_GCR_SCON_CCACHE_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS)) /**< SCON_CCACHE_FLUSH Mask */
+ #define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
+ #define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL (MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */
+ #define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL) /**< SCON_CCACHE_FLUSH_FLUSH Value */
+ #define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH (MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */
+
+ #define MXC_F_GCR_SCON_CCHK_POS 13 /**< SCON_CCHK Position */
+ #define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */
+ #define MXC_V_GCR_SCON_CCHK_COMPLETE ((uint32_t)0x0UL) /**< SCON_CCHK_COMPLETE Value */
+ #define MXC_S_GCR_SCON_CCHK_COMPLETE (MXC_V_GCR_SCON_CCHK_COMPLETE << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_COMPLETE Setting */
+ #define MXC_V_GCR_SCON_CCHK_START ((uint32_t)0x1UL) /**< SCON_CCHK_START Value */
+ #define MXC_S_GCR_SCON_CCHK_START (MXC_V_GCR_SCON_CCHK_START << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_START Setting */
+
+ #define MXC_F_GCR_SCON_CHKRES_POS 15 /**< SCON_CHKRES Position */
+ #define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) /**< SCON_CHKRES Mask */
+ #define MXC_V_GCR_SCON_CHKRES_PASS ((uint32_t)0x0UL) /**< SCON_CHKRES_PASS Value */
+ #define MXC_S_GCR_SCON_CHKRES_PASS (MXC_V_GCR_SCON_CHKRES_PASS << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_PASS Setting */
+ #define MXC_V_GCR_SCON_CHKRES_FAIL ((uint32_t)0x1UL) /**< SCON_CHKRES_FAIL Value */
+ #define MXC_S_GCR_SCON_CHKRES_FAIL (MXC_V_GCR_SCON_CHKRES_FAIL << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_FAIL Setting */
+
+ #define MXC_F_GCR_SCON_OVR_POS 16 /**< SCON_OVR Position */
+ #define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS)) /**< SCON_OVR Mask */
+ #define MXC_V_GCR_SCON_OVR_0_9V ((uint32_t)0x0UL) /**< SCON_OVR_0_9V Value */
+ #define MXC_S_GCR_SCON_OVR_0_9V (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_0_9V Setting */
+ #define MXC_V_GCR_SCON_OVR_1_0V ((uint32_t)0x1UL) /**< SCON_OVR_1_0V Value */
+ #define MXC_S_GCR_SCON_OVR_1_0V (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_0V Setting */
+ #define MXC_V_GCR_SCON_OVR_1_1V ((uint32_t)0x2UL) /**< SCON_OVR_1_1V Value */
+ #define MXC_S_GCR_SCON_OVR_1_1V (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_1V Setting */
+
+ #define MXC_F_GCR_SCON_MEMPROT_EN_POS 20 /**< SCON_MEMPROT_EN Position */
+ #define MXC_F_GCR_SCON_MEMPROT_EN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_EN_POS)) /**< SCON_MEMPROT_EN Mask */
+ #define MXC_V_GCR_SCON_MEMPROT_EN_DIS ((uint32_t)0x0UL) /**< SCON_MEMPROT_EN_DIS Value */
+ #define MXC_S_GCR_SCON_MEMPROT_EN_DIS (MXC_V_GCR_SCON_MEMPROT_EN_DIS << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_DIS Setting */
+ #define MXC_V_GCR_SCON_MEMPROT_EN_EN ((uint32_t)0x1UL) /**< SCON_MEMPROT_EN_EN Value */
+ #define MXC_S_GCR_SCON_MEMPROT_EN_EN (MXC_V_GCR_SCON_MEMPROT_EN_EN << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_EN Setting */
+
+ #define MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS 21 /**< SCON_MEMPROT_KEYSZ Position */
+ #define MXC_F_GCR_SCON_MEMPROT_KEYSZ ((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS)) /**< SCON_MEMPROT_KEYSZ Mask */
+ #define MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 ((uint32_t)0x0UL) /**< SCON_MEMPROT_KEYSZ_128 Value */
+ #define MXC_S_GCR_SCON_MEMPROT_KEYSZ_128 (MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_128 Setting */
+ #define MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 ((uint32_t)0x1UL) /**< SCON_MEMPROT_KEYSZ_256 Value */
+ #define MXC_S_GCR_SCON_MEMPROT_KEYSZ_256 (MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_256 Setting */
+
+/**@} end of group GCR_SCON_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_RSTR0 GCR_RSTR0
+ * @brief Reset.
+ * @{
+ */
+ #define MXC_F_GCR_RSTR0_DMA_POS 0 /**< RSTR0_DMA Position */
+ #define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
+ #define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL) /**< RSTR0_DMA_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR0_DMA_RESET_DONE (MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL) /**< RSTR0_DMA_BUSY Value */
+ #define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR0_WDT_POS 1 /**< RSTR0_WDT Position */
+ #define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
+
+ #define MXC_F_GCR_RSTR0_GPIO0_POS 2 /**< RSTR0_GPIO0 Position */
+ #define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
+
+ #define MXC_F_GCR_RSTR0_GPIO1_POS 3 /**< RSTR0_GPIO1 Position */
+ #define MXC_F_GCR_RSTR0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS)) /**< RSTR0_GPIO1 Mask */
+
+ #define MXC_F_GCR_RSTR0_TIMER0_POS 5 /**< RSTR0_TIMER0 Position */
+ #define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
+
+ #define MXC_F_GCR_RSTR0_TIMER1_POS 6 /**< RSTR0_TIMER1 Position */
+ #define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
+
+ #define MXC_F_GCR_RSTR0_TIMER2_POS 7 /**< RSTR0_TIMER2 Position */
+ #define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
+
+ #define MXC_F_GCR_RSTR0_TIMER3_POS 8 /**< RSTR0_TIMER3 Position */
+ #define MXC_F_GCR_RSTR0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS)) /**< RSTR0_TIMER3 Mask */
+
+ #define MXC_F_GCR_RSTR0_UART0_POS 11 /**< RSTR0_UART0 Position */
+ #define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
+
+ #define MXC_F_GCR_RSTR0_SPI0_POS 13 /**< RSTR0_SPI0 Position */
+ #define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
+
+ #define MXC_F_GCR_RSTR0_SPI1_POS 14 /**< RSTR0_SPI1 Position */
+ #define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
+
+ #define MXC_F_GCR_RSTR0_I2C0_POS 16 /**< RSTR0_I2C0 Position */
+ #define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
+
+ #define MXC_F_GCR_RSTR0_CRYPTO_POS 18 /**< RSTR0_CRYPTO Position */
+ #define MXC_F_GCR_RSTR0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS)) /**< RSTR0_CRYPTO Mask */
+
+ #define MXC_F_GCR_RSTR0_SMPHR_POS 22 /**< RSTR0_SMPHR Position */
+ #define MXC_F_GCR_RSTR0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS)) /**< RSTR0_SMPHR Mask */
+
+ #define MXC_F_GCR_RSTR0_TRNG_POS 24 /**< RSTR0_TRNG Position */
+ #define MXC_F_GCR_RSTR0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TRNG_POS)) /**< RSTR0_TRNG Mask */
+
+ #define MXC_F_GCR_RSTR0_SRST_POS 29 /**< RSTR0_SRST Position */
+ #define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */
+
+ #define MXC_F_GCR_RSTR0_PRST_POS 30 /**< RSTR0_PRST Position */
+ #define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */
+
+ #define MXC_F_GCR_RSTR0_SYSTEM_POS 31 /**< RSTR0_SYSTEM Position */
+ #define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
+
+/**@} end of group GCR_RSTR0_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_CLKCN GCR_CLKCN
+ * @brief Clock Control.
+ * @{
+ */
+ #define MXC_F_GCR_CLKCN_PSC_POS 6 /**< CLKCN_PSC Position */
+ #define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS)) /**< CLKCN_PSC Mask */
+ #define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL) /**< CLKCN_PSC_DIV1 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV1 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL) /**< CLKCN_PSC_DIV2 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV2 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL) /**< CLKCN_PSC_DIV4 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV4 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL) /**< CLKCN_PSC_DIV8 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV8 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL) /**< CLKCN_PSC_DIV16 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL) /**< CLKCN_PSC_DIV32 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL) /**< CLKCN_PSC_DIV64 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting */
+ #define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL) /**< CLKCN_PSC_DIV128 Value */
+ #define MXC_S_GCR_CLKCN_PSC_DIV128 (MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
+
+ #define MXC_F_GCR_CLKCN_CLKSEL_POS 9 /**< CLKCN_CLKSEL Position */
+ #define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
+ #define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL) /**< CLKCN_CLKSEL_HIRC Value */
+ #define MXC_S_GCR_CLKCN_CLKSEL_HIRC (MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
+ #define MXC_V_GCR_CLKCN_CLKSEL_LIRC8 ((uint32_t)0x3UL) /**< CLKCN_CLKSEL_LIRC8 Value */
+ #define MXC_S_GCR_CLKCN_CLKSEL_LIRC8 (MXC_V_GCR_CLKCN_CLKSEL_LIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_LIRC8 Setting */
+ #define MXC_V_GCR_CLKCN_CLKSEL_HIRC8 ((uint32_t)0x5UL) /**< CLKCN_CLKSEL_HIRC8 Value */
+ #define MXC_S_GCR_CLKCN_CLKSEL_HIRC8 (MXC_V_GCR_CLKCN_CLKSEL_HIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC8 Setting */
+
+ #define MXC_F_GCR_CLKCN_CKRDY_POS 13 /**< CLKCN_CKRDY Position */
+ #define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
+ #define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL) /**< CLKCN_CKRDY_BUSY Value */
+ #define MXC_S_GCR_CLKCN_CKRDY_BUSY (MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
+ #define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL) /**< CLKCN_CKRDY_READY Value */
+ #define MXC_S_GCR_CLKCN_CKRDY_READY (MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
+
+ #define MXC_F_GCR_CLKCN_HIRC_EN_POS 18 /**< CLKCN_HIRC_EN Position */
+ #define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
+ #define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL) /**< CLKCN_HIRC_EN_DIS Value */
+ #define MXC_S_GCR_CLKCN_HIRC_EN_DIS (MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
+ #define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL) /**< CLKCN_HIRC_EN_EN Value */
+ #define MXC_S_GCR_CLKCN_HIRC_EN_EN (MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
+
+ #define MXC_F_GCR_CLKCN_HIRC8M_EN_POS 20 /**< CLKCN_HIRC8M_EN Position */
+ #define MXC_F_GCR_CLKCN_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_EN_POS)) /**< CLKCN_HIRC8M_EN Mask */
+
+ #define MXC_F_GCR_CLKCN_HIRC8M_VS_POS 21 /**< CLKCN_HIRC8M_VS Position */
+ #define MXC_F_GCR_CLKCN_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_VS_POS)) /**< CLKCN_HIRC8M_VS Mask */
+ #define MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR ((uint32_t)0x0UL) /**< CLKCN_HIRC8M_VS_VCOR Value */
+ #define MXC_S_GCR_CLKCN_HIRC8M_VS_VCOR (MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_VCOR Setting */
+ #define MXC_V_GCR_CLKCN_HIRC8M_VS_1V ((uint32_t)0x1UL) /**< CLKCN_HIRC8M_VS_1V Value */
+ #define MXC_S_GCR_CLKCN_HIRC8M_VS_1V (MXC_V_GCR_CLKCN_HIRC8M_VS_1V << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_1V Setting */
+
+ #define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26 /**< CLKCN_HIRC_RDY Position */
+ #define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
+ #define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL) /**< CLKCN_HIRC_RDY_NOT Value */
+ #define MXC_S_GCR_CLKCN_HIRC_RDY_NOT (MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
+ #define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL) /**< CLKCN_HIRC_RDY_READY Value */
+ #define MXC_S_GCR_CLKCN_HIRC_RDY_READY (MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
+
+ #define MXC_F_GCR_CLKCN_HIRC8M_RDY_POS 28 /**< CLKCN_HIRC8M_RDY Position */
+ #define MXC_F_GCR_CLKCN_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_RDY_POS)) /**< CLKCN_HIRC8M_RDY Mask */
+
+ #define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
+ #define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */
+
+/**@} end of group GCR_CLKCN_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_PM GCR_PM
+ * @brief Power Management.
+ * @{
+ */
+ #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */
+ #define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */
+ #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */
+ #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
+ #define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */
+ #define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */
+ #define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */
+ #define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */
+ #define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */
+ #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+
+ #define MXC_F_GCR_PM_GPIOWKEN_POS 4 /**< PM_GPIOWKEN Position */
+ #define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
+ #define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL) /**< PM_GPIOWKEN_DIS Value */
+ #define MXC_S_GCR_PM_GPIOWKEN_DIS (MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_DIS Setting */
+ #define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL) /**< PM_GPIOWKEN_EN Value */
+ #define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting */
+
+ #define MXC_F_GCR_PM_HIRCPD_POS 15 /**< PM_HIRCPD Position */
+ #define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
+ #define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL) /**< PM_HIRCPD_ACTIVE Value */
+ #define MXC_S_GCR_PM_HIRCPD_ACTIVE (MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
+ #define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL) /**< PM_HIRCPD_DEEPSLEEP Value */
+ #define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP (MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
+
+ #define MXC_F_GCR_PM_HIRC8MPD_POS 17 /**< PM_HIRC8MPD Position */
+ #define MXC_F_GCR_PM_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) /**< PM_HIRC8MPD Mask */
+
+/**@} end of group GCR_PM_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_PCKDIV GCR_PCKDIV
+ * @brief Peripheral Clock Divider.
+ * @{
+ */
+ #define MXC_F_GCR_PCKDIV_PCF_POS 0 /**< PCKDIV_PCF Position */
+ #define MXC_F_GCR_PCKDIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCKDIV_PCF_POS)) /**< PCKDIV_PCF Mask */
+ #define MXC_V_GCR_PCKDIV_PCF_96MHZ ((uint32_t)0x2UL) /**< PCKDIV_PCF_96MHZ Value */
+ #define MXC_S_GCR_PCKDIV_PCF_96MHZ (MXC_V_GCR_PCKDIV_PCF_96MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_96MHZ Setting */
+ #define MXC_V_GCR_PCKDIV_PCF_48MHZ ((uint32_t)0x3UL) /**< PCKDIV_PCF_48MHZ Value */
+ #define MXC_S_GCR_PCKDIV_PCF_48MHZ (MXC_V_GCR_PCKDIV_PCF_48MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_48MHZ Setting */
+ #define MXC_V_GCR_PCKDIV_PCF_24MHZ ((uint32_t)0x4UL) /**< PCKDIV_PCF_24MHZ Value */
+ #define MXC_S_GCR_PCKDIV_PCF_24MHZ (MXC_V_GCR_PCKDIV_PCF_24MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_24MHZ Setting */
+ #define MXC_V_GCR_PCKDIV_PCF_12MHZ ((uint32_t)0x5UL) /**< PCKDIV_PCF_12MHZ Value */
+ #define MXC_S_GCR_PCKDIV_PCF_12MHZ (MXC_V_GCR_PCKDIV_PCF_12MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_12MHZ Setting */
+ #define MXC_V_GCR_PCKDIV_PCF_6MHZ ((uint32_t)0x6UL) /**< PCKDIV_PCF_6MHZ Value */
+ #define MXC_S_GCR_PCKDIV_PCF_6MHZ (MXC_V_GCR_PCKDIV_PCF_6MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_6MHZ Setting */
+ #define MXC_V_GCR_PCKDIV_PCF_3MHZ ((uint32_t)0x7UL) /**< PCKDIV_PCF_3MHZ Value */
+ #define MXC_S_GCR_PCKDIV_PCF_3MHZ (MXC_V_GCR_PCKDIV_PCF_3MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_3MHZ Setting */
+
+ #define MXC_F_GCR_PCKDIV_PCFWEN_POS 3 /**< PCKDIV_PCFWEN Position */
+ #define MXC_F_GCR_PCKDIV_PCFWEN ((uint32_t)(0x1UL << MXC_F_GCR_PCKDIV_PCFWEN_POS)) /**< PCKDIV_PCFWEN Mask */
+ #define MXC_V_GCR_PCKDIV_PCFWEN_DISABLED ((uint32_t)0x0UL) /**< PCKDIV_PCFWEN_DISABLED Value */
+ #define MXC_S_GCR_PCKDIV_PCFWEN_DISABLED (MXC_V_GCR_PCKDIV_PCFWEN_DISABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_DISABLED Setting */
+ #define MXC_V_GCR_PCKDIV_PCFWEN_ENABLED ((uint32_t)0x1UL) /**< PCKDIV_PCFWEN_ENABLED Value */
+ #define MXC_S_GCR_PCKDIV_PCFWEN_ENABLED (MXC_V_GCR_PCKDIV_PCFWEN_ENABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_ENABLED Setting */
+
+ #define MXC_F_GCR_PCKDIV_AONCD_POS 14 /**< PCKDIV_AONCD Position */
+ #define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL) /**< PCKDIV_AONCD_DIV_4 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_4 (MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL) /**< PCKDIV_AONCD_DIV_8 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_8 (MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL) /**< PCKDIV_AONCD_DIV_16 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_16 (MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
+ #define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL) /**< PCKDIV_AONCD_DIV_32 Value */
+ #define MXC_S_GCR_PCKDIV_AONCD_DIV_32 (MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
+
+/**@} end of group GCR_PCKDIV_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_PERCKCN0 GCR_PERCKCN0
+ * @brief Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0 /**< PERCKCN0_GPIO0D Position */
+ #define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */
+ #define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL) /**< PERCKCN0_GPIO0D_EN Value */
+ #define MXC_S_GCR_PERCKCN0_GPIO0D_EN (MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
+ #define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL) /**< PERCKCN0_GPIO0D_DIS Value */
+ #define MXC_S_GCR_PERCKCN0_GPIO0D_DIS (MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN0_GPIO1D_POS 1 /**< PERCKCN0_GPIO1D Position */
+ #define MXC_F_GCR_PERCKCN0_GPIO1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO1D_POS)) /**< PERCKCN0_GPIO1D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_DMAD_POS 5 /**< PERCKCN0_DMAD Position */
+ #define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
+
+ #define MXC_F_GCR_PERCKCN0_SPI0D_POS 6 /**< PERCKCN0_SPI0D Position */
+ #define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_SPI1D_POS 7 /**< PERCKCN0_SPI1D Position */
+ #define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_UART0D_POS 9 /**< PERCKCN0_UART0D Position */
+ #define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_I2C0D_POS 13 /**< PERCKCN0_I2C0D Position */
+ #define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_CRYPTOD_POS 14 /**< PERCKCN0_CRYPTOD Position */
+ #define MXC_F_GCR_PERCKCN0_CRYPTOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) /**< PERCKCN0_CRYPTOD Mask */
+
+ #define MXC_F_GCR_PERCKCN0_T0D_POS 15 /**< PERCKCN0_T0D Position */
+ #define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_T1D_POS 16 /**< PERCKCN0_T1D Position */
+ #define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_T2D_POS 17 /**< PERCKCN0_T2D Position */
+ #define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
+
+ #define MXC_F_GCR_PERCKCN0_T3D_POS 18 /**< PERCKCN0_T3D Position */
+ #define MXC_F_GCR_PERCKCN0_T3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T3D_POS)) /**< PERCKCN0_T3D Mask */
+
+/**@} end of group GCR_PERCKCN0_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_MEMCKCN GCR_MEMCKCN
+ * @brief Memory Clock Control Register.
+ * @{
+ */
+ #define MXC_F_GCR_MEMCKCN_FWS_POS 0 /**< MEMCKCN_FWS Position */
+ #define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 16 /**< MEMCKCN_SYSRAM0LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM0LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS)) /**< MEMCKCN_SYSRAM0LS Mask */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE (MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */
+ #define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
+ #define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP (MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 17 /**< MEMCKCN_SYSRAM1LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM1LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 18 /**< MEMCKCN_SYSRAM2LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM2LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 19 /**< MEMCKCN_SYSRAM3LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM3LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS 20 /**< MEMCKCN_SYSRAM4LS Position */
+ #define MXC_F_GCR_MEMCKCN_SYSRAM4LS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS)) /**< MEMCKCN_SYSRAM4LS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_ICACHELS_POS 24 /**< MEMCKCN_ICACHELS Position */
+ #define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */
+
+ #define MXC_F_GCR_MEMCKCN_ROMLS_POS 29 /**< MEMCKCN_ROMLS Position */
+ #define MXC_F_GCR_MEMCKCN_ROMLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROMLS_POS)) /**< MEMCKCN_ROMLS Mask */
+
+/**@} end of group GCR_MEMCKCN_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_MEMZCN GCR_MEMZCN
+ * @brief Memory Zeroize Control.
+ * @{
+ */
+ #define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0 /**< MEMZCN_SRAM0Z Position */
+ #define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
+ #define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL) /**< MEMZCN_SRAM0Z_NOP Value */
+ #define MXC_S_GCR_MEMZCN_SRAM0Z_NOP (MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
+ #define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL) /**< MEMZCN_SRAM0Z_START Value */
+ #define MXC_S_GCR_MEMZCN_SRAM0Z_START (MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
+
+ #define MXC_F_GCR_MEMZCN_SRAM1Z_POS 1 /**< MEMZCN_SRAM1Z Position */
+ #define MXC_F_GCR_MEMZCN_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM1Z_POS)) /**< MEMZCN_SRAM1Z Mask */
+
+ #define MXC_F_GCR_MEMZCN_SRAM2Z_POS 2 /**< MEMZCN_SRAM2Z Position */
+ #define MXC_F_GCR_MEMZCN_SRAM2Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM2Z_POS)) /**< MEMZCN_SRAM2Z Mask */
+
+ #define MXC_F_GCR_MEMZCN_SRAM3Z_POS 3 /**< MEMZCN_SRAM3Z Position */
+ #define MXC_F_GCR_MEMZCN_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM3Z_POS)) /**< MEMZCN_SRAM3Z Mask */
+
+ #define MXC_F_GCR_MEMZCN_SRAM4Z_POS 4 /**< MEMZCN_SRAM4Z Position */
+ #define MXC_F_GCR_MEMZCN_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM4Z_POS)) /**< MEMZCN_SRAM4Z Mask */
+
+ #define MXC_F_GCR_MEMZCN_ICACHEZ_POS 8 /**< MEMZCN_ICACHEZ Position */
+ #define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
+
+/**@} end of group GCR_MEMZCN_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_SYSST GCR_SYSST
+ * @brief System Status Register.
+ * @{
+ */
+ #define MXC_F_GCR_SYSST_ICECLOCK_POS 0 /**< SYSST_ICECLOCK Position */
+ #define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
+ #define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
+ #define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED (MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */
+ #define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL) /**< SYSST_ICECLOCK_LOCKED Value */
+ #define MXC_S_GCR_SYSST_ICECLOCK_LOCKED (MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */
+
+/**@} end of group GCR_SYSST_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_RSTR1 GCR_RSTR1
+ * @brief Reset 1.
+ * @{
+ */
+ #define MXC_F_GCR_RSTR1_WDT1_POS 8 /**< RSTR1_WDT1 Position */
+ #define MXC_F_GCR_RSTR1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) /**< RSTR1_WDT1 Mask */
+ #define MXC_V_GCR_RSTR1_WDT1_RESET_DONE ((uint32_t)0x0UL) /**< RSTR1_WDT1_RESET_DONE Value */
+ #define MXC_S_GCR_RSTR1_WDT1_RESET_DONE (MXC_V_GCR_RSTR1_WDT1_RESET_DONE << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_RESET_DONE Setting */
+ #define MXC_V_GCR_RSTR1_WDT1_BUSY ((uint32_t)0x1UL) /**< RSTR1_WDT1_BUSY Value */
+ #define MXC_S_GCR_RSTR1_WDT1_BUSY (MXC_V_GCR_RSTR1_WDT1_BUSY << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_BUSY Setting */
+
+ #define MXC_F_GCR_RSTR1_PUFC_POS 27 /**< RSTR1_PUFC Position */
+ #define MXC_F_GCR_RSTR1_PUFC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PUFC_POS)) /**< RSTR1_PUFC Mask */
+
+ #define MXC_F_GCR_RSTR1_CSPIS_POS 28 /**< RSTR1_CSPIS Position */
+ #define MXC_F_GCR_RSTR1_CSPIS ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_CSPIS_POS)) /**< RSTR1_CSPIS Mask */
+
+/**@} end of group GCR_RSTR1_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_PERCKCN1 GCR_PERCKCN1
+ * @brief Peripheral Clock Disable.
+ * @{
+ */
+ #define MXC_F_GCR_PERCKCN1_TRNGD_POS 2 /**< PERCKCN1_TRNGD Position */
+ #define MXC_F_GCR_PERCKCN1_TRNGD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_TRNGD_POS)) /**< PERCKCN1_TRNGD Mask */
+ #define MXC_V_GCR_PERCKCN1_TRNGD_EN ((uint32_t)0x0UL) /**< PERCKCN1_TRNGD_EN Value */
+ #define MXC_S_GCR_PERCKCN1_TRNGD_EN (MXC_V_GCR_PERCKCN1_TRNGD_EN << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_EN Setting */
+ #define MXC_V_GCR_PERCKCN1_TRNGD_DIS ((uint32_t)0x1UL) /**< PERCKCN1_TRNGD_DIS Value */
+ #define MXC_S_GCR_PERCKCN1_TRNGD_DIS (MXC_V_GCR_PERCKCN1_TRNGD_DIS << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_DIS Setting */
+
+ #define MXC_F_GCR_PERCKCN1_PUFCD_POS 3 /**< PERCKCN1_PUFCD Position */
+ #define MXC_F_GCR_PERCKCN1_PUFCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_PUFCD_POS)) /**< PERCKCN1_PUFCD Mask */
+
+ #define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
+ #define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */
+
+ #define MXC_F_GCR_PERCKCN1_CSPISD_POS 30 /**< PERCKCN1_CSPISD Position */
+ #define MXC_F_GCR_PERCKCN1_CSPISD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_CSPISD_POS)) /**< PERCKCN1_CSPISD Mask */
+
+/**@} end of group GCR_PERCKCN1_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_EVTEN GCR_EVTEN
+ * @brief Event Enable Register.
+ * @{
+ */
+ #define MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS 0 /**< EVTEN_CPU0DMAEVENT Position */
+ #define MXC_F_GCR_EVTEN_CPU0DMAEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS)) /**< EVTEN_CPU0DMAEVENT Mask */
+
+ #define MXC_F_GCR_EVTEN_CPU0RXEVENT_POS 1 /**< EVTEN_CPU0RXEVENT Position */
+ #define MXC_F_GCR_EVTEN_CPU0RXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0RXEVENT_POS)) /**< EVTEN_CPU0RXEVENT Mask */
+
+ #define MXC_F_GCR_EVTEN_CPU0TXEVENT_POS 2 /**< EVTEN_CPU0TXEVENT Position */
+ #define MXC_F_GCR_EVTEN_CPU0TXEVENT ((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0TXEVENT_POS)) /**< EVTEN_CPU0TXEVENT Mask */
+
+/**@} end of group GCR_EVTEN_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_REVISION GCR_REVISION
+ * @brief Revision Register.
+ * @{
+ */
+ #define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */
+ #define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */
+
+/**@} end of group GCR_REVISION_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_SYSSIE GCR_SYSSIE
+ * @brief System Status Interrupt Enable Register.
+ * @{
+ */
+ #define MXC_F_GCR_SYSSIE_ICEULIE_POS 0 /**< SYSSIE_ICEULIE Position */
+ #define MXC_F_GCR_SYSSIE_ICEULIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSSIE_ICEULIE_POS)) /**< SYSSIE_ICEULIE Mask */
+ #define MXC_V_GCR_SYSSIE_ICEULIE_DIS ((uint32_t)0x0UL) /**< SYSSIE_ICEULIE_DIS Value */
+ #define MXC_S_GCR_SYSSIE_ICEULIE_DIS (MXC_V_GCR_SYSSIE_ICEULIE_DIS << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_DIS Setting */
+ #define MXC_V_GCR_SYSSIE_ICEULIE_EN ((uint32_t)0x1UL) /**< SYSSIE_ICEULIE_EN Value */
+ #define MXC_S_GCR_SYSSIE_ICEULIE_EN (MXC_V_GCR_SYSSIE_ICEULIE_EN << MXC_F_GCR_SYSSIE_ICEULIE_POS) /**< SYSSIE_ICEULIE_EN Setting */
+
+/**@} end of group GCR_SYSSIE_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_ECCERR GCR_ECCERR
+ * @brief ECC Error Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCERR_SYSRAM0ECCERR_POS 0 /**< ECCERR_SYSRAM0ECCERR Position */
+ #define MXC_F_GCR_ECCERR_SYSRAM0ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM0ECCERR_POS)) /**< ECCERR_SYSRAM0ECCERR Mask */
+
+ #define MXC_F_GCR_ECCERR_SYSRAM1ECCERR_POS 1 /**< ECCERR_SYSRAM1ECCERR Position */
+ #define MXC_F_GCR_ECCERR_SYSRAM1ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM1ECCERR_POS)) /**< ECCERR_SYSRAM1ECCERR Mask */
+
+ #define MXC_F_GCR_ECCERR_SYSRAM2ECCERR_POS 2 /**< ECCERR_SYSRAM2ECCERR Position */
+ #define MXC_F_GCR_ECCERR_SYSRAM2ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM2ECCERR_POS)) /**< ECCERR_SYSRAM2ECCERR Mask */
+
+ #define MXC_F_GCR_ECCERR_SYSRAM3ECCERR_POS 3 /**< ECCERR_SYSRAM3ECCERR Position */
+ #define MXC_F_GCR_ECCERR_SYSRAM3ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM3ECCERR_POS)) /**< ECCERR_SYSRAM3ECCERR Mask */
+
+ #define MXC_F_GCR_ECCERR_SYSRAM4ECCERR_POS 4 /**< ECCERR_SYSRAM4ECCERR Position */
+ #define MXC_F_GCR_ECCERR_SYSRAM4ECCERR ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_SYSRAM4ECCERR_POS)) /**< ECCERR_SYSRAM4ECCERR Mask */
+
+/**@} end of group GCR_ECCERR_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_ECCNDED GCR_ECCNDED
+ * @brief ECC Not Double Error Detect Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS 0 /**< ECCNDED_SYSRAM0ECCNDED Position */
+ #define MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM0ECCNDED_POS)) /**< ECCNDED_SYSRAM0ECCNDED Mask */
+
+ #define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS 1 /**< ECCNDED_SYSRAM1ECCNDED Position */
+ #define MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM1ECCNDED_POS)) /**< ECCNDED_SYSRAM1ECCNDED Mask */
+
+ #define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS 2 /**< ECCNDED_SYSRAM2ECCNDED Position */
+ #define MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM2ECCNDED_POS)) /**< ECCNDED_SYSRAM2ECCNDED Mask */
+
+ #define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS 3 /**< ECCNDED_SYSRAM3ECCNDED Position */
+ #define MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM3ECCNDED_POS)) /**< ECCNDED_SYSRAM3ECCNDED Mask */
+
+ #define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS 4 /**< ECCNDED_SYSRAM4ECCNDED Position */
+ #define MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED ((uint32_t)(0x1UL << MXC_F_GCR_ECCNDED_SYSRAM4ECCNDED_POS)) /**< ECCNDED_SYSRAM4ECCNDED Mask */
+
+/**@} end of group GCR_ECCNDED_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_ECCIRQEN GCR_ECCIRQEN
+ * @brief ECC IRQ Enable Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCIRQEN_ECCERAD_POS 0 /**< ECCIRQEN_ECCERAD Position */
+ #define MXC_F_GCR_ECCIRQEN_ECCERAD ((uint32_t)(0x7FFFFFFFUL << MXC_F_GCR_ECCIRQEN_ECCERAD_POS)) /**< ECCIRQEN_ECCERAD Mask */
+
+/**@} end of group GCR_ECCIRQEN_Register */
+
+/**
+ * @ingroup gcr_registers
+ * @defgroup GCR_ECCERRAD GCR_ECCERRAD
+ * @brief ECC Error Address Register
+ * @{
+ */
+ #define MXC_F_GCR_ECCERRAD_ECCERAD_POS 0 /**< ECCERRAD_ECCERAD Position */
+ #define MXC_F_GCR_ECCERRAD_ECCERAD ((uint32_t)(0x7FFFFFFFUL << MXC_F_GCR_ECCERRAD_ECCERAD_POS)) /**< ECCERRAD_ECCERAD Mask */
+
+/**@} end of group GCR_ECCERRAD_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _GCR_REGS_H_ */
diff --git a/contrib/loaders/flash/max32xxx/max32xxx.inc b/contrib/loaders/flash/max32xxx/max32xxx.inc
deleted file mode 100644
index 826dc4461d052975d82b63ccb2e9ec151688035c..0000000000000000000000000000000000000000
--- a/contrib/loaders/flash/max32xxx/max32xxx.inc
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0xa6,0x68,0x46,0xf0,0x10,0x06,0xa6,0x60,0x15,0xf0,0x01,0x0f,0x03,0xd0,0xa6,0x68,
-0x26,0xf0,0x10,0x06,0xa6,0x60,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x55,0xd0,
-0x47,0x68,0x47,0x45,0xf7,0xd0,0x22,0x60,0x02,0xf1,0x04,0x02,0x15,0xf0,0x01,0x0f,
-0x01,0xd0,0x02,0xf1,0x0c,0x02,0x57,0xf8,0x04,0x8b,0xc4,0xf8,0x30,0x80,0x8f,0x42,
-0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,0x15,0xf0,0x01,0x0f,0x32,0xd0,0xd0,0xf8,
-0x00,0x80,0xb8,0xf1,0x00,0x0f,0x39,0xd0,0x47,0x68,0x47,0x45,0xf7,0xd0,0x57,0xf8,
-0x04,0x8b,0xc4,0xf8,0x34,0x80,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07,0x47,0x60,
-0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x28,0xd0,0x47,0x68,0x47,0x45,0xf7,0xd0,
-0x57,0xf8,0x04,0x8b,0xc4,0xf8,0x38,0x80,0x8f,0x42,0x28,0xbf,0x00,0xf1,0x08,0x07,
-0x47,0x60,0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x17,0xd0,0x47,0x68,0x47,0x45,
-0xf7,0xd0,0x57,0xf8,0x04,0x8b,0xc4,0xf8,0x3c,0x80,0x8f,0x42,0x28,0xbf,0x00,0xf1,
-0x08,0x07,0x47,0x60,0xa6,0x68,0x46,0xf0,0x01,0x06,0xa6,0x60,0xd4,0xf8,0x08,0x80,
-0x18,0xf0,0x07,0x0f,0xfa,0xd1,0x01,0x3b,0x03,0xb1,0xa4,0xe7,0xa6,0x68,0x46,0xf0,
-0x10,0x06,0xa6,0x60,0x00,0xbe,
diff --git a/contrib/loaders/flash/max32xxx/max32xxx.s b/contrib/loaders/flash/max32xxx/max32xxx.s
deleted file mode 100644
index 9dcede9d657cadb021cfbb7fe9b066ebb1863569..0000000000000000000000000000000000000000
--- a/contrib/loaders/flash/max32xxx/max32xxx.s
+++ /dev/null
@@ -1,146 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2016 by Maxim Integrated *
- * Kevin Gillespie <kevin.gillespie@maximintegrated.com *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
- ***************************************************************************/
-
-.text
-.syntax unified
-.cpu cortex-m3
-.thumb
-.thumb_func
-
-/*
- * Params :
- * r0 = workarea start
- * r1 = workarea end
- * r2 = target address
- * r3 = count (number of writes)
- * r4 = pFLASH_CTRL_BASE
- * r5 = 128-bit write
-
- * Clobbered:
- * r6 = FLASHWRITECMD
- * r7 - rp
- * r8 - wp, tmp
- */
-
-write:
-
- /* write in 32-bit units by default */
- ldr r6, [r4, #0x08] /* FLSH_CN */
- orr r6, r6, #0x10 /* Width 32 bits */
- str r6, [r4, #0x08] /* FLSH_CN */
-
- tst r5, #1 /* Check 32-bit write options */
- beq wait_fifo
-
- /* Enable 128-bit write */
- ldr r6, [r4, #0x08] /* FLSH_CN */
- bic r6, r6, #0x10 /* Width 128 bits */
- str r6, [r4, #0x08] /* FLSH_CN */
-
-wait_fifo:
- ldr r8, [r0, #0x00] /* read wp */
- cmp r8, #0x00 /* abort if wp == 0 */
- beq exit
- ldr r7, [r0, #0x04] /* read rp */
- cmp r7, r8 /* wait until rp != wp */
- beq wait_fifo
-
-mainloop:
-
- str r2, [r4, #0x00] /* FLSH_ADDR - write address */
- add r2, r2, #0x04 /* increment target address */
- tst r5, #1 /* Check 32-bit write options */
- beq inc32
- add r2, r2, #0x0C /* additional 12 if 128-bit write*/
-
-inc32:
- ldr r8, [r7], #0x04
- str r8, [r4, #0x30] /* FLSH_DATA0 - write data */
- cmp r7, r1 /* wrap rp at end of buffer */
- it cs
- addcs r7, r0, #0x08 /* skip loader args */
- str r7, [r0, #0x04] /* store rp */
-
- tst r5, #1 /* Check 32-bit write options */
- beq write32
-
-wait_fifo0:
- ldr r8, [r0, #0x00] /* read wp */
- cmp r8, #0x00 /* abort if wp == 0 */
- beq exit
- ldr r7, [r0, #0x04] /* read rp */
- cmp r7, r8 /* wait until rp != wp */
- beq wait_fifo0
-
- ldr r8, [r7], #0x04
- str r8, [r4, #0x34] /* FLSH_DATA1 - write data */
- cmp r7, r1 /* wrap rp at end of buffer */
- it cs
- addcs r7, r0, #0x08 /* skip loader args */
- str r7, [r0, #0x04] /* store rp */
-
-wait_fifo1:
- ldr r8, [r0, #0x00] /* read wp */
- cmp r8, #0x00 /* abort if wp == 0 */
- beq exit
- ldr r7, [r0, #0x04] /* read rp */
- cmp r7, r8 /* wait until rp != wp */
- beq wait_fifo1
-
- ldr r8, [r7], #0x04
- str r8, [r4, #0x38] /* FLSH_DATA2 - write data */
- cmp r7, r1 /* wrap rp at end of buffer */
- it cs
- addcs r7, r0, #0x08 /* skip loader args */
- str r7, [r0, #0x04] /* store rp */
-
-wait_fifo2:
- ldr r8, [r0, #0x00] /* read wp */
- cmp r8, #0x00 /* abort if wp == 0 */
- beq exit
- ldr r7, [r0, #0x04] /* read rp */
- cmp r7, r8 /* wait until rp != wp */
- beq wait_fifo2
-
- ldr r8, [r7], #0x04
- str r8, [r4, #0x3C] /* FLSH_DATA3 - write data */
- cmp r7, r1 /* wrap rp at end of buffer */
- it cs
- addcs r7, r0, #0x08 /* skip loader args */
- str r7, [r0, #0x04] /* store rp */
-
-write32:
- ldr r6, [r4, #0x08] /* FLSH_CN */
- orr r6, r6, #0x01 /* WE */
- str r6, [r4, #0x08] /* FLSH_CN - enable write */
-
-busy:
- ldr r8, [r4, #0x08] /* FLSH_CN */
- tst r8, #0x07
- bne busy
-
- subs r3, r3, #0x01 /* decrement write count */
- cbz r3, exit /* loop if not done */
- b wait_fifo
-
-exit:
- /* restore flash settings */
- ldr r6, [r4, #0x08] /* FLSH_CN */
- orr r6, r6, #0x10 /* Width 32 bits */
- str r6, [r4, #0x08] /* FLSH_CN */
- bkpt
diff --git a/contrib/loaders/flash/max32xxx/max32xxx_write.c b/contrib/loaders/flash/max32xxx/max32xxx_write.c
new file mode 100644
index 0000000000000000000000000000000000000000..cfdd13711b45f1da720b8b571723c17b717b3884
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/max32xxx_write.c
@@ -0,0 +1,300 @@
+/*******************************************************************************
+ * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *******************************************************************************
+ */
+
+/***** Includes *****/
+#ifdef ALGO_TEST
+#include "mxc_config.h"
+#endif
+
+#include "tpu_regs.h"
+#include "gcr_regs.h"
+#include "flc_regs.h"
+#include "algo_options.h"
+
+#ifdef ALGO_TEST
+#include <stdio.h>
+#else
+#define printf(...)
+#endif
+
+/***** Definitions *****/
+#define MXC_BASE_TPU ((uint32_t)0x40001000UL)
+#define MXC_TPU ((mxc_tpu_regs_t*)MXC_BASE_TPU)
+#define MXC_BASE_GCR ((uint32_t)0x40000000UL)
+#define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
+#define MXC_BASE_FLC ((uint32_t)0x40029000UL)
+#define MXC_FLC ((mxc_flc_regs_t*)MXC_BASE_FLC)
+
+/******************************************************************************/
+#define getbyte(temp8) \
+ /* Wait for the Read FIFO to not equal the Write FIFO */ \
+ while (*read_ptr == *write_ptr); \
+ temp8 = **read_ptr; \
+ \
+ /* Increment and wrap around the read pointer */ \
+ if ((*read_ptr + 1) >= (uint8_t*)(work_end - 4 - 256)) { \
+ *read_ptr = (uint8_t *)(work_start + 8); \
+ } else { \
+ (*read_ptr)++; \
+ } \
+ len--; \
+ addr++;
+
+/******************************************************************************/
+#ifndef ALGO_TEST
+__attribute__ ((naked, section(".algo")))
+#endif
+void algo_write(uint8_t *work_start, uint8_t *work_end, uint32_t len, uint32_t addr)
+{
+
+ printf(" > algo_write() starting\n");
+
+ uint8_t * volatile *write_ptr = (uint8_t **)work_start;
+ uint8_t * volatile *read_ptr = (uint8_t **)(work_start + 4);
+ uint32_t options = *(uint32_t *)(work_end - 4 - 128);
+ uint32_t *enc_buffer = (uint32_t *)(work_end - 4 - 256);
+ uint8_t temp8;
+ uint32_t addr_save;
+ int i;
+
+ printf(" > w%08x r%08x o%08x b%08x b%08x\n",
+ (uint32_t)write_ptr, (uint32_t)read_ptr, (uint32_t)options, (uint32_t)enc_buffer, (uint32_t)(enc_buffer + 256));
+
+ if(options & OPTIONS_ENC) {
+ // Setup the AES
+
+ /* Enable CRYPTO clock */
+ if ((MXC_GCR->clkcn & MXC_F_GCR_CLKCN_HIRC_EN) == 0) {
+ MXC_GCR->clkcn |= MXC_F_GCR_CLKCN_HIRC_EN;
+ }
+
+ /* Disable CRYPTO clock gate */
+ if (MXC_GCR->perckcn0 & MXC_F_GCR_PERCKCN0_CRYPTOD) {
+ MXC_GCR->perckcn0 &= ~(MXC_F_GCR_PERCKCN0_CRYPTOD);
+ }
+
+ // Reset Crypto block and clear state
+ MXC_TPU->ctrl = MXC_F_TPU_CTRL_RST;
+
+ // Set the legacy bit
+ MXC_TPU->ctrl |= MXC_F_TPU_CTRL_FLAG_MODE;
+
+ // Byte swap the input and output
+ MXC_TPU->ctrl |= MXC_F_TPU_CTRL_BSO;
+ MXC_TPU->ctrl |= MXC_F_TPU_CTRL_BSI;
+ }
+
+ while(len) {
+
+ if((options & OPTIONS_128) == 0) {
+
+ // Save the current address before we read from the working area
+ addr_save = addr;
+
+ // 32-bit write
+ MXC_FLC->cn |= MXC_F_FLC_CN_WDTH;
+
+ enc_buffer[0] = 0;
+ for(i = 0; i < 4; i++) {
+ // Get data from the working area, pad with 0xFF
+ if(len) {
+ getbyte(temp8);
+ } else {
+ temp8 = 0xFF;
+ }
+ enc_buffer[0] |= (temp8 << (i*8));
+ }
+
+ // Unlock the flash
+ MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) | MXC_S_FLC_CN_UNLOCK_UNLOCKED;
+
+ MXC_FLC->addr = addr_save;
+ MXC_FLC->data[0] = enc_buffer[0];
+
+ // Enable the write
+ MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+ // Wait for the operation to complete
+ while(MXC_FLC->cn & MXC_F_FLC_CN_WR) {}
+
+ /* Lock flash */
+ MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+ /* Check access violations */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+ #ifndef ALGO_TEST
+ __asm("bkpt\n");
+ #else
+ printf(" > Error writing to flash\n");
+ return;
+ #endif
+ }
+ } else {
+
+ // Save the current address before we read from the working area
+ addr_save = addr;
+
+ // Fill the buffer with the plain text data from the working area
+ for(i = 0; i < 4; i++) {
+ // Get data from the working area, pad with 0xFF
+ enc_buffer[i] = 0;
+ if(len) {
+ getbyte(temp8);
+ } else {
+ temp8 = 0xFF;
+ }
+ enc_buffer[i] |= (temp8 << (0));
+ // Get data from the working area, pad with 0xFF
+ if(len) {
+ getbyte(temp8);
+ } else {
+ temp8 = 0xFF;
+ }
+ enc_buffer[i] |= (temp8 << (8));
+ // Get data from the working area, pad with 0xFF
+ if(len) {
+ getbyte(temp8);
+ } else {
+ temp8 = 0xFF;
+ }
+ enc_buffer[i] |= (temp8 << (16));
+ // Get data from the working area, pad with 0xFF
+ if(len) {
+ getbyte(temp8);
+ } else {
+ temp8 = 0xFF;
+ }
+ enc_buffer[i] |= (temp8 << (24));
+ }
+
+ if(options & OPTIONS_ENC) {
+
+ // XOR data with the address
+ for(i = 0; i < 4; i++) {
+ if(options & OPTIONS_RELATIVE_XOR) {
+ enc_buffer[i] ^= ((addr_save & 0x00FFFFFF) + i*4);
+ } else {
+ enc_buffer[i] ^= (addr_save + i*4);
+ }
+ }
+
+ // Encrypt the plain text
+ // Clear interrupt flags
+ MXC_TPU->ctrl |= MXC_F_TPU_CTRL_CPH_DONE;
+
+ MXC_TPU->cipher_ctrl = ((0x0 << MXC_F_TPU_CIPHER_CTRL_MODE_POS) |
+ (0x0 << MXC_F_TPU_CIPHER_CTRL_ENC_POS));
+
+ if(options & OPTIONS_KEYSIZE) {
+ // ECB, AES-256, encrypt
+ MXC_TPU->cipher_ctrl |= (0x3 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS);
+ } else {
+ // ECB, AES-128, encrypt
+ MXC_TPU->cipher_ctrl |= (0x1 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS);
+ }
+
+ // Set the key source
+ MXC_TPU->cipher_ctrl = ((MXC_TPU->cipher_ctrl & ~MXC_F_TPU_CIPHER_CTRL_SRC) |
+ (0x3 << MXC_F_TPU_CIPHER_CTRL_SRC_POS));
+
+ // Copy data to start the operation
+ MXC_TPU->din[0] = enc_buffer[0];
+ MXC_TPU->din[1] = enc_buffer[1];
+ MXC_TPU->din[2] = enc_buffer[2];
+ MXC_TPU->din[3] = enc_buffer[3];
+
+ // Wait until operation is complete
+ while(!(MXC_TPU->ctrl & MXC_F_TPU_CTRL_CPH_DONE)) {}
+
+ // Copy the data out
+ enc_buffer[0] = MXC_TPU->dout[0];
+ enc_buffer[1] = MXC_TPU->dout[1];
+ enc_buffer[2] = MXC_TPU->dout[2];
+ enc_buffer[3] = MXC_TPU->dout[3];
+ }
+
+ // Unlock the flash
+ MXC_FLC->cn = (MXC_FLC->cn & ~MXC_F_FLC_CN_UNLOCK) | MXC_S_FLC_CN_UNLOCK_UNLOCKED;
+
+ // 128-bit write
+ MXC_FLC->cn &= ~MXC_F_FLC_CN_WDTH;
+
+ MXC_FLC->addr = addr_save;
+ MXC_FLC->data[0] = enc_buffer[0];
+ MXC_FLC->data[1] = enc_buffer[1];
+ MXC_FLC->data[2] = enc_buffer[2];
+ MXC_FLC->data[3] = enc_buffer[3];
+
+ // Enable the write
+ MXC_FLC->cn |= MXC_F_FLC_CN_WR;
+
+ // Wait for the operation to complete
+ while(MXC_FLC->cn & MXC_F_FLC_CN_WR) {}
+
+ /* Lock flash */
+ MXC_FLC->cn &= ~MXC_F_FLC_CN_UNLOCK;
+
+ /* Check access violations */
+ if (MXC_FLC->intr & MXC_F_FLC_INTR_AF) {
+ MXC_FLC->intr &= ~MXC_F_FLC_INTR_AF;
+ #ifndef ALGO_TEST
+ __asm("bkpt\n");
+ #else
+ printf(" > Error writing to flash\n");
+ return;
+ #endif
+ }
+ }
+ }
+
+ if(options & OPTIONS_ENC) {
+ /* Setup the memory protection */
+ MXC_GCR->scon |= MXC_F_GCR_SCON_MEMPROT_EN;
+
+ /* Set the keysize */
+ if(options & OPTIONS_KEYSIZE) {
+ MXC_GCR->scon |= MXC_F_GCR_SCON_MEMPROT_KEYSZ;
+ } else {
+ MXC_GCR->scon &= ~(MXC_F_GCR_SCON_MEMPROT_KEYSZ);
+ }
+ }
+
+ #ifndef ALGO_TEST
+ __asm("bkpt\n");
+ #else
+ printf(" > algo_write returning\n");
+ return;
+ #endif
+}
diff --git a/contrib/loaders/flash/max32xxx/max32xxx_write.inc b/contrib/loaders/flash/max32xxx/max32xxx_write.inc
new file mode 100644
index 0000000000000000000000000000000000000000..4f4f904520d2aacc34eab1ff1febcd8d59147513
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/max32xxx_write.inc
@@ -0,0 +1,58 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
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diff --git a/contrib/loaders/flash/max32xxx/tpu_regs.h b/contrib/loaders/flash/max32xxx/tpu_regs.h
new file mode 100644
index 0000000000000000000000000000000000000000..7f95de1e6e316f37a2298e52f136fdb8bba19322
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/tpu_regs.h
@@ -0,0 +1,562 @@
+/**
+ * @file tpu_regs.h
+ * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module.
+ */
+
+/* ****************************************************************************
+ * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *
+ *
+ *************************************************************************** */
+
+#ifndef _TPU_REGS_H_
+#define _TPU_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined (__ICCARM__)
+ #pragma system_include
+#endif
+
+/// @cond
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/// @endcond
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup tpu
+ * @defgroup tpu_registers Registers
+ * @brief Registers, Bit Masks and Bit Positions for the TPU Peripheral Module.
+ * @description The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms.
+ */
+
+/**
+ * @ingroup tpu_registers
+ * Structure type to access the TPU Registers.
+ */
+typedef struct {
+ __IO uint32_t ctrl; /**< <tt>\b 0x00:<\tt> TPU CTRL Register */
+ __IO uint32_t cipher_ctrl; /**< <tt>\b 0x04:<\tt> TPU CIPHER_CTRL Register */
+ __IO uint32_t hash_ctrl; /**< <tt>\b 0x08:<\tt> TPU HASH_CTRL Register */
+ __IO uint32_t crc_ctrl; /**< <tt>\b 0x0C:<\tt> TPU CRC_CTRL Register */
+ __IO uint32_t dma_src; /**< <tt>\b 0x10:<\tt> TPU DMA_SRC Register */
+ __IO uint32_t dma_dest; /**< <tt>\b 0x14:<\tt> TPU DMA_DEST Register */
+ __IO uint32_t dma_cnt; /**< <tt>\b 0x18:<\tt> TPU DMA_CNT Register */
+ __IO uint32_t maa_ctrl; /**< <tt>\b 0x1C:<\tt> TPU MAA_CTRL Register */
+ __O uint32_t din[4]; /**< <tt>\b 0x20:<\tt> TPU DIN Register */
+ __I uint32_t dout[4]; /**< <tt>\b 0x30:<\tt> TPU DOUT Register */
+ __IO uint32_t crc_poly; /**< <tt>\b 0x40:<\tt> TPU CRC_POLY Register */
+ __IO uint32_t crc_val; /**< <tt>\b 0x44:<\tt> TPU CRC_VAL Register */
+ __I uint32_t crc_prng; /**< <tt>\b 0x48:<\tt> TPU CRC_PRNG Register */
+ __IO uint32_t ham_ecc; /**< <tt>\b 0x4C:<\tt> TPU HAM_ECC Register */
+ __IO uint32_t cipher_init[4]; /**< <tt>\b 0x50:<\tt> TPU CIPHER_INIT Register */
+ __O uint32_t cipher_key[8]; /**< <tt>\b 0x60:<\tt> TPU CIPHER_KEY Register */
+ __IO uint32_t hash_digest[16]; /**< <tt>\b 0x80:<\tt> TPU HASH_DIGEST Register */
+ __IO uint32_t hash_msg_sz[4]; /**< <tt>\b 0xC0:<\tt> TPU HASH_MSG_SZ Register */
+ __IO uint32_t maa_maws; /**< <tt>\b 0xD0:<\tt> TPU MAA_MAWS Register */
+} mxc_tpu_regs_t;
+
+/* Register offsets for module TPU */
+/**
+ * @ingroup tpu_registers
+ * @defgroup TPU_Register_Offsets Register Offsets
+ * @brief TPU Peripheral Register Offsets from the TPU Base Peripheral Address.
+ * @{
+ */
+ #define MXC_R_TPU_CTRL ((uint32_t)0x00000000UL) /**< Offset from TPU Base Address: <tt> 0x0x000 */
+ #define MXC_R_TPU_CIPHER_CTRL ((uint32_t)0x00000004UL) /**< Offset from TPU Base Address: <tt> 0x0x004 */
+ #define MXC_R_TPU_HASH_CTRL ((uint32_t)0x00000008UL) /**< Offset from TPU Base Address: <tt> 0x0x008 */
+ #define MXC_R_TPU_CRC_CTRL ((uint32_t)0x0000000CUL) /**< Offset from TPU Base Address: <tt> 0x0x00C */
+ #define MXC_R_TPU_DMA_SRC ((uint32_t)0x00000010UL) /**< Offset from TPU Base Address: <tt> 0x0x010 */
+ #define MXC_R_TPU_DMA_DEST ((uint32_t)0x00000014UL) /**< Offset from TPU Base Address: <tt> 0x0x014 */
+ #define MXC_R_TPU_DMA_CNT ((uint32_t)0x00000018UL) /**< Offset from TPU Base Address: <tt> 0x0x018 */
+ #define MXC_R_TPU_MAA_CTRL ((uint32_t)0x0000001CUL) /**< Offset from TPU Base Address: <tt> 0x0x01C */
+ #define MXC_R_TPU_DIN ((uint32_t)0x00000020UL) /**< Offset from TPU Base Address: <tt> 0x0x020 */
+ #define MXC_R_TPU_DOUT ((uint32_t)0x00000030UL) /**< Offset from TPU Base Address: <tt> 0x0x030 */
+ #define MXC_R_TPU_CRC_POLY ((uint32_t)0x00000040UL) /**< Offset from TPU Base Address: <tt> 0x0x040 */
+ #define MXC_R_TPU_CRC_VAL ((uint32_t)0x00000044UL) /**< Offset from TPU Base Address: <tt> 0x0x044 */
+ #define MXC_R_TPU_CRC_PRNG ((uint32_t)0x00000048UL) /**< Offset from TPU Base Address: <tt> 0x0x048 */
+ #define MXC_R_TPU_HAM_ECC ((uint32_t)0x0000004CUL) /**< Offset from TPU Base Address: <tt> 0x0x04C */
+ #define MXC_R_TPU_CIPHER_INIT ((uint32_t)0x00000050UL) /**< Offset from TPU Base Address: <tt> 0x0x050 */
+ #define MXC_R_TPU_CIPHER_KEY ((uint32_t)0x00000060UL) /**< Offset from TPU Base Address: <tt> 0x0x060 */
+ #define MXC_R_TPU_HASH_DIGEST ((uint32_t)0x00000080UL) /**< Offset from TPU Base Address: <tt> 0x0x080 */
+ #define MXC_R_TPU_HASH_MSG_SZ ((uint32_t)0x000000C0UL) /**< Offset from TPU Base Address: <tt> 0x0x0C0 */
+ #define MXC_R_TPU_MAA_MAWS ((uint32_t)0x000000D0UL) /**< Offset from TPU Base Address: <tt> 0x0x0D0 */
+/**@} end of group tpu_registers */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CTRL_Register
+ * @brief Crypto Control Register.
+ * @{
+ */
+ #define MXC_F_TPU_CTRL_RST_POS 0 /**< CTRL_RST Position */
+ #define MXC_F_TPU_CTRL_RST ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RST_POS)) /**< CTRL_RST Mask */
+
+ #define MXC_F_TPU_CTRL_INTR_POS 1 /**< CTRL_INTR Position */
+ #define MXC_F_TPU_CTRL_INTR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_INTR_POS)) /**< CTRL_INTR Mask */
+
+ #define MXC_F_TPU_CTRL_SRC_POS 2 /**< CTRL_SRC Position */
+ #define MXC_F_TPU_CTRL_SRC ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_SRC_POS)) /**< CTRL_SRC Mask */
+
+ #define MXC_F_TPU_CTRL_BSO_POS 4 /**< CTRL_BSO Position */
+ #define MXC_F_TPU_CTRL_BSO ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSO_POS)) /**< CTRL_BSO Mask */
+
+ #define MXC_F_TPU_CTRL_BSI_POS 5 /**< CTRL_BSI Position */
+ #define MXC_F_TPU_CTRL_BSI ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_BSI_POS)) /**< CTRL_BSI Mask */
+
+ #define MXC_F_TPU_CTRL_WAIT_EN_POS 6 /**< CTRL_WAIT_EN Position */
+ #define MXC_F_TPU_CTRL_WAIT_EN ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_EN_POS)) /**< CTRL_WAIT_EN Mask */
+
+ #define MXC_F_TPU_CTRL_WAIT_POL_POS 7 /**< CTRL_WAIT_POL Position */
+ #define MXC_F_TPU_CTRL_WAIT_POL ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_WAIT_POL_POS)) /**< CTRL_WAIT_POL Mask */
+
+ #define MXC_F_TPU_CTRL_WRSRC_POS 8 /**< CTRL_WRSRC Position */
+ #define MXC_F_TPU_CTRL_WRSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_WRSRC_POS)) /**< CTRL_WRSRC Mask */
+ #define MXC_V_TPU_CTRL_WRSRC_NONE ((uint32_t)0x0UL) /**< CTRL_WRSRC_NONE Value */
+ #define MXC_S_TPU_CTRL_WRSRC_NONE (MXC_V_TPU_CTRL_WRSRC_NONE << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_NONE Setting */
+ #define MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT ((uint32_t)0x1UL) /**< CTRL_WRSRC_CIPHEROUTPUT Value */
+ #define MXC_S_TPU_CTRL_WRSRC_CIPHEROUTPUT (MXC_V_TPU_CTRL_WRSRC_CIPHEROUTPUT << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_CIPHEROUTPUT Setting */
+ #define MXC_V_TPU_CTRL_WRSRC_READFIFO ((uint32_t)0x2UL) /**< CTRL_WRSRC_READFIFO Value */
+ #define MXC_S_TPU_CTRL_WRSRC_READFIFO (MXC_V_TPU_CTRL_WRSRC_READFIFO << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_READFIFO Setting */
+ #define MXC_V_TPU_CTRL_WRSRC_RFU ((uint32_t)0x3UL) /**< CTRL_WRSRC_RFU Value */
+ #define MXC_S_TPU_CTRL_WRSRC_RFU (MXC_V_TPU_CTRL_WRSRC_RFU << MXC_F_TPU_CTRL_WRSRC_POS) /**< CTRL_WRSRC_RFU Setting */
+
+ #define MXC_F_TPU_CTRL_RDSRC_POS 10 /**< CTRL_RDSRC Position */
+ #define MXC_F_TPU_CTRL_RDSRC ((uint32_t)(0x3UL << MXC_F_TPU_CTRL_RDSRC_POS)) /**< CTRL_RDSRC Mask */
+ #define MXC_V_TPU_CTRL_RDSRC_DMADISABLED ((uint32_t)0x0UL) /**< CTRL_RDSRC_DMADISABLED Value */
+ #define MXC_S_TPU_CTRL_RDSRC_DMADISABLED (MXC_V_TPU_CTRL_RDSRC_DMADISABLED << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMADISABLED Setting */
+ #define MXC_V_TPU_CTRL_RDSRC_DMAORAPB ((uint32_t)0x1UL) /**< CTRL_RDSRC_DMAORAPB Value */
+ #define MXC_S_TPU_CTRL_RDSRC_DMAORAPB (MXC_V_TPU_CTRL_RDSRC_DMAORAPB << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_DMAORAPB Setting */
+ #define MXC_V_TPU_CTRL_RDSRC_RNG ((uint32_t)0x2UL) /**< CTRL_RDSRC_RNG Value */
+ #define MXC_S_TPU_CTRL_RDSRC_RNG (MXC_V_TPU_CTRL_RDSRC_RNG << MXC_F_TPU_CTRL_RDSRC_POS) /**< CTRL_RDSRC_RNG Setting */
+
+ #define MXC_F_TPU_CTRL_FLAG_MODE_POS 14 /**< CTRL_FLAG_MODE Position */
+ #define MXC_F_TPU_CTRL_FLAG_MODE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_FLAG_MODE_POS)) /**< CTRL_FLAG_MODE Mask */
+
+ #define MXC_F_TPU_CTRL_DMADNEMSK_POS 15 /**< CTRL_DMADNEMSK Position */
+ #define MXC_F_TPU_CTRL_DMADNEMSK ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMADNEMSK_POS)) /**< CTRL_DMADNEMSK Mask */
+
+ #define MXC_F_TPU_CTRL_DMA_DONE_POS 24 /**< CTRL_DMA_DONE Position */
+ #define MXC_F_TPU_CTRL_DMA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DMA_DONE_POS)) /**< CTRL_DMA_DONE Mask */
+
+ #define MXC_F_TPU_CTRL_GLS_DONE_POS 25 /**< CTRL_GLS_DONE Position */
+ #define MXC_F_TPU_CTRL_GLS_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_GLS_DONE_POS)) /**< CTRL_GLS_DONE Mask */
+
+ #define MXC_F_TPU_CTRL_HSH_DONE_POS 26 /**< CTRL_HSH_DONE Position */
+ #define MXC_F_TPU_CTRL_HSH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_HSH_DONE_POS)) /**< CTRL_HSH_DONE Mask */
+
+ #define MXC_F_TPU_CTRL_CPH_DONE_POS 27 /**< CTRL_CPH_DONE Position */
+ #define MXC_F_TPU_CTRL_CPH_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_CPH_DONE_POS)) /**< CTRL_CPH_DONE Mask */
+
+ #define MXC_F_TPU_CTRL_MAA_DONE_POS 28 /**< CTRL_MAA_DONE Position */
+ #define MXC_F_TPU_CTRL_MAA_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_MAA_DONE_POS)) /**< CTRL_MAA_DONE Mask */
+
+ #define MXC_F_TPU_CTRL_ERR_POS 29 /**< CTRL_ERR Position */
+ #define MXC_F_TPU_CTRL_ERR ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_ERR_POS)) /**< CTRL_ERR Mask */
+
+ #define MXC_F_TPU_CTRL_RDY_POS 30 /**< CTRL_RDY Position */
+ #define MXC_F_TPU_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_RDY_POS)) /**< CTRL_RDY Mask */
+
+ #define MXC_F_TPU_CTRL_DONE_POS 31 /**< CTRL_DONE Position */
+ #define MXC_F_TPU_CTRL_DONE ((uint32_t)(0x1UL << MXC_F_TPU_CTRL_DONE_POS)) /**< CTRL_DONE Mask */
+
+/**@} end of group CTRL_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CIPHER_CTRL_Register
+ * @brief Cipher Control Register.
+ * @{
+ */
+ #define MXC_F_TPU_CIPHER_CTRL_ENC_POS 0 /**< CIPHER_CTRL_ENC Position */
+ #define MXC_F_TPU_CIPHER_CTRL_ENC ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_ENC_POS)) /**< CIPHER_CTRL_ENC Mask */
+
+ #define MXC_F_TPU_CIPHER_CTRL_KEY_POS 1 /**< CIPHER_CTRL_KEY Position */
+ #define MXC_F_TPU_CIPHER_CTRL_KEY ((uint32_t)(0x1UL << MXC_F_TPU_CIPHER_CTRL_KEY_POS)) /**< CIPHER_CTRL_KEY Mask */
+
+ #define MXC_F_TPU_CIPHER_CTRL_SRC_POS 2 /**< CIPHER_CTRL_SRC Position */
+ #define MXC_F_TPU_CIPHER_CTRL_SRC ((uint32_t)(0x3UL << MXC_F_TPU_CIPHER_CTRL_SRC_POS)) /**< CIPHER_CTRL_SRC Mask */
+ #define MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY ((uint32_t)0x0UL) /**< CIPHER_CTRL_SRC_CIPHERKEY Value */
+ #define MXC_S_TPU_CIPHER_CTRL_SRC_CIPHERKEY (MXC_V_TPU_CIPHER_CTRL_SRC_CIPHERKEY << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_CIPHERKEY Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE ((uint32_t)0x2UL) /**< CIPHER_CTRL_SRC_REGFILE Value */
+ #define MXC_S_TPU_CIPHER_CTRL_SRC_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_REGFILE Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE ((uint32_t)0x3UL) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Value */
+ #define MXC_S_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE (MXC_V_TPU_CIPHER_CTRL_SRC_QSPIKEY_REGFILE << MXC_F_TPU_CIPHER_CTRL_SRC_POS) /**< CIPHER_CTRL_SRC_QSPIKEY_REGFILE Setting */
+
+ #define MXC_F_TPU_CIPHER_CTRL_CIPHER_POS 4 /**< CIPHER_CTRL_CIPHER Position */
+ #define MXC_F_TPU_CIPHER_CTRL_CIPHER ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS)) /**< CIPHER_CTRL_CIPHER Mask */
+ #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS ((uint32_t)0x0UL) /**< CIPHER_CTRL_CIPHER_DIS Value */
+ #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DIS (MXC_V_TPU_CIPHER_CTRL_CIPHER_DIS << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DIS Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 ((uint32_t)0x1UL) /**< CIPHER_CTRL_CIPHER_AES128 Value */
+ #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES128 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES128 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES128 Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 ((uint32_t)0x2UL) /**< CIPHER_CTRL_CIPHER_AES192 Value */
+ #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES192 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES192 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES192 Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 ((uint32_t)0x3UL) /**< CIPHER_CTRL_CIPHER_AES256 Value */
+ #define MXC_S_TPU_CIPHER_CTRL_CIPHER_AES256 (MXC_V_TPU_CIPHER_CTRL_CIPHER_AES256 << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_AES256 Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_CIPHER_DES ((uint32_t)0x4UL) /**< CIPHER_CTRL_CIPHER_DES Value */
+ #define MXC_S_TPU_CIPHER_CTRL_CIPHER_DES (MXC_V_TPU_CIPHER_CTRL_CIPHER_DES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_DES Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES ((uint32_t)0x5UL) /**< CIPHER_CTRL_CIPHER_TDES Value */
+ #define MXC_S_TPU_CIPHER_CTRL_CIPHER_TDES (MXC_V_TPU_CIPHER_CTRL_CIPHER_TDES << MXC_F_TPU_CIPHER_CTRL_CIPHER_POS) /**< CIPHER_CTRL_CIPHER_TDES Setting */
+
+ #define MXC_F_TPU_CIPHER_CTRL_MODE_POS 8 /**< CIPHER_CTRL_MODE Position */
+ #define MXC_F_TPU_CIPHER_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TPU_CIPHER_CTRL_MODE_POS)) /**< CIPHER_CTRL_MODE Mask */
+ #define MXC_V_TPU_CIPHER_CTRL_MODE_ECB ((uint32_t)0x0UL) /**< CIPHER_CTRL_MODE_ECB Value */
+ #define MXC_S_TPU_CIPHER_CTRL_MODE_ECB (MXC_V_TPU_CIPHER_CTRL_MODE_ECB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_ECB Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_MODE_CBC ((uint32_t)0x1UL) /**< CIPHER_CTRL_MODE_CBC Value */
+ #define MXC_S_TPU_CIPHER_CTRL_MODE_CBC (MXC_V_TPU_CIPHER_CTRL_MODE_CBC << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CBC Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_MODE_CFB ((uint32_t)0x2UL) /**< CIPHER_CTRL_MODE_CFB Value */
+ #define MXC_S_TPU_CIPHER_CTRL_MODE_CFB (MXC_V_TPU_CIPHER_CTRL_MODE_CFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CFB Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_MODE_OFB ((uint32_t)0x3UL) /**< CIPHER_CTRL_MODE_OFB Value */
+ #define MXC_S_TPU_CIPHER_CTRL_MODE_OFB (MXC_V_TPU_CIPHER_CTRL_MODE_OFB << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_OFB Setting */
+ #define MXC_V_TPU_CIPHER_CTRL_MODE_CTR ((uint32_t)0x4UL) /**< CIPHER_CTRL_MODE_CTR Value */
+ #define MXC_S_TPU_CIPHER_CTRL_MODE_CTR (MXC_V_TPU_CIPHER_CTRL_MODE_CTR << MXC_F_TPU_CIPHER_CTRL_MODE_POS) /**< CIPHER_CTRL_MODE_CTR Setting */
+
+/**@} end of group CIPHER_CTRL_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup HASH_CTRL_Register
+ * @brief HASH Control Register.
+ * @{
+ */
+ #define MXC_F_TPU_HASH_CTRL_INIT_POS 0 /**< HASH_CTRL_INIT Position */
+ #define MXC_F_TPU_HASH_CTRL_INIT ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_INIT_POS)) /**< HASH_CTRL_INIT Mask */
+
+ #define MXC_F_TPU_HASH_CTRL_XOR_POS 1 /**< HASH_CTRL_XOR Position */
+ #define MXC_F_TPU_HASH_CTRL_XOR ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_XOR_POS)) /**< HASH_CTRL_XOR Mask */
+
+ #define MXC_F_TPU_HASH_CTRL_HASH_POS 2 /**< HASH_CTRL_HASH Position */
+ #define MXC_F_TPU_HASH_CTRL_HASH ((uint32_t)(0x7UL << MXC_F_TPU_HASH_CTRL_HASH_POS)) /**< HASH_CTRL_HASH Mask */
+ #define MXC_V_TPU_HASH_CTRL_HASH_DIS ((uint32_t)0x0UL) /**< HASH_CTRL_HASH_DIS Value */
+ #define MXC_S_TPU_HASH_CTRL_HASH_DIS (MXC_V_TPU_HASH_CTRL_HASH_DIS << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_DIS Setting */
+ #define MXC_V_TPU_HASH_CTRL_HASH_SHA1 ((uint32_t)0x1UL) /**< HASH_CTRL_HASH_SHA1 Value */
+ #define MXC_S_TPU_HASH_CTRL_HASH_SHA1 (MXC_V_TPU_HASH_CTRL_HASH_SHA1 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA1 Setting */
+ #define MXC_V_TPU_HASH_CTRL_HASH_SHA224 ((uint32_t)0x2UL) /**< HASH_CTRL_HASH_SHA224 Value */
+ #define MXC_S_TPU_HASH_CTRL_HASH_SHA224 (MXC_V_TPU_HASH_CTRL_HASH_SHA224 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA224 Setting */
+ #define MXC_V_TPU_HASH_CTRL_HASH_SHA256 ((uint32_t)0x3UL) /**< HASH_CTRL_HASH_SHA256 Value */
+ #define MXC_S_TPU_HASH_CTRL_HASH_SHA256 (MXC_V_TPU_HASH_CTRL_HASH_SHA256 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA256 Setting */
+ #define MXC_V_TPU_HASH_CTRL_HASH_SHA384 ((uint32_t)0x4UL) /**< HASH_CTRL_HASH_SHA384 Value */
+ #define MXC_S_TPU_HASH_CTRL_HASH_SHA384 (MXC_V_TPU_HASH_CTRL_HASH_SHA384 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA384 Setting */
+ #define MXC_V_TPU_HASH_CTRL_HASH_SHA512 ((uint32_t)0x5UL) /**< HASH_CTRL_HASH_SHA512 Value */
+ #define MXC_S_TPU_HASH_CTRL_HASH_SHA512 (MXC_V_TPU_HASH_CTRL_HASH_SHA512 << MXC_F_TPU_HASH_CTRL_HASH_POS) /**< HASH_CTRL_HASH_SHA512 Setting */
+
+ #define MXC_F_TPU_HASH_CTRL_LAST_POS 5 /**< HASH_CTRL_LAST Position */
+ #define MXC_F_TPU_HASH_CTRL_LAST ((uint32_t)(0x1UL << MXC_F_TPU_HASH_CTRL_LAST_POS)) /**< HASH_CTRL_LAST Mask */
+
+/**@} end of group HASH_CTRL_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CRC_CTRL_Register
+ * @brief CRC Control Register.
+ * @{
+ */
+ #define MXC_F_TPU_CRC_CTRL_CRC_POS 0 /**< CRC_CTRL_CRC Position */
+ #define MXC_F_TPU_CRC_CTRL_CRC ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_CRC_POS)) /**< CRC_CTRL_CRC Mask */
+
+ #define MXC_F_TPU_CRC_CTRL_MSB_POS 1 /**< CRC_CTRL_MSB Position */
+ #define MXC_F_TPU_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_MSB_POS)) /**< CRC_CTRL_MSB Mask */
+
+ #define MXC_F_TPU_CRC_CTRL_PRNG_POS 2 /**< CRC_CTRL_PRNG Position */
+ #define MXC_F_TPU_CRC_CTRL_PRNG ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_PRNG_POS)) /**< CRC_CTRL_PRNG Mask */
+
+ #define MXC_F_TPU_CRC_CTRL_ENT_POS 3 /**< CRC_CTRL_ENT Position */
+ #define MXC_F_TPU_CRC_CTRL_ENT ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_ENT_POS)) /**< CRC_CTRL_ENT Mask */
+
+ #define MXC_F_TPU_CRC_CTRL_HAM_POS 4 /**< CRC_CTRL_HAM Position */
+ #define MXC_F_TPU_CRC_CTRL_HAM ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HAM_POS)) /**< CRC_CTRL_HAM Mask */
+
+ #define MXC_F_TPU_CRC_CTRL_HRST_POS 5 /**< CRC_CTRL_HRST Position */
+ #define MXC_F_TPU_CRC_CTRL_HRST ((uint32_t)(0x1UL << MXC_F_TPU_CRC_CTRL_HRST_POS)) /**< CRC_CTRL_HRST Mask */
+
+/**@} end of group CRC_CTRL_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup DMA_SRC_Register
+ * @brief Crypto DMA Source Address.
+ * @{
+ */
+ #define MXC_F_TPU_DMA_SRC_ADDR_POS 0 /**< DMA_SRC_ADDR Position */
+ #define MXC_F_TPU_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_SRC_ADDR_POS)) /**< DMA_SRC_ADDR Mask */
+
+/**@} end of group DMA_SRC_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup DMA_DEST_Register
+ * @brief Crypto DMA Destination Address.
+ * @{
+ */
+ #define MXC_F_TPU_DMA_DEST_ADDR_POS 0 /**< DMA_DEST_ADDR Position */
+ #define MXC_F_TPU_DMA_DEST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_DEST_ADDR_POS)) /**< DMA_DEST_ADDR Mask */
+
+/**@} end of group DMA_DEST_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup DMA_CNT_Register
+ * @brief Crypto DMA Byte Count.
+ * @{
+ */
+ #define MXC_F_TPU_DMA_CNT_ADDR_POS 0 /**< DMA_CNT_ADDR Position */
+ #define MXC_F_TPU_DMA_CNT_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DMA_CNT_ADDR_POS)) /**< DMA_CNT_ADDR Mask */
+
+/**@} end of group DMA_CNT_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup MAA_CTRL_Register
+ * @brief MAA Control Register.
+ * @{
+ */
+ #define MXC_F_TPU_MAA_CTRL_STC_POS 0 /**< MAA_CTRL_STC Position */
+ #define MXC_F_TPU_MAA_CTRL_STC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_STC_POS)) /**< MAA_CTRL_STC Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_CLC_POS 1 /**< MAA_CTRL_CLC Position */
+ #define MXC_F_TPU_MAA_CTRL_CLC ((uint32_t)(0x7UL << MXC_F_TPU_MAA_CTRL_CLC_POS)) /**< MAA_CTRL_CLC Mask */
+ #define MXC_V_TPU_MAA_CTRL_CLC_EXP ((uint32_t)0x0UL) /**< MAA_CTRL_CLC_EXP Value */
+ #define MXC_S_TPU_MAA_CTRL_CLC_EXP (MXC_V_TPU_MAA_CTRL_CLC_EXP << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_EXP Setting */
+ #define MXC_V_TPU_MAA_CTRL_CLC_SQ ((uint32_t)0x1UL) /**< MAA_CTRL_CLC_SQ Value */
+ #define MXC_S_TPU_MAA_CTRL_CLC_SQ (MXC_V_TPU_MAA_CTRL_CLC_SQ << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQ Setting */
+ #define MXC_V_TPU_MAA_CTRL_CLC_MUL ((uint32_t)0x2UL) /**< MAA_CTRL_CLC_MUL Value */
+ #define MXC_S_TPU_MAA_CTRL_CLC_MUL (MXC_V_TPU_MAA_CTRL_CLC_MUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_MUL Setting */
+ #define MXC_V_TPU_MAA_CTRL_CLC_SQMUL ((uint32_t)0x3UL) /**< MAA_CTRL_CLC_SQMUL Value */
+ #define MXC_S_TPU_MAA_CTRL_CLC_SQMUL (MXC_V_TPU_MAA_CTRL_CLC_SQMUL << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SQMUL Setting */
+ #define MXC_V_TPU_MAA_CTRL_CLC_ADD ((uint32_t)0x4UL) /**< MAA_CTRL_CLC_ADD Value */
+ #define MXC_S_TPU_MAA_CTRL_CLC_ADD (MXC_V_TPU_MAA_CTRL_CLC_ADD << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_ADD Setting */
+ #define MXC_V_TPU_MAA_CTRL_CLC_SUB ((uint32_t)0x5UL) /**< MAA_CTRL_CLC_SUB Value */
+ #define MXC_S_TPU_MAA_CTRL_CLC_SUB (MXC_V_TPU_MAA_CTRL_CLC_SUB << MXC_F_TPU_MAA_CTRL_CLC_POS) /**< MAA_CTRL_CLC_SUB Setting */
+
+ #define MXC_F_TPU_MAA_CTRL_OCALC_POS 4 /**< MAA_CTRL_OCALC Position */
+ #define MXC_F_TPU_MAA_CTRL_OCALC ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_OCALC_POS)) /**< MAA_CTRL_OCALC Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_MAAER_POS 7 /**< MAA_CTRL_MAAER Position */
+ #define MXC_F_TPU_MAA_CTRL_MAAER ((uint32_t)(0x1UL << MXC_F_TPU_MAA_CTRL_MAAER_POS)) /**< MAA_CTRL_MAAER Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_AMS_POS 8 /**< MAA_CTRL_AMS Position */
+ #define MXC_F_TPU_MAA_CTRL_AMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_AMS_POS)) /**< MAA_CTRL_AMS Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_BMS_POS 10 /**< MAA_CTRL_BMS Position */
+ #define MXC_F_TPU_MAA_CTRL_BMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_BMS_POS)) /**< MAA_CTRL_BMS Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_EMS_POS 12 /**< MAA_CTRL_EMS Position */
+ #define MXC_F_TPU_MAA_CTRL_EMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_EMS_POS)) /**< MAA_CTRL_EMS Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_MMS_POS 14 /**< MAA_CTRL_MMS Position */
+ #define MXC_F_TPU_MAA_CTRL_MMS ((uint32_t)(0x3UL << MXC_F_TPU_MAA_CTRL_MMS_POS)) /**< MAA_CTRL_MMS Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_AMA_POS 16 /**< MAA_CTRL_AMA Position */
+ #define MXC_F_TPU_MAA_CTRL_AMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_AMA_POS)) /**< MAA_CTRL_AMA Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_BMA_POS 20 /**< MAA_CTRL_BMA Position */
+ #define MXC_F_TPU_MAA_CTRL_BMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_BMA_POS)) /**< MAA_CTRL_BMA Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_RMA_POS 24 /**< MAA_CTRL_RMA Position */
+ #define MXC_F_TPU_MAA_CTRL_RMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_RMA_POS)) /**< MAA_CTRL_RMA Mask */
+
+ #define MXC_F_TPU_MAA_CTRL_TMA_POS 28 /**< MAA_CTRL_TMA Position */
+ #define MXC_F_TPU_MAA_CTRL_TMA ((uint32_t)(0xFUL << MXC_F_TPU_MAA_CTRL_TMA_POS)) /**< MAA_CTRL_TMA Mask */
+
+/**@} end of group MAA_CTRL_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup DIN_Register
+ * @brief Crypto Data Input. Data input can be written to this register instead of using
+ * the DMA. This register writes to the FIFO. This register occupies four
+ * successive words to allow the use of multi-store instructions. Words can be
+ * written to any location, they will be placed in the FIFO in the order they are
+ * written. The endian swap input control bit affects this register.
+ * @{
+ */
+ #define MXC_F_TPU_DIN_DATA_POS 0 /**< DIN_DATA Position */
+ #define MXC_F_TPU_DIN_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DIN_DATA_POS)) /**< DIN_DATA Mask */
+
+/**@} end of group DIN_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup DOUT_Register
+ * @brief Crypto Data Output. Resulting data from cipher calculation. Data is placed in
+ * the lower words of these four registers depending on the algorithm. For block
+ * cipher modes, this register holds the result of most recent encryption or
+ * decryption operation. These registers are affected by the endian swap bits.
+ * @{
+ */
+ #define MXC_F_TPU_DOUT_DATA_POS 0 /**< DOUT_DATA Position */
+ #define MXC_F_TPU_DOUT_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_DOUT_DATA_POS)) /**< DOUT_DATA Mask */
+
+/**@} end of group DOUT_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CRC_POLY_Register
+ * @brief CRC Polynomial. The polynomial to be used for Galois Field calculations (CRC or
+ * LFSR) should be written to this register. This register is affected by the MSB
+ * control bit.
+ * @{
+ */
+ #define MXC_F_TPU_CRC_POLY_POLY_POS 0 /**< CRC_POLY_POLY Position */
+ #define MXC_F_TPU_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_POLY_POLY_POS)) /**< CRC_POLY_POLY Mask */
+
+/**@} end of group CRC_POLY_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CRC_VAL_Register
+ * @brief CRC Value. This is the state for the Galois Field. This register holds the
+ * result of a CRC calculation or the current state of the LFSR. This register is
+ * affected by the MSB control bit.
+ * @{
+ */
+ #define MXC_F_TPU_CRC_VAL_VAL_POS 0 /**< CRC_VAL_VAL Position */
+ #define MXC_F_TPU_CRC_VAL_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_VAL_VAL_POS)) /**< CRC_VAL_VAL Mask */
+
+/**@} end of group CRC_VAL_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CRC_PRNG_Register
+ * @brief Pseudo Random Value. Output of the Galois Field shift register. This holds the
+ * resulting pseudo-random number if entropy is disabled or true random number if
+ * entropy is enabled.
+ * @{
+ */
+ #define MXC_F_TPU_CRC_PRNG_PRNG_POS 0 /**< CRC_PRNG_PRNG Position */
+ #define MXC_F_TPU_CRC_PRNG_PRNG ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CRC_PRNG_PRNG_POS)) /**< CRC_PRNG_PRNG Mask */
+
+/**@} end of group CRC_PRNG_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup HAM_ECC_Register
+ * @brief Hamming ECC Register.
+ * @{
+ */
+ #define MXC_F_TPU_HAM_ECC_ECC_POS 0 /**< HAM_ECC_ECC Position */
+ #define MXC_F_TPU_HAM_ECC_ECC ((uint32_t)(0xFFFFUL << MXC_F_TPU_HAM_ECC_ECC_POS)) /**< HAM_ECC_ECC Mask */
+
+ #define MXC_F_TPU_HAM_ECC_PAR_POS 16 /**< HAM_ECC_PAR Position */
+ #define MXC_F_TPU_HAM_ECC_PAR ((uint32_t)(0x1UL << MXC_F_TPU_HAM_ECC_PAR_POS)) /**< HAM_ECC_PAR Mask */
+
+/**@} end of group HAM_ECC_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CIPHER_INIT_Register
+ * @brief Initial Vector. For block cipher operations that use CBC, CFB, OFB, or CNTR
+ * modes, this register holds the initial value. This register is updated with each
+ * encryption or decryption operation. This register is affected by the endian swap
+ * bits.
+ * @{
+ */
+ #define MXC_F_TPU_CIPHER_INIT_IVEC_POS 0 /**< CIPHER_INIT_IVEC Position */
+ #define MXC_F_TPU_CIPHER_INIT_IVEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_INIT_IVEC_POS)) /**< CIPHER_INIT_IVEC Mask */
+
+/**@} end of group CIPHER_INIT_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup CIPHER_KEY_Register
+ * @brief Cipher Key. This register holds the key used for block cipher operations. The
+ * lower words are used for block ciphers that use shorter key lengths. This
+ * register is affected by the endian swap input control bits.
+ * @{
+ */
+ #define MXC_F_TPU_CIPHER_KEY_KEY_POS 0 /**< CIPHER_KEY_KEY Position */
+ #define MXC_F_TPU_CIPHER_KEY_KEY ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_CIPHER_KEY_KEY_POS)) /**< CIPHER_KEY_KEY Mask */
+
+/**@} end of group CIPHER_KEY_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup HASH_DIGEST_Register
+ * @brief This register holds the calculated hash value. This register is affected by the
+ * endian swap bits.
+ * @{
+ */
+ #define MXC_F_TPU_HASH_DIGEST_HASH_POS 0 /**< HASH_DIGEST_HASH Position */
+ #define MXC_F_TPU_HASH_DIGEST_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_DIGEST_HASH_POS)) /**< HASH_DIGEST_HASH Mask */
+
+/**@} end of group HASH_DIGEST_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup HASH_MSG_SZ_Register
+ * @brief Message Size. This register holds the lowest 32-bit of message size in bytes.
+ * @{
+ */
+ #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS 0 /**< HASH_MSG_SZ_MSGSZ Position */
+ #define MXC_F_TPU_HASH_MSG_SZ_MSGSZ ((uint32_t)(0xFFFFFFFFUL << MXC_F_TPU_HASH_MSG_SZ_MSGSZ_POS)) /**< HASH_MSG_SZ_MSGSZ Mask */
+
+/**@} end of group HASH_MSG_SZ_Register */
+
+/**
+ * @ingroup tpu_registers
+ * @defgroup MAA_MAWS_Register
+ * @brief MAA Word Size. This register defines the number of bits for a modular operation.
+ * This register must be set to a valid value prior to the MAA operation start.
+ * Valid values are from 1 to 2048. Invalid values are ignored and will not
+ * initiate a MAA operation.
+ * @{
+ */
+ #define MXC_F_TPU_MAA_MAWS_MAWS_POS 0 /**< MAA_MAWS_MAWS Position */
+ #define MXC_F_TPU_MAA_MAWS_MAWS ((uint32_t)(0xFFFUL << MXC_F_TPU_MAA_MAWS_MAWS_POS)) /**< MAA_MAWS_MAWS Mask */
+
+/**@} end of group MAA_MAWS_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TPU_REGS_H_ */
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index b4d7bbc86f72bc6c90751842dab8574bf4e60684..d33c14489907f6f3285cb0a3ef9df079c84c49dc 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -109,51 +109,7 @@ struct max32xxx_flash_bank {
};
static const uint8_t write_code[] = {
- 0x9b, 0x46, 0x51, 0xf8, 0x84, 0x3c, 0xa1, 0xf5, 0x82, 0x77, 0x02, 0x93, 0x13, 0xf0, 0x02, 0x03, 0x05, 0x93, 0x1e, 0xd0,
- 0x4f, 0xf0, 0x80, 0x43, 0x9c, 0x68, 0x64, 0x03, 0x5e, 0xbf, 0x9c, 0x68, 0x44, 0xf4, 0x80, 0x24, 0x9c, 0x60, 0x5c, 0x6a,
- 0x64, 0x04, 0x42, 0xbf, 0x5c, 0x6a, 0x24, 0xf4, 0x80, 0x44, 0x5c, 0x62, 0x01, 0x24, 0x45, 0x4b, 0x1c, 0x60, 0x1c, 0x68,
- 0x44, 0xf4, 0x80, 0x44, 0x1c, 0x60, 0x1c, 0x68, 0x44, 0xf0, 0x10, 0x04, 0x1c, 0x60, 0x1c, 0x68, 0x44, 0xf0, 0x20, 0x04,
- 0x1c, 0x60, 0x02, 0x9b, 0x3d, 0x4c, 0x03, 0xf0, 0x01, 0x03, 0x04, 0x93, 0x00, 0xf1, 0x08, 0x03, 0x03, 0x93, 0x3b, 0x4b,
- 0xa1, 0xf5, 0x80, 0x7a, 0x92, 0xb9, 0x05, 0x9b, 0x7b, 0xb1, 0x4f, 0xf0, 0x80, 0x43, 0x1a, 0x68, 0x42, 0xf4, 0x80, 0x12,
- 0x1a, 0x60, 0x02, 0x9a, 0x12, 0xf0, 0x40, 0x0f, 0x1a, 0x68, 0x14, 0xbf, 0x42, 0xf4, 0x00, 0x12, 0x22, 0xf4, 0x00, 0x12,
- 0x1a, 0x60, 0x00, 0xbe, 0x04, 0x9d, 0x00, 0x2d, 0x5e, 0xd1, 0x9d, 0x68, 0xa1, 0xf5, 0x82, 0x7c, 0x45, 0xf0, 0x10, 0x05,
- 0x9d, 0x60, 0x04, 0x9d, 0xcd, 0xf8, 0x04, 0xb0, 0xae, 0x46, 0xcc, 0xf8, 0x00, 0x50, 0x00, 0x2a, 0x4a, 0xd0, 0xd0, 0xf8,
- 0x04, 0x80, 0x05, 0x68, 0xa8, 0x45, 0xfa, 0xd0, 0x45, 0x68, 0xd0, 0xf8, 0x04, 0x80, 0x2d, 0x78, 0x08, 0xf1, 0x01, 0x08,
- 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08,
- 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x3a, 0x01, 0x96, 0x05, 0xfa, 0x0e, 0xf8, 0xdc, 0xf8,
- 0x00, 0x50, 0x0e, 0xf1, 0x08, 0x0e, 0x45, 0xea, 0x08, 0x05, 0xbe, 0xf1, 0x20, 0x0f, 0xcc, 0xf8, 0x00, 0x50, 0xd4, 0xd1,
- 0x9d, 0x68, 0x25, 0xf0, 0x70, 0x45, 0x45, 0xf0, 0x00, 0x55, 0x9d, 0x60, 0xc3, 0xf8, 0x00, 0xb0, 0xdc, 0xf8, 0x00, 0x50,
- 0x1d, 0x63, 0x9d, 0x68, 0x45, 0xf0, 0x01, 0x05, 0x9d, 0x60, 0x9d, 0x68, 0xed, 0x07, 0xfc, 0xd4, 0x9d, 0x68, 0x25, 0xf0,
- 0x70, 0x45, 0x9d, 0x60, 0x5d, 0x6a, 0x15, 0xf0, 0x02, 0x0f, 0x04, 0xd0, 0x5d, 0x6a, 0x25, 0xf0, 0x02, 0x05, 0x5d, 0x62,
- 0x00, 0xbe, 0xdd, 0xf8, 0x04, 0xb0, 0x8f, 0xe7, 0xff, 0x25, 0xce, 0xe7, 0x00, 0x10, 0x00, 0x40, 0x00, 0x90, 0x02, 0x40,
- 0xa1, 0xf5, 0x84, 0x7e, 0xf4, 0x46, 0xa1, 0xf1, 0xf8, 0x05, 0x06, 0x95, 0xcd, 0xf8, 0x04, 0xb0, 0x00, 0x25, 0x4c, 0xf8,
- 0x04, 0x5f, 0x00, 0x2a, 0x00, 0xf0, 0xfd, 0x80, 0xd0, 0xf8, 0x04, 0x80, 0x05, 0x68, 0xa8, 0x45, 0xfa, 0xd0, 0x45, 0x68,
- 0xd0, 0xf8, 0x04, 0x80, 0x2d, 0x78, 0x08, 0xf1, 0x01, 0x08, 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80,
- 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08, 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80,
- 0x01, 0x3a, 0x01, 0x96, 0xcc, 0xf8, 0x00, 0x50, 0x00, 0x2a, 0x00, 0xf0, 0xde, 0x80, 0xd0, 0xf8, 0x04, 0x90, 0xd0, 0xf8,
- 0x00, 0x80, 0xc1, 0x45, 0xf9, 0xd0, 0xd0, 0xf8, 0x04, 0x80, 0x01, 0x3a, 0x98, 0xf8, 0x00, 0x90, 0xd0, 0xf8, 0x04, 0x80,
- 0x08, 0xf1, 0x01, 0x08, 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf,
- 0x08, 0xf1, 0x01, 0x08, 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x96, 0x45, 0xea, 0x09, 0x25,
- 0xcc, 0xf8, 0x00, 0x50, 0x00, 0x2a, 0x00, 0xf0, 0xbb, 0x80, 0xd0, 0xf8, 0x04, 0x90, 0xd0, 0xf8, 0x00, 0x80, 0xc1, 0x45,
- 0xf9, 0xd0, 0xd0, 0xf8, 0x04, 0x80, 0x01, 0x3a, 0x98, 0xf8, 0x00, 0x90, 0xd0, 0xf8, 0x04, 0x80, 0x08, 0xf1, 0x01, 0x08,
- 0x47, 0x45, 0x96, 0xbf, 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08,
- 0x06, 0xf1, 0x01, 0x06, 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x96, 0x45, 0xea, 0x09, 0x45, 0xcc, 0xf8, 0x00, 0x50,
- 0x00, 0x2a, 0x00, 0xf0, 0x98, 0x80, 0xd0, 0xf8, 0x04, 0x90, 0xd0, 0xf8, 0x00, 0x80, 0xc1, 0x45, 0xf9, 0xd0, 0xd0, 0xf8,
- 0x04, 0x80, 0x01, 0x3a, 0x98, 0xf8, 0x00, 0x90, 0xd0, 0xf8, 0x04, 0x80, 0x08, 0xf1, 0x01, 0x08, 0x47, 0x45, 0x96, 0xbf,
- 0x03, 0x9e, 0xd0, 0xf8, 0x04, 0x80, 0x46, 0x60, 0x01, 0x9e, 0x88, 0xbf, 0x08, 0xf1, 0x01, 0x08, 0x06, 0xf1, 0x01, 0x06,
- 0x88, 0xbf, 0xc0, 0xf8, 0x04, 0x80, 0x01, 0x96, 0x45, 0xea, 0x09, 0x65, 0xcc, 0xf8, 0x00, 0x50, 0x06, 0x9d, 0x65, 0x45,
- 0x7f, 0xf4, 0x66, 0xaf, 0x05, 0x9d, 0x00, 0x2d, 0x46, 0xd0, 0x02, 0x9d, 0x05, 0xf0, 0x20, 0x05, 0x06, 0x95, 0x2b, 0xf0,
- 0x7f, 0x45, 0x07, 0x95, 0x06, 0x9e, 0x0e, 0xf5, 0x84, 0x75, 0x0e, 0xf1, 0x04, 0x09, 0xde, 0xf8, 0x04, 0x80, 0x6d, 0x1a,
- 0x00, 0x2e, 0x5f, 0xd0, 0x07, 0x9e, 0x35, 0x44, 0x85, 0xea, 0x08, 0x05, 0xe1, 0x45, 0xce, 0xf8, 0x04, 0x50, 0xce, 0x46,
- 0xec, 0xd1, 0x25, 0x68, 0x45, 0xf0, 0x00, 0x65, 0x25, 0x60, 0x00, 0x25, 0x65, 0x60, 0x02, 0x9d, 0x15, 0xf0, 0x40, 0x0f,
- 0x65, 0x68, 0x14, 0xbf, 0x45, 0xf0, 0x30, 0x05, 0x45, 0xf0, 0x10, 0x05, 0x65, 0x60, 0x65, 0x68, 0x45, 0xf0, 0x0c, 0x05,
- 0x65, 0x60, 0x3d, 0x68, 0x25, 0x62, 0xda, 0xf8, 0x00, 0x50, 0x65, 0x62, 0x51, 0xf8, 0xfc, 0x5c, 0xa5, 0x62, 0x51, 0xf8,
- 0xf8, 0x5c, 0xe5, 0x62, 0x25, 0x68, 0x2d, 0x01, 0xfc, 0xd5, 0x25, 0x6b, 0x3d, 0x60, 0x65, 0x6b, 0xca, 0xf8, 0x00, 0x50,
- 0xa5, 0x6b, 0x41, 0xf8, 0xfc, 0x5c, 0xe5, 0x6b, 0x41, 0xf8, 0xf8, 0x5c, 0x9d, 0x68, 0x25, 0xf0, 0x70, 0x45, 0x45, 0xf0,
- 0x00, 0x55, 0x9d, 0x60, 0x9d, 0x68, 0x25, 0xf0, 0x10, 0x05, 0x9d, 0x60, 0xc3, 0xf8, 0x00, 0xb0, 0x3d, 0x68, 0x1d, 0x63,
- 0xda, 0xf8, 0x00, 0x50, 0x5d, 0x63, 0x51, 0xf8, 0xfc, 0x5c, 0x9d, 0x63, 0x51, 0xf8, 0xf8, 0x5c, 0xdd, 0x63, 0x9d, 0x68,
- 0x45, 0xf0, 0x01, 0x05, 0x9d, 0x60, 0x9d, 0x68, 0xed, 0x07, 0xfc, 0xd4, 0xde, 0xe6, 0xff, 0x25, 0x1c, 0xe7, 0x4f, 0xf0,
- 0xff, 0x09, 0x3d, 0xe7, 0x4f, 0xf0, 0xff, 0x09, 0x60, 0xe7, 0x4f, 0xf0, 0xff, 0x09, 0x83, 0xe7, 0x5d, 0x44, 0x9f, 0xe7,
+#include "../../contrib/loaders/flash/max32xxx/max32xxx_write.inc"
};
FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
diff --git a/tcl/target/max32520.cfg b/tcl/target/max32520.cfg
index 4e75a99c3c68621b921750f9b5cfa9bc429cfa73..8324da6724e22789d13d64f527775caf4fb0da29 100644
--- a/tcl/target/max32520.cfg
+++ b/tcl/target/max32520.cfg
@@ -14,6 +14,6 @@ set FLASH_SECTOR 0x2000
# Currently set for Emulator
set FLASH_CLK 40
-set FLASH_OPTIONS 0x63
+set FLASH_OPTIONS 0x23
source [find target/max32xxx.cfg]