From e8ead33804f1aede5157a5afc1bc249038799e6b Mon Sep 17 00:00:00 2001
From: drath <drath@b42882b7-edfa-0310-969c-e2dbd0fdcd60>
Date: Thu, 19 Oct 2006 10:07:24 +0000
Subject: [PATCH] - fixed endianness handling in arm7_9_read_core_reg (thanks
 to Magnus Lundin for reporting this) - correctly handle ft2232_device_desc
 and ft2232_serial when both are given at the same time

git-svn-id: svn://svn.berlios.de/openocd/trunk@104 b42882b7-edfa-0310-969c-e2dbd0fdcd60
---
 src/jtag/ft2232.c          |  3 ++-
 src/target/arm7_9_common.c | 22 ++++++++++++----------
 2 files changed, 14 insertions(+), 11 deletions(-)

diff --git a/src/jtag/ft2232.c b/src/jtag/ft2232.c
index e9fce54be..06b419a06 100644
--- a/src/jtag/ft2232.c
+++ b/src/jtag/ft2232.c
@@ -994,7 +994,8 @@ int ft2232_init(void)
 		WARNING("can't open by device description and serial number, giving precedence to serial");
 		ft2232_device_desc = NULL;
 	}
-	else if (ft2232_device_desc)
+	
+	if (ft2232_device_desc)
 	{
 		openex_string = ft2232_device_desc;
 		openex_flags = FT_OPEN_BY_DESCRIPTION;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index c1a39b6b5..b793ba515 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1509,6 +1509,7 @@ int arm7_9_step(struct target_s *target, int current, u32 address, int handle_br
 int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
 {
 	u32* reg_p[16];
+	u32 value;
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -1533,7 +1534,7 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 	if ((num >= 0) && (num <= 15))
 	{
 		/* read a normal core register */
-		reg_p[num] = (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value;
+		reg_p[num] = &value;
 		
 		arm7_9->read_core_regs(target, 1 << num, reg_p);
 	}
@@ -1545,11 +1546,18 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 		armv4_5_core_reg_t *arch_info = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).arch_info;
 		int spsr = (arch_info->mode == ARMV4_5_MODE_ANY) ? 0 : 1;
 		
-		arm7_9->read_xpsr(target, (u32*)ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, spsr);
+		arm7_9->read_xpsr(target, &value, spsr);
 	}
 	
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		ERROR("JTAG failure");
+		exit(-1);
+	}
+		
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
 	ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, num).value, 0, 32, value);
 		
 	if ((mode != ARMV4_5_MODE_ANY)
 			&& (mode != armv4_5->core_mode)
@@ -1558,12 +1566,6 @@ int arm7_9_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mod
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 	}
 	
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		ERROR("JTAG failure");
-		exit(-1);
-	}
-	
 	return ERROR_OK;
 	
 }
@@ -1768,7 +1770,7 @@ int arm7_9_read_memory(struct target_s *target, u32 address, u32 size, u32 count
 
 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
 	{
-		ERROR("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+		WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
 
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -1933,7 +1935,7 @@ int arm7_9_write_memory(struct target_s *target, u32 address, u32 size, u32 coun
 
 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
 	{
-		ERROR("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+		WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
 
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
-- 
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