diff --git a/components/bootloader/Kconfig.projbuild b/components/bootloader/Kconfig.projbuild
index beae2f4f7c06dafc9617f769f9a780bdab6bd8ae..984042d3b96ac6bb92c35e4cebf76577cb0ec496 100644
--- a/components/bootloader/Kconfig.projbuild
+++ b/components/bootloader/Kconfig.projbuild
@@ -681,7 +681,7 @@ menu "Security features"
     choice SECURE_FLASH_ENCRYPTION_KEYSIZE
         bool "Size of generated AES-XTS key"
         default SECURE_FLASH_ENCRYPTION_AES128
-        depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && SECURE_FLASH_ENC_ENABLED
+        depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 || IDF_TARGET_ESP8684) && SECURE_FLASH_ENC_ENABLED
         help
             Size of generated AES-XTS key.
 
@@ -693,9 +693,11 @@ menu "Security features"
 
         config SECURE_FLASH_ENCRYPTION_AES128
             bool "AES-128 (256-bit key)"
+            depends on !IDF_TARGET_ESP8684 # TODO: IDF-3899
 
         config SECURE_FLASH_ENCRYPTION_AES256
             bool "AES-256 (512-bit key)"
+            depends on !IDF_TARGET_ESP8684 # TODO: IDF-3899
     endchoice
 
     choice SECURE_FLASH_ENCRYPTION_MODE
@@ -862,9 +864,13 @@ menu "Security features"
 
             If not set, the app does not care if the flash encryption eFuse bit is set or not.
 
+    config SECURE_ROM_DL_MODE_ENABLED
+        bool
+        default y if SECURE_TARGET_HAS_SECURE_ROM_DL_MODE && !SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT
+
     choice SECURE_UART_ROM_DL_MODE
         bool "UART ROM download mode"
-        default SECURE_ENABLE_SECURE_ROM_DL_MODE if SECURE_TARGET_HAS_SECURE_ROM_DL_MODE && !SECURE_FLASH_ENCRYPTION_MODE_DEVELOPMENT # NOERROR
+        default SECURE_ENABLE_SECURE_ROM_DL_MODE if SECURE_ROM_DL_MODE_ENABLED # NOERROR
         default SECURE_INSECURE_ALLOW_DL_MODE
         depends on SECURE_BOOT_V2_ENABLED || SECURE_FLASH_ENC_ENABLED
         depends on !IDF_TARGET_ESP32 || ESP32_REV_MIN_3
diff --git a/components/bootloader/subproject/main/CMakeLists.txt b/components/bootloader/subproject/main/CMakeLists.txt
index ee13316859edbb50e87bc2543b226c1b4d1abfe8..90b9c47322a84e90f14c16f989b8372d653e4515 100644
--- a/components/bootloader/subproject/main/CMakeLists.txt
+++ b/components/bootloader/subproject/main/CMakeLists.txt
@@ -4,10 +4,7 @@ idf_component_register(SRCS "bootloader_start.c"
 idf_build_get_property(target IDF_TARGET)
 set(scripts "ld/${target}/bootloader.ld")
 
-if(NOT CONFIG_IDF_TARGET_ESP32H2)
-    list(APPEND scripts "ld/${target}/bootloader.rom.ld")
-endif()
-
+list(APPEND scripts "ld/${target}/bootloader.rom.ld")
 target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}")
 
 target_link_libraries(${COMPONENT_LIB} INTERFACE "-u bootloader_hooks_include")
diff --git a/components/bootloader/subproject/main/ld/esp32h2/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp32h2/bootloader.rom.ld
new file mode 100644
index 0000000000000000000000000000000000000000..185a5c2ee38dc84ea211a2ee58ad1c64da6af022
--- /dev/null
+++ b/components/bootloader/subproject/main/ld/esp32h2/bootloader.rom.ld
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP32-H2 target */
diff --git a/components/bootloader/subproject/main/ld/esp8684/bootloader.ld b/components/bootloader/subproject/main/ld/esp8684/bootloader.ld
new file mode 100644
index 0000000000000000000000000000000000000000..88b7d8d5488c7e3ec4d3e0159a8e5fcb4ce16395
--- /dev/null
+++ b/components/bootloader/subproject/main/ld/esp8684/bootloader.ld
@@ -0,0 +1,196 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *  We put 2nd bootloader in the high address space (before ROM stack/data/bss).
+ *  See memory usage for ROM bootloader at the end of this file.
+ */
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = 0x403AE000, len = 0x2000
+  iram_loader_seg (RWX) :           org = 0x403B0000, len = 0x6000
+  dram_seg (RW) :                   org = 0x3FCD6000, len = 0x4000
+}
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+     *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse_esp8684.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+}
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ *  +--------+--------------+------+ 0x3FCC_B0B0
+ *  |        ^              |
+ *  |        |              |
+ *  |        | data/bss     |
+ *  |        |              |
+ *  |        v              |
+ *  +------------------------------+ 0x3FCD_C9C0
+ *  |        ^              |
+ *  |        |              |
+ *  |        | stack        |
+ *  |        |              |
+ *  |        v              |
+ *  +------------------------------+ 0x3FCD_E9C0
+ */
diff --git a/components/bootloader/subproject/main/ld/esp8684/bootloader.rom.ld b/components/bootloader/subproject/main/ld/esp8684/bootloader.rom.ld
new file mode 100644
index 0000000000000000000000000000000000000000..f6cb44d8656cec86060298a5cb7a0d480608a096
--- /dev/null
+++ b/components/bootloader/subproject/main/ld/esp8684/bootloader.rom.ld
@@ -0,0 +1,6 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* No definition for ESP8684 target */
diff --git a/components/bootloader_support/component.mk b/components/bootloader_support/component.mk
index 4dd0ab75c2cdeee8f3e6527ff1647074a04a7158..cd4f992cb0814b04ab0d969f257867f30ed5e55d 100644
--- a/components/bootloader_support/component.mk
+++ b/components/bootloader_support/component.mk
@@ -32,14 +32,17 @@ COMPONENT_OBJEXCLUDE += src/bootloader_flash_config_esp32s2.o \
 			src/bootloader_flash_config_esp32s3.o \
 			src/bootloader_flash_config_esp32c3.o \
 			src/bootloader_flash_config_esp32h2.o \
+			src/bootloader_flash_config_esp8684.o \
 			src/bootloader_efuse_esp32s2.o \
 			src/bootloader_efuse_esp32s3.o \
 			src/bootloader_efuse_esp32c3.o \
 			src/bootloader_efuse_esp32h2.o \
+			src/bootloader_efuse_esp8684.o \
 			src/bootloader_random_esp32s2.o \
 			src/bootloader_random_esp32s3.o \
 			src/bootloader_random_esp32c3.o \
-			src/bootloader_random_esp32h2.o
+			src/bootloader_random_esp32h2.o \
+			src/bootloader_random_esp8684.o
 
 ifdef IS_BOOTLOADER_BUILD
 	ifndef CONFIG_SECURE_SIGNED_APPS_ECDSA_SCHEME
diff --git a/components/bootloader_support/include/bootloader_common.h b/components/bootloader_support/include/bootloader_common.h
index 2f4e9062200af2a907be50aadf846e52079dcb44..4c7e0fc7270e3cf27c0f5208df533edb17ef6b39 100644
--- a/components/bootloader_support/include/bootloader_common.h
+++ b/components/bootloader_support/include/bootloader_common.h
@@ -20,6 +20,8 @@
 #include "esp32c3/rom/rtc.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/rtc.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/rtc.h"
 #endif
 
 #ifdef __cplusplus
diff --git a/components/bootloader_support/include/esp_app_format.h b/components/bootloader_support/include/esp_app_format.h
index 64744fdfe5a5846f58dfc5190ed55aab4bcedca5..2a1a08a33d80b2c853af97669bbe11cddbff5e46 100644
--- a/components/bootloader_support/include/esp_app_format.h
+++ b/components/bootloader_support/include/esp_app_format.h
@@ -17,6 +17,7 @@ typedef enum {
     ESP_CHIP_ID_ESP32C3 = 0x0005, /*!< chip ID: ESP32-C3 */
     ESP_CHIP_ID_ESP32S3 = 0x0009, /*!< chip ID: ESP32-S3 */
     ESP_CHIP_ID_ESP32H2 = 0x000A, /*!< chip ID: ESP32-H2 */  // ESP32H2-TODO: IDF-3475
+    ESP_CHIP_ID_ESP8684 = 0x000C, /*!< chip ID: ESP32-8684 */
     ESP_CHIP_ID_INVALID = 0xFFFF /*!< Invalid chip ID (we defined it to make sure the esp_chip_id_t is 2 bytes size) */
 } __attribute__((packed)) esp_chip_id_t;
 
diff --git a/components/bootloader_support/include/esp_flash_encrypt.h b/components/bootloader_support/include/esp_flash_encrypt.h
index efb7eb8bce38934955c5a7c22a74143212f63fc1..d8c9400429424e16b3e5991cf822c4687eba3513 100644
--- a/components/bootloader_support/include/esp_flash_encrypt.h
+++ b/components/bootloader_support/include/esp_flash_encrypt.h
@@ -55,7 +55,11 @@ static inline /** @cond */ IRAM_ATTR /** @endcond */ bool esp_flash_encryption_e
     #endif
 #else
     #ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
-        flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT);
+        #if CONFIG_IDF_TARGET_ESP8684
+            // 	IDF-3899
+        #else
+            flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT);
+        #endif
     #else
         esp_efuse_read_field_blob(ESP_EFUSE_SPI_BOOT_CRYPT_CNT, &flash_crypt_cnt, ESP_EFUSE_SPI_BOOT_CRYPT_CNT[0]->bit_count);
     #endif
diff --git a/components/bootloader_support/include/esp_secure_boot.h b/components/bootloader_support/include/esp_secure_boot.h
index 9bb8dfec0b7bddf3f011e930b12752b06fbdb5ab..62c93bae6db2a4652996247a9e96005fc700fff8 100644
--- a/components/bootloader_support/include/esp_secure_boot.h
+++ b/components/bootloader_support/include/esp_secure_boot.h
@@ -28,6 +28,9 @@
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/efuse.h"
 #include "esp32h2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/efuse.h"
+#include "esp8684/rom/secure_boot.h"
 #endif
 
 #ifdef CONFIG_SECURE_BOOT_V1_ENABLED
diff --git a/components/bootloader_support/include_bootloader/bootloader_flash_priv.h b/components/bootloader_support/include_bootloader/bootloader_flash_priv.h
index d898cae1244a5a1476827e4b961d110523c668f7..ee1bfbea248d8a945c7522874ca080f861b84a5d 100644
--- a/components/bootloader_support/include_bootloader/bootloader_flash_priv.h
+++ b/components/bootloader_support/include_bootloader/bootloader_flash_priv.h
@@ -15,8 +15,8 @@
 #include "bootloader_flash.h"
 
 #define FLASH_SECTOR_SIZE 0x1000
-#define FLASH_BLOCK_SIZE 0x10000
-#define MMAP_ALIGNED_MASK 0x0000FFFF
+#define FLASH_BLOCK_SIZE 	0x10000
+#define MMAP_ALIGNED_MASK 	0x0000FFFF
 
 /* SPI commands (actual on-wire commands not SPI controller bitmasks)
    Suitable for use with the bootloader_execute_flash_command static function.
@@ -130,7 +130,7 @@ esp_err_t bootloader_flash_erase_sector(size_t sector);
 esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size);
 
 /* Cache MMU block size */
-#define MMU_BLOCK_SIZE    0x00010000
+#define MMU_BLOCK_SIZE    0x10000
 
 /* Cache MMU address mask (MMU tables ignore bits which are zero) */
 #define MMU_FLASH_MASK    (~(MMU_BLOCK_SIZE - 1))
diff --git a/components/bootloader_support/src/bootloader_common.c b/components/bootloader_support/src/bootloader_common.c
index 2acbd74fa9e3f628fceb04ebebedb201267b7ee6..9cdcc6a975e07d8fc8307c262897383d2a39659c 100644
--- a/components/bootloader_support/src/bootloader_common.c
+++ b/components/bootloader_support/src/bootloader_common.c
@@ -19,6 +19,8 @@
 #include "esp32c3/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/spi_flash.h"
 #endif
 #include "esp_rom_crc.h"
 #include "esp_rom_gpio.h"
diff --git a/components/bootloader_support/src/bootloader_console.c b/components/bootloader_support/src/bootloader_console.c
index 211e95e30bca0f13b1d8790c4cd2adf52604a796..245e5a317f54c71bd67ffc85699ec057ec24b7fa 100644
--- a/components/bootloader_support/src/bootloader_console.c
+++ b/components/bootloader_support/src/bootloader_console.c
@@ -25,6 +25,9 @@
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/ets_sys.h"
 #include "esp32h2/rom/uart.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/ets_sys.h"
+#include "esp8684/rom/uart.h"
 #endif
 #include "esp_rom_gpio.h"
 #include "esp_rom_uart.h"
diff --git a/components/bootloader_support/src/bootloader_efuse_esp8684.c b/components/bootloader_support/src/bootloader_efuse_esp8684.c
new file mode 100644
index 0000000000000000000000000000000000000000..c6469de4e9c827e84498e00e48389a7c2a4f4b69
--- /dev/null
+++ b/components/bootloader_support/src/bootloader_efuse_esp8684.c
@@ -0,0 +1,20 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include "soc/efuse_reg.h"
+
+uint8_t bootloader_common_get_chip_revision(void)
+{
+    // should return the same value as esp_efuse_get_chip_ver()
+    return REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_WAFER_VERSION);
+}
+
+uint32_t bootloader_common_get_chip_ver_pkg(void)
+{
+    // should return the same value as esp_efuse_get_pkg_ver()
+    return REG_GET_FIELD(EFUSE_RD_BLK2_DATA1_REG, EFUSE_PKG_VERSION);
+}
diff --git a/components/bootloader_support/src/bootloader_flash.c b/components/bootloader_support/src/bootloader_flash.c
index c049ecbe04598bcc426ad7628a888d37e7174be9..ec1ebd96487e5ac6902e44bd02a24a3199626447 100644
--- a/components/bootloader_support/src/bootloader_flash.c
+++ b/components/bootloader_support/src/bootloader_flash.c
@@ -33,6 +33,8 @@
 #include "esp32c3/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/spi_flash.h"
 #endif
 
 #ifdef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
@@ -143,6 +145,10 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
 #include "esp32h2/rom/spi_flash.h"
 #include "esp32h2/rom/cache.h"
 #include "soc/cache_memory.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/spi_flash.h"
+#include "esp8684/rom/cache.h"
+#include "soc/cache_memory.h"
 #endif
 static const char *TAG = "bootloader_flash";
 
diff --git a/components/bootloader_support/src/bootloader_flash_config_esp8684.c b/components/bootloader_support/src/bootloader_flash_config_esp8684.c
new file mode 100644
index 0000000000000000000000000000000000000000..27fbf9d5ee72e4555d97994004132b4014c159ab
--- /dev/null
+++ b/components/bootloader_support/src/bootloader_flash_config_esp8684.c
@@ -0,0 +1,73 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <assert.h>
+#include "string.h"
+#include "sdkconfig.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp8684/rom/gpio.h"
+#include "esp8684/rom/spi_flash.h"
+#include "esp8684/rom/efuse.h"
+#include "soc/gpio_periph.h"
+#include "soc/efuse_reg.h"
+#include "soc/spi_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "soc/soc_caps.h"
+#include "flash_qio_mode.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_common.h"
+
+#define FLASH_IO_MATRIX_DUMMY_40M   0
+#define FLASH_IO_MATRIX_DUMMY_80M   0
+
+void bootloader_flash_update_id()
+{
+    esp_rom_spiflash_chip_t *chip = &rom_spiflash_legacy_data->chip;
+    chip->device_id = bootloader_read_flash_id();
+}
+
+void IRAM_ATTR bootloader_flash_cs_timing_config()
+{
+    SET_PERI_REG_MASK(SPI_MEM_USER_REG(0), SPI_MEM_CS_HOLD_M | SPI_MEM_CS_SETUP_M);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_HOLD_TIME_V, 0, SPI_MEM_CS_HOLD_TIME_S);
+    SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
+}
+
+void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
+{
+    uint32_t spi_clk_div = 0;
+    switch (pfhdr->spi_speed) {
+    // TODO: change MSPI freq, IDF-3831
+    case ESP_IMAGE_SPI_SPEED_80M:
+        spi_clk_div = 1;
+        break;
+    case ESP_IMAGE_SPI_SPEED_40M:
+        spi_clk_div = 2;
+        break;
+    case ESP_IMAGE_SPI_SPEED_26M:
+        spi_clk_div = 3;
+        break;
+    case ESP_IMAGE_SPI_SPEED_20M:
+        spi_clk_div = 4;
+        break;
+    default:
+        break;
+    }
+    esp_rom_spiflash_config_clk(spi_clk_div, 0);
+}
+
+void IRAM_ATTR bootloader_flash_set_dummy_out(void)
+{
+    REG_SET_BIT(SPI_MEM_CTRL_REG(0), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
+    REG_SET_BIT(SPI_MEM_CTRL_REG(1), SPI_MEM_FDUMMY_OUT | SPI_MEM_D_POL | SPI_MEM_Q_POL);
+}
+
+void IRAM_ATTR bootloader_flash_dummy_config(const esp_image_header_t *pfhdr)
+{
+    bootloader_configure_spi_pins(1);
+    bootloader_flash_set_dummy_out();
+}
diff --git a/components/bootloader_support/src/bootloader_random_esp8684.c b/components/bootloader_support/src/bootloader_random_esp8684.c
new file mode 100644
index 0000000000000000000000000000000000000000..598fa24bb8947973a327b0c599c5b5507c1a3449
--- /dev/null
+++ b/components/bootloader_support/src/bootloader_random_esp8684.c
@@ -0,0 +1,23 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "sdkconfig.h"
+#include "bootloader_random.h"
+#include "esp_log.h"
+#include "soc/syscon_reg.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/apb_saradc_reg.h"
+#include "soc/system_reg.h"
+#include "regi2c_ctrl.h"
+
+void bootloader_random_enable(void)
+{
+    // TODO: IDF-4021
+}
+
+void bootloader_random_disable(void)
+{
+    // TODO: IDF-4021
+}
diff --git a/components/bootloader_support/src/bootloader_utility.c b/components/bootloader_support/src/bootloader_utility.c
index a4df6d9e1a3d209d5b3104c587147ce0518e6419..65d8f65262ccf11467eb77848e1b3643d16ba538 100644
--- a/components/bootloader_support/src/bootloader_utility.c
+++ b/components/bootloader_support/src/bootloader_utility.c
@@ -53,6 +53,18 @@
 #include "esp32h2/rom/secure_boot.h"
 #include "soc/extmem_reg.h"
 #include "soc/cache_memory.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/cache.h"
+#include "esp8684/rom/efuse.h"
+#include "esp8684/rom/ets_sys.h"
+#include "esp8684/rom/spi_flash.h"
+#include "esp8684/rom/crc.h"
+#include "esp8684/rom/rtc.h"
+#include "esp8684/rom/uart.h"
+#include "esp8684/rom/gpio.h"
+#include "esp8684/rom/secure_boot.h"
+#include "soc/extmem_reg.h"
+#include "soc/cache_memory.h"
 #else // CONFIG_IDF_TARGET_*
 #error "Unsupported IDF_TARGET"
 #endif
diff --git a/components/bootloader_support/src/esp8684/bootloader_esp8684.c b/components/bootloader_support/src/esp8684/bootloader_esp8684.c
new file mode 100644
index 0000000000000000000000000000000000000000..61aa3f394271f59dcbf943eeb68b9771629d52ae
--- /dev/null
+++ b/components/bootloader_support/src/esp8684/bootloader_esp8684.c
@@ -0,0 +1,302 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_image_format.h"
+#include "flash_qio_mode.h"
+#include "esp_rom_gpio.h"
+#include "esp_rom_efuse.h"
+#include "esp_rom_uart.h"
+#include "esp_rom_sys.h"
+#include "soc/efuse_reg.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/io_mux_reg.h"
+#include "soc/assist_debug_reg.h"
+#include "soc/cpu.h"
+#include "soc/rtc.h"
+#include "soc/spi_periph.h"
+#include "soc/extmem_reg.h"
+#include "soc/io_mux_reg.h"
+#include "soc/system_reg.h"
+#include "esp8684/rom/efuse.h"
+#include "esp8684/rom/spi_flash.h"
+#include "esp8684/rom/cache.h"
+#include "esp8684/rom/ets_sys.h"
+#include "esp8684/rom/spi_flash.h"
+#include "esp8684/rom/rtc.h"
+#include "bootloader_common.h"
+#include "bootloader_init.h"
+#include "bootloader_clock.h"
+#include "bootloader_flash_config.h"
+#include "bootloader_mem.h"
+#include "regi2c_ctrl.h"
+#include "bootloader_console.h"
+#include "bootloader_flash_priv.h"
+#include "esp_efuse.h"
+
+static const char *TAG = "boot.esp8684";
+
+void IRAM_ATTR bootloader_configure_spi_pins(int drv)
+{
+    // IDF-4066
+    const uint32_t spiconfig = 0;
+    uint8_t clk_gpio_num = SPI_CLK_GPIO_NUM;
+    uint8_t q_gpio_num   = SPI_Q_GPIO_NUM;
+    uint8_t d_gpio_num   = SPI_D_GPIO_NUM;
+    uint8_t cs0_gpio_num = SPI_CS0_GPIO_NUM;
+    uint8_t hd_gpio_num  = SPI_HD_GPIO_NUM;
+    uint8_t wp_gpio_num  = SPI_WP_GPIO_NUM;
+    if (spiconfig == 0) {
+
+    }
+    esp_rom_gpio_pad_set_drv(clk_gpio_num, drv);
+    esp_rom_gpio_pad_set_drv(q_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(d_gpio_num,   drv);
+    esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
+    if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
+        esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
+    }
+    if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
+        esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
+    }
+}
+
+static void bootloader_reset_mmu(void)
+{
+    int page_mode = MMU_Get_Page_Mode();
+    int size = (page_mode == 0? 16:
+                page_mode == 1? 32:
+                page_mode == 2? 64: 0);
+    ESP_LOGI(TAG, "mmu page mode = %dK", size);
+
+    Cache_Suspend_ICache();
+    Cache_Invalidate_ICache_All();
+    Cache_MMU_Init();
+
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_IBUS);
+    REG_CLR_BIT(EXTMEM_ICACHE_CTRL1_REG, EXTMEM_ICACHE_SHUT_DBUS);
+}
+
+static void update_flash_config(const esp_image_header_t *bootloader_hdr)
+{
+    uint32_t size;
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        size = 1;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        size = 2;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        size = 4;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        size = 8;
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        size = 16;
+        break;
+    default:
+        size = 2;
+    }
+    uint32_t autoload = Cache_Suspend_ICache();
+    // Set flash chip size
+    esp_rom_spiflash_config_param(rom_spiflash_legacy_data->chip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);    // TODO: set mode
+    Cache_Resume_ICache(autoload);
+}
+
+static void print_flash_info(const esp_image_header_t *bootloader_hdr)
+{
+    ESP_LOGD(TAG, "magic %02x", bootloader_hdr->magic);
+    ESP_LOGD(TAG, "segments %02x", bootloader_hdr->segment_count);
+    ESP_LOGD(TAG, "spi_mode %02x", bootloader_hdr->spi_mode);
+    ESP_LOGD(TAG, "spi_speed %02x", bootloader_hdr->spi_speed);
+    ESP_LOGD(TAG, "spi_size %02x", bootloader_hdr->spi_size);
+
+    const char *str;
+    switch (bootloader_hdr->spi_speed) {
+    case ESP_IMAGE_SPI_SPEED_40M:
+        str = "40MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_26M:
+        str = "26.7MHz";
+        break;
+    case ESP_IMAGE_SPI_SPEED_20M:
+        str = "20MHz";
+        break;
+    default:
+        str = "20MHz";
+        break;
+    }
+    ESP_LOGI(TAG, "SPI Speed      : %s", str);
+
+    /* SPI mode could have been set to QIO during boot already,
+       so test the SPI registers not the flash header */
+    uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
+    if (spi_ctrl & SPI_MEM_FREAD_QIO) {
+        str = "QIO";
+    } else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
+        str = "QOUT";
+    } else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
+        str = "DIO";
+    } else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
+        str = "DOUT";
+    } else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
+        str = "FAST READ";
+    } else {
+        str = "SLOW READ";
+    }
+    ESP_LOGI(TAG, "SPI Mode       : %s", str);
+
+    switch (bootloader_hdr->spi_size) {
+    case ESP_IMAGE_FLASH_SIZE_1MB:
+        str = "1MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_2MB:
+        str = "2MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_4MB:
+        str = "4MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_8MB:
+        str = "8MB";
+        break;
+    case ESP_IMAGE_FLASH_SIZE_16MB:
+        str = "16MB";
+        break;
+    default:
+        str = "2MB";
+        break;
+    }
+    ESP_LOGI(TAG, "SPI Flash Size : %s", str);
+}
+
+static void IRAM_ATTR bootloader_init_flash_configure(void)
+{
+    bootloader_flash_dummy_config(&bootloader_image_hdr);
+    bootloader_flash_cs_timing_config();
+}
+
+static void bootloader_spi_flash_resume(void)
+{
+    bootloader_execute_flash_command(CMD_RESUME, 0, 0, 0);
+    esp_rom_spiflash_wait_idle(&g_rom_flashchip);
+}
+
+static esp_err_t bootloader_init_spi_flash(void)
+{
+    bootloader_init_flash_configure();
+#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
+    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
+    if (spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_SPI && spiconfig != ESP_ROM_EFUSE_FLASH_DEFAULT_HSPI) {
+        ESP_LOGE(TAG, "SPI flash pins are overridden. Enable CONFIG_SPI_FLASH_ROM_DRIVER_PATCH in menuconfig");
+        return ESP_FAIL;
+    }
+#endif
+
+    bootloader_spi_flash_resume();
+    esp_rom_spiflash_unlock();
+
+#if CONFIG_ESPTOOLPY_FLASHMODE_QIO || CONFIG_ESPTOOLPY_FLASHMODE_QOUT
+    bootloader_enable_qio_mode();
+#endif
+
+    print_flash_info(&bootloader_image_hdr);
+    update_flash_config(&bootloader_image_hdr);
+    //ensure the flash is write-protected
+    bootloader_enable_wp();
+    return ESP_OK;
+}
+
+static void wdt_reset_cpu0_info_enable(void)
+{
+    REG_SET_BIT(SYSTEM_CPU_PERI_CLK_EN_REG, SYSTEM_CLK_EN_ASSIST_DEBUG);
+    REG_CLR_BIT(SYSTEM_CPU_PERI_RST_EN_REG, SYSTEM_RST_EN_ASSIST_DEBUG);
+    REG_WRITE(ASSIST_DEBUG_CORE_0_RCD_EN_REG, ASSIST_DEBUG_CORE_0_RCD_PDEBUGEN | ASSIST_DEBUG_CORE_0_RCD_RECORDEN);
+}
+
+static void wdt_reset_info_dump(int cpu)
+{
+    (void) cpu;
+    // saved PC was already printed by the ROM bootloader.
+    // nothing to do here.
+}
+
+static void bootloader_check_wdt_reset(void)
+{
+    int wdt_rst = 0;
+    soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
+    if (rst_reason == RESET_REASON_CORE_RTC_WDT || rst_reason == RESET_REASON_CORE_MWDT0 ||
+        rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_RTC_WDT) {
+        ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
+        wdt_rst = 1;
+    }
+    if (wdt_rst) {
+        // if reset by WDT dump info from trace port
+        wdt_reset_info_dump(0);
+    }
+    wdt_reset_cpu0_info_enable();
+}
+
+static void bootloader_super_wdt_auto_feed(void)
+{
+    REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, RTC_CNTL_SWD_WKEY_VALUE);
+    REG_SET_BIT(RTC_CNTL_SWD_CONF_REG, RTC_CNTL_SWD_AUTO_FEED_EN);
+    REG_WRITE(RTC_CNTL_SWD_WPROTECT_REG, 0);
+}
+
+esp_err_t bootloader_init(void)
+{
+    esp_err_t ret = ESP_OK;
+
+    bootloader_super_wdt_auto_feed();
+    // protect memory region
+    bootloader_init_mem();
+    /* check that static RAM is after the stack */
+    assert(&_bss_start <= &_bss_end);
+    assert(&_data_start <= &_data_end);
+    // clear bss section
+    bootloader_clear_bss_section();
+    // init eFuse virtual mode (read eFuses to RAM)
+#ifdef CONFIG_EFUSE_VIRTUAL
+    ESP_LOGW(TAG, "eFuse virtual mode is enabled. If Secure boot or Flash encryption is enabled then it does not provide any security. FOR TESTING ONLY!");
+#ifndef CONFIG_EFUSE_VIRTUAL_KEEP_IN_FLASH
+    esp_efuse_init_virtual_mode_in_ram();
+#endif
+#endif
+    // reset MMU
+    bootloader_reset_mmu();
+    // config clock
+    bootloader_clock_configure();
+    // initialize console, from now on, we can use esp_log
+    bootloader_console_init();
+    /* print 2nd bootloader banner */
+    bootloader_print_banner();
+    // update flash ID
+    bootloader_flash_update_id();
+    // read bootloader header
+    if ((ret = bootloader_read_bootloader_header()) != ESP_OK) {
+        goto err;
+    }
+    // read chip revision and check if it's compatible to bootloader
+    if ((ret = bootloader_check_bootloader_validity()) != ESP_OK) {
+        goto err;
+    }
+    // initialize spi flash
+    if ((ret = bootloader_init_spi_flash()) != ESP_OK) {
+        goto err;
+    }
+    // check whether a WDT reset happend
+    bootloader_check_wdt_reset();
+    // config WDT
+    bootloader_config_wdt();
+    // enable RNG early entropy source
+    bootloader_enable_random();
+err:
+    return ret;
+}
diff --git a/components/bootloader_support/src/esp8684/bootloader_sha.c b/components/bootloader_support/src/esp8684/bootloader_sha.c
new file mode 100644
index 0000000000000000000000000000000000000000..8fe5b2986c9c715cdad676f45a93b32149836b20
--- /dev/null
+++ b/components/bootloader_support/src/esp8684/bootloader_sha.c
@@ -0,0 +1,40 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "bootloader_sha.h"
+#include <stdbool.h>
+#include <string.h>
+#include <assert.h>
+#include <sys/param.h>
+
+#include "esp8684/rom/sha.h"
+
+static SHA_CTX ctx;
+
+bootloader_sha256_handle_t bootloader_sha256_start()
+{
+    // Enable SHA hardware
+    ets_sha_enable();
+    ets_sha_init(&ctx, SHA2_256);
+    return &ctx; // Meaningless non-NULL value
+}
+
+void bootloader_sha256_data(bootloader_sha256_handle_t handle, const void *data, size_t data_len)
+{
+    assert(handle != NULL);
+    assert(data_len % 4 == 0);
+    ets_sha_update(&ctx, data, data_len, false);
+}
+
+void bootloader_sha256_finish(bootloader_sha256_handle_t handle, uint8_t *digest)
+{
+    assert(handle != NULL);
+
+    if (digest == NULL) {
+        bzero(&ctx, sizeof(ctx));
+        return;
+    }
+    ets_sha_finish(&ctx, digest);
+}
diff --git a/components/bootloader_support/src/esp8684/bootloader_soc.c b/components/bootloader_support/src/esp8684/bootloader_soc.c
new file mode 100644
index 0000000000000000000000000000000000000000..be708ca820b22d99bd012d6e3053f9b77b72ecf8
--- /dev/null
+++ b/components/bootloader_support/src/esp8684/bootloader_soc.c
@@ -0,0 +1,21 @@
+/*
+ * SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+
+void bootloader_ana_super_wdt_reset_config(bool enable)
+{
+    (void)enable; // ESP8684 has none of these features.
+}
+
+void bootloader_ana_bod_reset_config(bool enable)
+{
+    (void)enable; // ESP8684 has none of these features.
+}
+
+void bootloader_ana_clock_glitch_reset_config(bool enable)
+{
+    (void)enable; // ESP8684 has none of these features.
+}
diff --git a/components/bootloader_support/src/esp8684/flash_encryption_secure_features.c b/components/bootloader_support/src/esp8684/flash_encryption_secure_features.c
new file mode 100644
index 0000000000000000000000000000000000000000..25dc0544839fda4ecb5dd4cd9523d68516b8fd18
--- /dev/null
+++ b/components/bootloader_support/src/esp8684/flash_encryption_secure_features.c
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "flash_encrypt";
+
+esp_err_t esp_flash_encryption_enable_secure_features(void)
+{
+#ifndef CONFIG_SECURE_FLASH_UART_BOOTLOADER_ALLOW_ENC
+    ESP_LOGI(TAG, "Disable UART bootloader encryption...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT);
+#else
+    ESP_LOGW(TAG, "Not disabling UART bootloader encryption");
+#endif
+
+    ESP_LOGI(TAG, "Disable UART bootloader cache...");
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_DIRECT_BOOT);
+
+    return ESP_OK;
+}
diff --git a/components/bootloader_support/src/esp8684/secure_boot_secure_features.c b/components/bootloader_support/src/esp8684/secure_boot_secure_features.c
new file mode 100644
index 0000000000000000000000000000000000000000..bc37fba1cea5e99c9560210e67b57cf99adf7a68
--- /dev/null
+++ b/components/bootloader_support/src/esp8684/secure_boot_secure_features.c
@@ -0,0 +1,44 @@
+/*
+ * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <strings.h>
+#include "esp_flash_encrypt.h"
+#include "esp_secure_boot.h"
+#include "esp_efuse.h"
+#include "esp_efuse_table.h"
+#include "esp_log.h"
+#include "sdkconfig.h"
+
+static __attribute__((unused)) const char *TAG = "secure_boot";
+
+esp_err_t esp_secure_boot_enable_secure_features(void)
+{
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_LEGACY_SPI_BOOT);
+
+#ifdef CONFIG_SECURE_ENABLE_SECURE_ROM_DL_MODE
+    ESP_LOGI(TAG, "Enabling Security download mode...");
+    esp_efuse_write_field_bit(ESP_EFUSE_ENABLE_SECURITY_DOWNLOAD);
+#else
+    ESP_LOGW(TAG, "Not enabling Security download mode - SECURITY COMPROMISED");
+#endif
+
+#ifndef CONFIG_SECURE_BOOT_ALLOW_JTAG
+    ESP_LOGI(TAG, "Disable hardware & software JTAG...");
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_PAD_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_DIS_USB_JTAG);
+    esp_efuse_write_field_bit(ESP_EFUSE_SOFT_DIS_JTAG);
+#else
+    ESP_LOGW(TAG, "Not disabling JTAG - SECURITY COMPROMISED");
+#endif
+
+#ifdef CONFIG_SECURE_BOOT_ENABLE_AGGRESSIVE_KEY_REVOKE
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE);
+#endif
+
+    esp_efuse_write_field_bit(ESP_EFUSE_SECURE_BOOT_EN);
+
+    return ESP_OK;
+}
diff --git a/components/bootloader_support/src/esp_image_format.c b/components/bootloader_support/src/esp_image_format.c
index ebdf7f334f5f5584f28112f59b5e06b7f9767ddf..803a8879d3c2deb59d45be38f063bbfc1b1ca440 100644
--- a/components/bootloader_support/src/esp_image_format.c
+++ b/components/bootloader_support/src/esp_image_format.c
@@ -19,6 +19,7 @@
 #include "bootloader_common.h"
 #include "esp_rom_sys.h"
 #include "soc/soc_memory_types.h"
+#include "soc/soc_caps.h"
 #if CONFIG_IDF_TARGET_ESP32
 #include "esp32/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32S2
@@ -29,6 +30,9 @@
 #include "esp32c3/rom/secure_boot.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/secure_boot.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/rtc.h"
+#include "esp8684/rom/secure_boot.h"
 #endif
 
 /* Checking signatures as part of verifying images is necessary:
@@ -427,13 +431,22 @@ static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_
             }
         }
     /* Sections entirely in RTC memory won't overlap with a vanilla bootloader but are valid load addresses, thus skipping them from the check */
-    } else if (esp_ptr_in_rtc_iram_fast(load_addr_p) && esp_ptr_in_rtc_iram_fast(load_inclusive_end_p)){
+    }
+#if SOC_RTC_FAST_MEM_SUPPORTED
+    else if (esp_ptr_in_rtc_iram_fast(load_addr_p) && esp_ptr_in_rtc_iram_fast(load_inclusive_end_p)){
         return true;
     } else if (esp_ptr_in_rtc_dram_fast(load_addr_p) && esp_ptr_in_rtc_dram_fast(load_inclusive_end_p)){
         return true;
-    } else if (esp_ptr_in_rtc_slow(load_addr_p) && esp_ptr_in_rtc_slow(load_inclusive_end_p)) {
+    }
+#endif
+
+#if SOC_RTC_SLOW_MEM_SUPPORTED
+    else if (esp_ptr_in_rtc_slow(load_addr_p) && esp_ptr_in_rtc_slow(load_inclusive_end_p)) {
         return true;
-    } else { /* Not a DRAM or an IRAM or RTC Fast IRAM, RTC Fast DRAM or RTC Slow address */
+    }
+#endif
+
+    else { /* Not a DRAM or an IRAM or RTC Fast IRAM, RTC Fast DRAM or RTC Slow address */
         reason = "bad load address range";
         goto invalid;
     }
@@ -696,6 +709,7 @@ static bool should_load(uint32_t load_addr)
     }
 
     if (!load_rtc_memory) {
+#if SOC_RTC_FAST_MEM_SUPPORTED
         if (load_addr >= SOC_RTC_IRAM_LOW && load_addr < SOC_RTC_IRAM_HIGH) {
             ESP_LOGD(TAG, "Skipping RTC fast memory segment at 0x%08x", load_addr);
             return false;
@@ -704,10 +718,14 @@ static bool should_load(uint32_t load_addr)
             ESP_LOGD(TAG, "Skipping RTC fast memory segment at 0x%08x", load_addr);
             return false;
         }
+#endif
+
+#if SOC_RTC_SLOW_MEM_SUPPORTED
         if (load_addr >= SOC_RTC_DATA_LOW && load_addr < SOC_RTC_DATA_HIGH) {
             ESP_LOGD(TAG, "Skipping RTC slow memory segment at 0x%08x", load_addr);
             return false;
         }
+#endif
     }
 
     return true;
diff --git a/components/bootloader_support/src/flash_encryption/flash_encrypt.c b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
index 4ca3fbc368394404138cb233ffde5256dbd55335..e672f5cf28c206c9745180f8fbeb7f88d31f1d5c 100644
--- a/components/bootloader_support/src/flash_encryption/flash_encrypt.c
+++ b/components/bootloader_support/src/flash_encryption/flash_encrypt.c
@@ -15,6 +15,10 @@
 #include "esp_efuse_table.h"
 #include "esp_log.h"
 #include "hal/wdt_hal.h"
+#ifdef CONFIG_IDF_TARGET_ESP8684
+// IDF-3899
+#warning "Not support flash encryption on esp8684 yet."
+#endif
 
 #ifdef CONFIG_SECURE_FLASH_ENC_ENABLED
 
diff --git a/components/bootloader_support/src/flash_partitions.c b/components/bootloader_support/src/flash_partitions.c
index 9731244cfbb08065f8773d38841803b892d78956..3289906e826217618e84290153fc54a8d5f19e46 100644
--- a/components/bootloader_support/src/flash_partitions.c
+++ b/components/bootloader_support/src/flash_partitions.c
@@ -15,6 +15,8 @@
 #include "esp32s3/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/spi_flash.h"
 #else
 #include "esp32/rom/spi_flash.h"
 #endif
@@ -48,7 +50,7 @@ esp_err_t esp_partition_table_verify(const esp_partition_info_t *partition_table
                 return ESP_ERR_INVALID_STATE;
             }
 
-            struct MD5Context context;
+            md5_context_t context;
             unsigned char digest[16];
             esp_rom_md5_init(&context);
             esp_rom_md5_update(&context, (unsigned char *) partition_table, num_parts * sizeof(esp_partition_info_t));
diff --git a/components/bootloader_support/src/flash_qio_mode.c b/components/bootloader_support/src/flash_qio_mode.c
index 0447627ab9e2cf205c485f5b9c7daf1c167fcf5b..486172057800cfcbff0a916a28af82bae3ebd2bf 100644
--- a/components/bootloader_support/src/flash_qio_mode.c
+++ b/components/bootloader_support/src/flash_qio_mode.c
@@ -23,6 +23,8 @@
 #include "esp32c3/rom/spi_flash.h"
 #elif CONFIG_IDF_TARGET_ESP32H2
 #include "esp32h2/rom/spi_flash.h"
+#elif CONFIG_IDF_TARGET_ESP8684
+#include "esp8684/rom/spi_flash.h"
 #endif
 #include "soc/efuse_periph.h"
 #include "soc/io_mux_reg.h"
@@ -146,7 +148,6 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
                                  uint8_t status_qio_bit)
 {
     uint32_t status;
-    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
 
     esp_rom_spiflash_wait_idle(&g_rom_flashchip);
 
@@ -181,9 +182,17 @@ static esp_err_t enable_qio_mode(read_status_fn_t read_status_fn,
 
     esp_rom_spiflash_config_readmode(mode);
 
+#if !CONFIG_IDF_TARGET_ESP8684
+    //IDF-3914
+    const uint32_t spiconfig = esp_rom_efuse_get_flash_gpio_info();
+#endif
+
 #if CONFIG_IDF_TARGET_ESP32
     int wp_pin = bootloader_flash_get_wp_pin();
     esp_rom_spiflash_select_qio_pins(wp_pin, spiconfig);
+#elif CONFIG_IDF_TARGET_ESP8684
+    //IDF-3914
+    esp_rom_spiflash_select_qio_pins(0, 0);
 #else
     esp_rom_spiflash_select_qio_pins(esp_rom_efuse_get_flash_wp_gpio(), spiconfig);
 #endif
diff --git a/components/esp_rom/CMakeLists.txt b/components/esp_rom/CMakeLists.txt
index b66eb7b4f414694221bc6811ae75045b74e35317..74c81258401c53e86aeda3e82c408d62ae2bb5b5 100644
--- a/components/esp_rom/CMakeLists.txt
+++ b/components/esp_rom/CMakeLists.txt
@@ -67,6 +67,10 @@ if(BOOTLOADER_BUILD)
 
     elseif(target STREQUAL "esp32h2")
         rom_linker_script("newlib")
+
+    elseif(target STREQUAL "esp8684")
+        rom_linker_script("newlib")
+        rom_linker_script("mbedtls")
     endif()
 
 else() # Regular app build
@@ -134,6 +138,15 @@ else() # Regular app build
         rom_linker_script("newlib")
         rom_linker_script("version")
 
+        if(CONFIG_NEWLIB_NANO_FORMAT)
+            rom_linker_script("newlib-nano")
+        endif()
+
+    elseif(target STREQUAL "esp8684")
+        rom_linker_script("newlib")
+        rom_linker_script("version")
+        rom_linker_script("mbedtls")
+
         if(CONFIG_NEWLIB_NANO_FORMAT)
             rom_linker_script("newlib-nano")
         endif()
diff --git a/components/esp_rom/esp32c3/esp_rom_caps.h b/components/esp_rom/esp32c3/esp_rom_caps.h
index 7a210f1a53638fcad1daa87719432b4d24c95248..151fb44e0872c1874d58880a5288e82130f51dc3 100644
--- a/components/esp_rom/esp32c3/esp_rom_caps.h
+++ b/components/esp_rom/esp32c3/esp_rom_caps.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -21,3 +13,4 @@
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
diff --git a/components/esp_rom/esp32h2/esp_rom_caps.h b/components/esp_rom/esp32h2/esp_rom_caps.h
index 7a210f1a53638fcad1daa87719432b4d24c95248..151fb44e0872c1874d58880a5288e82130f51dc3 100644
--- a/components/esp_rom/esp32h2/esp_rom_caps.h
+++ b/components/esp_rom/esp32h2/esp_rom_caps.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -21,3 +13,4 @@
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (3) // UART uses USB_SERIAL_JTAG port in ROM.
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
diff --git a/components/esp_rom/esp32s3/esp_rom_caps.h b/components/esp_rom/esp32s3/esp_rom_caps.h
index 5955f2c371e6ef19bf3ed38622d47719757bcc57..9c8a4931cfdf3a1d5d134ddb5304ecf135f9c529 100644
--- a/components/esp_rom/esp32s3/esp_rom_caps.h
+++ b/components/esp_rom/esp32s3/esp_rom_caps.h
@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -22,3 +14,4 @@
 #define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
 #define ESP_ROM_USB_SERIAL_DEVICE_NUM       (4) // The serial port ID (UART, USB, ...) of USB_SERIAL_JTAG in the ROM.
 #define ESP_ROM_HAS_ERASE_0_REGION_BUG      (1) // ROM has esp_flash_erase_region(size=0) bug
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
diff --git a/components/esp_rom/esp8684/esp_rom_caps.h b/components/esp_rom/esp8684/esp_rom_caps.h
new file mode 100644
index 0000000000000000000000000000000000000000..3b91332a3e17e605fcd48852b466f122b867b09b
--- /dev/null
+++ b/components/esp_rom/esp8684/esp_rom_caps.h
@@ -0,0 +1,13 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#define ESP_ROM_HAS_CRC_LE                  (1) // ROM CRC library supports Little Endian
+#define ESP_ROM_HAS_CRC_BE                  (1) // ROM CRC library supports Big Endian
+#define ESP_ROM_UART_CLK_IS_XTAL            (1) // UART clock source is selected to XTAL in ROM
+#define ESP_ROM_HAS_RETARGETABLE_LOCKING    (1) // ROM was built with retargetable locking
+#define ESP_ROM_GET_CLK_FREQ                (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.api.ld b/components/esp_rom/esp8684/ld/esp8684.rom.api.ld
new file mode 100644
index 0000000000000000000000000000000000000000..b4ef7b84060a8fcf8cc4a97dc3cff3f8599763c0
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.api.ld
@@ -0,0 +1,39 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/** ROM APIs
+ */
+PROVIDE ( esp_rom_crc32_le = crc32_le );
+PROVIDE ( esp_rom_crc16_le = crc16_le );
+PROVIDE ( esp_rom_crc8_le  = crc8_le );
+PROVIDE ( esp_rom_crc32_be = crc32_be );
+PROVIDE ( esp_rom_crc16_be = crc16_be );
+PROVIDE ( esp_rom_crc8_be  = crc8_be );
+
+PROVIDE ( esp_rom_gpio_pad_select_gpio    = gpio_pad_select_gpio );
+PROVIDE ( esp_rom_gpio_pad_pullup_only    = gpio_pad_pullup );
+PROVIDE ( esp_rom_gpio_pad_set_drv        = gpio_pad_set_drv );
+PROVIDE ( esp_rom_gpio_pad_unhold         = gpio_pad_unhold );
+PROVIDE ( esp_rom_gpio_connect_in_signal  = gpio_matrix_in );
+PROVIDE ( esp_rom_gpio_connect_out_signal = gpio_matrix_out );
+
+PROVIDE ( esp_rom_efuse_mac_address_crc8       = esp_crc8 );
+PROVIDE ( esp_rom_efuse_get_flash_wp_gpio      = ets_efuse_get_wp_pad );
+PROVIDE ( esp_rom_efuse_is_secure_boot_enabled = ets_efuse_secure_boot_enabled );
+
+PROVIDE ( esp_rom_uart_flush_tx       = uart_tx_flush );
+PROVIDE ( esp_rom_uart_tx_one_char    = uart_tx_one_char );
+PROVIDE ( esp_rom_uart_tx_wait_idle   = uart_tx_wait_idle );
+PROVIDE ( esp_rom_uart_rx_one_char    = uart_rx_one_char );
+PROVIDE ( esp_rom_uart_rx_string      = UartRxString );
+PROVIDE ( esp_rom_uart_putc           = ets_write_char_uart );
+
+PROVIDE ( esp_rom_mbedtls_md5_starts_ret = 0x40002a34 );
+PROVIDE ( esp_rom_mbedtls_md5_update_ret = 0x40002a38 );
+PROVIDE ( esp_rom_mbedtls_md5_finish_ret = 0x40002a3c );
+
+PROVIDE ( esp_rom_printf   = ets_printf );
+PROVIDE ( esp_rom_delay_us = ets_delay_us );
+PROVIDE ( esp_rom_get_reset_reason = rtc_get_reset_reason );
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.ld b/components/esp_rom/esp8684/ld/esp8684.rom.ld
new file mode 100644
index 0000000000000000000000000000000000000000..e55c412ef314e22753e3a82fd0a032f40120c736
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.ld
@@ -0,0 +1,2463 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM function interface esp8684.rom.ld for esp8684
+ *
+ *
+ * Generated from ./interface-esp8684.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group common
+ ***************************************/
+
+/* Functions */
+rtc_get_reset_reason = 0x40000018;
+analog_super_wdt_reset_happened = 0x4000001c;
+rtc_get_wakeup_cause = 0x40000020;
+rtc_select_apb_bridge = 0x40000024;
+rtc_unhold_all_pads = 0x40000028;
+ets_is_print_boot = 0x4000002c;
+ets_printf = 0x40000030;
+ets_install_putc1 = 0x40000034;
+ets_install_uart_printf = 0x40000038;
+ets_install_putc2 = 0x4000003c;
+PROVIDE( ets_delay_us = 0x40000040 );
+ets_get_stack_info = 0x40000044;
+ets_install_lock = 0x40000048;
+ets_backup_dma_copy = 0x4000004c;
+ets_apb_backup_init_lock_func = 0x40000050;
+UartRxString = 0x40000054;
+uart_tx_one_char = 0x40000058;
+uart_tx_one_char2 = 0x4000005c;
+uart_rx_one_char = 0x40000060;
+uart_rx_one_char_block = 0x40000064;
+uart_rx_readbuff = 0x40000068;
+uartAttach = 0x4000006c;
+uart_tx_flush = 0x40000070;
+uart_tx_wait_idle = 0x40000074;
+uart_div_modify = 0x40000078;
+ets_write_char_uart = 0x4000007c;
+uart_tx_switch = 0x40000080;
+multofup = 0x40000084;
+software_reset = 0x40000088;
+software_reset_cpu = 0x4000008c;
+assist_debug_clock_enable = 0x40000090;
+assist_debug_record_enable = 0x40000094;
+clear_super_wdt_reset_flag = 0x40000098;
+disable_default_watchdog = 0x4000009c;
+send_packet = 0x400000a0;
+recv_packet = 0x400000a4;
+GetUartDevice = 0x400000a8;
+UartDwnLdProc = 0x400000ac;
+Uart_Init = 0x400000b0;
+ets_set_user_start = 0x400000b4;
+/* Data (.data, .bss, .rodata) */
+ets_rom_layout_p = 0x3ff4fffc;
+ets_ops_table_ptr = 0x3fcdfffc;
+
+
+/***************************************
+ Group miniz
+ ***************************************/
+
+/* Functions */
+mz_adler32 = 0x400000b8;
+mz_free = 0x400000bc;
+tdefl_compress = 0x400000c0;
+tdefl_compress_buffer = 0x400000c4;
+tdefl_compress_mem_to_heap = 0x400000c8;
+tdefl_compress_mem_to_mem = 0x400000cc;
+tdefl_compress_mem_to_output = 0x400000d0;
+tdefl_get_adler32 = 0x400000d4;
+tdefl_get_prev_return_status = 0x400000d8;
+tdefl_init = 0x400000dc;
+tdefl_write_image_to_png_file_in_memory = 0x400000e0;
+tdefl_write_image_to_png_file_in_memory_ex = 0x400000e4;
+tinfl_decompress = 0x400000e8;
+tinfl_decompress_mem_to_callback = 0x400000ec;
+tinfl_decompress_mem_to_heap = 0x400000f0;
+tinfl_decompress_mem_to_mem = 0x400000f4;
+
+
+/***************************************
+ Group spiflash_legacy
+ ***************************************/
+
+/* Functions */
+PROVIDE( esp_rom_spiflash_wait_idle = 0x400000f8 );
+PROVIDE( esp_rom_spiflash_write_encrypted = 0x400000fc );
+PROVIDE( esp_rom_spiflash_write_encrypted_dest = 0x40000100 );
+PROVIDE( esp_rom_spiflash_write_encrypted_enable = 0x40000104 );
+PROVIDE( esp_rom_spiflash_write_encrypted_disable = 0x40000108 );
+PROVIDE( esp_rom_spiflash_erase_chip = 0x4000010c );
+PROVIDE( _esp_rom_spiflash_erase_sector = 0x40000110 );
+PROVIDE( _esp_rom_spiflash_erase_block = 0x40000114 );
+PROVIDE( _esp_rom_spiflash_write = 0x40000118 );
+PROVIDE( _esp_rom_spiflash_read = 0x4000011c );
+PROVIDE( _esp_rom_spiflash_unlock = 0x40000120 );
+PROVIDE( _SPIEraseArea = 0x40000124 );
+PROVIDE( _SPI_write_enable = 0x40000128 );
+PROVIDE( esp_rom_spiflash_erase_sector = 0x4000012c );
+PROVIDE( esp_rom_spiflash_erase_block = 0x40000130 );
+PROVIDE( esp_rom_spiflash_write = 0x40000134 );
+PROVIDE( esp_rom_spiflash_read = 0x40000138 );
+PROVIDE( esp_rom_spiflash_unlock = 0x4000013c );
+PROVIDE( SPIEraseArea = 0x40000140 );
+PROVIDE( SPI_write_enable = 0x40000144 );
+PROVIDE( esp_rom_spiflash_config_param = 0x40000148 );
+PROVIDE( esp_rom_spiflash_read_user_cmd = 0x4000014c );
+PROVIDE( esp_rom_spiflash_select_qio_pins = 0x40000150 );
+PROVIDE( esp_rom_spi_flash_auto_sus_res = 0x40000154 );
+PROVIDE( esp_rom_spi_flash_send_resume = 0x40000158 );
+PROVIDE( esp_rom_spi_flash_update_id = 0x4000015c );
+PROVIDE( esp_rom_spiflash_config_clk = 0x40000160 );
+PROVIDE( esp_rom_spiflash_config_readmode = 0x40000164 );
+PROVIDE( esp_rom_spiflash_read_status = 0x40000168 );
+PROVIDE( esp_rom_spiflash_read_statushigh = 0x4000016c );
+PROVIDE( esp_rom_spiflash_write_status = 0x40000170 );
+PROVIDE( spi_flash_attach = 0x40000174 );
+PROVIDE( spi_flash_get_chip_size = 0x40000178 );
+PROVIDE( spi_flash_guard_set = 0x4000017c );
+PROVIDE( spi_flash_guard_get = 0x40000180 );
+PROVIDE( spi_flash_read_encrypted = 0x40000184 );
+PROVIDE( spi_flash_mmap_os_func_set = 0x40000188 );
+PROVIDE( spi_flash_mmap_page_num_init = 0x4000018c );
+PROVIDE( spi_flash_mmap = 0x40000190 );
+PROVIDE( spi_flash_mmap_pages = 0x40000194 );
+PROVIDE( spi_flash_munmap = 0x40000198 );
+PROVIDE( spi_flash_mmap_dump = 0x4000019c );
+PROVIDE( spi_flash_check_and_flush_cache = 0x400001a0 );
+PROVIDE( spi_flash_mmap_get_free_pages = 0x400001a4 );
+PROVIDE( spi_flash_cache2phys = 0x400001a8 );
+PROVIDE( spi_flash_phys2cache = 0x400001ac );
+PROVIDE( spi_flash_disable_cache = 0x400001b0 );
+PROVIDE( spi_flash_restore_cache = 0x400001b4 );
+PROVIDE( spi_flash_cache_enabled = 0x400001b8 );
+PROVIDE( spi_flash_enable_cache = 0x400001bc );
+PROVIDE( spi_cache_mode_switch = 0x400001c0 );
+PROVIDE( spi_common_set_dummy_output = 0x400001c4 );
+PROVIDE( spi_common_set_flash_cs_timing = 0x400001c8 );
+PROVIDE( esp_rom_spi_set_address_bit_len = 0x400001cc );
+PROVIDE( esp_enable_cache_flash_wrap = 0x400001d0 );
+PROVIDE( SPILock = 0x400001d4 );
+PROVIDE( SPIMasterReadModeCnfig = 0x400001d8 );
+PROVIDE( SPI_Common_Command = 0x400001dc );
+PROVIDE( SPI_WakeUp = 0x400001e0 );
+PROVIDE( SPI_block_erase = 0x400001e4 );
+PROVIDE( SPI_chip_erase = 0x400001e8 );
+PROVIDE( SPI_init = 0x400001ec );
+PROVIDE( SPI_page_program = 0x400001f0 );
+PROVIDE( SPI_read_data = 0x400001f4 );
+PROVIDE( SPI_sector_erase = 0x400001f8 );
+PROVIDE( SelectSpiFunction = 0x400001fc );
+PROVIDE( SetSpiDrvs = 0x40000200 );
+PROVIDE( Wait_SPI_Idle = 0x40000204 );
+PROVIDE( spi_dummy_len_fix = 0x40000208 );
+PROVIDE( Disable_QMode = 0x4000020c );
+PROVIDE( Enable_QMode = 0x40000210 );
+/* Data (.data, .bss, .rodata) */
+PROVIDE( rom_spiflash_legacy_funcs = 0x3fcdfff4 );
+PROVIDE( rom_spiflash_legacy_data = 0x3fcdfff0 );
+PROVIDE( g_flash_guard_ops = 0x3fcdfff8 );
+
+
+/***************************************
+ Group hal_soc
+ ***************************************/
+
+/* Functions */
+PROVIDE( spi_flash_hal_poll_cmd_done = 0x40000214 );
+PROVIDE( spi_flash_hal_device_config = 0x40000218 );
+PROVIDE( spi_flash_hal_configure_host_io_mode = 0x4000021c );
+PROVIDE( spi_flash_hal_common_command = 0x40000220 );
+PROVIDE( spi_flash_hal_read = 0x40000224 );
+PROVIDE( spi_flash_hal_erase_chip = 0x40000228 );
+PROVIDE( spi_flash_hal_erase_sector = 0x4000022c );
+PROVIDE( spi_flash_hal_erase_block = 0x40000230 );
+PROVIDE( spi_flash_hal_program_page = 0x40000234 );
+PROVIDE( spi_flash_hal_set_write_protect = 0x40000238 );
+PROVIDE( spi_flash_hal_host_idle = 0x4000023c );
+PROVIDE( spi_flash_hal_check_status = 0x40000240 );
+PROVIDE( spi_flash_hal_setup_read_suspend = 0x40000244 );
+PROVIDE( spi_flash_hal_setup_auto_suspend_mode = 0x40000248 );
+PROVIDE( spi_flash_hal_setup_auto_resume_mode = 0x4000024c );
+PROVIDE( spi_flash_hal_disable_auto_suspend_mode = 0x40000250 );
+PROVIDE( spi_flash_hal_disable_auto_resume_mode = 0x40000254 );
+PROVIDE( spi_flash_hal_resume = 0x40000258 );
+PROVIDE( spi_flash_hal_suspend = 0x4000025c );
+PROVIDE( spi_flash_encryption_hal_enable = 0x40000260 );
+PROVIDE( spi_flash_encryption_hal_disable = 0x40000264 );
+PROVIDE( spi_flash_encryption_hal_prepare = 0x40000268 );
+PROVIDE( spi_flash_encryption_hal_done = 0x4000026c );
+PROVIDE( spi_flash_encryption_hal_destroy = 0x40000270 );
+PROVIDE( spi_flash_encryption_hal_check = 0x40000274 );
+PROVIDE( wdt_hal_init = 0x40000278 );
+PROVIDE( wdt_hal_deinit = 0x4000027c );
+PROVIDE( wdt_hal_config_stage = 0x40000280 );
+PROVIDE( wdt_hal_write_protect_disable = 0x40000284 );
+PROVIDE( wdt_hal_write_protect_enable = 0x40000288 );
+PROVIDE( wdt_hal_enable = 0x4000028c );
+PROVIDE( wdt_hal_disable = 0x40000290 );
+PROVIDE( wdt_hal_handle_intr = 0x40000294 );
+PROVIDE( wdt_hal_feed = 0x40000298 );
+PROVIDE( wdt_hal_set_flashboot_en = 0x4000029c );
+PROVIDE( wdt_hal_is_enabled = 0x400002a0 );
+PROVIDE( systimer_hal_init = 0x400002a4 );
+PROVIDE( systimer_hal_get_counter_value = 0x400002a8 );
+PROVIDE( systimer_hal_get_time = 0x400002ac );
+PROVIDE( systimer_hal_set_alarm_target = 0x400002b0 );
+PROVIDE( systimer_hal_set_alarm_period = 0x400002b4 );
+PROVIDE( systimer_hal_get_alarm_value = 0x400002b8 );
+PROVIDE( systimer_hal_enable_alarm_int = 0x400002bc );
+PROVIDE( systimer_hal_on_apb_freq_update = 0x400002c0 );
+PROVIDE( systimer_hal_counter_value_advance = 0x400002c4 );
+PROVIDE( systimer_hal_enable_counter = 0x400002c8 );
+PROVIDE( systimer_hal_select_alarm_mode = 0x400002cc );
+PROVIDE( systimer_hal_connect_alarm_counter = 0x400002d0 );
+PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d4 );
+
+
+/***************************************
+ Group heap
+ ***************************************/
+
+/* Functions */
+PROVIDE( tlsf_create = 0x400002d8 );
+PROVIDE( tlsf_create_with_pool = 0x400002dc );
+PROVIDE( tlsf_get_pool = 0x400002e0 );
+PROVIDE( tlsf_add_pool = 0x400002e4 );
+PROVIDE( tlsf_remove_pool = 0x400002e8 );
+PROVIDE( tlsf_malloc = 0x400002ec );
+PROVIDE( tlsf_memalign = 0x400002f0 );
+PROVIDE( tlsf_memalign_offs = 0x400002f4 );
+PROVIDE( tlsf_realloc = 0x400002f8 );
+PROVIDE( tlsf_free = 0x400002fc );
+PROVIDE( tlsf_block_size = 0x40000300 );
+PROVIDE( tlsf_size = 0x40000304 );
+PROVIDE( tlsf_align_size = 0x40000308 );
+PROVIDE( tlsf_block_size_min = 0x4000030c );
+PROVIDE( tlsf_block_size_max = 0x40000310 );
+PROVIDE( tlsf_pool_overhead = 0x40000314 );
+PROVIDE( tlsf_alloc_overhead = 0x40000318 );
+PROVIDE( tlsf_walk_pool = 0x4000031c );
+PROVIDE( tlsf_check = 0x40000320 );
+PROVIDE( tlsf_check_pool = 0x40000324 );
+PROVIDE( tlsf_poison_fill_pfunc_set = 0x40000328 );
+PROVIDE( multi_heap_get_block_address_impl = 0x4000032c );
+PROVIDE( multi_heap_get_allocated_size_impl = 0x40000330 );
+PROVIDE( multi_heap_register_impl = 0x40000334 );
+PROVIDE( multi_heap_set_lock = 0x40000338 );
+PROVIDE( multi_heap_mutex_init = 0x4000033c );
+PROVIDE( multi_heap_internal_lock = 0x40000340 );
+PROVIDE( multi_heap_internal_unlock = 0x40000344 );
+PROVIDE( multi_heap_get_first_block = 0x40000348 );
+PROVIDE( multi_heap_get_next_block = 0x4000034c );
+PROVIDE( multi_heap_is_free = 0x40000350 );
+PROVIDE( multi_heap_malloc_impl = 0x40000354 );
+PROVIDE( multi_heap_free_impl = 0x40000358 );
+PROVIDE( multi_heap_realloc_impl = 0x4000035c );
+PROVIDE( multi_heap_aligned_alloc_impl_offs = 0x40000360 );
+PROVIDE( multi_heap_aligned_alloc_impl = 0x40000364 );
+PROVIDE( multi_heap_check = 0x40000368 );
+PROVIDE( multi_heap_dump = 0x4000036c );
+PROVIDE( multi_heap_free_size_impl = 0x40000370 );
+PROVIDE( multi_heap_minimum_free_size_impl = 0x40000374 );
+PROVIDE( multi_heap_get_info_impl = 0x40000378 );
+/* Data (.data, .bss, .rodata) */
+PROVIDE( heap_tlsf_table_ptr = 0x3fcdffec );
+
+
+/***************************************
+ Group spi_flash_chips
+ ***************************************/
+
+/* Functions */
+PROVIDE( spi_flash_chip_generic_probe = 0x4000037c );
+PROVIDE( spi_flash_chip_generic_detect_size = 0x40000380 );
+PROVIDE( spi_flash_chip_generic_write = 0x40000384 );
+PROVIDE( spi_flash_chip_generic_write_encrypted = 0x40000388 );
+PROVIDE( spi_flash_chip_generic_set_write_protect = 0x4000038c );
+PROVIDE( spi_flash_common_write_status_16b_wrsr = 0x40000390 );
+PROVIDE( spi_flash_chip_generic_reset = 0x40000394 );
+PROVIDE( spi_flash_chip_generic_erase_chip = 0x40000398 );
+PROVIDE( spi_flash_chip_generic_erase_sector = 0x4000039c );
+PROVIDE( spi_flash_chip_generic_erase_block = 0x400003a0 );
+PROVIDE( spi_flash_chip_generic_page_program = 0x400003a4 );
+PROVIDE( spi_flash_chip_generic_get_write_protect = 0x400003a8 );
+PROVIDE( spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x400003ac );
+PROVIDE( spi_flash_chip_generic_read_reg = 0x400003b0 );
+PROVIDE( spi_flash_chip_generic_yield = 0x400003b4 );
+PROVIDE( spi_flash_generic_wait_host_idle = 0x400003b8 );
+PROVIDE( spi_flash_chip_generic_wait_idle = 0x400003bc );
+PROVIDE( spi_flash_chip_generic_config_host_io_mode = 0x400003c0 );
+PROVIDE( spi_flash_chip_generic_read = 0x400003c4 );
+PROVIDE( spi_flash_common_read_status_8b_rdsr2 = 0x400003c8 );
+PROVIDE( spi_flash_chip_generic_get_io_mode = 0x400003cc );
+PROVIDE( spi_flash_common_read_status_8b_rdsr = 0x400003d0 );
+PROVIDE( spi_flash_common_write_status_8b_wrsr = 0x400003d4 );
+PROVIDE( spi_flash_common_write_status_8b_wrsr2 = 0x400003d8 );
+PROVIDE( spi_flash_common_set_io_mode = 0x400003dc );
+PROVIDE( spi_flash_chip_generic_set_io_mode = 0x400003e0 );
+PROVIDE( spi_flash_chip_generic_read_unique_id = 0x400003e4 );
+PROVIDE( spi_flash_chip_generic_get_caps = 0x400003e8 );
+PROVIDE( spi_flash_chip_generic_suspend_cmd_conf = 0x400003ec );
+PROVIDE( spi_flash_chip_gd_get_io_mode = 0x400003f0 );
+PROVIDE( spi_flash_chip_gd_probe = 0x400003f4 );
+PROVIDE( spi_flash_chip_gd_set_io_mode = 0x400003f8 );
+/* Data (.data, .bss, .rodata) */
+PROVIDE( spi_flash_chip_generic_config_data = 0x3fcdffe8 );
+PROVIDE( spi_flash_encryption = 0x3fcdffe4 );
+
+
+/***************************************
+ Group memspi_host
+ ***************************************/
+
+/* Functions */
+PROVIDE( memspi_host_read_id_hs = 0x400003fc );
+PROVIDE( memspi_host_read_status_hs = 0x40000400 );
+PROVIDE( memspi_host_flush_cache = 0x40000404 );
+PROVIDE( memspi_host_erase_chip = 0x40000408 );
+PROVIDE( memspi_host_erase_sector = 0x4000040c );
+PROVIDE( memspi_host_erase_block = 0x40000410 );
+PROVIDE( memspi_host_program_page = 0x40000414 );
+PROVIDE( memspi_host_read = 0x40000418 );
+PROVIDE( memspi_host_set_write_protect = 0x4000041c );
+PROVIDE( memspi_host_set_max_read_len = 0x40000420 );
+PROVIDE( memspi_host_read_data_slicer = 0x40000424 );
+PROVIDE( memspi_host_write_data_slicer = 0x40000428 );
+
+
+/***************************************
+ Group esp_flash
+ ***************************************/
+
+/* Functions */
+PROVIDE( esp_flash_chip_driver_initialized = 0x4000042c );
+PROVIDE( esp_flash_read_id = 0x40000430 );
+PROVIDE( esp_flash_get_size = 0x40000434 );
+PROVIDE( esp_flash_erase_chip = 0x40000438 );
+PROVIDE( esp_flash_erase_region = 0x4000043c );
+PROVIDE( esp_flash_get_chip_write_protect = 0x40000440 );
+PROVIDE( esp_flash_set_chip_write_protect = 0x40000444 );
+PROVIDE( esp_flash_get_protectable_regions = 0x40000448 );
+PROVIDE( esp_flash_get_protected_region = 0x4000044c );
+PROVIDE( esp_flash_set_protected_region = 0x40000450 );
+PROVIDE( esp_flash_read = 0x40000454 );
+PROVIDE( esp_flash_write = 0x40000458 );
+PROVIDE( esp_flash_write_encrypted = 0x4000045c );
+PROVIDE( esp_flash_read_encrypted = 0x40000460 );
+PROVIDE( esp_flash_get_io_mode = 0x40000464 );
+PROVIDE( esp_flash_set_io_mode = 0x40000468 );
+PROVIDE( spi_flash_boot_attach = 0x4000046c );
+PROVIDE( esp_flash_read_chip_id = 0x40000470 );
+PROVIDE( detect_spi_flash_chip = 0x40000474 );
+PROVIDE( esp_rom_spiflash_write_disable = 0x40000478 );
+PROVIDE( esp_flash_suspend_cmd_init = 0x4000047c );
+/* Data (.data, .bss, .rodata) */
+PROVIDE( esp_flash_default_chip = 0x3fcdffe0 );
+PROVIDE( esp_flash_api_funcs = 0x3fcdffdc );
+
+
+/***************************************
+ Group cache
+ ***************************************/
+
+/* Functions */
+PROVIDE( Cache_Get_ICache_Line_Size = 0x400006dc );
+PROVIDE( Cache_Get_Mode = 0x400006e0 );
+PROVIDE( Cache_Address_Through_IBus = 0x400006e4 );
+PROVIDE( Cache_Address_Through_DBus = 0x400006e8 );
+PROVIDE( Cache_Set_Default_Mode = 0x400006ec );
+PROVIDE( Cache_Enable_Defalut_ICache_Mode = 0x400006f0 );
+PROVIDE( ROM_Boot_Cache_Init = 0x400006f4 );
+PROVIDE( MMU_Set_Page_Mode = 0x400006f8 );
+PROVIDE( MMU_Get_Page_Mode = 0x400006fc );
+PROVIDE( Cache_Invalidate_ICache_Items = 0x40000700 );
+PROVIDE( Cache_Op_Addr = 0x40000704 );
+PROVIDE( Cache_Invalidate_Addr = 0x40000708 );
+PROVIDE( Cache_Invalidate_ICache_All = 0x4000070c );
+PROVIDE( Cache_Mask_All = 0x40000710 );
+PROVIDE( Cache_UnMask_Dram0 = 0x40000714 );
+PROVIDE( Cache_Disable_ICache = 0x40000718 );
+PROVIDE( Cache_Enable_ICache = 0x4000071c );
+PROVIDE( Cache_Suspend_ICache = 0x40000720 );
+PROVIDE( Cache_Resume_ICache = 0x40000724 );
+PROVIDE( Cache_Freeze_ICache_Enable = 0x40000728 );
+PROVIDE( Cache_Freeze_ICache_Disable = 0x4000072c );
+PROVIDE( Cache_Set_IDROM_MMU_Size = 0x40000730 );
+PROVIDE( Cache_Get_IROM_MMU_End = 0x40000734 );
+PROVIDE( Cache_Get_DROM_MMU_End = 0x40000738 );
+PROVIDE( Cache_Owner_Init = 0x4000073c );
+PROVIDE( Cache_Occupy_ICache_MEMORY = 0x40000740 );
+PROVIDE( Cache_MMU_Init = 0x40000744 );
+PROVIDE( Cache_Ibus_MMU_Set = 0x40000748 );
+PROVIDE( Cache_Dbus_MMU_Set = 0x4000074c );
+PROVIDE( Cache_Count_Flash_Pages = 0x40000750 );
+PROVIDE( Cache_Travel_Tag_Memory = 0x40000754 );
+PROVIDE( Cache_Get_Virtual_Addr = 0x40000758 );
+PROVIDE( Cache_Get_Memory_BaseAddr = 0x4000075c );
+PROVIDE( Cache_Get_Memory_Addr = 0x40000760 );
+PROVIDE( Cache_Get_Memory_value = 0x40000764 );
+/* Data (.data, .bss, .rodata) */
+PROVIDE( rom_cache_op_cb = 0x3fcdffd0 );
+PROVIDE( rom_cache_internal_table_ptr = 0x3fcdffcc );
+
+
+/***************************************
+ Group clock
+ ***************************************/
+
+/* Functions */
+ets_get_apb_freq = 0x40000768;
+ets_get_cpu_frequency = 0x4000076c;
+ets_update_cpu_frequency = 0x40000770;
+ets_get_printf_channel = 0x40000774;
+ets_get_xtal_div = 0x40000778;
+ets_set_xtal_div = 0x4000077c;
+ets_get_xtal_freq = 0x40000780;
+
+
+/***************************************
+ Group gpio
+ ***************************************/
+
+/* Functions */
+gpio_input_get = 0x40000784;
+gpio_matrix_in = 0x40000788;
+gpio_matrix_out = 0x4000078c;
+gpio_output_disable = 0x40000790;
+gpio_output_enable = 0x40000794;
+gpio_output_set = 0x40000798;
+gpio_pad_hold = 0x4000079c;
+gpio_pad_input_disable = 0x400007a0;
+gpio_pad_input_enable = 0x400007a4;
+gpio_pad_pulldown = 0x400007a8;
+gpio_pad_pullup = 0x400007ac;
+gpio_pad_select_gpio = 0x400007b0;
+gpio_pad_set_drv = 0x400007b4;
+gpio_pad_unhold = 0x400007b8;
+gpio_pin_wakeup_disable = 0x400007bc;
+gpio_pin_wakeup_enable = 0x400007c0;
+gpio_bypass_matrix_in = 0x400007c4;
+
+
+/***************************************
+ Group interrupts
+ ***************************************/
+
+/* Functions */
+esprv_intc_int_set_priority = 0x400007c8;
+esprv_intc_int_set_threshold = 0x400007cc;
+esprv_intc_int_enable = 0x400007d0;
+esprv_intc_int_disable = 0x400007d4;
+esprv_intc_int_set_type = 0x400007d8;
+PROVIDE( intr_handler_set = 0x400007dc );
+intr_matrix_set = 0x400007e0;
+ets_intr_lock = 0x400007e4;
+ets_intr_unlock = 0x400007e8;
+ets_isr_attach = 0x400007ec;
+ets_isr_mask = 0x400007f0;
+ets_isr_unmask = 0x400007f4;
+
+
+/***************************************
+ Group crypto
+ ***************************************/
+
+/* Functions */
+crc32_le = 0x400007f8;
+crc16_le = 0x400007fc;
+crc8_le = 0x40000800;
+crc32_be = 0x40000804;
+crc16_be = 0x40000808;
+crc8_be = 0x4000080c;
+esp_crc8 = 0x40000810;
+ets_sha_enable = 0x40000814;
+ets_sha_disable = 0x40000818;
+ets_sha_get_state = 0x4000081c;
+ets_sha_init = 0x40000820;
+ets_sha_process = 0x40000824;
+ets_sha_starts = 0x40000828;
+ets_sha_update = 0x4000082c;
+ets_sha_finish = 0x40000830;
+ets_sha_clone = 0x40000834;
+/* Data (.data, .bss, .rodata) */
+crc32_le_table_ptr = 0x3ff4fff8;
+crc16_le_table_ptr = 0x3ff4fff4;
+crc8_le_table_ptr = 0x3ff4fff0;
+crc32_be_table_ptr = 0x3ff4ffec;
+crc16_be_table_ptr = 0x3ff4ffe8;
+crc8_be_table_ptr = 0x3ff4ffe4;
+
+
+/***************************************
+ Group efuse
+ ***************************************/
+
+/* Functions */
+ets_efuse_read = 0x40000838;
+ets_efuse_program = 0x4000083c;
+ets_efuse_clear_program_registers = 0x40000840;
+ets_efuse_write_key = 0x40000844;
+ets_efuse_get_read_register_address = 0x40000848;
+ets_efuse_get_key_purpose = 0x4000084c;
+ets_efuse_key_block_unused = 0x40000850;
+ets_efuse_find_unused_key_block = 0x40000854;
+ets_efuse_rs_calculate = 0x40000858;
+ets_efuse_count_unused_key_blocks = 0x4000085c;
+ets_efuse_secure_boot_enabled = 0x40000860;
+ets_efuse_secure_boot_aggressive_revoke_enabled = 0x40000864;
+ets_efuse_cache_encryption_enabled = 0x40000868;
+ets_efuse_download_modes_disabled = 0x4000086c;
+ets_efuse_find_purpose = 0x40000870;
+ets_efuse_force_send_resume = 0x40000874;
+ets_efuse_get_flash_delay_us = 0x40000878;
+ets_efuse_get_mac = 0x4000087c;
+ets_efuse_get_uart_print_control = 0x40000880;
+ets_efuse_direct_boot_mode_disabled = 0x40000884;
+ets_efuse_security_download_modes_enabled = 0x40000888;
+ets_efuse_set_timing = 0x4000088c;
+ets_efuse_jtag_disabled = 0x40000890;
+
+
+/***************************************
+ Group secureboot
+ ***************************************/
+
+/* Functions */
+ets_ecdsa_verify = 0x40000894;
+ets_secure_boot_verify_bootloader_with_keys = 0x40000898;
+ets_secure_boot_verify_signature = 0x4000089c;
+ets_secure_boot_read_key_digests = 0x400008a0;
+
+
+/***************************************
+ Group usb_uart
+ ***************************************/
+
+/* Data (.data, .bss, .rodata) */
+g_uart_print = 0x3fcdffc9;
+g_usb_print = 0x3fcdffc8;
+
+
+/***************************************
+ Group bluetooth
+ ***************************************/
+
+/* Functions */
+ble_controller_rom_data_init = 0x40000a14;
+ble_osi_coex_funcs_register = 0x40000a18;
+bt_rf_coex_cfg_get_default = 0x40000a1c;
+bt_rf_coex_dft_pti_get_default = 0x40000a20;
+bt_rf_coex_hooks_p_set = 0x40000a24;
+r__os_mbuf_copypkthdr = 0x40000a28;
+r__os_msys_find_pool = 0x40000a2c;
+r_ble_controller_get_rom_compile_version = 0x40000a30;
+r_ble_hci_ram_hs_acl_tx = 0x40000a34;
+r_ble_hci_ram_hs_cmd_tx = 0x40000a38;
+r_ble_hci_ram_ll_acl_tx = 0x40000a3c;
+r_ble_hci_ram_ll_evt_tx = 0x40000a40;
+r_ble_hci_ram_reset = 0x40000a44;
+r_ble_hci_ram_set_acl_free_cb = 0x40000a48;
+r_ble_hci_trans_acl_buf_alloc = 0x40000a4c;
+r_ble_hci_trans_buf_alloc = 0x40000a50;
+r_ble_hci_trans_buf_free = 0x40000a54;
+r_ble_hci_trans_cfg_hs = 0x40000a58;
+r_ble_hci_trans_cfg_ll = 0x40000a5c;
+r_ble_hci_trans_deinit = 0x40000a60;
+r_ble_hci_trans_env_init = 0x40000a64;
+r_ble_hci_trans_init = 0x40000a68;
+r_ble_hci_uart_acl_tx = 0x40000a6c;
+r_ble_hci_uart_cmdevt_tx = 0x40000a70;
+r_ble_hci_uart_config = 0x40000a74;
+r_ble_hci_uart_free_pkt = 0x40000a78;
+r_ble_hci_uart_hs_acl_tx = 0x40000a7c;
+r_ble_hci_uart_hs_cmd_tx = 0x40000a80;
+r_ble_hci_uart_ll_acl_tx = 0x40000a84;
+r_ble_hci_uart_ll_evt_tx = 0x40000a88;
+r_ble_hci_uart_rx_acl = 0x40000a8c;
+r_ble_hci_uart_rx_char = 0x40000a90;
+r_ble_hci_uart_rx_cmd = 0x40000a94;
+r_ble_hci_uart_rx_evt = 0x40000a98;
+r_ble_hci_uart_rx_evt_cb = 0x40000a9c;
+r_ble_hci_uart_rx_le_evt = 0x40000aa0;
+r_ble_hci_uart_rx_pkt_type = 0x40000aa4;
+r_ble_hci_uart_rx_skip_acl = 0x40000aa8;
+r_ble_hci_uart_rx_skip_cmd = 0x40000aac;
+r_ble_hci_uart_rx_skip_evt = 0x40000ab0;
+r_ble_hci_uart_rx_sync_loss = 0x40000ab4;
+r_ble_hci_uart_set_acl_free_cb = 0x40000ab8;
+r_ble_hci_uart_sync_lost = 0x40000abc;
+r_ble_hci_uart_trans_reset = 0x40000ac0;
+r_ble_hci_uart_tx_char = 0x40000ac4;
+r_ble_hci_uart_tx_pkt_type = 0x40000ac8;
+r_ble_hw_driver_deinit = 0x40000acc;
+r_ble_hw_driver_env_init = 0x40000ad0;
+r_ble_hw_encrypt_block = 0x40000ad4;
+r_ble_hw_get_public_addr = 0x40000ad8;
+r_ble_hw_get_static_addr = 0x40000adc;
+r_ble_hw_periodiclist_add = 0x40000ae0;
+r_ble_hw_periodiclist_clear = 0x40000ae4;
+r_ble_hw_periodiclist_rmv = 0x40000ae8;
+r_ble_hw_resolv_list_cur_entry = 0x40000aec;
+r_ble_hw_resolv_list_match = 0x40000af0;
+r_ble_hw_resolv_list_set = 0x40000af4;
+r_ble_hw_rng_init = 0x40000af8;
+r_ble_hw_rng_start = 0x40000afc;
+r_ble_hw_rng_stop = 0x40000b00;
+r_ble_hw_rx_local_is_rpa = 0x40000b04;
+r_ble_hw_whitelist_add = 0x40000b08;
+r_ble_hw_whitelist_clear = 0x40000b0c;
+r_ble_hw_whitelist_dev_num = 0x40000b10;
+r_ble_hw_whitelist_get_base = 0x40000b14;
+r_ble_hw_whitelist_rmv = 0x40000b18;
+r_ble_hw_whitelist_search = 0x40000b1c;
+r_ble_hw_whitelist_sort = 0x40000b20;
+r_ble_ll_acl_data_in = 0x40000b24;
+r_ble_ll_addr_is_id = 0x40000b28;
+r_ble_ll_addr_subtype = 0x40000b2c;
+r_ble_ll_adv_active_chanset_clear = 0x40000b30;
+r_ble_ll_adv_active_chanset_is_pri = 0x40000b34;
+r_ble_ll_adv_active_chanset_is_sec = 0x40000b38;
+r_ble_ll_adv_active_chanset_set_pri = 0x40000b3c;
+r_ble_ll_adv_active_chanset_set_sec = 0x40000b40;
+r_ble_ll_adv_aux_calculate = 0x40000b44;
+r_ble_ll_adv_aux_conn_rsp_pdu_make = 0x40000b48;
+r_ble_ll_adv_aux_pdu_make = 0x40000b4c;
+r_ble_ll_adv_aux_scannable_pdu_make = 0x40000b50;
+r_ble_ll_adv_aux_scannable_pdu_payload_len = 0x40000b54;
+r_ble_ll_adv_aux_schedule = 0x40000b58;
+r_ble_ll_adv_aux_schedule_first = 0x40000b5c;
+r_ble_ll_adv_aux_schedule_next = 0x40000b60;
+r_ble_ll_adv_aux_scheduled = 0x40000b64;
+r_ble_ll_adv_aux_set_start_time = 0x40000b68;
+r_ble_ll_adv_aux_txed = 0x40000b6c;
+r_ble_ll_adv_can_chg_whitelist = 0x40000b70;
+r_ble_ll_adv_chk_rpa_timeout = 0x40000b74;
+r_ble_ll_adv_clear_all = 0x40000b78;
+r_ble_ll_adv_coex_dpc_calc_pti_update_itvl = 0x40000b7c;
+r_ble_ll_adv_coex_dpc_process_pri = 0x40000b80;
+r_ble_ll_adv_coex_dpc_process_sec = 0x40000b84;
+r_ble_ll_adv_coex_dpc_pti_get = 0x40000b88;
+r_ble_ll_adv_coex_dpc_update = 0x40000b8c;
+r_ble_ll_adv_coex_dpc_update_on_adv_start = 0x40000b90;
+r_ble_ll_adv_coex_dpc_update_on_aux_scheduled = 0x40000b94;
+r_ble_ll_adv_coex_dpc_update_on_data_updated = 0x40000b98;
+r_ble_ll_adv_coex_dpc_update_on_event_end = 0x40000b9c;
+r_ble_ll_adv_coex_dpc_update_on_event_scheduled = 0x40000ba0;
+r_ble_ll_adv_conn_req_rxd = 0x40000ba4;
+r_ble_ll_adv_deinit = 0x40000ba8;
+r_ble_ll_adv_done = 0x40000bac;
+r_ble_ll_adv_drop_event = 0x40000bb0;
+r_ble_ll_adv_enabled = 0x40000bb4;
+r_ble_ll_adv_env_init = 0x40000bb8;
+r_ble_ll_adv_event_done = 0x40000bbc;
+r_ble_ll_adv_event_rmvd_from_sched = 0x40000bc0;
+r_ble_ll_adv_ext_estimate_data_itvl = 0x40000bc4;
+r_ble_ll_adv_ext_set_adv_data = 0x40000bc8;
+r_ble_ll_adv_ext_set_enable = 0x40000bcc;
+r_ble_ll_adv_ext_set_param = 0x40000bd0;
+r_ble_ll_adv_ext_set_scan_rsp = 0x40000bd4;
+r_ble_ll_adv_final_chan = 0x40000bd8;
+r_ble_ll_adv_first_chan = 0x40000bdc;
+r_ble_ll_adv_flags_clear = 0x40000be0;
+r_ble_ll_adv_flags_set = 0x40000be4;
+r_ble_ll_adv_get_local_rpa = 0x40000be8;
+r_ble_ll_adv_get_peer_rpa = 0x40000bec;
+r_ble_ll_adv_get_sec_pdu_len = 0x40000bf0;
+r_ble_ll_adv_halt = 0x40000bf4;
+r_ble_ll_adv_hci_set_random_addr = 0x40000bf8;
+r_ble_ll_adv_init = 0x40000bfc;
+r_ble_ll_adv_legacy_pdu_make = 0x40000c00;
+r_ble_ll_adv_make_done = 0x40000c04;
+r_ble_ll_adv_pdu_make = 0x40000c08;
+r_ble_ll_adv_periodic_check_data_itvl = 0x40000c0c;
+r_ble_ll_adv_periodic_done = 0x40000c10;
+r_ble_ll_adv_periodic_enable = 0x40000c14;
+r_ble_ll_adv_periodic_estimate_data_itvl = 0x40000c18;
+r_ble_ll_adv_periodic_event_done = 0x40000c1c;
+r_ble_ll_adv_periodic_rmvd_from_sched = 0x40000c20;
+r_ble_ll_adv_periodic_schedule_first = 0x40000c24;
+r_ble_ll_adv_periodic_schedule_next = 0x40000c28;
+r_ble_ll_adv_periodic_send_sync_ind = 0x40000c2c;
+r_ble_ll_adv_periodic_set_data = 0x40000c30;
+r_ble_ll_adv_periodic_set_info_transfer = 0x40000c34;
+r_ble_ll_adv_periodic_set_param = 0x40000c38;
+r_ble_ll_adv_put_aux_ptr = 0x40000c3c;
+r_ble_ll_adv_put_syncinfo = 0x40000c40;
+r_ble_ll_adv_rd_max_adv_data_len = 0x40000c44;
+r_ble_ll_adv_rd_sup_adv_sets = 0x40000c48;
+r_ble_ll_adv_read_txpwr = 0x40000c4c;
+r_ble_ll_adv_remove = 0x40000c50;
+r_ble_ll_adv_reschedule_event = 0x40000c54;
+r_ble_ll_adv_reschedule_periodic_event = 0x40000c58;
+r_ble_ll_adv_reset = 0x40000c5c;
+r_ble_ll_adv_rpa_timeout = 0x40000c60;
+r_ble_ll_adv_rpa_update = 0x40000c64;
+r_ble_ll_adv_rx_isr_end = 0x40000c68;
+r_ble_ll_adv_rx_isr_start = 0x40000c6c;
+r_ble_ll_adv_rx_pkt_in = 0x40000c70;
+r_ble_ll_adv_rx_req = 0x40000c74;
+r_ble_ll_adv_scan_rsp_legacy_pdu_make = 0x40000c78;
+r_ble_ll_adv_scan_rsp_pdu_make = 0x40000c7c;
+r_ble_ll_adv_scheduled = 0x40000c80;
+r_ble_ll_adv_sec_done = 0x40000c84;
+r_ble_ll_adv_sec_event_done = 0x40000c88;
+r_ble_ll_adv_secondary_tx_start_cb = 0x40000c8c;
+r_ble_ll_adv_send_conn_comp_ev = 0x40000c90;
+r_ble_ll_adv_set_adv_data = 0x40000c94;
+r_ble_ll_adv_set_adv_params = 0x40000c98;
+r_ble_ll_adv_set_enable = 0x40000c9c;
+r_ble_ll_adv_set_random_addr = 0x40000ca0;
+r_ble_ll_adv_set_scan_rsp_data = 0x40000ca4;
+r_ble_ll_adv_set_sched = 0x40000ca8;
+r_ble_ll_adv_sm_deinit = 0x40000cac;
+r_ble_ll_adv_sm_event_init = 0x40000cb0;
+r_ble_ll_adv_sm_event_restore = 0x40000cb4;
+r_ble_ll_adv_sm_event_store = 0x40000cb8;
+r_ble_ll_adv_sm_find_configured = 0x40000cbc;
+r_ble_ll_adv_sm_get = 0x40000cc0;
+r_ble_ll_adv_sm_init = 0x40000cc4;
+r_ble_ll_adv_sm_reset = 0x40000cc8;
+r_ble_ll_adv_sm_start = 0x40000ccc;
+r_ble_ll_adv_sm_start_periodic = 0x40000cd0;
+r_ble_ll_adv_sm_stop = 0x40000cd4;
+r_ble_ll_adv_sm_stop_limit_reached = 0x40000cd8;
+r_ble_ll_adv_sm_stop_periodic = 0x40000cdc;
+r_ble_ll_adv_sm_stop_timeout = 0x40000ce0;
+r_ble_ll_adv_sync_calculate = 0x40000ce4;
+r_ble_ll_adv_sync_get_pdu_len = 0x40000ce8;
+r_ble_ll_adv_sync_next_scheduled = 0x40000cec;
+r_ble_ll_adv_sync_pdu_make = 0x40000cf0;
+r_ble_ll_adv_sync_schedule = 0x40000cf4;
+r_ble_ll_adv_sync_tx_done = 0x40000cf8;
+r_ble_ll_adv_sync_tx_end = 0x40000cfc;
+r_ble_ll_adv_sync_tx_start_cb = 0x40000d00;
+r_ble_ll_adv_tx_done = 0x40000d04;
+r_ble_ll_adv_tx_start_cb = 0x40000d08;
+r_ble_ll_adv_update_adv_scan_rsp_data = 0x40000d0c;
+r_ble_ll_adv_update_data_mbuf = 0x40000d10;
+r_ble_ll_adv_update_did = 0x40000d14;
+r_ble_ll_adv_update_periodic_data = 0x40000d18;
+r_ble_ll_adv_wfr_timer_exp = 0x40000d1c;
+r_ble_ll_arr_pool_init = 0x40000d20;
+r_ble_ll_auth_pyld_tmo_event_send = 0x40000d24;
+r_ble_ll_aux_scan_cb = 0x40000d28;
+r_ble_ll_aux_scan_drop = 0x40000d2c;
+r_ble_ll_aux_scan_drop_event_cb = 0x40000d30;
+r_ble_ll_calc_offset_ticks_us_for_rampup = 0x40000d34;
+r_ble_ll_calc_session_key = 0x40000d38;
+r_ble_ll_calc_ticks_per_slot = 0x40000d3c;
+r_ble_ll_calc_us_convert_tick_unit = 0x40000d40;
+r_ble_ll_check_scan_params = 0x40000d44;
+r_ble_ll_chk_txrx_octets = 0x40000d48;
+r_ble_ll_chk_txrx_time = 0x40000d4c;
+r_ble_ll_conn_adjust_pyld_len = 0x40000d50;
+r_ble_ll_conn_auth_pyld_timer_cb = 0x40000d54;
+r_ble_ll_conn_auth_pyld_timer_start = 0x40000d58;
+r_ble_ll_conn_calc_dci = 0x40000d5c;
+r_ble_ll_conn_calc_dci_csa1 = 0x40000d60;
+r_ble_ll_conn_calc_itvl_ticks = 0x40000d64;
+r_ble_ll_conn_can_send_next_pdu = 0x40000d68;
+r_ble_ll_conn_chk_csm_flags = 0x40000d6c;
+r_ble_ll_conn_chk_phy_upd_start = 0x40000d70;
+r_ble_ll_conn_coex_dpc_process = 0x40000d74;
+r_ble_ll_conn_coex_dpc_pti_get = 0x40000d78;
+r_ble_ll_conn_coex_dpc_update = 0x40000d7c;
+r_ble_ll_conn_coex_dpc_update_on_event_scheduled = 0x40000d80;
+r_ble_ll_conn_comp_event_send = 0x40000d84;
+r_ble_ll_conn_connect_ind_pdu_make = 0x40000d88;
+r_ble_ll_conn_create = 0x40000d8c;
+r_ble_ll_conn_create_cancel = 0x40000d90;
+r_ble_ll_conn_created = 0x40000d94;
+r_ble_ll_conn_cth_flow_alloc_credit = 0x40000d98;
+r_ble_ll_conn_cth_flow_enable = 0x40000d9c;
+r_ble_ll_conn_cth_flow_error_fn = 0x40000da0;
+r_ble_ll_conn_cth_flow_free_credit = 0x40000da4;
+r_ble_ll_conn_cth_flow_have_credit = 0x40000da8;
+r_ble_ll_conn_cth_flow_is_enabled = 0x40000dac;
+r_ble_ll_conn_cth_flow_process_cmd = 0x40000db0;
+r_ble_ll_conn_cth_flow_set_buffers = 0x40000db4;
+r_ble_ll_conn_cur_pducb = 0x40000db8;
+r_ble_ll_conn_current_sm_over = 0x40000dbc;
+r_ble_ll_conn_end = 0x40000dc0;
+r_ble_ll_conn_enqueue_pkt = 0x40000dc4;
+r_ble_ll_conn_env_init = 0x40000dc8;
+r_ble_ll_conn_event_end = 0x40000dcc;
+r_ble_ll_conn_event_end_timer_cb = 0x40000dd0;
+r_ble_ll_conn_event_halt = 0x40000dd4;
+r_ble_ll_conn_event_is_over = 0x40000dd8;
+r_ble_ll_conn_event_start_cb = 0x40000ddc;
+r_ble_ll_conn_ext_master_init = 0x40000de0;
+r_ble_ll_conn_ext_set_params = 0x40000de4;
+r_ble_ll_conn_find_active_conn = 0x40000de8;
+r_ble_ll_conn_get_anchor = 0x40000dec;
+r_ble_ll_conn_get_ce_end_time = 0x40000df0;
+r_ble_ll_conn_get_new_pdu = 0x40000df4;
+r_ble_ll_conn_get_next_sched_time = 0x40000df8;
+r_ble_ll_conn_halt = 0x40000dfc;
+r_ble_ll_conn_hcc_params_set_fallback = 0x40000e00;
+r_ble_ll_conn_hci_cancel_conn_complete_event = 0x40000e04;
+r_ble_ll_conn_hci_chk_conn_params = 0x40000e08;
+r_ble_ll_conn_hci_chk_scan_params = 0x40000e0c;
+r_ble_ll_conn_hci_disconnect_cmd = 0x40000e10;
+r_ble_ll_conn_hci_le_ltk_neg_reply = 0x40000e14;
+r_ble_ll_conn_hci_le_ltk_reply = 0x40000e18;
+r_ble_ll_conn_hci_le_rd_phy = 0x40000e1c;
+r_ble_ll_conn_hci_le_set_phy = 0x40000e20;
+r_ble_ll_conn_hci_le_start_encrypt = 0x40000e24;
+r_ble_ll_conn_hci_param_nrr = 0x40000e28;
+r_ble_ll_conn_hci_param_rr = 0x40000e2c;
+r_ble_ll_conn_hci_rd_auth_pyld_tmo = 0x40000e30;
+r_ble_ll_conn_hci_rd_chan_map = 0x40000e34;
+r_ble_ll_conn_hci_rd_rem_ver_cmd = 0x40000e38;
+r_ble_ll_conn_hci_rd_rssi = 0x40000e3c;
+r_ble_ll_conn_hci_read_rem_features = 0x40000e40;
+r_ble_ll_conn_hci_set_chan_class = 0x40000e44;
+r_ble_ll_conn_hci_set_data_len = 0x40000e48;
+r_ble_ll_conn_hci_update = 0x40000e4c;
+r_ble_ll_conn_hci_wr_auth_pyld_tmo = 0x40000e50;
+r_ble_ll_conn_init_pending_aux_conn_rsp = 0x40000e54;
+r_ble_ll_conn_init_phy = 0x40000e58;
+r_ble_ll_conn_init_wfr_timer_exp = 0x40000e5c;
+r_ble_ll_conn_is_empty_pdu = 0x40000e60;
+r_ble_ll_conn_is_lru = 0x40000e64;
+r_ble_ll_conn_master_common_init = 0x40000e68;
+r_ble_ll_conn_master_init = 0x40000e6c;
+r_ble_ll_conn_module_deinit = 0x40000e70;
+r_ble_ll_conn_module_init = 0x40000e74;
+r_ble_ll_conn_module_reset = 0x40000e78;
+r_ble_ll_conn_new_pducb = 0x40000e7c;
+r_ble_ll_conn_next_event = 0x40000e80;
+r_ble_ll_conn_num_comp_pkts_event_send = 0x40000e84;
+r_ble_ll_conn_process_conn_params = 0x40000e88;
+r_ble_ll_conn_recv_ack = 0x40000e8c;
+r_ble_ll_conn_reset_pending_aux_conn_rsp = 0x40000e90;
+r_ble_ll_conn_rx_data_pdu = 0x40000e94;
+r_ble_ll_conn_rx_isr_end = 0x40000e98;
+r_ble_ll_conn_rx_isr_start = 0x40000e9c;
+r_ble_ll_conn_rxend_unencrypt = 0x40000ea0;
+r_ble_ll_conn_set_csa = 0x40000ea4;
+r_ble_ll_conn_set_global_chanmap = 0x40000ea8;
+r_ble_ll_conn_set_md_flag = 0x40000eac;
+r_ble_ll_conn_set_phy = 0x40000eb0;
+r_ble_ll_conn_set_slave_flow_control = 0x40000eb4;
+r_ble_ll_conn_set_txpwr_by_handle = 0x40000eb8;
+r_ble_ll_conn_set_unknown_rx_octets = 0x40000ebc;
+r_ble_ll_conn_slave_start = 0x40000ec0;
+r_ble_ll_conn_sm_get = 0x40000ec4;
+r_ble_ll_conn_sm_new = 0x40000ec8;
+r_ble_ll_conn_sm_npl_deinit = 0x40000ecc;
+r_ble_ll_conn_sm_npl_init = 0x40000ed0;
+r_ble_ll_conn_start_rx_encrypt = 0x40000ed4;
+r_ble_ll_conn_start_rx_unencrypt = 0x40000ed8;
+r_ble_ll_conn_timeout = 0x40000edc;
+r_ble_ll_conn_tx_pdu = 0x40000ee0;
+r_ble_ll_conn_tx_pkt_in = 0x40000ee4;
+r_ble_ll_conn_txend_encrypt = 0x40000ee8;
+r_ble_ll_conn_update_conn_params = 0x40000eec;
+r_ble_ll_conn_update_eff_data_len = 0x40000ef0;
+r_ble_ll_conn_update_new_pdu_len = 0x40000ef4;
+r_ble_ll_conn_wait_txend = 0x40000ef8;
+r_ble_ll_conn_wfr_timer_exp = 0x40000efc;
+r_ble_ll_copy_data = 0x40000f00;
+r_ble_ll_count_rx_adv_pdus = 0x40000f04;
+r_ble_ll_count_rx_stats = 0x40000f08;
+r_ble_ll_ctrl_chanmap_req_make = 0x40000f0c;
+r_ble_ll_ctrl_chk_proc_start = 0x40000f10;
+r_ble_ll_ctrl_conn_param_pdu_make = 0x40000f14;
+r_ble_ll_ctrl_conn_param_pdu_proc = 0x40000f18;
+r_ble_ll_ctrl_conn_param_reply = 0x40000f1c;
+r_ble_ll_ctrl_conn_upd_make = 0x40000f20;
+r_ble_ll_ctrl_datalen_upd_make = 0x40000f24;
+r_ble_ll_ctrl_enc_allowed_pdu = 0x40000f28;
+r_ble_ll_ctrl_enc_allowed_pdu_rx = 0x40000f2c;
+r_ble_ll_ctrl_enc_allowed_pdu_tx = 0x40000f30;
+r_ble_ll_ctrl_enc_req_make = 0x40000f34;
+r_ble_ll_ctrl_find_new_phy = 0x40000f38;
+r_ble_ll_ctrl_initiate_dle = 0x40000f3c;
+r_ble_ll_ctrl_is_start_enc_rsp = 0x40000f40;
+r_ble_ll_ctrl_is_terminate_ind = 0x40000f44;
+r_ble_ll_ctrl_len_proc = 0x40000f48;
+r_ble_ll_ctrl_phy_from_phy_mask = 0x40000f4c;
+r_ble_ll_ctrl_phy_req_rsp_make = 0x40000f50;
+r_ble_ll_ctrl_phy_tx_transition_get = 0x40000f54;
+r_ble_ll_ctrl_phy_update_cancel = 0x40000f58;
+r_ble_ll_ctrl_phy_update_ind_make = 0x40000f5c;
+r_ble_ll_ctrl_phy_update_proc_complete = 0x40000f60;
+r_ble_ll_ctrl_proc_init = 0x40000f64;
+r_ble_ll_ctrl_proc_rsp_timer_cb = 0x40000f68;
+r_ble_ll_ctrl_proc_start = 0x40000f6c;
+r_ble_ll_ctrl_proc_stop = 0x40000f70;
+r_ble_ll_ctrl_proc_unk_rsp = 0x40000f74;
+r_ble_ll_ctrl_proc_with_instant_initiated = 0x40000f78;
+r_ble_ll_ctrl_rej_ext_ind_make = 0x40000f7c;
+r_ble_ll_ctrl_reject_ind_send = 0x40000f80;
+r_ble_ll_ctrl_rx_chanmap_req = 0x40000f84;
+r_ble_ll_ctrl_rx_conn_param_req = 0x40000f88;
+r_ble_ll_ctrl_rx_conn_param_rsp = 0x40000f8c;
+r_ble_ll_ctrl_rx_conn_update = 0x40000f90;
+r_ble_ll_ctrl_rx_enc_req = 0x40000f94;
+r_ble_ll_ctrl_rx_enc_rsp = 0x40000f98;
+r_ble_ll_ctrl_rx_feature_req = 0x40000f9c;
+r_ble_ll_ctrl_rx_feature_rsp = 0x40000fa0;
+r_ble_ll_ctrl_rx_pause_enc_req = 0x40000fa4;
+r_ble_ll_ctrl_rx_pause_enc_rsp = 0x40000fa8;
+r_ble_ll_ctrl_rx_pdu = 0x40000fac;
+r_ble_ll_ctrl_rx_periodic_sync_ind = 0x40000fb0;
+r_ble_ll_ctrl_rx_phy_req = 0x40000fb4;
+r_ble_ll_ctrl_rx_phy_rsp = 0x40000fb8;
+r_ble_ll_ctrl_rx_phy_update_ind = 0x40000fbc;
+r_ble_ll_ctrl_rx_ping_rsp = 0x40000fc0;
+r_ble_ll_ctrl_rx_reject_ind = 0x40000fc4;
+r_ble_ll_ctrl_rx_start_enc_req = 0x40000fc8;
+r_ble_ll_ctrl_rx_start_enc_rsp = 0x40000fcc;
+r_ble_ll_ctrl_rx_version_ind = 0x40000fd0;
+r_ble_ll_ctrl_start_enc_send = 0x40000fd4;
+r_ble_ll_ctrl_start_rsp_timer = 0x40000fd8;
+r_ble_ll_ctrl_terminate_start = 0x40000fdc;
+r_ble_ll_ctrl_tx_done = 0x40000fe0;
+r_ble_ll_ctrl_update_features = 0x40000fe4;
+r_ble_ll_ctrl_version_ind_make = 0x40000fe8;
+r_ble_ll_data_buffer_overflow = 0x40000fec;
+r_ble_ll_deinit = 0x40000ff0;
+r_ble_ll_disconn_comp_event_send = 0x40000ff4;
+r_ble_ll_dtm_calculate_itvl = 0x40000ff8;
+r_ble_ll_dtm_ctx_free = 0x40000ffc;
+r_ble_ll_dtm_deinit = 0x40001000;
+r_ble_ll_dtm_end_test = 0x40001004;
+r_ble_ll_dtm_ev_rx_restart_cb = 0x40001008;
+r_ble_ll_dtm_ev_tx_resched_cb = 0x4000100c;
+r_ble_ll_dtm_init = 0x40001010;
+r_ble_ll_dtm_reset = 0x40001014;
+r_ble_ll_dtm_rx_create_ctx = 0x40001018;
+r_ble_ll_dtm_rx_isr_end = 0x4000101c;
+r_ble_ll_dtm_rx_isr_start = 0x40001020;
+r_ble_ll_dtm_rx_pkt_in = 0x40001024;
+r_ble_ll_dtm_rx_sched_cb = 0x40001028;
+r_ble_ll_dtm_rx_start = 0x4000102c;
+r_ble_ll_dtm_rx_test = 0x40001030;
+r_ble_ll_dtm_set_next = 0x40001034;
+r_ble_ll_dtm_tx_create_ctx = 0x40001038;
+r_ble_ll_dtm_tx_done = 0x4000103c;
+r_ble_ll_dtm_tx_sched_cb = 0x40001040;
+r_ble_ll_dtm_tx_test = 0x40001044;
+r_ble_ll_dtm_wfr_timer_exp = 0x40001048;
+r_ble_ll_env_init = 0x4000104c;
+r_ble_ll_event_comp_pkts = 0x40001050;
+r_ble_ll_event_dbuf_overflow = 0x40001054;
+r_ble_ll_event_rx_pkt = 0x40001058;
+r_ble_ll_event_send = 0x4000105c;
+r_ble_ll_event_tx_pkt = 0x40001060;
+r_ble_ll_ext_adv_phy_mode_to_local_phy = 0x40001064;
+r_ble_ll_ext_conn_create = 0x40001068;
+r_ble_ll_ext_scan_coex_dpc_process = 0x4000106c;
+r_ble_ll_ext_scan_coex_dpc_pti_get = 0x40001070;
+r_ble_ll_ext_scan_coex_dpc_update = 0x40001074;
+r_ble_ll_ext_scan_coex_dpc_update_on_start = 0x40001078;
+r_ble_ll_ext_scan_parse_adv_info = 0x4000107c;
+r_ble_ll_ext_scan_parse_aux_ptr = 0x40001080;
+r_ble_ll_flush_pkt_queue = 0x40001084;
+r_ble_ll_generic_data_init = 0x40001088;
+r_ble_ll_get_addr_type = 0x4000108c;
+r_ble_ll_get_chan_to_scan = 0x40001090;
+r_ble_ll_get_our_devaddr = 0x40001094;
+r_ble_ll_get_tx_pwr_compensation = 0x40001098;
+r_ble_ll_hci_acl_rx = 0x4000109c;
+r_ble_ll_hci_adv_mode_ext = 0x400010a0;
+r_ble_ll_hci_adv_set_enable = 0x400010a4;
+r_ble_ll_hci_cb_host_buf_size = 0x400010a8;
+r_ble_ll_hci_cb_set_ctrlr_to_host_fc = 0x400010ac;
+r_ble_ll_hci_cb_set_event_mask = 0x400010b0;
+r_ble_ll_hci_cb_set_event_mask2 = 0x400010b4;
+r_ble_ll_hci_chk_phy_masks = 0x400010b8;
+r_ble_ll_hci_cmd_proc = 0x400010bc;
+r_ble_ll_hci_cmd_rx = 0x400010c0;
+r_ble_ll_hci_ctlr_bb_cmd_proc = 0x400010c4;
+r_ble_ll_hci_deinit = 0x400010c8;
+r_ble_ll_hci_disconnect = 0x400010cc;
+r_ble_ll_hci_dtm_rx_test = 0x400010d0;
+r_ble_ll_hci_dtm_rx_test_v2 = 0x400010d4;
+r_ble_ll_hci_dtm_tx_test = 0x400010d8;
+r_ble_ll_hci_dtm_tx_test_ext = 0x400010dc;
+r_ble_ll_hci_dtm_tx_test_v2 = 0x400010e0;
+r_ble_ll_hci_dtm_tx_test_v2_ext = 0x400010e4;
+r_ble_ll_hci_env_init = 0x400010e8;
+r_ble_ll_hci_ev_conn_update = 0x400010ec;
+r_ble_ll_hci_ev_databuf_overflow = 0x400010f0;
+r_ble_ll_hci_ev_datalen_chg = 0x400010f4;
+r_ble_ll_hci_ev_encrypt_chg = 0x400010f8;
+r_ble_ll_hci_ev_hw_err = 0x400010fc;
+r_ble_ll_hci_ev_le_csa = 0x40001100;
+r_ble_ll_hci_ev_ltk_req = 0x40001104;
+r_ble_ll_hci_ev_phy_update = 0x40001108;
+r_ble_ll_hci_ev_rd_rem_used_feat = 0x4000110c;
+r_ble_ll_hci_ev_rd_rem_ver = 0x40001110;
+r_ble_ll_hci_ev_rem_conn_parm_req = 0x40001114;
+r_ble_ll_hci_ev_send_adv_set_terminated = 0x40001118;
+r_ble_ll_hci_ev_send_scan_req_recv = 0x4000111c;
+r_ble_ll_hci_ev_send_scan_timeout = 0x40001120;
+r_ble_ll_hci_ev_send_vendor_err = 0x40001124;
+r_ble_ll_hci_event_send = 0x40001128;
+r_ble_ll_hci_ext_scan_set_enable = 0x4000112c;
+r_ble_ll_hci_get_num_cmd_pkts = 0x40001130;
+r_ble_ll_hci_info_params_cmd_proc = 0x40001134;
+r_ble_ll_hci_init = 0x40001138;
+r_ble_ll_hci_is_event_enabled = 0x4000113c;
+r_ble_ll_hci_is_le_event_enabled = 0x40001140;
+r_ble_ll_hci_le_cmd_proc = 0x40001144;
+r_ble_ll_hci_le_cmd_send_cmd_status = 0x40001148;
+r_ble_ll_hci_le_encrypt = 0x4000114c;
+r_ble_ll_hci_le_rand = 0x40001150;
+r_ble_ll_hci_le_rd_max_data_len = 0x40001154;
+r_ble_ll_hci_le_rd_sugg_data_len = 0x40001158;
+r_ble_ll_hci_le_read_bufsize = 0x4000115c;
+r_ble_ll_hci_le_read_local_features = 0x40001160;
+r_ble_ll_hci_le_read_supp_states = 0x40001164;
+r_ble_ll_hci_le_set_def_phy = 0x40001168;
+r_ble_ll_hci_le_wr_sugg_data_len = 0x4000116c;
+r_ble_ll_hci_link_ctrl_cmd_proc = 0x40001170;
+r_ble_ll_hci_npl_init = 0x40001174;
+r_ble_ll_hci_rd_bd_addr = 0x40001178;
+r_ble_ll_hci_rd_local_supp_cmd = 0x4000117c;
+r_ble_ll_hci_rd_local_supp_feat = 0x40001180;
+r_ble_ll_hci_rd_local_version = 0x40001184;
+r_ble_ll_hci_scan_set_enable = 0x40001188;
+r_ble_ll_hci_send_adv_report = 0x4000118c;
+r_ble_ll_hci_send_dir_adv_report = 0x40001190;
+r_ble_ll_hci_send_ext_adv_report = 0x40001194;
+r_ble_ll_hci_send_legacy_ext_adv_report = 0x40001198;
+r_ble_ll_hci_send_noop = 0x4000119c;
+r_ble_ll_hci_set_adv_data = 0x400011a0;
+r_ble_ll_hci_set_le_event_mask = 0x400011a4;
+r_ble_ll_hci_set_scan_rsp_data = 0x400011a8;
+r_ble_ll_hci_status_params_cmd_proc = 0x400011ac;
+r_ble_ll_hci_vs_cmd_proc = 0x400011b0;
+r_ble_ll_hci_vs_rd_static_addr = 0x400011b4;
+r_ble_ll_hw_err_timer_cb = 0x400011b8;
+r_ble_ll_hw_error = 0x400011bc;
+r_ble_ll_init = 0x400011c0;
+r_ble_ll_init_alloc_conn_comp_ev = 0x400011c4;
+r_ble_ll_init_get_conn_comp_ev = 0x400011c8;
+r_ble_ll_init_rx_isr_end = 0x400011cc;
+r_ble_ll_init_rx_isr_start = 0x400011d0;
+r_ble_ll_init_rx_pkt_in = 0x400011d4;
+r_ble_ll_is_addr_empty = 0x400011d8;
+r_ble_ll_is_controller_busy = 0x400011dc;
+r_ble_ll_is_on_resolv_list = 0x400011e0;
+r_ble_ll_is_our_devaddr = 0x400011e4;
+r_ble_ll_is_rpa = 0x400011e8;
+r_ble_ll_is_valid_adv_mode = 0x400011ec;
+r_ble_ll_is_valid_own_addr_type = 0x400011f0;
+r_ble_ll_is_valid_public_addr = 0x400011f4;
+r_ble_ll_is_valid_random_addr = 0x400011f8;
+r_ble_ll_mbuf_init = 0x400011fc;
+r_ble_ll_misc_options_set = 0x40001200;
+r_ble_ll_pdu_max_tx_octets_get = 0x40001204;
+r_ble_ll_pdu_tx_time_get = 0x40001208;
+r_ble_ll_per_adv_coex_dpc_calc_pti_update_itvl = 0x4000120c;
+r_ble_ll_per_adv_coex_dpc_process = 0x40001210;
+r_ble_ll_per_adv_coex_dpc_pti_get = 0x40001214;
+r_ble_ll_per_adv_coex_dpc_update = 0x40001218;
+r_ble_ll_per_adv_coex_dpc_update_on_data_updated = 0x4000121c;
+r_ble_ll_per_adv_coex_dpc_update_on_scheduled = 0x40001220;
+r_ble_ll_per_adv_coex_dpc_update_on_start = 0x40001224;
+r_ble_ll_phy_to_phy_mode = 0x40001228;
+r_ble_ll_process_rx_data = 0x4000122c;
+r_ble_ll_qa_enable = 0x40001230;
+r_ble_ll_rand = 0x40001234;
+r_ble_ll_rand_data_get = 0x40001238;
+r_ble_ll_rand_deinit = 0x4000123c;
+r_ble_ll_rand_env_init = 0x40001240;
+r_ble_ll_rand_init = 0x40001244;
+r_ble_ll_rand_prand_get = 0x40001248;
+r_ble_ll_rand_sample = 0x4000124c;
+r_ble_ll_rand_start = 0x40001250;
+r_ble_ll_read_rf_path_compensation = 0x40001254;
+r_ble_ll_read_supp_features = 0x40001258;
+r_ble_ll_read_supp_states = 0x4000125c;
+r_ble_ll_read_tx_power = 0x40001260;
+r_ble_ll_reset = 0x40001264;
+r_ble_ll_resolv_clear_all_pl_bit = 0x40001268;
+r_ble_ll_resolv_clear_all_wl_bit = 0x4000126c;
+r_ble_ll_resolv_deinit = 0x40001270;
+r_ble_ll_resolv_enable_cmd = 0x40001274;
+r_ble_ll_resolv_enabled = 0x40001278;
+r_ble_ll_resolv_env_init = 0x4000127c;
+r_ble_ll_resolv_gen_priv_addr = 0x40001280;
+r_ble_ll_resolv_gen_rpa = 0x40001284;
+r_ble_ll_resolv_get_addr_pointer = 0x40001288;
+r_ble_ll_resolv_get_entry = 0x4000128c;
+r_ble_ll_resolv_get_index = 0x40001290;
+r_ble_ll_resolv_get_irk_pointer = 0x40001294;
+r_ble_ll_resolv_get_list = 0x40001298;
+r_ble_ll_resolv_get_priv_addr = 0x4000129c;
+r_ble_ll_resolv_get_rpa_tmo = 0x400012a0;
+r_ble_ll_resolv_init = 0x400012a4;
+r_ble_ll_resolv_irk_nonzero = 0x400012a8;
+r_ble_ll_resolv_list_add = 0x400012ac;
+r_ble_ll_resolv_list_chg_allowed = 0x400012b0;
+r_ble_ll_resolv_list_clr = 0x400012b4;
+r_ble_ll_resolv_list_find = 0x400012b8;
+r_ble_ll_resolv_list_read_size = 0x400012bc;
+r_ble_ll_resolv_list_reset = 0x400012c0;
+r_ble_ll_resolv_list_rmv = 0x400012c4;
+r_ble_ll_resolv_local_addr_rd = 0x400012c8;
+r_ble_ll_resolv_peer_addr_rd = 0x400012cc;
+r_ble_ll_resolv_peer_rpa_any = 0x400012d0;
+r_ble_ll_resolv_reset = 0x400012d4;
+r_ble_ll_resolv_rpa = 0x400012d8;
+r_ble_ll_resolv_rpa_timer_cb = 0x400012dc;
+r_ble_ll_resolv_set_local_rpa = 0x400012e0;
+r_ble_ll_resolv_set_peer_rpa = 0x400012e4;
+r_ble_ll_resolv_set_rpa_tmo = 0x400012e8;
+r_ble_ll_resolve_set_priv_mode = 0x400012ec;
+r_ble_ll_rfmgmt_controller_sleep_en = 0x400012f0;
+r_ble_ll_rfmgmt_deinit = 0x400012f4;
+r_ble_ll_rfmgmt_disable = 0x400012f8;
+r_ble_ll_rfmgmt_enable = 0x400012fc;
+r_ble_ll_rfmgmt_enable_now = 0x40001300;
+r_ble_ll_rfmgmt_init = 0x40001304;
+r_ble_ll_rfmgmt_is_enabled = 0x40001308;
+r_ble_ll_rfmgmt_release = 0x4000130c;
+r_ble_ll_rfmgmt_release_ev = 0x40001310;
+r_ble_ll_rfmgmt_reset = 0x40001314;
+r_ble_ll_rfmgmt_scan_changed = 0x40001318;
+r_ble_ll_rfmgmt_sched_changed = 0x4000131c;
+r_ble_ll_rfmgmt_set_sleep_cb = 0x40001320;
+r_ble_ll_rfmgmt_ticks_to_enabled = 0x40001324;
+r_ble_ll_rfmgmt_timer_exp = 0x40001328;
+r_ble_ll_rfmgmt_timer_reschedule = 0x4000132c;
+r_ble_ll_rx_end = 0x40001330;
+r_ble_ll_rx_pdu_in = 0x40001334;
+r_ble_ll_rx_pkt_in = 0x40001338;
+r_ble_ll_rx_start = 0x4000133c;
+r_ble_ll_rxpdu_alloc = 0x40001340;
+r_ble_ll_scan_add_scan_rsp_adv = 0x40001344;
+r_ble_ll_scan_adv_decode_addr = 0x40001348;
+r_ble_ll_scan_aux_data_free = 0x4000134c;
+r_ble_ll_scan_aux_data_ref = 0x40001350;
+r_ble_ll_scan_aux_data_unref = 0x40001354;
+r_ble_ll_scan_can_chg_whitelist = 0x40001358;
+r_ble_ll_scan_check_periodic_sync = 0x4000135c;
+r_ble_ll_scan_chk_resume = 0x40001360;
+r_ble_ll_scan_clean_cur_aux_data = 0x40001364;
+r_ble_ll_scan_common_init = 0x40001368;
+r_ble_ll_scan_continue_en = 0x4000136c;
+r_ble_ll_scan_deinit = 0x40001370;
+r_ble_ll_scan_dup_check_ext = 0x40001374;
+r_ble_ll_scan_dup_check_legacy = 0x40001378;
+r_ble_ll_scan_dup_move_to_head = 0x4000137c;
+r_ble_ll_scan_dup_new = 0x40001380;
+r_ble_ll_scan_dup_update_ext = 0x40001384;
+r_ble_ll_scan_dup_update_legacy = 0x40001388;
+r_ble_ll_scan_duration_period_timers_restart = 0x4000138c;
+r_ble_ll_scan_duration_timer_cb = 0x40001390;
+r_ble_ll_scan_enabled = 0x40001394;
+r_ble_ll_scan_end_adv_evt = 0x40001398;
+r_ble_ll_scan_env_init = 0x4000139c;
+r_ble_ll_scan_event_proc = 0x400013a0;
+r_ble_ll_scan_ext_adv_init = 0x400013a4;
+r_ble_ll_scan_ext_initiator_start = 0x400013a8;
+r_ble_ll_scan_get_addr_data_from_legacy = 0x400013ac;
+r_ble_ll_scan_get_addr_from_ext_adv = 0x400013b0;
+r_ble_ll_scan_get_cur_sm = 0x400013b4;
+r_ble_ll_scan_get_ext_adv_report = 0x400013b8;
+r_ble_ll_scan_get_local_rpa = 0x400013bc;
+r_ble_ll_scan_get_next_adv_prim_chan = 0x400013c0;
+r_ble_ll_scan_get_pdu_data = 0x400013c4;
+r_ble_ll_scan_get_peer_rpa = 0x400013c8;
+r_ble_ll_scan_halt = 0x400013cc;
+r_ble_ll_scan_has_sent_scan_req = 0x400013d0;
+r_ble_ll_scan_have_rxd_scan_rsp = 0x400013d4;
+r_ble_ll_scan_init = 0x400013d8;
+r_ble_ll_scan_initiator_start = 0x400013dc;
+r_ble_ll_scan_interrupted = 0x400013e0;
+r_ble_ll_scan_interrupted_event_cb = 0x400013e4;
+r_ble_ll_scan_is_inside_window = 0x400013e8;
+r_ble_ll_scan_move_window_to = 0x400013ec;
+r_ble_ll_scan_npl_init = 0x400013f0;
+r_ble_ll_scan_npl_reset = 0x400013f4;
+r_ble_ll_scan_npl_restore = 0x400013f8;
+r_ble_ll_scan_npl_store = 0x400013fc;
+r_ble_ll_scan_parse_ext_hdr = 0x40001400;
+r_ble_ll_scan_period_timer_cb = 0x40001404;
+r_ble_ll_scan_record_new_adv = 0x40001408;
+r_ble_ll_scan_refresh_nrpa = 0x4000140c;
+r_ble_ll_scan_req_backoff = 0x40001410;
+r_ble_ll_scan_reset = 0x40001414;
+r_ble_ll_scan_rx_filter = 0x40001418;
+r_ble_ll_scan_rx_isr_end = 0x4000141c;
+r_ble_ll_scan_rx_isr_on_aux = 0x40001420;
+r_ble_ll_scan_rx_isr_on_legacy = 0x40001424;
+r_ble_ll_scan_rx_isr_start = 0x40001428;
+r_ble_ll_scan_rx_pkt_in = 0x4000142c;
+r_ble_ll_scan_rx_pkt_in_on_aux = 0x40001430;
+r_ble_ll_scan_rx_pkt_in_on_legacy = 0x40001434;
+r_ble_ll_scan_rx_pkt_in_restore_addr_data = 0x40001438;
+r_ble_ll_scan_rxed = 0x4000143c;
+r_ble_ll_scan_sched_remove = 0x40001440;
+r_ble_ll_scan_send_adv_report = 0x40001444;
+r_ble_ll_scan_send_truncated = 0x40001448;
+r_ble_ll_scan_set_enable = 0x4000144c;
+r_ble_ll_scan_set_peer_rpa = 0x40001450;
+r_ble_ll_scan_set_scan_params = 0x40001454;
+r_ble_ll_scan_sm_start = 0x40001458;
+r_ble_ll_scan_sm_stop = 0x4000145c;
+r_ble_ll_scan_start = 0x40001460;
+r_ble_ll_scan_time_hci_to_ticks = 0x40001464;
+r_ble_ll_scan_timer_cb = 0x40001468;
+r_ble_ll_scan_update_aux_data = 0x4000146c;
+r_ble_ll_scan_wfr_timer_exp = 0x40001470;
+r_ble_ll_scan_whitelist_enabled = 0x40001474;
+r_ble_ll_sched_adv_new = 0x40001478;
+r_ble_ll_sched_adv_resched_pdu = 0x4000147c;
+r_ble_ll_sched_adv_reschedule = 0x40001480;
+r_ble_ll_sched_aux_scan = 0x40001484;
+r_ble_ll_sched_conn_overlap = 0x40001488;
+r_ble_ll_sched_conn_reschedule = 0x4000148c;
+r_ble_ll_sched_deinit = 0x40001490;
+r_ble_ll_sched_dtm = 0x40001494;
+r_ble_ll_sched_env_init = 0x40001498;
+r_ble_ll_sched_execute_item = 0x4000149c;
+r_ble_ll_sched_init = 0x400014a0;
+r_ble_ll_sched_insert_if_empty = 0x400014a4;
+r_ble_ll_sched_is_overlap = 0x400014a8;
+r_ble_ll_sched_master_new = 0x400014ac;
+r_ble_ll_sched_next_time = 0x400014b0;
+r_ble_ll_sched_overlaps_current = 0x400014b4;
+r_ble_ll_sched_periodic_adv = 0x400014b8;
+r_ble_ll_sched_rmv_elem = 0x400014bc;
+r_ble_ll_sched_rmv_elem_type = 0x400014c0;
+r_ble_ll_sched_run = 0x400014c4;
+r_ble_ll_sched_scan_req_over_aux_ptr = 0x400014c8;
+r_ble_ll_sched_slave_new = 0x400014cc;
+r_ble_ll_sched_stop = 0x400014d0;
+r_ble_ll_sched_sync = 0x400014d4;
+r_ble_ll_sched_sync_overlaps_current = 0x400014d8;
+r_ble_ll_sched_sync_reschedule = 0x400014dc;
+r_ble_ll_set_default_privacy_mode = 0x400014e0;
+r_ble_ll_set_default_sync_transfer_params = 0x400014e4;
+r_ble_ll_set_ext_scan_params = 0x400014e8;
+r_ble_ll_set_host_feat = 0x400014ec;
+r_ble_ll_set_public_addr = 0x400014f0;
+r_ble_ll_set_random_addr = 0x400014f4;
+r_ble_ll_set_sync_transfer_params = 0x400014f8;
+r_ble_ll_slave_rx_isr_end = 0x400014fc;
+r_ble_ll_state_get = 0x40001500;
+r_ble_ll_state_set = 0x40001504;
+r_ble_ll_sync_adjust_ext_hdr = 0x40001508;
+r_ble_ll_sync_cancel = 0x4000150c;
+r_ble_ll_sync_cancel_complete_event = 0x40001510;
+r_ble_ll_sync_chain_start_cb = 0x40001514;
+r_ble_ll_sync_check_acad = 0x40001518;
+r_ble_ll_sync_check_failed = 0x4000151c;
+r_ble_ll_sync_coex_dpc_process = 0x40001520;
+r_ble_ll_sync_coex_dpc_pti_get = 0x40001524;
+r_ble_ll_sync_coex_dpc_update = 0x40001528;
+r_ble_ll_sync_create = 0x4000152c;
+r_ble_ll_sync_current_sm_over = 0x40001530;
+r_ble_ll_sync_deinit = 0x40001534;
+r_ble_ll_sync_enabled = 0x40001538;
+r_ble_ll_sync_env_init = 0x4000153c;
+r_ble_ll_sync_est_event_failed = 0x40001540;
+r_ble_ll_sync_est_event_success = 0x40001544;
+r_ble_ll_sync_established = 0x40001548;
+r_ble_ll_sync_event_end = 0x4000154c;
+r_ble_ll_sync_event_start_cb = 0x40001550;
+r_ble_ll_sync_filter_enabled = 0x40001554;
+r_ble_ll_sync_find = 0x40001558;
+r_ble_ll_sync_get_cur_sm = 0x4000155c;
+r_ble_ll_sync_get_event_end_time = 0x40001560;
+r_ble_ll_sync_get_handle = 0x40001564;
+r_ble_ll_sync_halt = 0x40001568;
+r_ble_ll_sync_has_been_reported = 0x4000156c;
+r_ble_ll_sync_info_event = 0x40001570;
+r_ble_ll_sync_init = 0x40001574;
+r_ble_ll_sync_list_add = 0x40001578;
+r_ble_ll_sync_list_clear = 0x4000157c;
+r_ble_ll_sync_list_empty = 0x40001580;
+r_ble_ll_sync_list_get_free = 0x40001584;
+r_ble_ll_sync_list_remove = 0x40001588;
+r_ble_ll_sync_list_search = 0x4000158c;
+r_ble_ll_sync_list_size = 0x40001590;
+r_ble_ll_sync_lost_event = 0x40001594;
+r_ble_ll_sync_next_event = 0x40001598;
+r_ble_ll_sync_on_list = 0x4000159c;
+r_ble_ll_sync_parse_aux_ptr = 0x400015a0;
+r_ble_ll_sync_parse_ext_hdr = 0x400015a4;
+r_ble_ll_sync_periodic_ind = 0x400015a8;
+r_ble_ll_sync_phy_mode_to_aux_phy = 0x400015ac;
+r_ble_ll_sync_phy_mode_to_hci = 0x400015b0;
+r_ble_ll_sync_put_syncinfo = 0x400015b4;
+r_ble_ll_sync_reserve = 0x400015b8;
+r_ble_ll_sync_reset = 0x400015bc;
+r_ble_ll_sync_reset_sm = 0x400015c0;
+r_ble_ll_sync_rmvd_from_sched = 0x400015c4;
+r_ble_ll_sync_rx_isr_end = 0x400015c8;
+r_ble_ll_sync_rx_isr_start = 0x400015cc;
+r_ble_ll_sync_rx_pkt_in = 0x400015d0;
+r_ble_ll_sync_schedule_chain = 0x400015d4;
+r_ble_ll_sync_send_per_adv_rpt = 0x400015d8;
+r_ble_ll_sync_send_sync_ind = 0x400015dc;
+r_ble_ll_sync_send_truncated_per_adv_rpt = 0x400015e0;
+r_ble_ll_sync_sm_clear = 0x400015e4;
+r_ble_ll_sync_terminate = 0x400015e8;
+r_ble_ll_sync_transfer = 0x400015ec;
+r_ble_ll_sync_transfer_get = 0x400015f0;
+r_ble_ll_sync_transfer_received = 0x400015f4;
+r_ble_ll_sync_wfr_timer_exp = 0x400015f8;
+r_ble_ll_task = 0x400015fc;
+r_ble_ll_trace_set_func = 0x40001600;
+r_ble_ll_trace_u32 = 0x40001604;
+r_ble_ll_trace_u32x2 = 0x40001608;
+r_ble_ll_trace_u32x3 = 0x4000160c;
+r_ble_ll_tx_flat_mbuf_pducb = 0x40001610;
+r_ble_ll_tx_mbuf_pducb = 0x40001614;
+r_ble_ll_tx_pkt_in = 0x40001618;
+r_ble_ll_update_max_tx_octets_phy_mode = 0x4000161c;
+r_ble_ll_usecs_to_ticks_round_up = 0x40001620;
+r_ble_ll_utils_calc_access_addr = 0x40001624;
+r_ble_ll_utils_calc_dci_csa2 = 0x40001628;
+r_ble_ll_utils_calc_num_used_chans = 0x4000162c;
+r_ble_ll_utils_calc_window_widening = 0x40001630;
+r_ble_ll_utils_csa2_perm = 0x40001634;
+r_ble_ll_utils_csa2_prng = 0x40001638;
+r_ble_ll_utils_remapped_channel = 0x4000163c;
+r_ble_ll_wfr_timer_exp = 0x40001640;
+r_ble_ll_whitelist_add = 0x40001644;
+r_ble_ll_whitelist_chg_allowed = 0x40001648;
+r_ble_ll_whitelist_clear = 0x4000164c;
+r_ble_ll_whitelist_read_size = 0x40001650;
+r_ble_ll_whitelist_rmv = 0x40001654;
+r_ble_ll_whitelist_search = 0x40001658;
+r_ble_ll_write_rf_path_compensation = 0x4000165c;
+r_ble_phy_access_addr_get = 0x40001660;
+r_ble_phy_bb_bug_is_triggered = 0x40001664;
+r_ble_phy_calculate_rxtx_ifs = 0x40001668;
+r_ble_phy_calculate_rxwindow = 0x4000166c;
+r_ble_phy_calculate_txrx_ifs = 0x40001670;
+r_ble_phy_config_access_addr = 0x40001674;
+r_ble_phy_data_make = 0x40001678;
+r_ble_phy_disable = 0x4000167c;
+r_ble_phy_disable_irq = 0x40001680;
+r_ble_phy_disable_whitening = 0x40001684;
+r_ble_phy_enable_scan_seq_immediately = 0x40001688;
+r_ble_phy_enable_whitening = 0x4000168c;
+r_ble_phy_encrypt_disable = 0x40001690;
+r_ble_phy_env_init = 0x40001694;
+r_ble_phy_get_current_phy = 0x40001698;
+r_ble_phy_get_packet_counter = 0x4000169c;
+r_ble_phy_get_packet_status = 0x400016a0;
+r_ble_phy_get_pyld_time_offset = 0x400016a4;
+r_ble_phy_get_rx_phy_mode = 0x400016a8;
+r_ble_phy_init = 0x400016ac;
+r_ble_phy_isr = 0x400016b0;
+r_ble_phy_max_data_pdu_pyld = 0x400016b4;
+r_ble_phy_mode_config = 0x400016b8;
+r_ble_phy_mode_convert = 0x400016bc;
+r_ble_phy_mode_write = 0x400016c0;
+r_ble_phy_module_deinit = 0x400016c4;
+r_ble_phy_module_init = 0x400016c8;
+r_ble_phy_monitor_bb_sync = 0x400016cc;
+r_ble_phy_need_to_report = 0x400016d0;
+r_ble_phy_pkt_received = 0x400016d4;
+r_ble_phy_reset_bb_monitor = 0x400016d8;
+r_ble_phy_resolv_list_disable = 0x400016dc;
+r_ble_phy_resolv_list_enable = 0x400016e0;
+r_ble_phy_restart_sequence = 0x400016e4;
+r_ble_phy_rfclk_disable = 0x400016e8;
+r_ble_phy_rfclk_enable = 0x400016ec;
+r_ble_phy_rx_is_expected = 0x400016f0;
+r_ble_phy_rxpdu_copy = 0x400016f4;
+r_ble_phy_scan_set_start_time = 0x400016f8;
+r_ble_phy_seq_encrypt_enable = 0x400016fc;
+r_ble_phy_seq_encrypt_set_pkt_cntr = 0x40001700;
+r_ble_phy_sequence_adv_end = 0x40001704;
+r_ble_phy_sequence_copy_rx_flags = 0x40001708;
+r_ble_phy_sequence_end_isr = 0x4000170c;
+r_ble_phy_sequence_get_mode = 0x40001710;
+r_ble_phy_sequence_get_state = 0x40001714;
+r_ble_phy_sequence_init_end = 0x40001718;
+r_ble_phy_sequence_is_running = 0x4000171c;
+r_ble_phy_sequence_is_waiting_rsp = 0x40001720;
+r_ble_phy_sequence_isr_copy_data = 0x40001724;
+r_ble_phy_sequence_master_end = 0x40001728;
+r_ble_phy_sequence_rx_end_isr = 0x4000172c;
+r_ble_phy_sequence_scan_end = 0x40001730;
+r_ble_phy_sequence_single_end = 0x40001734;
+r_ble_phy_sequence_slave_end = 0x40001738;
+r_ble_phy_sequence_tx_end_invoke = 0x4000173c;
+r_ble_phy_sequence_update_conn_params = 0x40001740;
+r_ble_phy_set_adv_sequence = 0x40001744;
+r_ble_phy_set_coex_pti = 0x40001748;
+r_ble_phy_set_dev_address = 0x4000174c;
+r_ble_phy_set_master_sequence = 0x40001750;
+r_ble_phy_set_rx_pwr_compensation = 0x40001754;
+r_ble_phy_set_rxhdr_flags = 0x40001758;
+r_ble_phy_set_rxhdr_info = 0x4000175c;
+r_ble_phy_set_scan_sequence = 0x40001760;
+r_ble_phy_set_single_packet_rx_sequence = 0x40001764;
+r_ble_phy_set_single_packet_tx_sequence = 0x40001768;
+r_ble_phy_set_slave_sequence = 0x4000176c;
+r_ble_phy_set_txend_cb = 0x40001770;
+r_ble_phy_setchan = 0x40001774;
+r_ble_phy_slave_set_start_time = 0x40001778;
+r_ble_phy_state_get = 0x4000177c;
+r_ble_phy_timer_config_start_time = 0x40001780;
+r_ble_phy_timer_start_now = 0x40001784;
+r_ble_phy_timer_stop = 0x40001788;
+r_ble_phy_tx_set_start_time = 0x4000178c;
+r_ble_phy_txpower_round = 0x40001790;
+r_ble_phy_txpwr_set = 0x40001794;
+r_ble_phy_wfr_enable = 0x40001798;
+r_ble_phy_xcvr_state_get = 0x4000179c;
+r_ble_plf_set_log_level = 0x400017a0;
+r_ble_rtc_wake_up_cpu_init = 0x400017a4;
+r_ble_rtc_wake_up_state_clr = 0x400017a8;
+r_bleonly_os_tick_init = 0x400017ac;
+r_bt_rf_coex_cfg_set = 0x400017b0;
+r_bt_rf_coex_coded_txrx_time_upper_lim = 0x400017b4;
+r_bt_rf_coex_dft_pti_set = 0x400017b8;
+r_bt_rf_coex_hook_deinit = 0x400017bc;
+r_bt_rf_coex_hook_init = 0x400017c0;
+r_bt_rf_coex_hook_st_set = 0x400017c4;
+r_bt_rf_coex_hooks_p_set_default = 0x400017c8;
+r_btdm_disable_adv_delay = 0x400017cc;
+r_btdm_switch_phy_coded = 0x400017d0;
+r_esp_wait_disabled = 0x400017d4;
+r_get_be16 = 0x400017d8;
+r_get_be24 = 0x400017dc;
+r_get_be32 = 0x400017e0;
+r_get_be64 = 0x400017e4;
+r_get_le16 = 0x400017e8;
+r_get_le24 = 0x400017ec;
+r_get_le32 = 0x400017f0;
+r_get_le64 = 0x400017f4;
+r_get_local_irk_offset = 0x400017f8;
+r_get_local_rpa_offset = 0x400017fc;
+r_get_max_skip = 0x40001800;
+r_get_peer_id_offset = 0x40001804;
+r_get_peer_irk_offset = 0x40001808;
+r_get_peer_rpa_offset = 0x4000180c;
+r_hal_os_tick_read_tick = 0x40001810;
+r_hal_os_tick_set_exp_tick = 0x40001814;
+r_hal_rtc_intr_init = 0x40001818;
+r_hal_rtc_irq_handler = 0x4000181c;
+r_hal_timer_deinit = 0x40001820;
+r_hal_timer_disable_irq = 0x40001824;
+r_hal_timer_env_init = 0x40001828;
+r_hal_timer_init = 0x4000182c;
+r_hal_timer_process = 0x40001830;
+r_hal_timer_read = 0x40001834;
+r_hal_timer_read_tick = 0x40001838;
+r_hal_timer_set_cb = 0x4000183c;
+r_hal_timer_set_exp_tick = 0x40001840;
+r_hal_timer_start = 0x40001844;
+r_hal_timer_start_at = 0x40001848;
+r_hal_timer_stop = 0x4000184c;
+r_hal_timer_task_start = 0x40001850;
+r_ll_assert = 0x40001854;
+r_mem_init_mbuf_pool = 0x40001858;
+r_mem_malloc_mbuf_pool = 0x4000185c;
+r_mem_malloc_mbufpkt_pool = 0x40001860;
+r_mem_malloc_mempool = 0x40001864;
+r_mem_malloc_mempool_ext = 0x40001868;
+r_mem_malloc_mempool_gen = 0x4000186c;
+r_mem_pullup_obj = 0x40001870;
+r_mem_split_frag = 0x40001874;
+r_os_cputime_delay_ticks = 0x40001878;
+r_os_cputime_delay_usecs = 0x4000187c;
+r_os_cputime_get32 = 0x40001880;
+r_os_cputime_ticks_to_usecs = 0x40001884;
+r_os_cputime_timer_init = 0x40001888;
+r_os_cputime_timer_relative = 0x4000188c;
+r_os_cputime_timer_start = 0x40001890;
+r_os_cputime_timer_stop = 0x40001894;
+r_os_cputime_usecs_to_ticks = 0x40001898;
+r_os_mbuf_adj = 0x4000189c;
+r_os_mbuf_append = 0x400018a0;
+r_os_mbuf_appendfrom = 0x400018a4;
+r_os_mbuf_cmpf = 0x400018a8;
+r_os_mbuf_cmpm = 0x400018ac;
+r_os_mbuf_concat = 0x400018b0;
+r_os_mbuf_copydata = 0x400018b4;
+r_os_mbuf_copyinto = 0x400018b8;
+r_os_mbuf_dup = 0x400018bc;
+r_os_mbuf_extend = 0x400018c0;
+r_os_mbuf_free = 0x400018c4;
+r_os_mbuf_free_chain = 0x400018c8;
+r_os_mbuf_get = 0x400018cc;
+r_os_mbuf_get_pkthdr = 0x400018d0;
+r_os_mbuf_len = 0x400018d4;
+r_os_mbuf_off = 0x400018d8;
+r_os_mbuf_pack_chains = 0x400018dc;
+r_os_mbuf_pool_init = 0x400018e0;
+r_os_mbuf_prepend = 0x400018e4;
+r_os_mbuf_prepend_pullup = 0x400018e8;
+r_os_mbuf_pullup = 0x400018ec;
+r_os_mbuf_trim_front = 0x400018f0;
+r_os_mbuf_widen = 0x400018f4;
+r_os_memblock_from = 0x400018f8;
+r_os_memblock_get = 0x400018fc;
+r_os_memblock_put = 0x40001900;
+r_os_memblock_put_from_cb = 0x40001904;
+r_os_mempool_clear = 0x40001908;
+r_os_mempool_ext_clear = 0x4000190c;
+r_os_mempool_ext_init = 0x40001910;
+r_os_mempool_info_get_next = 0x40001914;
+r_os_mempool_init = 0x40001918;
+r_os_mempool_init_internal = 0x4000191c;
+r_os_mempool_is_sane = 0x40001920;
+r_os_mempool_module_init = 0x40001924;
+r_os_mempool_unregister = 0x40001928;
+r_os_mqueue_get = 0x4000192c;
+r_os_mqueue_init = 0x40001930;
+r_os_mqueue_put = 0x40001934;
+r_os_msys_count = 0x40001938;
+r_os_msys_get = 0x4000193c;
+r_os_msys_get_pkthdr = 0x40001940;
+r_os_msys_num_free = 0x40001944;
+r_os_msys_register = 0x40001948;
+r_os_msys_reset = 0x4000194c;
+r_os_tick_idle = 0x40001950;
+r_pri_phy_valid = 0x40001954;
+r_put_be16 = 0x40001958;
+r_put_be24 = 0x4000195c;
+r_put_be32 = 0x40001960;
+r_put_be64 = 0x40001964;
+r_put_le16 = 0x40001968;
+r_put_le24 = 0x4000196c;
+r_put_le32 = 0x40001970;
+r_put_le64 = 0x40001974;
+r_rtc0_timer_handler = 0x40001978;
+r_rtc1_timer_handler = 0x4000197c;
+r_sdkconfig_get_opts = 0x40001980;
+r_sdkconfig_set_opts = 0x40001984;
+r_sec_phy_valid = 0x40001988;
+r_sub24 = 0x4000198c;
+r_swap_buf = 0x40001990;
+r_swap_in_place = 0x40001994;
+/* Data (.data, .bss, .rodata) */
+ble_hci_uart_reset_cmd = 0x3ff4ffe0;
+ble_hci_trans_env_p = 0x3fcdffc4;
+ble_hci_trans_mode = 0x3fcdfeb8;
+ble_ll_adv_env_p = 0x3fcdffc0;
+ble_ll_conn_env_p = 0x3fcdffbc;
+g_ble_ll_conn_cth_flow = 0x3fcdffb4;
+g_ble_ll_conn_cth_flow_error_ev = 0x3fcdffb0;
+g_ble_ll_ctrl_pkt_lengths_ro = 0x3ff4ffbc;
+ble_ll_dtm_module_env_p = 0x3fcdffac;
+channel_rf_to_index = 0x3ff4ff94;
+g_ble_ll_dtm_prbs15_data = 0x3ff4fe94;
+g_ble_ll_dtm_prbs9_data = 0x3ff4fd94;
+ble_ll_hci_env_p = 0x3fcdffa8;
+ble_ll_rand_env_p = 0x3fcdffa4;
+ble_ll_resolv_env_p = 0x3fcdffa0;
+g_ble_ll_resolve_hdr = 0x3fcdff98;
+g_device_mode_default = 0x3fcdfeb6;
+g_ble_ll_rfmgmt_data = 0x3fcdff50;
+g_ble_sleep_enter_cb = 0x3fcdff4c;
+g_ble_sleep_exit_cb = 0x3fcdff48;
+g_rfclk_enabled = 0x3fcdff44;
+ble_ll_scan_env_p = 0x3fcdff40;
+ble_ll_sched_env_p = 0x3fcdff3c;
+g_ble_ll_supp_cmds_ro = 0x3ff4fd64;
+ble_ll_sync_env_p = 0x3fcdff38;
+g_ble_sca_ppm_tbl_ro = 0x3ff4fd54;
+ble_ll_env_p = 0x3fcdff34;
+g_ble_ll_pdu_header_tx_time_ro = 0x3ff4fd4c;
+priv_config_opts = 0x3fcdfea0;
+ble_hci_trans_funcs_ptr = 0x3fcdff30;
+r_ble_stub_funcs_ptr = 0x3fcdff2c;
+r_ext_funcs_p = 0x3fcdff28;
+r_npl_funcs = 0x3fcdff24;
+ble_hw_env_p = 0x3fcdff20;
+already_inited.10221 = 0x3fcdff1c;
+ble_phy_module_env_p = 0x3fcdff18;
+g_ble_phy_chan_freq_ro = 0x3ff4fd24;
+g_ble_phy_mode_pkt_start_off_ro = 0x3ff4fd1c;
+g_ble_phy_rxtx_ifs_compensation_ro = 0x3ff4fd0c;
+g_ble_phy_t_rxaddrdelay_ro = 0x3ff4fd08;
+g_ble_phy_t_rxenddelay_ro = 0x3ff4fd04;
+g_ble_phy_t_txdelay_ro = 0x3ff4fd00;
+g_ble_phy_t_txenddelay_ro = 0x3ff4fcfc;
+g_ble_phy_txrx_ifs_compensation_ro = 0x3ff4fcec;
+hal_timer_env_p = 0x3fcdff14;
+g_hal_os_tick = 0x3fcdff08;
+r_osi_coex_funcs_p = 0x3fcdff04;
+bt_rf_coex_hooks = 0x3fcdfefc;
+bt_rf_coex_hooks_p = 0x3fcdfef8;
+coex_hook_st_group_tab = 0x3ff4fce0;
+coex_hook_st_group_to_coex_schm_st_tab = 0x3ff4fcdc;
+s_ble_act_count_by_group = 0x3fcdfef4;
+s_ble_coex_st_map = 0x3fcdfee0;
+bt_rf_coex_cfg_cb = 0x3fcdfec4;
+bt_rf_coex_cfg_p = 0x3fcdfec0;
+bt_rf_coex_cfg_rom = 0x3ff4fcc0;
+bt_rf_coex_pti_dft_p = 0x3fcdfebc;
+bt_rf_coex_pti_dft_rom = 0x3fcdfe60;
+conn_dynamic_pti_param_rom = 0x3ff4fca8;
+conn_phy_coded_max_data_time_param_rom = 0x3ff4fca4;
+ext_adv_dynamic_pti_param_rom = 0x3ff4fc70;
+ext_scan_dynamic_param_rom = 0x3ff4fc38;
+legacy_adv_dynamic_pti_param_rom = 0x3ff4fc18;
+per_adv_dynamic_pti_param_rom = 0x3ff4fbfc;
+sync_dynamic_param_rom = 0x3ff4fbe4;
+g_ble_plf_log_level = 0x3fcdfe5c;
+g_msys_pool_list = 0x3fcdfe54;
+g_os_mempool_list = 0x3fcdfe4c;
+
+
+/***************************************
+ Group rom_pp
+ ***************************************/
+
+/* Functions */
+esp_pp_rom_version_get = 0x40001998;
+RC_GetBlockAckTime = 0x4000199c;
+ebuf_list_remove = 0x400019a0;
+esf_buf_alloc = 0x400019a4;
+esf_buf_alloc_dynamic = 0x400019a8;
+esf_buf_recycle = 0x400019ac;
+GetAccess = 0x400019b0;
+hal_mac_is_low_rate_enabled = 0x400019b4;
+hal_mac_tx_get_blockack = 0x400019b8;
+hal_mac_tx_set_ppdu = 0x400019bc;
+ic_get_trc = 0x400019c0;
+ic_mac_deinit = 0x400019c4;
+ic_mac_init = 0x400019c8;
+ic_interface_enabled = 0x400019cc;
+is_lmac_idle = 0x400019d0;
+lmacAdjustTimestamp = 0x400019d4;
+lmacDiscardAgedMSDU = 0x400019d8;
+lmacDiscardMSDU = 0x400019dc;
+lmacEndFrameExchangeSequence = 0x400019e0;
+lmacIsIdle = 0x400019e4;
+lmacIsLongFrame = 0x400019e8;
+lmacMSDUAged = 0x400019ec;
+lmacPostTxComplete = 0x400019f0;
+lmacProcessAllTxTimeout = 0x400019f4;
+lmacProcessCollisions = 0x400019f8;
+lmacProcessRxSucData = 0x400019fc;
+lmacReachLongLimit = 0x40001a00;
+lmacReachShortLimit = 0x40001a04;
+lmacRecycleMPDU = 0x40001a08;
+lmacRxDone = 0x40001a0c;
+lmacSetTxFrame = 0x40001a10;
+lmacTxDone = 0x40001a14;
+lmacTxFrame = 0x40001a18;
+mac_tx_set_duration = 0x40001a1c;
+mac_tx_set_htsig = 0x40001a20;
+mac_tx_set_plcp0 = 0x40001a24;
+mac_tx_set_plcp1 = 0x40001a28;
+mac_tx_set_plcp2 = 0x40001a2c;
+pm_check_state = 0x40001a30;
+pm_disable_dream_timer = 0x40001a34;
+pm_disable_sleep_delay_timer = 0x40001a38;
+pm_dream = 0x40001a3c;
+pm_mac_wakeup = 0x40001a40;
+pm_mac_sleep = 0x40001a44;
+pm_enable_active_timer = 0x40001a48;
+pm_enable_sleep_delay_timer = 0x40001a4c;
+pm_local_tsf_process = 0x40001a50;
+pm_set_beacon_filter = 0x40001a54;
+pm_is_in_wifi_slice_threshold = 0x40001a58;
+pm_is_waked = 0x40001a5c;
+pm_keep_alive = 0x40001a60;
+pm_on_beacon_rx = 0x40001a64;
+pm_on_data_rx = 0x40001a68;
+pm_on_tbtt = 0x40001a6c;
+pm_parse_beacon = 0x40001a70;
+pm_process_tim = 0x40001a74;
+pm_rx_beacon_process = 0x40001a78;
+pm_rx_data_process = 0x40001a7c;
+pm_sleep = 0x40001a80;
+pm_sleep_for = 0x40001a84;
+pm_tbtt_process = 0x40001a88;
+ppAMPDU2Normal = 0x40001a8c;
+ppAssembleAMPDU = 0x40001a90;
+ppCalFrameTimes = 0x40001a94;
+ppCalSubFrameLength = 0x40001a98;
+ppCalTxAMPDULength = 0x40001a9c;
+ppCheckTxAMPDUlength = 0x40001aa0;
+ppDequeueRxq_Locked = 0x40001aa4;
+ppDequeueTxQ = 0x40001aa8;
+ppEmptyDelimiterLength = 0x40001aac;
+ppEnqueueRxq = 0x40001ab0;
+ppEnqueueTxDone = 0x40001ab4;
+ppGetTxQFirstAvail_Locked = 0x40001ab8;
+ppGetTxframe = 0x40001abc;
+ppMapTxQueue = 0x40001ac0;
+ppProcTxSecFrame = 0x40001ac4;
+ppProcessRxPktHdr = 0x40001ac8;
+ppProcessTxQ = 0x40001acc;
+ppRecordBarRRC = 0x40001ad0;
+lmacRequestTxopQueue = 0x40001ad4;
+lmacReleaseTxopQueue = 0x40001ad8;
+ppRecycleAmpdu = 0x40001adc;
+ppRecycleRxPkt = 0x40001ae0;
+ppResortTxAMPDU = 0x40001ae4;
+ppResumeTxAMPDU = 0x40001ae8;
+ppRxFragmentProc = 0x40001aec;
+ppRxPkt = 0x40001af0;
+ppRxProtoProc = 0x40001af4;
+ppSearchTxQueue = 0x40001af8;
+ppSearchTxframe = 0x40001afc;
+ppSelectNextQueue = 0x40001b00;
+ppSubFromAMPDU = 0x40001b04;
+ppTask = 0x40001b08;
+ppTxPkt = 0x40001b0c;
+ppTxProtoProc = 0x40001b10;
+ppTxqUpdateBitmap = 0x40001b14;
+pp_coex_tx_request = 0x40001b18;
+pp_hdrsize = 0x40001b1c;
+pp_post = 0x40001b20;
+pp_process_hmac_waiting_txq = 0x40001b24;
+rcGetAmpduSched = 0x40001b28;
+rcUpdateRxDone = 0x40001b2c;
+rc_get_trc = 0x40001b30;
+rc_get_trc_by_index = 0x40001b34;
+rcAmpduLowerRate = 0x40001b38;
+rcampduuprate = 0x40001b3c;
+rcClearCurAMPDUSched = 0x40001b40;
+rcClearCurSched = 0x40001b44;
+rcClearCurStat = 0x40001b48;
+rcGetSched = 0x40001b4c;
+rcLowerSched = 0x40001b50;
+rcSetTxAmpduLimit = 0x40001b54;
+rcTxUpdatePer = 0x40001b58;
+rcUpdateAckSnr = 0x40001b5c;
+rcUpdateRate = 0x40001b60;
+rcUpdateTxDone = 0x40001b64;
+rcUpdateTxDoneAmpdu2 = 0x40001b68;
+rcUpSched = 0x40001b6c;
+rssi_margin = 0x40001b70;
+rx11NRate2AMPDULimit = 0x40001b74;
+TRC_AMPDU_PER_DOWN_THRESHOLD = 0x40001b78;
+TRC_AMPDU_PER_UP_THRESHOLD = 0x40001b7c;
+trc_calc_duration = 0x40001b80;
+trc_isTxAmpduOperational = 0x40001b84;
+trc_onAmpduOp = 0x40001b88;
+TRC_PER_IS_GOOD = 0x40001b8c;
+trc_SetTxAmpduState = 0x40001b90;
+trc_tid_isTxAmpduOperational = 0x40001b94;
+trcAmpduSetState = 0x40001b98;
+wDevCheckBlockError = 0x40001b9c;
+wDev_AppendRxBlocks = 0x40001ba0;
+wDev_DiscardFrame = 0x40001ba4;
+wDev_GetNoiseFloor = 0x40001ba8;
+wDev_IndicateAmpdu = 0x40001bac;
+wDev_IndicateFrame = 0x40001bb0;
+wdev_bank_store = 0x40001bb4;
+wdev_bank_load = 0x40001bb8;
+wdev_mac_reg_load = 0x40001bbc;
+wdev_mac_reg_store = 0x40001bc0;
+wdev_mac_special_reg_load = 0x40001bc4;
+wdev_mac_special_reg_store = 0x40001bc8;
+wdev_mac_wakeup = 0x40001bcc;
+wdev_mac_sleep = 0x40001bd0;
+wDev_ProcessFiq = 0x40001bd4;
+wDev_ProcessRxSucData = 0x40001bd8;
+wdevProcessRxSucDataAll = 0x40001bdc;
+wdev_csi_len_align = 0x40001be0;
+ppDequeueTxDone_Locked = 0x40001be4;
+ppProcTxDone = 0x40001be8;
+pm_tx_data_done_process = 0x40001bec;
+config_is_cache_tx_buf_enabled = 0x40001bf0;
+ppMapWaitTxq = 0x40001bf4;
+ppProcessWaitingQueue = 0x40001bf8;
+ppDisableQueue = 0x40001bfc;
+pm_allow_tx = 0x40001c00;
+wdev_is_data_in_rxlist = 0x40001c04;
+ppProcTxCallback = 0x40001c08;
+pm_is_open = 0x40001c0c;
+pm_wake_up = 0x40001c10;
+pm_wake_done = 0x40001c14;
+pm_disable_disconnected_sleep_delay_timer = 0x40001c18;
+pm_enable_disconnected_sleep_delay_timer = 0x40001c1c;
+hal_mac_get_txq_state = 0x40001c20;
+hal_mac_clr_txq_state = 0x40001c24;
+hal_mac_tx_set_cca = 0x40001c28;
+hal_mac_set_txq_invalid = 0x40001c2c;
+hal_mac_txq_disable = 0x40001c30;
+hal_mac_is_txq_enabled = 0x40001c34;
+hal_mac_get_txq_pmd = 0x40001c38;
+lmacDiscardFrameExchangeSequence = 0x40001c3c;
+lmacDisableTransmit = 0x40001c40;
+lmacProcessTxTimeout = 0x40001c44;
+lmacProcessTxSuccess = 0x40001c48;
+lmacProcessCollision = 0x40001c4c;
+lmacProcessTxRtsError = 0x40001c50;
+lmacProcessCtsTimeout = 0x40001c54;
+lmacProcessTxComplete = 0x40001c58;
+lmacProcessAckTimeout = 0x40001c5c;
+lmacProcessTxError = 0x40001c60;
+lmacProcessTxseckiderr = 0x40001c64;
+rcReachRetryLimit = 0x40001c68;
+lmacProcessShortRetryFail = 0x40001c6c;
+lmacEndRetryAMPDUFail = 0x40001c70;
+ppFillAMPDUBar = 0x40001c74;
+rcGetRate = 0x40001c78;
+ppReSendBar = 0x40001c7c;
+lmacProcessLongRetryFail = 0x40001c80;
+lmacRetryTxFrame = 0x40001c84;
+lmacProcessCollisions_task = 0x40001c88;
+lmacProcessTxopQComplete = 0x40001c8c;
+lmacInitAc = 0x40001c90;
+lmacInit = 0x40001c94;
+mac_tx_set_txop_q = 0x40001c98;
+hal_init = 0x40001c9c;
+hal_mac_rx_set_policy = 0x40001ca0;
+hal_mac_set_bssid = 0x40001ca4;
+mac_rx_policy_init = 0x40001ca8;
+mac_txrx_init = 0x40001cac;
+mac_rxbuf_init = 0x40001cb0;
+mac_last_rxbuf_init = 0x40001cb4;
+hal_attenna_init = 0x40001cb8;
+hal_timer_update_by_rtc = 0x40001cbc;
+hal_coex_pti_init = 0x40001cc0;
+lmac_stop_hw_txq = 0x40001cc4;
+ppDirectRecycleAmpdu = 0x40001cc8;
+esp_wifi_internal_set_rts = 0x40001ccc;
+esp_wifi_internal_get_rts = 0x40001cd0;
+ppTxFragmentProc = 0x40001cd4;
+esf_buf_setup = 0x40001cd8;
+hal_agreement_add_rx_ba = 0x40001cdc;
+hal_agreement_del_rx_ba = 0x40001ce0;
+hal_crypto_set_key_entry = 0x40001ce4;
+hal_crypto_get_key_entry = 0x40001ce8;
+hal_crypto_clr_key_entry = 0x40001cec;
+config_get_wifi_task_stack_size = 0x40001cf0;
+pp_create_task = 0x40001cf4;
+hal_set_sta_tsf_wakeup = 0x40001cf8;
+hal_set_rx_beacon_pti = 0x40001cfc;
+pm_start = 0x40001d00;
+pm_stop = 0x40001d04;
+hal_disable_sta_tbtt = 0x40001d08;
+ppCalTxopDur = 0x40001d0c;
+wDev_IndicateCtrlFrame = 0x40001d10;
+hal_enable_sta_tbtt = 0x40001d14;
+hal_set_sta_tbtt = 0x40001d18;
+pm_update_next_tbtt = 0x40001d1c;
+pm_set_sleep_type = 0x40001d20;
+wDev_Rxbuf_Init = 0x40001d24;
+wDev_Rxbuf_Deinit = 0x40001d28;
+ppCalTkipMic = 0x40001d2c;
+wDev_SnifferRxData = 0x40001d30;
+hal_crypto_enable = 0x40001d34;
+hal_crypto_disable = 0x40001d38;
+wDev_Insert_KeyEntry = 0x40001d3c;
+wDev_remove_KeyEntry = 0x40001d40;
+rc_enable_trc = 0x40001d44;
+rc_set_per_conn_fix_rate = 0x40001d48;
+wdev_csi_rx_process = 0x40001d4c;
+wDev_SnifferRxAmpdu = 0x40001d50;
+hal_mac_tsf_reset = 0x40001d54;
+dbg_lmac_statis_dump = 0x40001d58;
+dbg_lmac_rxtx_statis_dump = 0x40001d5c;
+dbg_lmac_hw_statis_dump = 0x40001d60;
+dbg_lmac_diag_statis_dump = 0x40001d64;
+dbg_lmac_ps_statis_dump = 0x40001d68;
+pp_timer_do_process = 0x40001d6c;
+rcUpdateAMPDUParam = 0x40001d70;
+rcUpdatePhyMode = 0x40001d74;
+rcGetHighestRateIdx = 0x40001d78;
+pm_tx_null_data_done_process = 0x40001d7c;
+pm_tx_data_process = 0x40001d80;
+pm_attach = 0x40001d84;
+pm_coex_schm_process = 0x40001d88;
+ppInitTxq = 0x40001d8c;
+pp_attach = 0x40001d90;
+pp_deattach = 0x40001d94;
+pm_on_probe_resp_rx = 0x40001d98;
+hal_set_sta_tsf = 0x40001d9c;
+ic_update_sta_tsf = 0x40001da0;
+ic_tx_pkt = 0x40001da4;
+pm_send_probe_stop = 0x40001da8;
+sta_pm_phy_ref_release = 0x40001dac;
+sta_pm_phy_ref_acquire = 0x40001db0;
+pm_send_probe_start = 0x40001db4;
+pm_on_coex_schm_process_restart = 0x40001db8;
+hal_mac_set_rxq_policy = 0x40001dbc;
+hal_sniffer_enable = 0x40001dc0;
+hal_sniffer_disable = 0x40001dc4;
+hal_sniffer_rx_set_promis = 0x40001dc8;
+hal_sniffer_rx_clr_statistics = 0x40001dcc;
+hal_sniffer_set_promis_misc_pkt = 0x40001dd0;
+/* Data (.data, .bss, .rodata) */
+our_instances_ptr = 0x3ff4fbe0;
+pTxRx = 0x3fcdfe48;
+lmacConfMib_ptr = 0x3fcdfe44;
+our_wait_eb = 0x3fcdfe40;
+our_tx_eb = 0x3fcdfe3c;
+pp_wdev_funcs = 0x3fcdfe38;
+g_osi_funcs_p = 0x3fcdfe34;
+wDevCtrl_ptr = 0x3fcdfe30;
+g_wdev_last_desc_reset_ptr = 0x3ff4fbdc;
+wDevMacSleep_ptr = 0x3fcdfe2c;
+g_lmac_cnt_ptr = 0x3fcdfe28;
+our_controls_ptr = 0x3ff4fbd8;
+pp_sig_cnt_ptr = 0x3fcdfe24;
+g_eb_list_desc_ptr = 0x3fcdfe20;
+s_fragment_ptr = 0x3fcdfe1c;
+if_ctrl_ptr = 0x3fcdfe18;
+g_intr_lock_mux = 0x3fcdfe14;
+g_wifi_global_lock = 0x3fcdfe10;
+s_wifi_queue = 0x3fcdfe0c;
+pp_task_hdl = 0x3fcdfe08;
+s_pp_task_create_sem = 0x3fcdfe04;
+s_pp_task_del_sem = 0x3fcdfe00;
+g_wifi_menuconfig_ptr = 0x3fcdfdfc;
+xphyQueue = 0x3fcdfdf8;
+ap_no_lr_ptr = 0x3fcdfdf4;
+rc11BSchedTbl_ptr = 0x3fcdfdf0;
+rc11NSchedTbl_ptr = 0x3fcdfdec;
+rcLoRaSchedTbl_ptr = 0x3fcdfde8;
+BasicOFDMSched_ptr = 0x3fcdfde4;
+trc_ctl_ptr = 0x3fcdfde0;
+g_pm_cnt_ptr = 0x3fcdfddc;
+g_pm_ptr = 0x3fcdfdd8;
+g_pm_cfg_ptr = 0x3fcdfdd4;
+g_esp_mesh_quick_funcs_ptr = 0x3fcdfdd0;
+g_txop_queue_status_ptr = 0x3fcdfdcc;
+g_mac_sleep_en_ptr = 0x3fcdfdc8;
+g_mesh_is_root_ptr = 0x3fcdfdc4;
+g_mesh_topology_ptr = 0x3fcdfdc0;
+g_mesh_init_ps_type_ptr = 0x3fcdfdbc;
+g_mesh_is_started_ptr = 0x3fcdfdb8;
+g_config_func = 0x3fcdfdb4;
+g_net80211_tx_func = 0x3fcdfdb0;
+g_timer_func = 0x3fcdfdac;
+s_michael_mic_failure_cb = 0x3fcdfda8;
+wifi_sta_rx_probe_req = 0x3fcdfda4;
+g_tx_done_cb_func = 0x3fcdfda0;
+g_per_conn_trc = 0x3fcdfd84;
+s_encap_amsdu_func = 0x3fcdfd80;
+bars = 0x3fcdfce0;
+eb_txdesc_space = 0x3fcdfc50;
+eb_space = 0x3fcdfbb0;
+g_pd_mac_in_light_sleep = 0x3fcdfbac;
+s_fix_rate_mask = 0x3fcdfba8;
+s_fix_rate = 0x3fcdfba0;
+g_wdev_csi_rx = 0x3fcdfb9c;
+g_wdev_csi_rx_ctx = 0x3fcdfb98;
+BcnSendTick = 0x3fcdfb94;
+g_pp_timer_info_ptr = 0x3fcdfb90;
+rcP2P11NSchedTbl_ptr = 0x3fcdfb8c;
+rcP2P11GSchedTbl_ptr = 0x3fcdfb88;
+rc11GSchedTbl_ptr = 0x3fcdfb84;
+
+
+/***************************************
+ Group rom_net80211
+ ***************************************/
+
+/* Functions */
+esp_net80211_rom_version_get = 0x40001dd4;
+ampdu_dispatch = 0x40001dd8;
+ampdu_dispatch_all = 0x40001ddc;
+ampdu_dispatch_as_many_as_possible = 0x40001de0;
+ampdu_dispatch_movement = 0x40001de4;
+ampdu_dispatch_upto = 0x40001de8;
+chm_is_at_home_channel = 0x40001dec;
+cnx_node_is_existing = 0x40001df0;
+cnx_node_search = 0x40001df4;
+ic_ebuf_recycle_rx = 0x40001df8;
+ic_ebuf_recycle_tx = 0x40001dfc;
+ic_reset_rx_ba = 0x40001e00;
+ieee80211_align_eb = 0x40001e04;
+ieee80211_ampdu_reorder = 0x40001e08;
+ieee80211_ampdu_start_age_timer = 0x40001e0c;
+ieee80211_encap_esfbuf = 0x40001e10;
+ieee80211_is_tx_allowed = 0x40001e14;
+ieee80211_output_pending_eb = 0x40001e18;
+ieee80211_output_process = 0x40001e1c;
+ieee80211_set_tx_desc = 0x40001e20;
+sta_input = 0x40001e24;
+wifi_get_macaddr = 0x40001e28;
+wifi_rf_phy_disable = 0x40001e2c;
+wifi_rf_phy_enable = 0x40001e30;
+ic_ebuf_alloc = 0x40001e34;
+ieee80211_classify = 0x40001e38;
+ieee80211_copy_eb_header = 0x40001e3c;
+ieee80211_recycle_cache_eb = 0x40001e40;
+ieee80211_search_node = 0x40001e44;
+roundup2 = 0x40001e48;
+ieee80211_crypto_encap = 0x40001e4c;
+ieee80211_crypto_decap = 0x40001e50;
+ieee80211_decap = 0x40001e54;
+ieee80211_set_tx_pti = 0x40001e58;
+wifi_is_started = 0x40001e5c;
+ieee80211_gettid = 0x40001e60;
+ieee80211_ccmp_decrypt = 0x40001e64;
+ieee80211_ccmp_encrypt = 0x40001e68;
+ccmp_encap = 0x40001e6c;
+ccmp_decap = 0x40001e70;
+tkip_encap = 0x40001e74;
+tkip_decap = 0x40001e78;
+wep_encap = 0x40001e7c;
+wep_decap = 0x40001e80;
+dbg_hmac_rxtx_statis_dump = 0x40001e84;
+dbg_hmac_statis_dump = 0x40001e88;
+ieee80211_send_action_vendor_spec = 0x40001e8c;
+ieee80211_send_mgmt = 0x40001e90;
+ieee80211_auth_construct = 0x40001e94;
+ieee80211_deauth_construct = 0x40001e98;
+ieee80211_disassoc_construct = 0x40001e9c;
+ieee80211_vnd_lora_ie_size = 0x40001ea0;
+ieee80211_vnd_ie_size = 0x40001ea4;
+ieee80211_add_ssid = 0x40001ea8;
+ieee80211_add_rates = 0x40001eac;
+ieee80211_add_xrates = 0x40001eb0;
+ieee80211_is_ht_cipher = 0x40001eb4;
+ieee80211_assoc_req_construct = 0x40001eb8;
+ieee80211_assoc_resp_construct = 0x40001ebc;
+ieee80211_setup_lr_rates = 0x40001ec0;
+ieee80211_ht_node_init = 0x40001ec4;
+ieee80211_is_support_rate = 0x40001ec8;
+ieee80211_setup_rates = 0x40001ecc;
+ieee80211_is_lr_only = 0x40001ed0;
+ieee80211_setup_phy_mode = 0x40001ed4;
+ieee80211_sta_is_connected = 0x40001ed8;
+current_task_is_wifi_task = 0x40001edc;
+wifi_get_init_state = 0x40001ee0;
+ieee80211_timer_process = 0x40001ee4;
+cnx_coexist_timeout = 0x40001ee8;
+sta_recv_mgmt = 0x40001eec;
+ieee80211_send_setup = 0x40001ef0;
+ieee80211_send_probereq = 0x40001ef4;
+sta_auth_open = 0x40001ef8;
+sta_auth_shared = 0x40001efc;
+sta_auth_sae = 0x40001f00;
+cnx_coexist_timeout_process = 0x40001f04;
+ieee80211_alloc_challenge = 0x40001f08;
+cnx_assoc_timeout = 0x40001f0c;
+ieee80211_vnd_ie_set = 0x40001f10;
+ieee80211_vnd_lora_ie_set = 0x40001f14;
+ieee80211_add_wme_param = 0x40001f18;
+ieee80211_add_dsparams = 0x40001f1c;
+ieee80211_add_csa = 0x40001f20;
+ieee80211_add_extcap = 0x40001f24;
+ieee80211_regdomain_get_country = 0x40001f28;
+ieee80211_add_countryie = 0x40001f2c;
+ieee80211_alloc_proberesp = 0x40001f30;
+ieee80211_amsdu_adjust_head = 0x40001f34;
+ieee80211_amsdu_adjust_last_length = 0x40001f38;
+ieee80211_amsdu_send_check = 0x40001f3c;
+ieee80211_amsdu_encap_check = 0x40001f40;
+ieee80211_amsdu_length_check = 0x40001f44;
+ieee80211_encap_amsdu = 0x40001f48;
+ieee80211_output_raw_process = 0x40001f4c;
+esp_wifi_80211_tx = 0x40001f50;
+ieee80211_raw_frame_sanity_check = 0x40001f54;
+ieee80211_crypto_aes_128_cmac_encrypt = 0x40001f58;
+ieee80211_crypto_aes_128_cmac_decrypt = 0x40001f5c;
+ieee80211_alloc_tx_buf = 0x40001f60;
+ieee80211_output_do = 0x40001f64;
+ieee80211_send_nulldata = 0x40001f68;
+ieee80211_setup_robust_mgmtframe = 0x40001f6c;
+ieee80211_mgmt_output = 0x40001f70;
+ieee80211_encap_null_data = 0x40001f74;
+ieee80211_send_deauth = 0x40001f78;
+ieee80211_alloc_deauth = 0x40001f7c;
+ieee80211_send_proberesp = 0x40001f80;
+ieee80211_tx_mgt_cb = 0x40001f84;
+ieee80211_getcapinfo = 0x40001f88;
+sta_rx_csa = 0x40001f8c;
+sta_send_sa_query_req = 0x40001f90;
+sta_send_sa_query_resp = 0x40001f94;
+sta_recv_sa_query_req = 0x40001f98;
+sta_recv_sa_query_resp = 0x40001f9c;
+ieee80211_parse_beacon = 0x40001fa0;
+ieee80211_set_max_rate = 0x40001fa4;
+ic_set_sta = 0x40001fa8;
+ieee80211_match_security = 0x40001fac;
+ieee80211_parse_wpa = 0x40001fb0;
+ieee80211_parse_rsn = 0x40001fb4;
+ieee80211_add_assoc_req_ies = 0x40001fb8;
+ieee80211_add_probe_req_ies = 0x40001fbc;
+/* Data (.data, .bss, .rodata) */
+net80211_funcs = 0x3fcdfb80;
+g_scan = 0x3fcdfb7c;
+g_chm = 0x3fcdfb78;
+g_ic_ptr = 0x3fcdfb74;
+g_hmac_cnt_ptr = 0x3fcdfb50;
+g_tx_cacheq_ptr = 0x3fcdfb70;
+s_netstack_free = 0x3fcdfb6c;
+mesh_rxcb = 0x3fcdfb68;
+sta_rxcb = 0x3fcdfb64;
+ccmp_ptr = 0x3fcdfb60;
+s_wifi_nvs_ptr = 0x3fcdfb5c;
+tkip_ptr = 0x3fcdfb58;
+wep_ptr = 0x3fcdfb54;
+g_hmac_cnt_ptr = 0x3fcdfb50;
+g_misc_nvs = 0x3fcdfb4c;
+s_wifi_init_state = 0x3fcdfb1c;
+s_wifi_task_hdl = 0x3fcdfb48;
+in_rssi_adjust = 0x3fcdfb44;
+rssi_saved = 0x3fcdfb3c;
+rssi_index = 0x3fcdfb38;
+s_sa_query_retries = 0x3fcdfb34;
+s_sa_query_success = 0x3fcdfb31;
+g_sta_connected_flag = 0x3fcdfb30;
+wpa_crypto_funcs_ptr = 0x3fcdfb2c;
+s_netstack_ref = 0x3fcdfb28;
+sta_csa_timer_ptr = 0x3fcdfb24;
+s_trans_id = 0x3fcdfb20;
+
+
+/***************************************
+ Group rom_coexist
+ ***************************************/
+
+/* Functions */
+esp_coex_rom_version_get = 0x40001fc0;
+coex_bt_release = 0x40001fc4;
+coex_bt_request = 0x40001fc8;
+coex_core_ble_conn_dyn_prio_get = 0x40001fcc;
+coex_core_event_duration_get = 0x40001fd0;
+coex_core_pti_get = 0x40001fd4;
+coex_core_release = 0x40001fd8;
+coex_core_request = 0x40001fdc;
+coex_core_status_get = 0x40001fe0;
+coex_core_timer_idx_get = 0x40001fe4;
+coex_event_duration_get = 0x40001fe8;
+coex_hw_timer_disable = 0x40001fec;
+coex_hw_timer_enable = 0x40001ff0;
+coex_hw_timer_set = 0x40001ff4;
+coex_schm_interval_set = 0x40001ff8;
+coex_schm_lock = 0x40001ffc;
+coex_schm_unlock = 0x40002000;
+coex_status_get = 0x40002004;
+coex_wifi_release = 0x40002008;
+esp_coex_ble_conn_dynamic_prio_get = 0x4000200c;
+coex_hw_timer_tick_get = 0x40002010;
+/* Data (.data, .bss, .rodata) */
+coex_env_ptr = 0x3fcdfb18;
+coex_pti_tab_ptr = 0x3fcdfb14;
+coex_schm_env_ptr = 0x3fcdfb10;
+coexist_funcs = 0x3fcdfb0c;
+g_coa_funcs_p = 0x3fcdfb08;
+g_coex_param_ptr = 0x3fcdfb04;
+
+
+/***************************************
+ Group rom_phy
+ ***************************************/
+
+/* Functions */
+phy_param_addr = 0x40002014;
+phy_get_romfuncs = 0x40002018;
+chip729_phyrom_version = 0x4000201c;
+chip729_phyrom_version_num = 0x40002020;
+rom_get_bias_ref_code = 0x40002024;
+get_rc_dout = 0x40002028;
+rc_cal = 0x4000202c;
+phy_analog_delay_cal = 0x40002030;
+RFChannelSel = 0x40002034;
+phy_change_channel = 0x40002038;
+phy_set_most_tpw = 0x4000203c;
+phy_rx_rifs_en = 0x40002040;
+phy_get_most_tpw = 0x40002044;
+esp_tx_state_out = 0x40002048;
+phy_get_adc_rand = 0x4000204c;
+phy_internal_delay = 0x40002050;
+phy_ftm_comp = 0x40002054;
+phy_11p_set = 0x40002058;
+phy_current_level_set = 0x4000205c;
+phy_bbpll_en_usb = 0x40002060;
+phy_bt_power_track = 0x40002064;
+rom_enter_critical_phy = 0x40002068;
+rom_exit_critical_phy = 0x4000206c;
+rom_bb_bss_cbw40 = 0x40002070;
+rom_set_chan_reg = 0x40002074;
+abs_temp = 0x40002078;
+set_chan_cal_interp = 0x4000207c;
+loopback_mode_en = 0x40002080;
+get_data_sat = 0x40002084;
+phy_byte_to_word = 0x40002088;
+phy_get_rx_freq = 0x4000208c;
+i2c_master_reset = 0x40002090;
+chan14_mic_enable = 0x40002094;
+chan14_mic_cfg = 0x40002098;
+set_adc_rand = 0x4000209c;
+wr_rf_freq_mem = 0x400020a0;
+freq_i2c_write_set = 0x400020a4;
+write_pll_cap_mem = 0x400020a8;
+get_rf_freq_cap = 0x400020ac;
+get_rf_freq_init = 0x400020b0;
+freq_get_i2c_data = 0x400020b4;
+freq_i2c_data_write = 0x400020b8;
+set_chan_freq_hw_init = 0x400020bc;
+phy_en_hw_set_freq = 0x400020c0;
+phy_dis_hw_set_freq = 0x400020c4;
+register_chipv7_phy_init_param = 0x400020c8;
+phy_reg_init = 0x400020cc;
+phy_xpd_rf = 0x400020d0;
+phy_close_rf = 0x400020d4;
+rf_cal_data_recovery = 0x400020d8;
+rf_cal_data_backup = 0x400020dc;
+phy_rfcal_data_check = 0x400020e0;
+rom_pwdet_sar2_init = 0x400020e4;
+rom_en_pwdet = 0x400020e8;
+rom_get_sar_sig_ref = 0x400020ec;
+rom_pwdet_tone_start = 0x400020f0;
+rom_get_tone_sar_dout = 0x400020f4;
+rom_get_fm_sar_dout = 0x400020f8;
+rom_txtone_linear_pwr = 0x400020fc;
+rom_get_power_db = 0x40002100;
+rom_meas_tone_pwr_db = 0x40002104;
+rom_pkdet_vol_start = 0x40002108;
+rom_read_sar_dout = 0x4000210c;
+rom_read_sar2_code = 0x40002110;
+rom_get_sar2_vol = 0x40002114;
+rom_get_pll_vol = 0x40002118;
+rom_tx_pwctrl_bg_init = 0x4000211c;
+rom_phy_pwdet_always_en = 0x40002120;
+rom_phy_pwdet_onetime_en = 0x40002124;
+linear_to_db = 0x40002128;
+rom_get_pll_ref_code = 0x4000212c;
+mhz2ieee = 0x40002130;
+chan_to_freq = 0x40002134;
+restart_cal = 0x40002138;
+write_rfpll_sdm = 0x4000213c;
+wait_rfpll_cal_end = 0x40002140;
+rfpll_set_freq = 0x40002144;
+set_rf_freq_offset = 0x40002148;
+set_channel_rfpll_freq = 0x4000214c;
+set_rfpll_freq = 0x40002150;
+phy_set_freq = 0x40002154;
+correct_rfpll_offset = 0x40002158;
+set_chan_freq_sw_start = 0x4000215c;
+pll_vol_cal = 0x40002160;
+write_pll_cap = 0x40002164;
+read_pll_cap = 0x40002168;
+chip_v7_set_chan_misc = 0x4000216c;
+chip_v7_set_chan = 0x40002170;
+chip_v7_set_chan_offset = 0x40002174;
+chip_v7_set_chan_ana = 0x40002178;
+set_chanfreq = 0x4000217c;
+gen_rx_gain_table = 0x40002180;
+wr_rx_gain_mem = 0x40002184;
+set_rx_gain_param = 0x40002188;
+set_rx_gain_table = 0x4000218c;
+bt_track_pll_cap = 0x40002190;
+wifi_track_pll_cap = 0x40002194;
+phy_param_track = 0x40002198;
+txpwr_correct = 0x4000219c;
+txpwr_cal_track = 0x400021a0;
+tx_pwctrl_background = 0x400021a4;
+bt_track_tx_power = 0x400021a8;
+wifi_track_tx_power = 0x400021ac;
+bt_txdc_cal = 0x400021b0;
+bt_txiq_cal = 0x400021b4;
+txiq_cal_init = 0x400021b8;
+get_txcap_data = 0x400021bc;
+txdc_cal_init = 0x400021c0;
+txdc_cal_v70 = 0x400021c4;
+txiq_get_mis_pwr = 0x400021c8;
+txiq_cover = 0x400021cc;
+rfcal_txiq = 0x400021d0;
+get_power_atten = 0x400021d4;
+pwdet_ref_code = 0x400021d8;
+pwdet_code_cal = 0x400021dc;
+rfcal_txcap = 0x400021e0;
+tx_cap_init = 0x400021e4;
+rfcal_pwrctrl = 0x400021e8;
+tx_pwctrl_init_cal = 0x400021ec;
+tx_pwctrl_init = 0x400021f0;
+bt_tx_pwctrl_init = 0x400021f4;
+bt_txpwr_freq = 0x400021f8;
+rom_get_i2c_read_mask = 0x400021fc;
+rom_get_i2c_mst0_mask = 0x40002200;
+rom_get_i2c_hostid = 0x40002204;
+rom_chip_i2c_readReg_org = 0x40002208;
+rom_chip_i2c_readReg = 0x4000220c;
+rom_i2c_paral_set_mst0 = 0x40002210;
+rom_i2c_paral_set_read = 0x40002214;
+rom_i2c_paral_read = 0x40002218;
+rom_i2c_paral_write = 0x4000221c;
+rom_i2c_paral_write_num = 0x40002220;
+rom_i2c_paral_write_mask = 0x40002224;
+rom_i2c_readReg = 0x40002228;
+rom_chip_i2c_writeReg = 0x4000222c;
+rom_i2c_writeReg = 0x40002230;
+rom_i2c_readReg_Mask = 0x40002234;
+rom_i2c_writeReg_Mask = 0x40002238;
+rom_set_txcap_reg = 0x4000223c;
+i2c_sar2_init_code = 0x40002240;
+phy_i2c_init1 = 0x40002244;
+phy_i2c_init2 = 0x40002248;
+phy_get_i2c_data = 0x4000224c;
+bias_reg_set = 0x40002250;
+i2c_bbpll_set = 0x40002254;
+rom_pbus_force_mode = 0x40002258;
+rom_pbus_rd_addr = 0x4000225c;
+rom_pbus_rd_shift = 0x40002260;
+rom_pbus_force_test = 0x40002264;
+rom_pbus_rd = 0x40002268;
+rom_pbus_debugmode = 0x4000226c;
+rom_pbus_workmode = 0x40002270;
+rom_pbus_set_rxgain = 0x40002274;
+rom_pbus_xpd_rx_off = 0x40002278;
+rom_pbus_xpd_rx_on = 0x4000227c;
+rom_pbus_xpd_tx_off = 0x40002280;
+rom_pbus_xpd_tx_on = 0x40002284;
+rom_pbus_set_dco = 0x40002288;
+rom_set_loopback_gain = 0x4000228c;
+rom_txcal_debuge_mode = 0x40002290;
+rom_txcal_work_mode = 0x40002294;
+set_pbus_mem = 0x40002298;
+rom_disable_agc = 0x4000229c;
+rom_enable_agc = 0x400022a0;
+rom_disable_wifi_agc = 0x400022a4;
+rom_enable_wifi_agc = 0x400022a8;
+rom_write_gain_mem = 0x400022ac;
+rom_bb_bss_cbw40_dig = 0x400022b0;
+rom_cbw2040_cfg = 0x400022b4;
+rom_mac_tx_chan_offset = 0x400022b8;
+rom_tx_paon_set = 0x400022bc;
+rom_i2cmst_reg_init = 0x400022c0;
+rom_bt_gain_offset = 0x400022c4;
+rom_fe_reg_init = 0x400022c8;
+rom_mac_enable_bb = 0x400022cc;
+rom_bb_wdg_cfg = 0x400022d0;
+rom_fe_txrx_reset = 0x400022d4;
+rom_set_rx_comp = 0x400022d8;
+rom_write_chan_freq = 0x400022dc;
+rom_agc_reg_init = 0x400022e0;
+rom_bb_reg_init = 0x400022e4;
+rom_write_txrate_power_offset = 0x400022e8;
+rom_open_i2c_xpd = 0x400022ec;
+phy_disable_cca = 0x400022f0;
+phy_enable_cca = 0x400022f4;
+force_txon = 0x400022f8;
+txiq_set_reg = 0x400022fc;
+rxiq_set_reg = 0x40002300;
+rx_gain_force = 0x40002304;
+set_txclk_en = 0x40002308;
+set_rxclk_en = 0x4000230c;
+start_tx_tone_step = 0x40002310;
+stop_tx_tone = 0x40002314;
+bb_wdg_test_en = 0x40002318;
+noise_floor_auto_set = 0x4000231c;
+read_hw_noisefloor = 0x40002320;
+set_cca = 0x40002324;
+set_rx_sense = 0x40002328;
+phy_rx11blr_cfg = 0x4000232c;
+bb_wdt_rst_enable = 0x40002330;
+bb_wdt_int_enable = 0x40002334;
+bb_wdt_timeout_clear = 0x40002338;
+bb_wdt_get_status = 0x4000233c;
+wifi_rifs_mode_en = 0x40002340;
+phy_chan_filt_set = 0x40002344;
+iq_corr_enable = 0x40002348;
+bt_tx_dig_gain = 0x4000234c;
+wifi_tx_dig_reg = 0x40002350;
+wifi_agc_sat_gain = 0x40002354;
+phy_bbpll_cal = 0x40002358;
+phy_xpd_tsens = 0x4000235c;
+phy_freq_mem_backup = 0x40002360;
+phy_ant_init = 0x40002364;
+phy_set_bbfreq_init = 0x40002368;
+wifi_fbw_sel = 0x4000236c;
+phy_rx_sense_set = 0x40002370;
+ant_dft_cfg = 0x40002374;
+ant_wifitx_cfg = 0x40002378;
+ant_wifirx_cfg = 0x4000237c;
+ant_bttx_cfg = 0x40002380;
+tx_state_set = 0x40002384;
+phy_chan_dump_cfg = 0x40002388;
+phy_enable_low_rate = 0x4000238c;
+phy_disable_low_rate = 0x40002390;
+phy_close_pa = 0x40002394;
+bt_filter_reg = 0x40002398;
+phy_freq_correct = 0x4000239c;
+set_pbus_reg = 0x400023a0;
+phy_dig_reg_backup = 0x400023a4;
+iq_est_enable = 0x400023a8;
+iq_est_disable = 0x400023ac;
+dc_iq_est = 0x400023b0;
+set_cal_rxdc = 0x400023b4;
+rxiq_get_mis = 0x400023b8;
+rxiq_cover_mg_mp = 0x400023bc;
+rfcal_rxiq = 0x400023c0;
+get_rfcal_rxiq_data = 0x400023c4;
+pbus_rx_dco_cal = 0x400023c8;
+rxdc_est_min = 0x400023cc;
+pbus_rx_dco_cal_1step = 0x400023d0;
+set_rx_gain_cal_iq = 0x400023d4;
+set_rx_gain_cal_dc = 0x400023d8;
+spur_reg_write_one_tone = 0x400023dc;
+spur_cal = 0x400023e0;
+spur_coef_cfg = 0x400023e4;
+rom_tester_wifi_cali = 0x400023e8;
+esp_recover_efuse_data = 0x400023ec;
+rom_temp_to_power = 0x400023f0;
+tsens_read_init = 0x400023f4;
+code_to_temp = 0x400023f8;
+tsens_index_to_dac = 0x400023fc;
+tsens_index_to_offset = 0x40002400;
+tsens_dac_cal = 0x40002404;
+tsens_code_read = 0x40002408;
+tsens_temp_read = 0x4000240c;
+get_temp_init = 0x40002410;
+rom_txbbgain_to_index = 0x40002414;
+rom_index_to_txbbgain = 0x40002418;
+rom_bt_index_to_bb = 0x4000241c;
+rom_bt_bb_to_index = 0x40002420;
+rom_bt_get_tx_gain = 0x40002424;
+rom_get_tx_gain_value = 0x40002428;
+rom_wifi_get_tx_gain = 0x4000242c;
+rom_set_tx_gain_mem = 0x40002430;
+rom_get_rate_fcc_index = 0x40002434;
+rom_get_chan_target_power = 0x40002438;
+rom_wifi_tx_dig_gain = 0x4000243c;
+rom_wifi_set_tx_gain = 0x40002440;
+rom_bt_set_tx_gain = 0x40002444;
+wifi_11g_rate_chg = 0x40002448;
+bt_chan_pwr_interp = 0x4000244c;
+bt_tx_gain_init = 0x40002450;
+/* Data (.data, .bss, .rodata) */
+phy_param_rom = 0x3fcdfb00;
+
+
+/***************************************
+ Group rom_btbb
+ ***************************************/
+
+/* Functions */
+bt_agc_gain_offset = 0x40002454;
+bt_agc_gain_max = 0x40002458;
+bt_set_rx_comp = 0x4000245c;
+bt_agc_gain_set = 0x40002460;
+bt_agc_rssi_thresh = 0x40002464;
+bt_agc_target_set = 0x40002468;
+bt_agc_restart_set = 0x4000246c;
+bt_agc_recorrect_set = 0x40002470;
+bt_agc_detect_set = 0x40002474;
+bt_bb_rx_correlator_set = 0x40002478;
+bt_bb_rx_dpo_set = 0x4000247c;
+bt_bb_rx_filter_sel = 0x40002480;
+bt_bb_rx_set1 = 0x40002484;
+bt_bb_v2_rx_set = 0x40002488;
+bt_bb_v2_tx_set = 0x4000248c;
+bt_bb_tx_cca_period = 0x40002490;
+bt_bb_tx_cca_fifo_reset = 0x40002494;
+bt_bb_tx_cca_fifo_empty = 0x40002498;
+bt_bb_tx_cca_fifo_full = 0x4000249c;
+bt_bb_tx_cca_fifo_count = 0x400024a0;
+bt_bb_tx_cca_fifo_read = 0x400024a4;
+coex_pti_v2 = 0x400024a8;
+bt_bb_set_le_tx_on_delay = 0x400024ac;
+bt_bb_set_corr_thresh_le = 0x400024b0;
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.libgcc.ld b/components/esp_rom/esp8684/ld/esp8684.rom.libgcc.ld
new file mode 100644
index 0000000000000000000000000000000000000000..0d890dc6fe6e9b2a6273cd80e79ca681be134627
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.libgcc.ld
@@ -0,0 +1,113 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM function interface esp8684.rom.libgcc.ld for esp8684
+ *
+ *
+ * Generated from ./interface-esp8684.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libgcc
+ ***************************************/
+
+/* Functions */
+__absvdi2 = 0x400008a4;
+__absvsi2 = 0x400008a8;
+__adddf3 = 0x400008ac;
+__addsf3 = 0x400008b0;
+__addvdi3 = 0x400008b4;
+__addvsi3 = 0x400008b8;
+__ashldi3 = 0x400008bc;
+__ashrdi3 = 0x400008c0;
+__bswapdi2 = 0x400008c4;
+__bswapsi2 = 0x400008c8;
+__clear_cache = 0x400008cc;
+__clrsbdi2 = 0x400008d0;
+__clrsbsi2 = 0x400008d4;
+__clzdi2 = 0x400008d8;
+__clzsi2 = 0x400008dc;
+__cmpdi2 = 0x400008e0;
+__ctzdi2 = 0x400008e4;
+__ctzsi2 = 0x400008e8;
+__divdc3 = 0x400008ec;
+__divdf3 = 0x400008f0;
+__divdi3 = 0x400008f4;
+__divsc3 = 0x400008f8;
+__divsf3 = 0x400008fc;
+__divsi3 = 0x40000900;
+__eqdf2 = 0x40000904;
+__eqsf2 = 0x40000908;
+__extendsfdf2 = 0x4000090c;
+__ffsdi2 = 0x40000910;
+__ffssi2 = 0x40000914;
+__fixdfdi = 0x40000918;
+__fixdfsi = 0x4000091c;
+__fixsfdi = 0x40000920;
+__fixsfsi = 0x40000924;
+__fixunsdfsi = 0x40000928;
+__fixunssfdi = 0x4000092c;
+__fixunssfsi = 0x40000930;
+__floatdidf = 0x40000934;
+__floatdisf = 0x40000938;
+__floatsidf = 0x4000093c;
+__floatsisf = 0x40000940;
+__floatundidf = 0x40000944;
+__floatundisf = 0x40000948;
+__floatunsidf = 0x4000094c;
+__floatunsisf = 0x40000950;
+__gcc_bcmp = 0x40000954;
+__gedf2 = 0x40000958;
+__gesf2 = 0x4000095c;
+__gtdf2 = 0x40000960;
+__gtsf2 = 0x40000964;
+__ledf2 = 0x40000968;
+__lesf2 = 0x4000096c;
+__lshrdi3 = 0x40000970;
+__ltdf2 = 0x40000974;
+__ltsf2 = 0x40000978;
+__moddi3 = 0x4000097c;
+__modsi3 = 0x40000980;
+__muldc3 = 0x40000984;
+__muldf3 = 0x40000988;
+__muldi3 = 0x4000098c;
+__mulsc3 = 0x40000990;
+__mulsf3 = 0x40000994;
+__mulsi3 = 0x40000998;
+__mulvdi3 = 0x4000099c;
+__mulvsi3 = 0x400009a0;
+__nedf2 = 0x400009a4;
+__negdf2 = 0x400009a8;
+__negdi2 = 0x400009ac;
+__negsf2 = 0x400009b0;
+__negvdi2 = 0x400009b4;
+__negvsi2 = 0x400009b8;
+__nesf2 = 0x400009bc;
+__paritysi2 = 0x400009c0;
+__popcountdi2 = 0x400009c4;
+__popcountsi2 = 0x400009c8;
+__powidf2 = 0x400009cc;
+__powisf2 = 0x400009d0;
+__subdf3 = 0x400009d4;
+__subsf3 = 0x400009d8;
+__subvdi3 = 0x400009dc;
+__subvsi3 = 0x400009e0;
+__truncdfsf2 = 0x400009e4;
+__ucmpdi2 = 0x400009e8;
+__udivdi3 = 0x400009ec;
+__udivmoddi4 = 0x400009f0;
+__udivsi3 = 0x400009f4;
+__udiv_w_sdiv = 0x400009f8;
+__umoddi3 = 0x400009fc;
+__umodsi3 = 0x40000a00;
+__unorddf2 = 0x40000a04;
+__unordsf2 = 0x40000a08;
+__extenddftf2 = 0x40000a0c;
+__trunctfdf2 = 0x40000a10;
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.mbedtls.ld b/components/esp_rom/esp8684/ld/esp8684.rom.mbedtls.ld
new file mode 100644
index 0000000000000000000000000000000000000000..f9e85763d7b3523a4f4a9cf77480de2f1444af13
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.mbedtls.ld
@@ -0,0 +1,413 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM function interface esp8684.rom.mbedtls.ld for esp8684
+ *
+ *
+ * Generated from ./interface-esp8684.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group rom_mbedtls
+ ***************************************/
+
+/* Functions */
+r_mbedtls_aes_init = 0x400024b4;
+r_ssl_write_client_hello = 0x400024b8;
+r_ssl_parse_server_hello = 0x400024bc;
+r_ssl_parse_server_key_exchange = 0x400024c0;
+r_ssl_parse_certificate_request = 0x400024c4;
+r_ssl_parse_server_hello_done = 0x400024c8;
+r_ssl_write_client_key_exchange = 0x400024cc;
+r_ssl_write_certificate_verify = 0x400024d0;
+r_ssl_parse_new_session_ticket = 0x400024d4;
+r_mbedtls_aes_free = 0x400024d8;
+r_mbedtls_aes_setkey_enc = 0x400024dc;
+r_mbedtls_aes_setkey_dec = 0x400024e0;
+r_mbedtls_aes_crypt_ecb = 0x400024e4;
+r_mbedtls_aes_crypt_cbc = 0x400024e8;
+r_mbedtls_internal_aes_encrypt = 0x400024ec;
+r_mbedtls_internal_aes_decrypt = 0x400024f0;
+r_mbedtls_asn1_get_len = 0x400024f4;
+r_mbedtls_asn1_get_tag = 0x400024f8;
+r_mbedtls_asn1_get_bool = 0x400024fc;
+r_mbedtls_asn1_get_int = 0x40002500;
+r_mbedtls_asn1_get_bitstring = 0x40002504;
+r_mbedtls_asn1_get_bitstring_null = 0x40002508;
+r_mbedtls_asn1_get_sequence_of = 0x4000250c;
+r_mbedtls_asn1_get_mpi = 0x40002510;
+r_mbedtls_asn1_get_alg = 0x40002514;
+r_mbedtls_asn1_get_alg_null = 0x40002518;
+r_mbedtls_asn1_write_len = 0x4000251c;
+r_mbedtls_asn1_write_tag = 0x40002520;
+r_mbedtls_asn1_write_mpi = 0x40002524;
+r_mbedtls_base64_decode = 0x40002528;
+r_mbedtls_mpi_init = 0x4000252c;
+r_mbedtls_mpi_free = 0x40002530;
+r_mbedtls_mpi_grow = 0x40002534;
+r_mbedtls_mpi_shrink = 0x40002538;
+r_mbedtls_mpi_copy = 0x4000253c;
+r_mbedtls_mpi_safe_cond_assign = 0x40002540;
+r_mbedtls_mpi_safe_cond_swap = 0x40002544;
+r_mbedtls_mpi_lset = 0x40002548;
+r_mbedtls_mpi_get_bit = 0x4000254c;
+r_mbedtls_mpi_set_bit = 0x40002550;
+r_mbedtls_mpi_lsb = 0x40002554;
+r_mbedtls_mpi_bitlen = 0x40002558;
+r_mbedtls_mpi_size = 0x4000255c;
+r_mbedtls_mpi_read_binary = 0x40002560;
+r_mbedtls_mpi_write_binary = 0x40002564;
+r_mbedtls_mpi_shift_l = 0x40002568;
+r_mbedtls_mpi_shift_r = 0x4000256c;
+r_mbedtls_mpi_cmp_abs = 0x40002570;
+r_mbedtls_mpi_cmp_mpi = 0x40002574;
+r_mbedtls_mpi_lt_mpi_ct = 0x40002578;
+r_mbedtls_mpi_cmp_int = 0x4000257c;
+r_mbedtls_mpi_add_abs = 0x40002580;
+r_mbedtls_mpi_sub_abs = 0x40002584;
+r_mbedtls_mpi_add_mpi = 0x40002588;
+r_mbedtls_mpi_sub_mpi = 0x4000258c;
+r_mbedtls_mpi_add_int = 0x40002590;
+r_mbedtls_mpi_sub_int = 0x40002594;
+r_mbedtls_mpi_mul_mpi = 0x40002598;
+r_mbedtls_mpi_mul_int = 0x4000259c;
+r_mbedtls_mpi_div_mpi = 0x400025a0;
+r_mbedtls_mpi_div_int = 0x400025a4;
+r_mbedtls_mpi_mod_mpi = 0x400025a8;
+r_mbedtls_mpi_mod_int = 0x400025ac;
+r_mbedtls_mpi_exp_mod = 0x400025b0;
+r_mbedtls_mpi_fill_random = 0x400025b4;
+r_mbedtls_mpi_gcd = 0x400025b8;
+r_mbedtls_mpi_inv_mod = 0x400025bc;
+r_mbedtls_mpi_is_prime_ext = 0x400025c0;
+r_mbedtls_ccm_star_encrypt_and_tag = 0x400025c4;
+r_mbedtls_ccm_star_auth_decrypt = 0x400025c8;
+r_mbedtls_cipher_init = 0x400025cc;
+r_mbedtls_cipher_set_padding_mode = 0x400025d0;
+r_mbedtls_cipher_reset = 0x400025d4;
+r_mbedtls_cipher_finish = 0x400025d8;
+r_mbedtls_cipher_crypt = 0x400025dc;
+r_mbedtls_cipher_cmac_starts = 0x400025e0;
+r_mbedtls_cipher_cmac_update = 0x400025e4;
+r_mbedtls_cipher_cmac_finish = 0x400025e8;
+r_mbedtls_ctr_drbg_init = 0x400025ec;
+r_mbedtls_ctr_drbg_seed = 0x400025f0;
+r_mbedtls_ctr_drbg_free = 0x400025f4;
+r_mbedtls_ctr_drbg_reseed = 0x400025f8;
+r_mbedtls_ctr_drbg_random_with_add = 0x400025fc;
+r_mbedtls_ctr_drbg_random = 0x40002600;
+r_mbedtls_dhm_init = 0x40002604;
+r_mbedtls_dhm_read_params = 0x40002608;
+r_mbedtls_dhm_make_public = 0x4000260c;
+r_mbedtls_dhm_calc_secret = 0x40002610;
+r_mbedtls_dhm_free = 0x40002614;
+r_mbedtls_ecdh_init = 0x40002618;
+r_mbedtls_ecdh_setup = 0x4000261c;
+r_mbedtls_ecdh_free = 0x40002620;
+r_mbedtls_ecdh_read_params = 0x40002624;
+r_mbedtls_ecdh_get_params = 0x40002628;
+r_mbedtls_ecdh_make_public = 0x4000262c;
+r_mbedtls_ecdh_calc_secret = 0x40002630;
+r_mbedtls_ecdh_enable_restart = 0x40002634;
+r_mbedtls_ecdsa_write_signature = 0x40002638;
+r_mbedtls_ecdsa_write_signature_restartable = 0x4000263c;
+r_mbedtls_ecdsa_read_signature = 0x40002640;
+r_mbedtls_ecdsa_read_signature_restartable = 0x40002644;
+r_mbedtls_ecdsa_from_keypair = 0x40002648;
+r_mbedtls_ecdsa_init = 0x4000264c;
+r_mbedtls_ecdsa_free = 0x40002650;
+r_mbedtls_ecdsa_restart_init = 0x40002654;
+r_mbedtls_ecdsa_restart_free = 0x40002658;
+r_mbedtls_ecjpake_init = 0x4000265c;
+r_mbedtls_ecjpake_check = 0x40002660;
+r_mbedtls_ecjpake_write_round_one = 0x40002664;
+r_mbedtls_ecjpake_read_round_one = 0x40002668;
+r_mbedtls_ecjpake_write_round_two = 0x4000266c;
+r_mbedtls_ecjpake_read_round_two = 0x40002670;
+r_mbedtls_ecjpake_derive_secret = 0x40002674;
+r_mbedtls_ecjpake_free = 0x40002678;
+r_mbedtls_ecp_check_budget = 0x4000267c;
+r_mbedtls_ecp_restart_is_enabled = 0x40002680;
+r_mbedtls_ecp_curve_list = 0x40002684;
+r_mbedtls_ecp_grp_id_list = 0x40002688;
+r_mbedtls_ecp_curve_info_from_grp_id = 0x4000268c;
+r_mbedtls_ecp_curve_info_from_tls_id = 0x40002690;
+r_mbedtls_ecp_point_init = 0x40002694;
+r_mbedtls_ecp_group_init = 0x40002698;
+r_mbedtls_ecp_keypair_init = 0x4000269c;
+r_mbedtls_ecp_point_free = 0x400026a0;
+r_mbedtls_ecp_group_free = 0x400026a4;
+r_mbedtls_ecp_keypair_free = 0x400026a8;
+r_mbedtls_ecp_restart_init = 0x400026ac;
+r_mbedtls_ecp_restart_free = 0x400026b0;
+r_mbedtls_ecp_copy = 0x400026b4;
+r_mbedtls_ecp_group_copy = 0x400026b8;
+r_mbedtls_ecp_set_zero = 0x400026bc;
+r_mbedtls_ecp_is_zero = 0x400026c0;
+r_mbedtls_ecp_point_cmp = 0x400026c4;
+r_mbedtls_ecp_point_write_binary = 0x400026c8;
+r_mbedtls_ecp_point_read_binary = 0x400026cc;
+r_mbedtls_ecp_tls_read_point = 0x400026d0;
+r_mbedtls_ecp_tls_write_point = 0x400026d4;
+r_mbedtls_ecp_group_load = 0x400026d8;
+r_mbedtls_ecp_tls_read_group = 0x400026dc;
+r_mbedtls_ecp_tls_read_group_id = 0x400026e0;
+r_mbedtls_ecp_tls_write_group = 0x400026e4;
+r_mbedtls_ecp_mul = 0x400026e8;
+r_mbedtls_ecp_mul_restartable = 0x400026ec;
+r_mbedtls_ecp_muladd = 0x400026f0;
+r_mbedtls_ecp_muladd_restartable = 0x400026f4;
+r_mbedtls_ecp_check_pubkey = 0x400026f8;
+r_mbedtls_ecp_check_privkey = 0x400026fc;
+r_mbedtls_ecp_gen_privkey = 0x40002700;
+r_mbedtls_ecp_gen_keypair_base = 0x40002704;
+r_mbedtls_ecp_check_pub_priv = 0x40002708;
+r_mbedtls_entropy_add_source = 0x4000270c;
+r_mbedtls_entropy_func = 0x40002710;
+r_mbedtls_gcm_crypt_and_tag = 0x40002714;
+r_mbedtls_gcm_starts = 0x40002718;
+r_mbedtls_gcm_update = 0x4000271c;
+r_mbedtls_gcm_finish = 0x40002720;
+r_mbedtls_hmac_drbg_init = 0x40002724;
+r_mbedtls_hmac_drbg_seed_buf = 0x40002728;
+r_mbedtls_hmac_drbg_update_ret = 0x4000272c;
+r_mbedtls_hmac_drbg_reseed = 0x40002730;
+r_mbedtls_hmac_drbg_random_with_add = 0x40002734;
+r_mbedtls_hmac_drbg_random = 0x40002738;
+r_mbedtls_hmac_drbg_free = 0x4000273c;
+r_mbedtls_md_list = 0x40002740;
+r_mbedtls_md_init = 0x40002744;
+r_mbedtls_md_free = 0x40002748;
+r_mbedtls_md_setup = 0x4000274c;
+r_mbedtls_md_clone = 0x40002750;
+r_mbedtls_md_get_size = 0x40002754;
+r_mbedtls_md_get_type = 0x40002758;
+r_mbedtls_md_starts = 0x4000275c;
+r_mbedtls_md_update = 0x40002760;
+r_mbedtls_md_finish = 0x40002764;
+r_mbedtls_md = 0x40002768;
+r_mbedtls_md_hmac_starts = 0x4000276c;
+r_mbedtls_md_hmac_update = 0x40002770;
+r_mbedtls_md_hmac_finish = 0x40002774;
+r_mbedtls_md_hmac_reset = 0x40002778;
+r_mbedtls_oid_get_x509_ext_type = 0x4000277c;
+r_mbedtls_oid_get_pk_alg = 0x40002780;
+r_mbedtls_oid_get_ec_grp = 0x40002784;
+r_mbedtls_oid_get_sig_alg = 0x40002788;
+r_mbedtls_oid_get_md_alg = 0x4000278c;
+r_mbedtls_oid_get_md_hmac = 0x40002790;
+r_mbedtls_oid_get_oid_by_md = 0x40002794;
+r_mbedtls_oid_get_cipher_alg = 0x40002798;
+r_mbedtls_oid_get_pkcs12_pbe_alg = 0x4000279c;
+r_mbedtls_pem_init = 0x400027a0;
+r_mbedtls_pem_free = 0x400027a4;
+r_mbedtls_pkcs12_pbe_sha1_rc4_128 = 0x400027a8;
+r_mbedtls_pkcs12_pbe = 0x400027ac;
+r_mbedtls_pkcs12_derivation = 0x400027b0;
+r_mbedtls_pkcs5_pbes2 = 0x400027b4;
+r_mbedtls_pkcs5_pbkdf2_hmac = 0x400027b8;
+r_mbedtls_pk_info_from_type = 0x400027bc;
+r_mbedtls_pk_init = 0x400027c0;
+r_mbedtls_pk_free = 0x400027c4;
+r_mbedtls_pk_restart_init = 0x400027c8;
+r_mbedtls_pk_restart_free = 0x400027cc;
+r_mbedtls_pk_setup = 0x400027d0;
+r_mbedtls_pk_can_do = 0x400027d4;
+r_mbedtls_pk_verify = 0x400027d8;
+r_mbedtls_pk_verify_restartable = 0x400027dc;
+r_mbedtls_pk_verify_ext = 0x400027e0;
+r_mbedtls_pk_sign_restartable = 0x400027e4;
+r_mbedtls_pk_encrypt = 0x400027e8;
+r_mbedtls_pk_get_type = 0x400027ec;
+r_mbedtls_pk_parse_subpubkey = 0x400027f0;
+r_mbedtls_rsa_init = 0x400027f4;
+r_mbedtls_rsa_import = 0x400027f8;
+r_mbedtls_rsa_import_raw = 0x400027fc;
+r_mbedtls_rsa_complete = 0x40002800;
+r_mbedtls_rsa_set_padding = 0x40002804;
+r_mbedtls_rsa_get_len = 0x40002808;
+r_mbedtls_rsa_check_pubkey = 0x4000280c;
+r_mbedtls_rsa_check_privkey = 0x40002810;
+r_mbedtls_rsa_check_pub_priv = 0x40002814;
+r_mbedtls_rsa_public = 0x40002818;
+r_mbedtls_rsa_private = 0x4000281c;
+r_mbedtls_rsa_pkcs1_encrypt = 0x40002820;
+r_mbedtls_rsa_rsaes_pkcs1_v15_encrypt = 0x40002824;
+r_mbedtls_rsa_rsaes_oaep_encrypt = 0x40002828;
+r_mbedtls_rsa_pkcs1_decrypt = 0x4000282c;
+r_mbedtls_rsa_rsaes_pkcs1_v15_decrypt = 0x40002830;
+r_mbedtls_rsa_rsaes_oaep_decrypt = 0x40002834;
+r_mbedtls_rsa_pkcs1_sign = 0x40002838;
+r_mbedtls_rsa_rsassa_pkcs1_v15_sign = 0x4000283c;
+r_mbedtls_rsa_rsassa_pss_sign = 0x40002840;
+r_mbedtls_rsa_pkcs1_verify = 0x40002844;
+r_mbedtls_rsa_rsassa_pkcs1_v15_verify = 0x40002848;
+r_mbedtls_rsa_rsassa_pss_verify = 0x4000284c;
+r_mbedtls_rsa_rsassa_pss_verify_ext = 0x40002850;
+r_mbedtls_rsa_free = 0x40002854;
+r_mbedtls_rsa_deduce_primes = 0x40002858;
+r_mbedtls_rsa_deduce_private_exponent = 0x4000285c;
+r_mbedtls_rsa_deduce_crt = 0x40002860;
+r_mbedtls_rsa_validate_params = 0x40002864;
+r_mbedtls_rsa_validate_crt = 0x40002868;
+r_mbedtls_sha1_init = 0x4000286c;
+r_mbedtls_sha1_free = 0x40002870;
+r_mbedtls_sha1_clone = 0x40002874;
+r_mbedtls_sha1_starts_ret = 0x40002878;
+r_mbedtls_sha1_finish_ret = 0x4000287c;
+r_mbedtls_sha256_init = 0x40002880;
+r_mbedtls_sha256_free = 0x40002884;
+r_mbedtls_sha256_clone = 0x40002888;
+r_mbedtls_sha256_starts_ret = 0x4000288c;
+r_mbedtls_sha256_finish_ret = 0x40002890;
+r_mbedtls_sha256_ret = 0x40002894;
+r_mbedtls_sha512_init = 0x40002898;
+r_mbedtls_sha512_free = 0x4000289c;
+r_mbedtls_sha512_clone = 0x400028a0;
+r_mbedtls_sha512_starts_ret = 0x400028a4;
+r_mbedtls_sha512_update_ret = 0x400028a8;
+r_mbedtls_sha512_finish_ret = 0x400028ac;
+r_mbedtls_internal_sha512_process = 0x400028b0;
+r_mbedtls_sha512_ret = 0x400028b4;
+r_mbedtls_ssl_conf_endpoint = 0x400028b8;
+r_mbedtls_ssl_conf_transport = 0x400028bc;
+r_mbedtls_ssl_set_bio = 0x400028c0;
+r_mbedtls_ssl_conf_dh_param_bin = 0x400028c4;
+r_mbedtls_ssl_get_max_frag_len = 0x400028c8;
+r_mbedtls_ssl_get_max_out_record_payload = 0x400028cc;
+r_mbedtls_ssl_handshake = 0x400028d0;
+r_mbedtls_ssl_handshake_step = 0x400028d4;
+r_mbedtls_ssl_renegotiate = 0x400028d8;
+r_mbedtls_ssl_send_alert_message = 0x400028dc;
+r_mbedtls_ssl_config_defaults = 0x400028e0;
+r_mbedtls_ssl_session_init = 0x400028e4;
+r_mbedtls_ssl_session_free = 0x400028e8;
+r_mbedtls_ssl_transform_free = 0x400028ec;
+r_mbedtls_ssl_handshake_free = 0x400028f0;
+r_mbedtls_ssl_handshake_client_step = 0x400028f4;
+r_mbedtls_ssl_handshake_wrapup = 0x400028f8;
+r_mbedtls_ssl_derive_keys = 0x400028fc;
+r_mbedtls_ssl_handle_message_type = 0x40002900;
+r_mbedtls_ssl_prepare_handshake_record = 0x40002904;
+r_mbedtls_ssl_update_handshake_status = 0x40002908;
+r_mbedtls_ssl_read_record = 0x4000290c;
+r_mbedtls_ssl_fetch_input = 0x40002910;
+r_mbedtls_ssl_write_handshake_msg = 0x40002914;
+r_mbedtls_ssl_write_record = 0x40002918;
+r_mbedtls_ssl_flush_output = 0x4000291c;
+r_mbedtls_ssl_parse_certificate = 0x40002920;
+r_mbedtls_ssl_write_certificate = 0x40002924;
+r_mbedtls_ssl_parse_change_cipher_spec = 0x40002928;
+r_mbedtls_ssl_write_change_cipher_spec = 0x4000292c;
+r_mbedtls_ssl_parse_finished = 0x40002930;
+r_mbedtls_ssl_write_finished = 0x40002934;
+r_mbedtls_ssl_optimize_checksum = 0x40002938;
+r_mbedtls_ssl_psk_derive_premaster = 0x4000293c;
+r_mbedtls_ssl_sig_from_pk = 0x40002940;
+r_mbedtls_ssl_pk_alg_from_sig = 0x40002944;
+r_mbedtls_ssl_md_alg_from_hash = 0x40002948;
+r_mbedtls_ssl_hash_from_md_alg = 0x4000294c;
+r_mbedtls_ssl_check_curve = 0x40002950;
+r_mbedtls_ssl_check_sig_hash = 0x40002954;
+r_mbedtls_ssl_write_version = 0x40002958;
+r_mbedtls_ssl_read_version = 0x4000295c;
+r_mbedtls_ssl_get_key_exchange_md_ssl_tls = 0x40002960;
+r_mbedtls_ssl_get_key_exchange_md_tls1_2 = 0x40002964;
+r_mbedtls_ssl_cf_hmac = 0x40002968;
+r_mbedtls_ssl_cf_memcpy_offset = 0x4000296c;
+r_mbedtls_x509_crt_parse_der = 0x40002970;
+r_mbedtls_x509_crt_verify_restartable = 0x40002974;
+r_mbedtls_x509_crt_check_key_usage = 0x40002978;
+r_mbedtls_x509_crt_check_extended_key_usage = 0x4000297c;
+r_mbedtls_x509_crt_is_revoked = 0x40002980;
+r_mbedtls_x509_crt_init = 0x40002984;
+r_mbedtls_x509_crt_free = 0x40002988;
+r_mbedtls_x509_crt_restart_init = 0x4000298c;
+r_mbedtls_x509_crt_restart_free = 0x40002990;
+r_mbedtls_x509_get_name = 0x40002994;
+r_mbedtls_x509_get_alg_null = 0x40002998;
+r_mbedtls_x509_get_alg = 0x4000299c;
+r_mbedtls_x509_get_rsassa_pss_params = 0x400029a0;
+r_mbedtls_x509_get_sig = 0x400029a4;
+r_mbedtls_x509_get_sig_alg = 0x400029a8;
+r_mbedtls_x509_get_time = 0x400029ac;
+r_mbedtls_x509_get_serial = 0x400029b0;
+r_mbedtls_x509_get_ext = 0x400029b4;
+mbedtls_aes_xts_init = 0x400029b8;
+mbedtls_aes_xts_free = 0x400029bc;
+mbedtls_aes_xts_setkey_enc = 0x400029c0;
+mbedtls_aes_xts_setkey_dec = 0x400029c4;
+mbedtls_aes_crypt_xts = 0x400029c8;
+mbedtls_aes_crypt_cfb128 = 0x400029cc;
+mbedtls_aes_crypt_ofb = 0x400029d0;
+mbedtls_aes_crypt_ctr = 0x400029d4;
+mbedtls_arc4_init = 0x400029d8;
+mbedtls_arc4_free = 0x400029dc;
+mbedtls_arc4_setup = 0x400029e0;
+mbedtls_arc4_crypt = 0x400029e4;
+mbedtls_ccm_init = 0x400029e8;
+mbedtls_ccm_setkey = 0x400029ec;
+mbedtls_ccm_free = 0x400029f0;
+mbedtls_ccm_encrypt_and_tag = 0x400029f4;
+mbedtls_ccm_auth_decrypt = 0x400029f8;
+mbedtls_dhm_make_params = 0x400029fc;
+mbedtls_dhm_set_group = 0x40002a00;
+mbedtls_dhm_read_public = 0x40002a04;
+mbedtls_ecdh_make_params = 0x40002a08;
+mbedtls_ecdh_read_public = 0x40002a0c;
+mbedtls_entropy_init = 0x40002a10;
+mbedtls_entropy_free = 0x40002a14;
+mbedtls_gcm_init = 0x40002a18;
+mbedtls_gcm_setkey = 0x40002a1c;
+mbedtls_gcm_auth_decrypt = 0x40002a20;
+mbedtls_gcm_free = 0x40002a24;
+mbedtls_md5_init = 0x40002a28;
+mbedtls_md5_free = 0x40002a2c;
+mbedtls_md5_clone = 0x40002a30;
+mbedtls_md5_starts_ret = 0x40002a34;
+mbedtls_md5_update_ret = 0x40002a38;
+mbedtls_md5_finish_ret = 0x40002a3c;
+mbedtls_internal_md5_process = 0x40002a40;
+mbedtls_md5_ret = 0x40002a44;
+mbedtls_pk_get_bitlen = 0x40002a48;
+mbedtls_pk_sign = 0x40002a4c;
+mbedtls_pk_decrypt = 0x40002a50;
+mbedtls_pk_parse_key = 0x40002a54;
+mbedtls_sha1_ret = 0x40002a58;
+mbedtls_ssl_init = 0x40002a5c;
+mbedtls_ssl_setup = 0x40002a60;
+mbedtls_ssl_conf_authmode = 0x40002a64;
+mbedtls_ssl_conf_rng = 0x40002a68;
+mbedtls_ssl_conf_ca_chain = 0x40002a6c;
+mbedtls_ssl_conf_own_cert = 0x40002a70;
+mbedtls_ssl_read = 0x40002a74;
+mbedtls_ssl_write = 0x40002a78;
+mbedtls_ssl_config_init = 0x40002a7c;
+mbedtls_ssl_sig_hash_set_find = 0x40002a80;
+mbedtls_ssl_sig_hash_set_add = 0x40002a84;
+mbedtls_ssl_sig_hash_set_const_hash = 0x40002a88;
+mbedtls_ssl_sig_from_pk_alg = 0x40002a8c;
+mbedtls_ssl_set_calc_verify_md = 0x40002a90;
+mbedtls_x509_crt_parse = 0x40002a94;
+/* Data (.data, .bss, .rodata) */
+p_osi_mbedtls_rom_funcs = 0x3fcdfafc;
+mbedtls_x509_crt_profile_default = 0x3ff4fbc8;
+mbedtls_x509_crt_profile_suiteb = 0x3ff4fbb8;
+aes_FSb_ptr = 0x3fcdfaf8;
+AES_RT0_ptr = 0x3fcdfaf4;
+AES_RT1_ptr = 0x3fcdfaf0;
+AES_RT2_ptr = 0x3fcdfaec;
+AES_RT3_ptr = 0x3fcdfae8;
+AES_FT0_ptr = 0x3fcdfae4;
+AES_FT1_ptr = 0x3fcdfae0;
+AES_FT2_ptr = 0x3fcdfadc;
+AES_FT3_ptr = 0x3fcdfad8;
+bignum_small_prime_ptr = 0x3fcdfad4;
+sha512_K_ptr = 0x3fcdfad0;
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.newlib-nano.ld b/components/esp_rom/esp8684/ld/esp8684.rom.newlib-nano.ld
new file mode 100644
index 0000000000000000000000000000000000000000..c5f82e1eb04c9dcb280cbcc153b9fe46ad01cf89
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.newlib-nano.ld
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM function interface esp8684.rom.newlib-nano.ld for esp8684
+ *
+ *
+ * Generated from ./interface-esp8684.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib_nano_format
+ ***************************************/
+
+/* Functions */
+__sprint_r = 0x40000670;
+_fiprintf_r = 0x40000674;
+_fprintf_r = 0x40000678;
+_printf_common = 0x4000067c;
+_printf_i = 0x40000680;
+_vfiprintf_r = 0x40000684;
+_vfprintf_r = 0x40000688;
+fiprintf = 0x4000068c;
+fprintf = 0x40000690;
+printf = 0x40000694;
+vfiprintf = 0x40000698;
+vfprintf = 0x4000069c;
+asprintf = 0x400006a0;
+sprintf = 0x400006a4;
+snprintf = 0x400006a8;
+siprintf = 0x400006ac;
+sniprintf = 0x400006b0;
+vprintf = 0x400006b4;
+viprintf = 0x400006b8;
+vsnprintf = 0x400006bc;
+vsniprintf = 0x400006c0;
+__rom_printf_float = 0x400006c4;
+__rom_scanf_float = 0x400006c8;
+_scanf_i = 0x400006cc;
+_scanf_chars = 0x400006d0;
+sscanf = 0x400006d4;
+siscanf = 0x400006d8;
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.newlib.ld b/components/esp_rom/esp8684/ld/esp8684.rom.newlib.ld
new file mode 100644
index 0000000000000000000000000000000000000000..0d10b6b1877b2f19e9c1495dd2c2b4683299e0c8
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.newlib.ld
@@ -0,0 +1,147 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp8684.rom.newlib.ld for esp8684
+ *
+ *
+ * Generated from ./interface-esp8684.yml md5sum 6c4d0f3a9f2d0c93477024a1a8f13746
+ *
+ * Compatible with ROM where ECO version equal or greater to 0.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib
+ ***************************************/
+
+/* Functions */
+esp_rom_newlib_init_common_mutexes = 0x40000480;
+memset = 0x40000484;
+memcpy = 0x40000488;
+memmove = 0x4000048c;
+memcmp = 0x40000490;
+strcpy = 0x40000494;
+strncpy = 0x40000498;
+strcmp = 0x4000049c;
+strncmp = 0x400004a0;
+strlen = 0x400004a4;
+strstr = 0x400004a8;
+bzero = 0x400004ac;
+_isatty_r = 0x400004b0;
+sbrk = 0x400004b4;
+isalnum = 0x400004b8;
+isalpha = 0x400004bc;
+isascii = 0x400004c0;
+isblank = 0x400004c4;
+iscntrl = 0x400004c8;
+isdigit = 0x400004cc;
+islower = 0x400004d0;
+isgraph = 0x400004d4;
+isprint = 0x400004d8;
+ispunct = 0x400004dc;
+isspace = 0x400004e0;
+isupper = 0x400004e4;
+toupper = 0x400004e8;
+tolower = 0x400004ec;
+toascii = 0x400004f0;
+memccpy = 0x400004f4;
+memchr = 0x400004f8;
+memrchr = 0x400004fc;
+strcasecmp = 0x40000500;
+strcasestr = 0x40000504;
+strcat = 0x40000508;
+strdup = 0x4000050c;
+strchr = 0x40000510;
+strcspn = 0x40000514;
+strcoll = 0x40000518;
+strlcat = 0x4000051c;
+strlcpy = 0x40000520;
+strlwr = 0x40000524;
+strncasecmp = 0x40000528;
+strncat = 0x4000052c;
+strndup = 0x40000530;
+strnlen = 0x40000534;
+strrchr = 0x40000538;
+strsep = 0x4000053c;
+strspn = 0x40000540;
+strtok_r = 0x40000544;
+strupr = 0x40000548;
+longjmp = 0x4000054c;
+setjmp = 0x40000550;
+abs = 0x40000554;
+div = 0x40000558;
+labs = 0x4000055c;
+ldiv = 0x40000560;
+qsort = 0x40000564;
+rand_r = 0x40000568;
+rand = 0x4000056c;
+srand = 0x40000570;
+utoa = 0x40000574;
+itoa = 0x40000578;
+atoi = 0x4000057c;
+atol = 0x40000580;
+strtol = 0x40000584;
+strtoul = 0x40000588;
+fflush = 0x4000058c;
+_fflush_r = 0x40000590;
+_fwalk = 0x40000594;
+_fwalk_reent = 0x40000598;
+__smakebuf_r = 0x4000059c;
+__swhatbuf_r = 0x400005a0;
+__swbuf_r = 0x400005a4;
+__swbuf = 0x400005a8;
+__swsetup_r = 0x400005ac;
+_strtod_l = 0x400005b0;
+_strtod_r = 0x400005b4;
+strtod_l = 0x400005b8;
+strtod = 0x400005bc;
+strtof_l = 0x400005c0;
+strtof = 0x400005c4;
+_strtol_r = 0x400005c8;
+strtol_l = 0x400005cc;
+_strtoul_r = 0x400005d0;
+strtoul_l = 0x400005d4;
+__match = 0x400005d8;
+__hexnan = 0x400005dc;
+__hexdig_fun = 0x400005e0;
+__gethex = 0x400005e4;
+_Balloc = 0x400005e8;
+_Bfree = 0x400005ec;
+__multadd = 0x400005f0;
+__s2b = 0x400005f4;
+__hi0bits = 0x400005f8;
+__lo0bits = 0x400005fc;
+__i2b = 0x40000600;
+__multiply = 0x40000604;
+__pow5mult = 0x40000608;
+__lshift = 0x4000060c;
+__mcmp = 0x40000610;
+__mdiff = 0x40000614;
+__ulp = 0x40000618;
+__b2d = 0x4000061c;
+__d2b = 0x40000620;
+__ratio = 0x40000624;
+_mprec_log10 = 0x40000628;
+__copybits = 0x4000062c;
+__any_on = 0x40000630;
+asctime = 0x40000634;
+asctime_r = 0x40000638;
+atof = 0x4000063c;
+atoff = 0x40000640;
+_dtoa_r = 0x40000644;
+_wctomb_r = 0x40000648;
+__ascii_wctomb = 0x4000064c;
+_mbtowc_r = 0x40000650;
+__ascii_mbtowc = 0x40000654;
+puts = 0x40000658;
+putc = 0x4000065c;
+putchar = 0x40000660;
+nan = 0x40000664;
+nanf = 0x40000668;
+__errno = 0x4000066c;
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x3fcdffd8;
+_global_impure_ptr = 0x3fcdffd4;
diff --git a/components/esp_rom/esp8684/ld/esp8684.rom.version.ld b/components/esp_rom/esp8684/ld/esp8684.rom.version.ld
new file mode 100644
index 0000000000000000000000000000000000000000..eca45cf2547c9bd8b88514bde228e98e9cbf276d
--- /dev/null
+++ b/components/esp_rom/esp8684/ld/esp8684.rom.version.ld
@@ -0,0 +1,14 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM version variables for esp8684
+ *
+ * These addresses should be compatible with any ROM version for this chip.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+_rom_chip_id = 0x40000010;
+_rom_eco_version = 0x40000014;
diff --git a/components/esp_rom/include/esp8684/rom/apb_backup_dma.h b/components/esp_rom/include/esp8684/rom/apb_backup_dma.h
new file mode 100644
index 0000000000000000000000000000000000000000..8a2c05e266f879ea3051f0798ae6faf029399b7c
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/apb_backup_dma.h
@@ -0,0 +1,17 @@
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void ets_apb_backup_init_lock_func(void(* _apb_backup_lock)(void), void(* _apb_backup_unlock)(void));
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_rom/include/esp8684/rom/cache.h b/components/esp_rom/include/esp8684/rom/cache.h
new file mode 100644
index 0000000000000000000000000000000000000000..40740ab792a8c976a2bb7f2fee389531498a9396
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/cache.h
@@ -0,0 +1,812 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_CACHE_H_
+#define _ROM_CACHE_H_
+
+#include <stdint.h>
+#include "esp_bit_defs.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup cache_apis, cache operation related apis
+  * @brief cache apis
+  */
+
+/** @addtogroup cache_apis
+  * @{
+  */
+#define MIN_ICACHE_SIZE                 16384
+#define MAX_ICACHE_SIZE                 16384
+#define MIN_ICACHE_WAYS                 8
+#define MAX_ICACHE_WAYS                 8
+#define MAX_CACHE_WAYS                  8
+#define MIN_CACHE_LINE_SIZE             32
+#define TAG_SIZE                        4
+#define MIN_ICACHE_BANK_NUM             1
+#define MAX_ICACHE_BANK_NUM             1
+#define CACHE_MEMORY_BANK_NUM           1
+#define CACHE_MEMORY_IBANK_SIZE         0x4000
+
+#define MAX_ITAG_BANK_ITEMS             (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE)
+#define MAX_ITAG_BLOCK_ITEMS            (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE)
+#define MAX_ITAG_BANK_SIZE              (MAX_ITAG_BANK_ITEMS * TAG_SIZE)
+#define MAX_ITAG_BLOCK_SIZE             (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE)
+
+typedef enum {
+    CACHE_DCACHE = 0,
+    CACHE_ICACHE0 = 1,
+    CACHE_ICACHE1 = 2,
+} cache_t;
+
+typedef enum {
+    CACHE_MEMORY_INVALID = 0,
+    CACHE_MEMORY_IBANK0 = BIT(0),
+    CACHE_MEMORY_IBANK1 = BIT(1),
+    CACHE_MEMORY_IBANK2 = BIT(2),
+    CACHE_MEMORY_IBANK3 = BIT(3),
+    CACHE_MEMORY_DBANK0 = BIT(0),
+    CACHE_MEMORY_DBANK1 = BIT(1),
+    CACHE_MEMORY_DBANK2 = BIT(2),
+    CACHE_MEMORY_DBANK3 = BIT(3),
+} cache_array_t;
+
+#define ICACHE_SIZE_16KB  CACHE_SIZE_HALF
+#define ICACHE_SIZE_32KB  CACHE_SIZE_FULL
+#define DCACHE_SIZE_32KB  CACHE_SIZE_HALF
+#define DCACHE_SIZE_64KB  CACHE_SIZE_FULL
+
+typedef enum {
+    CACHE_SIZE_HALF = 0,                /*!< 8KB for icache and dcache */
+    CACHE_SIZE_FULL = 1,                /*!< 16KB for icache and dcache */
+} cache_size_t;
+
+typedef enum {
+    CACHE_4WAYS_ASSOC = 0,              /*!< 4 way associated cache */
+    CACHE_8WAYS_ASSOC = 1,              /*!< 8 way associated cache */
+} cache_ways_t;
+
+typedef enum {
+    CACHE_LINE_SIZE_16B = 0,            /*!< 16 Byte cache line size */
+    CACHE_LINE_SIZE_32B = 1,            /*!< 32 Byte cache line size */
+    CACHE_LINE_SIZE_64B = 2,            /*!< 64 Byte cache line size */
+} cache_line_size_t;
+
+typedef enum {
+    CACHE_AUTOLOAD_POSITIVE = 0,        /*!< cache autoload step is positive */
+    CACHE_AUTOLOAD_NEGATIVE = 1,        /*!< cache autoload step is negative */
+} cache_autoload_order_t;
+
+#define CACHE_AUTOLOAD_STEP(i) ((i) - 1)
+
+typedef enum {
+    CACHE_AUTOLOAD_MISS_TRIGGER = 0,    /*!< autoload only triggered by cache miss */
+    CACHE_AUTOLOAD_HIT_TRIGGER  = 1,    /*!< autoload only triggered by cache hit */
+    CACHE_AUTOLOAD_BOTH_TRIGGER = 2,    /*!< autoload triggered both by cache miss and hit */
+} cache_autoload_trigger_t;
+
+typedef enum {
+    CACHE_FREEZE_ACK_BUSY = 0,          /*!< in this mode, cache ack busy to CPU if a cache miss happens*/
+    CACHE_FREEZE_ACK_ERROR  = 1,        /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */
+} cache_freeze_mode_t;
+
+typedef enum {
+    CACHE_PAGE_16KB = 0,
+    CACHE_PAGE_32KB,
+    CACHE_PAGE_64KB,
+} mmu_page_mode_t;
+
+struct cache_mode {
+    uint32_t cache_size;                /*!< cache size in byte */
+    uint16_t cache_line_size;           /*!< cache line size in byte */
+    uint8_t cache_ways;                 /*!< cache ways, always 4 */
+    uint8_t ibus;                     /*!< the cache index, 0 for dcache, 1 for icache */
+};
+
+struct icache_tag_item {
+    uint32_t valid:1;                   /*!< the tag item is valid or not */
+    uint32_t lock:1;                    /*!< the cache line is locked or not */
+    uint32_t fifo_cnt:3;                /*!< fifo cnt, 0 ~ 3 for 4 ways cache */
+    uint32_t tag:13;                    /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */
+    uint32_t reserved:14;
+};
+
+struct autoload_config {
+    uint8_t order;                      /*!< autoload step is positive or negative */
+    uint8_t trigger;                    /*!< autoload trigger */
+    uint8_t ena0;                       /*!< autoload region0 enable */
+    uint8_t ena1;                       /*!< autoload region1 enable */
+    uint32_t addr0;                     /*!< autoload region0 start address */
+    uint32_t size0;                     /*!< autoload region0 size */
+    uint32_t addr1;                     /*!< autoload region1 start address */
+    uint32_t size1;                     /*!< autoload region1 size */
+};
+
+struct tag_group_info {
+    struct cache_mode mode;                         /*!< cache and cache mode */
+    uint32_t filter_addr;                           /*!< the address that used to generate the struct */
+    uint32_t vaddr_offset;                          /*!< virtual address offset of the cache ways */
+    uint32_t tag_addr[MAX_CACHE_WAYS];              /*!< tag memory address, only [0~mode.ways-1] is valid to use */
+    uint32_t cache_memory_offset[MAX_CACHE_WAYS];   /*!< cache memory address, only [0~mode.ways-1] is valid to use */
+};
+
+struct lock_config {
+    uint32_t addr;                                  /*!< manual lock address*/
+    uint16_t size;                                  /*!< manual lock size*/
+    uint16_t group;                                 /*!< manual lock group, 0 or 1*/
+};
+
+struct cache_internal_stub_table {
+    uint32_t (* icache_line_size)(void);
+    uint32_t (* icache_addr)(uint32_t addr);
+    uint32_t (* dcache_addr)(uint32_t addr);
+    void (* invalidate_icache_items)(uint32_t addr, uint32_t items);
+    void (* lock_icache_items)(uint32_t addr, uint32_t items);
+    void (* unlock_icache_items)(uint32_t addr, uint32_t items);
+    uint32_t (* suspend_icache_autoload)(void);
+    void (* resume_icache_autoload)(uint32_t autoload);
+    void (* freeze_icache_enable)(cache_freeze_mode_t mode);
+    void (* freeze_icache_disable)(void);
+    int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t));
+};
+
+/* Defined in the interface file, default value is rom_default_cache_internal_table */
+extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr;
+
+typedef void (* cache_op_start)(void);
+typedef void (* cache_op_end)(void);
+
+typedef struct {
+    cache_op_start start;
+    cache_op_end end;
+} cache_op_cb_t;
+
+/* Defined in the interface file, default value is NULL */
+extern const cache_op_cb_t* rom_cache_op_cb;
+
+#define ESP_ROM_ERR_INVALID_ARG         1
+#define MMU_SET_ADDR_ALIGNED_ERROR      2
+#define MMU_SET_PASE_SIZE_ERROR         3
+#define MMU_SET_VADDR_OUT_RANGE         4
+
+#define CACHE_OP_ICACHE_Y               1
+#define CACHE_OP_ICACHE_N               0
+
+/**
+  * @brief Initialise cache mmu, mark all entries as invalid.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_MMU_Init(void);
+
+/**
+  * @brief Set ICache mmu mapping.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
+  *                 esp32c3, external memory is always flash
+  *
+  * @param  uint32_t vaddr : virtual address in CPU address space.
+  *                              Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t paddr : physical address in external memory.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t psize : page size of ICache, in kilobytes. Should be 64 here.
+  *
+  * @param  uint32_t num : pages to be set.
+  *
+  * @param  uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
+  *
+  * @return uint32_t: error status
+  *                   0 : mmu set success
+  *                   2 : vaddr or paddr is not aligned
+  *                   3 : psize error
+  *                   4 : vaddr is out of range
+  */
+int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr,  uint32_t psize, uint32_t num, uint32_t fixed);
+
+/**
+  * @brief Set DCache mmu mapping.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In
+  *                 esp32c3, external memory is always flash
+  *
+  * @param  uint32_t vaddr : virtual address in CPU address space.
+  *                              Can be DRam0, DRam1, DRom0, DPort and AHB buses address.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t paddr : physical address in external memory.
+  *                              Should be aligned by psize.
+  *
+  * @param  uint32_t psize : page size of DCache, in kilobytes. Should be 64 here.
+  *
+  * @param  uint32_t num : pages to be set.
+
+  * @param  uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
+  *
+  * @return uint32_t: error status
+  *                   0 : mmu set success
+  *                   2 : vaddr or paddr is not aligned
+  *                   3 : psize error
+  *                   4 : vaddr is out of range
+  */
+int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed);
+
+/**
+  * @brief Count the pages in the bus room address which map to Flash.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t bus : the bus to count with.
+  *
+  * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count.
+  *
+  * return uint32_t : the number of pages which map to Flash.
+  */
+uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped);
+
+/**
+  * @brief allocate memory to used by ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0
+  *
+  * return none
+  */
+void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low);
+
+/**
+  * @brief Get cache mode of ICache or DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field
+  *
+  * return none
+  */
+void Cache_Get_Mode(struct cache_mode * mode);
+
+/**
+  * @brief set ICache modes: cache size, associate ways and cache line size.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL
+  *
+  * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC
+  *
+  * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B
+  *
+  * return none
+  */
+void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size);
+
+/**
+  * @brief set DCache modes: cache size, associate ways and cache line size.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB
+  *
+  * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC
+  *
+  * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B
+  *
+  * return none
+  */
+void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size);
+
+/**
+  * @brief check if the address is accessed through ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr : the address to check.
+  *
+  * @return 1 if the address is accessed through ICache, 0 if not.
+  */
+uint32_t Cache_Address_Through_ICache(uint32_t addr);
+
+/**
+  * @brief check if the address is accessed through DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr : the address to check.
+  *
+  * @return 1 if the address is accessed through DCache, 0 if not.
+  */
+uint32_t Cache_Address_Through_DCache(uint32_t addr);
+
+/**
+  * @brief Init mmu owner register to make i/d cache use half mmu entries.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void Cache_Owner_Init(void);
+
+/**
+  * @brief Invalidate the cache items for ICache.
+  *        Operation will be done CACHE_LINE_SIZE aligned.
+  *        If the region is not in ICache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr: start address to invalidate
+  *
+  * @param  uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
+  *
+  * @return None
+  */
+void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items);
+
+/**
+  * @brief Invalidate the Cache items in the region from ICache or DCache.
+  *        If the region is not in Cache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr : invalidated region start address.
+  *
+  * @param  uint32_t size : invalidated region size.
+  *
+  * @return 0 for success
+  *         1 for invalid argument
+  */
+int Cache_Invalidate_Addr(uint32_t addr, uint32_t size);
+
+/**
+  * @brief Invalidate all cache items in ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_Invalidate_ICache_All(void);
+
+/**
+  * @brief Mask all buses through ICache and DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_Mask_All(void);
+
+/**
+  * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return uint32_t : 0 for ICache not auto preload before suspend.
+  */
+uint32_t Cache_Suspend_ICache_Autoload(void);
+
+/**
+  * @brief Resume ICache auto preload operation after some ICache operations.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t autoload : 0 for ICache not auto preload before suspend.
+  *
+  * @return None.
+  */
+void Cache_Resume_ICache_Autoload(uint32_t autoload);
+
+/**
+  * @brief Start an ICache manual preload, will suspend auto preload of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t addr : start address of the preload region.
+  *
+  * @param uint32_t size : size of the preload region, should not exceed the size of ICache.
+  *
+  * @param uint32_t order : the preload order, 0 for positive, other for negative
+  *
+  * @return uint32_t : 0 for ICache not auto preload before manual preload.
+  */
+uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order);
+
+/**
+  * @brief Return if the ICache manual preload done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return uint32_t : 0 for ICache manual preload not done.
+  */
+uint32_t Cache_ICache_Preload_Done(void);
+
+/**
+  * @brief End the ICache manual preload to resume auto preload of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t autoload : 0 for ICache not auto preload before manual preload.
+  *
+  * @return None
+  */
+void Cache_End_ICache_Preload(uint32_t autoload);
+
+/**
+  * @brief Config autoload parameters of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param struct autoload_config * config : autoload parameters.
+  *
+  * @return None
+  */
+void Cache_Config_ICache_Autoload(const struct autoload_config * config);
+
+/**
+  * @brief Enable auto preload for ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void Cache_Enable_ICache_Autoload(void);
+
+/**
+  * @brief Disable auto preload for ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void Cache_Disable_ICache_Autoload(void);
+
+/**
+  * @brief Config a group of prelock parameters of ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param struct lock_config * config : a group of lock parameters.
+  *
+  * @return None
+  */
+
+void Cache_Enable_ICache_PreLock(const struct lock_config *config);
+
+/**
+  * @brief Disable a group of prelock parameters for ICache.
+  *        However, the locked data will not be released.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint16_t group : 0 for group0, 1 for group1.
+  *
+  * @return None
+  */
+void Cache_Disable_ICache_PreLock(uint16_t group);
+
+/**
+  * @brief Lock the cache items for ICache.
+  *        Operation will be done CACHE_LINE_SIZE aligned.
+  *        If the region is not in ICache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr: start address to lock
+  *
+  * @param  uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
+  *
+  * @return None
+  */
+void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items);
+
+/**
+  * @brief Unlock the cache items for ICache.
+  *        Operation will be done CACHE_LINE_SIZE aligned.
+  *        If the region is not in ICache addr room, nothing will be done.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t addr: start address to unlock
+  *
+  * @param  uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB)
+  *
+  * @return None
+  */
+void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items);
+
+/**
+  * @brief Lock the cache items in tag memory for ICache or DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t addr : start address of lock region.
+  *
+  * @param uint32_t size : size of lock region.
+  *
+  * @return 0 for success
+  *         1 for invalid argument
+  */
+int Cache_Lock_Addr(uint32_t addr, uint32_t size);
+
+/**
+  * @brief Unlock the cache items in tag memory for ICache or DCache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param uint32_t addr : start address of unlock region.
+  *
+  * @param uint32_t size : size of unlock region.
+  *
+  * @return 0 for success
+  *         1 for invalid argument
+  */
+int Cache_Unlock_Addr(uint32_t addr, uint32_t size);
+
+/**
+  * @brief Disable ICache access for the cpu.
+  *        This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle.
+  *        Please do not call this function in your SDK application.
+  *
+  * @return uint32_t : auto preload enabled before
+  */
+uint32_t Cache_Disable_ICache(void);
+
+/**
+  * @brief Enable ICache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t autoload : ICache will preload then.
+  *
+  * @return None
+  */
+void Cache_Enable_ICache(uint32_t autoload);
+
+/**
+  * @brief Suspend ICache access for the cpu.
+  *        The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle.
+  *        Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case).
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  None
+  *
+  * @return uint32_t : auto preload enabled before
+  */
+uint32_t Cache_Suspend_ICache(void);
+
+/**
+  * @brief Resume ICache access for the cpu.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t autoload : ICache will preload then.
+  *
+  * @return None
+  */
+void Cache_Resume_ICache(uint32_t autoload);
+
+/**
+  * @brief Get ICache cache line size
+  *
+  * @param  None
+  *
+  * @return uint32_t: 16, 32, 64 Byte
+  */
+uint32_t Cache_Get_ICache_Line_Size(void);
+
+/**
+  * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void Cache_Set_Default_Mode(void);
+
+/**
+  * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void Cache_Enable_Defalut_ICache_Mode(void);
+
+/**
+  * @brief Set mmu page mode.
+  *
+  * @param mmu_page_mode_t
+  *
+  * @return None
+  */
+void MMU_Set_Page_Mode(mmu_page_mode_t pg_mode);
+
+/**
+  * @brief Get mmu page mode.
+  *
+  * @param None
+  *
+  * @return page mode
+  */
+mmu_page_mode_t MMU_Get_Page_Mode(void);
+
+/**
+  * @brief Enable freeze for ICache.
+  *        Any miss request will be rejected, including cpu miss and preload/autoload miss.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit
+  *
+  * @return None
+  */
+void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode);
+
+/**
+  * @brief Disable freeze for ICache.
+  *        Please do not call this function in your SDK application.
+  *
+  * @return None
+  */
+void Cache_Freeze_ICache_Disable(void);
+
+/**
+  * @brief Travel tag memory to run a call back function.
+  *        ICache and DCache are suspend when doing this.
+  *        The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  struct cache_mode * mode : the cache to check and the cache mode.
+  *
+  * @param  uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function.
+  *                                0 for do not filter, all cache lines will be returned.
+  *
+  * @param  void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time.
+  *
+  * @return None
+  */
+void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *));
+
+/**
+  * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
+  *
+  * @param  uint32_t tag : the tag part fo a tag item, 12-14 bits.
+  *
+  * @param  uint32_t addr_offset : the virtual address offset of the cache ways.
+  *
+  * @return uint32_t : the virtual address.
+  */
+uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset);
+
+/**
+  * @brief Get cache memory block base address.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t icache : 0 for dcache, other for icache.
+  *
+  * @param  uint32_t bank_no : 0 ~ 3 bank.
+  *
+  * @return uint32_t : the cache memory block base address, 0 if the block not used.
+  */
+uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no);
+
+/**
+  * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  struct cache_mode * mode : the cache to calculate the virtual address and the cache mode.
+  *
+  * @param  uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line.
+  *
+  * @param  uint32_t addr_offset : the virtual address offset of the cache ways.
+  *
+  * @return uint32_t : the virtual address.
+  */
+uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset);
+
+/**
+  * @brief Get the cache memory value by DRAM address.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address.
+  *
+  * @return uint32_t : the word value of the address.
+  */
+uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr);
+/**
+  * @}
+  */
+
+/**
+  * @brief Get the cache MMU IROM end address.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  void
+  *
+  * @return uint32_t : the word value of the address.
+  */
+uint32_t Cache_Get_IROM_MMU_End(void);
+
+/**
+  * @brief Get the cache MMU DROM end address.
+  *        Please do not call this function in your SDK application.
+  *
+  * @param  void
+  *
+  * @return uint32_t : the word value of the address.
+  */
+uint32_t Cache_Get_DROM_MMU_End(void);
+
+/**
+  * @brief  Lock the permission control section configuration. After lock, any
+  *         configuration modification will be bypass. Digital reset will clear the lock!
+  *         Please do not call this function in your SDK application.
+  *
+  * @param  int ibus : 1 for lock ibus pms, 0 for lock dbus pms
+  *
+  * @return None
+  */
+void Cache_Pms_Lock(int ibus);
+
+/**
+  * @brief  Set three ibus pms boundary address, which will determine pms reject section and section 1/2.
+  *         Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t ibus_boundary0_addr : vaddress for split line0
+  *
+  * @param  uint32_t ibus_boundary1_addr : vaddress for split line1
+  *
+  * @param  uint32_t ibus_boundary2_addr : vaddress for split line2
+  *
+  * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
+  */
+int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr);
+
+/**
+  * @brief  Set three ibus pms attribute, which will determine pms in different section and world.
+  *         Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t ibus_pms_sct2_attr : attr for section2
+  *
+  * @param  uint32_t ibus_pms_sct1_attr : attr for section1
+  *
+  * @return None
+  */
+void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr);
+
+/**
+  * @brief  Set three dbus pms boundary address, which will determine pms reject section and section 1/2.
+  *         Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t dbus_boundary0_addr : vaddress for split line0
+  *
+  * @param  uint32_t dbus_boundary1_addr : vaddress for split line1
+  *
+  * @param  uint32_t dbus_boundary2_addr : vaddress for split line2
+  *
+  * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success
+  */
+int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr);
+
+/**
+  * @brief  Set three dbus pms attribute, which will determine pms in different section and world.
+  *         Please do not call this function in your SDK application.
+  *
+  * @param  uint32_t dbus_pms_sct2_attr : attr for section2
+  *
+  * @param  uint32_t dbus_pms_sct1_attr : attr for section1
+  *
+  * @return None
+  */
+void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr);
+
+/**
+  * @brief Used by SPI flash mmap
+  *
+  */
+uint32_t flash_instr_rodata_start_page(uint32_t bus);
+uint32_t flash_instr_rodata_end_page(uint32_t bus);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_CACHE_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/crc.h b/components/esp_rom/include/esp8684/rom/crc.h
new file mode 100644
index 0000000000000000000000000000000000000000..11a4a327b60ea06c84368ed2eab12a43ef38974d
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/crc.h
@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ROM_CRC_H
+#define ROM_CRC_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup crc_apis, uart configuration and communication related apis
+  * @brief crc apis
+  */
+
+/** @addtogroup crc_apis
+  * @{
+  */
+
+
+/* Standard CRC8/16/32 algorithms. */
+// CRC-8        x8+x2+x1+1              0x07
+// CRC16-CCITT  x16+x12+x5+1   1021   ISO HDLC, ITU X.25, V.34/V.41/V.42, PPP-FCS
+// CRC32:
+//G(x) = x32 +x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x1 + 1
+//If your buf is not continuous, you can use the first result to be the second parameter.
+
+/**
+  * @brief Crc32 value that is in little endian.
+  *
+  * @param  uint32_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint32_t crc32_le(uint32_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc32 value that is in big endian.
+  *
+  * @param  uint32_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint32_t crc32_be(uint32_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc16 value that is in little endian.
+  *
+  * @param  uint16_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint16_t crc16_le(uint16_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc16 value that is in big endian.
+  *
+  * @param  uint16_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint16_t crc16_be(uint16_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc8 value that is in little endian.
+  *
+  * @param  uint8_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint8_t crc8_le(uint8_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @brief Crc8 value that is in big endian.
+  *
+  * @param  uint32_t crc : init crc value, use 0 at the first use.
+  *
+  * @param  uint8_t const *buf : buffer to start calculate crc.
+  *
+  * @param  uint32_t len : buffer length in byte.
+  *
+  * @return None
+  */
+uint8_t crc8_be(uint8_t crc, uint8_t const *buf, uint32_t len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif
diff --git a/components/esp_rom/include/esp8684/rom/efuse.h b/components/esp_rom/include/esp8684/rom/efuse.h
new file mode 100644
index 0000000000000000000000000000000000000000..9f776b4980d31bec25bbe5fd0c823fc2a727bdf7
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/efuse.h
@@ -0,0 +1,372 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_EFUSE_H_
+#define _ROM_EFUSE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+/** \defgroup efuse_APIs efuse APIs
+  * @brief     ESP32 efuse read/write APIs
+  * @attention
+  *
+  */
+
+/** For ESP8684, there's no key purpose region for efuse keys, In order to maintain
+  * compatibility with the previous apis, we should set the parameter of 'ets_efuse_purpose_t'
+  * as default value ETS_EFUSE_KEY_PURPOSE_INVALID.
+  * (In fact, this parameter can be any value, the api in the rom will not process key_purpose region)
+  */
+typedef enum {
+    ETS_EFUSE_KEY_PURPOSE_INVALID = -1,
+} ets_efuse_purpose_t;
+
+typedef enum {
+    ETS_EFUSE_BLOCK0 = 0,
+    ETS_EFUSE_MAC_SPI_SYS_0 = 1,
+    ETS_EFUSE_BLOCK_SYS_DATA = 2,
+    ETS_EFUSE_BLOCK_USR_DATA = 3,
+    ETS_EFUSE_BLOCK_KEY0 = 4,
+    ETS_EFUSE_BLOCK_KEY1 = 5,
+    ETS_EFUSE_BLOCK_KEY2 = 6,
+    ETS_EFUSE_BLOCK_KEY3 = 7,
+    ETS_EFUSE_BLOCK_MAX,
+} ets_efuse_block_t;
+
+/**
+ * @brief set timing accroding the apb clock, so no read error or write error happens.
+ *
+ * @param clock: apb clock in HZ, only accept 5M(in FPGA), 10M(in FPGA), 20M, 40M, 80M.
+ *
+ * @return : 0 if success, others if clock not accepted
+ */
+int ets_efuse_set_timing(uint32_t clock);
+
+/**
+ * @brief Enable efuse subsystem. Called after reset. Doesn't need to be called again.
+ */
+void ets_efuse_start(void);
+
+/**
+  * @brief  Efuse read operation: copies data from physical efuses to efuse read registers.
+  *
+  * @param  null
+  *
+  * @return : 0 if success, others if apb clock is not accepted
+  */
+int ets_efuse_read(void);
+
+/**
+  * @brief  Efuse write operation: Copies data from efuse write registers to efuse. Operates on a single block of efuses at a time.
+  *
+  * @note This function does not update read efuses, call ets_efuse_read() once all programming is complete.
+  *
+  * @return : 0 if success, others if apb clock is not accepted
+  */
+int ets_efuse_program(ets_efuse_block_t block);
+
+/**
+ * @brief Set all Efuse program registers to zero.
+ *
+ * Call this before writing new data to the program registers.
+ */
+void ets_efuse_clear_program_registers(void);
+
+/**
+ * @brief Program a block of key data to an efuse block
+ *
+ * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6. Key block must be unused (@ref ets_efuse_key_block_unused).
+ * @param purpose Purpose to set for this key. Purpose must be already unset.
+ * @param data Pointer to data to write.
+ * @param data_len Length of data to write.
+ *
+ * @note This function also calls ets_efuse_program() for the specified block, and for block 0 (setting the purpose)
+ */
+int ets_efuse_write_key(ets_efuse_block_t key_block, ets_efuse_purpose_t purpose, const void *data, size_t data_len);
+
+
+/* @brief Return the address of a particular efuse block's first read register
+ *
+ * @param block Index of efuse block to look up
+ *
+ * @return 0 if block is invalid, otherwise a numeric read register address
+ * of the first word in the block.
+ */
+uint32_t ets_efuse_get_read_register_address(ets_efuse_block_t block);
+
+/**
+ * @brief Return the current purpose set for an efuse key block
+ *
+ * @param key_block Block to read purpose for. Must be in range ETS_EFUSE_BLOCK_KEY0 to ETS_EFUSE_BLOCK_KEY6.
+ */
+ets_efuse_purpose_t ets_efuse_get_key_purpose(ets_efuse_block_t key_block);
+
+/**
+ * @brief Find a key block with the particular purpose set
+ *
+ * @param purpose Purpose to search for.
+ * @param[out] key_block Pointer which will be set to the key block if found. Can be NULL, if only need to test the key block exists.
+ * @return true if found, false if not found. If false, value at key_block pointer is unchanged.
+ */
+bool ets_efuse_find_purpose(ets_efuse_purpose_t purpose, ets_efuse_block_t *key_block);
+
+/**
+ * Return true if the key block is unused, false otherwise.
+ *
+ * An unused key block is all zero content, not read or write protected,
+ * and has purpose 0 (ETS_EFUSE_KEY_PURPOSE_USER)
+ *
+ * @param key_block key block to check.
+ *
+ * @return true if key block is unused, false if key block or used
+ * or the specified block index is not a key block.
+ */
+bool ets_efuse_key_block_unused(ets_efuse_block_t key_block);
+
+
+/**
+ * @brief Search for an unused key block and return the first one found.
+ *
+ * See @ref ets_efuse_key_block_unused for a description of an unused key block.
+ *
+ * @return First unused key block, or ETS_EFUSE_BLOCK_MAX if no unused key block is found.
+ */
+ets_efuse_block_t ets_efuse_find_unused_key_block(void);
+
+/**
+ * @brief Return the number of unused efuse key blocks (0-6)
+ */
+unsigned ets_efuse_count_unused_key_blocks(void);
+
+/**
+ * @brief Calculate Reed-Solomon Encoding values for a block of efuse data.
+ *
+ * @param data Pointer to data buffer (length 32 bytes)
+ * @param rs_values Pointer to write encoded data to (length 12 bytes)
+ */
+void ets_efuse_rs_calculate(const void *data, void *rs_values);
+
+/**
+  * @brief  Read spi flash pads configuration from Efuse
+  *
+  * @return
+  * - 0 for default SPI pins.
+  * - 1 for default HSPI pins.
+  * - Other values define a custom pin configuration mask. Pins are encoded as per the EFUSE_SPICONFIG_RET_SPICLK,
+  *   EFUSE_SPICONFIG_RET_SPIQ, EFUSE_SPICONFIG_RET_SPID, EFUSE_SPICONFIG_RET_SPICS0, EFUSE_SPICONFIG_RET_SPIHD macros.
+  *   WP pin (for quad I/O modes) is not saved in efuse and not returned by this function.
+  */
+uint32_t ets_efuse_get_spiconfig(void);
+
+/**
+  * @brief  Read spi flash wp pad from Efuse
+  *
+  * @return
+  * - 0x3f for invalid.
+  * - 0~46 is valid.
+  */
+uint32_t ets_efuse_get_wp_pad(void);
+
+/**
+ * @brief Read opi flash pads configuration from Efuse
+ *
+ * @return
+ * - 0 for default SPI pins.
+ * - Other values define a custom pin configuration mask. From the LSB, every 6 bits represent a GPIO number which stand for:
+ *   DQS, D4, D5, D6, D7 accordingly.
+ */
+uint32_t ets_efuse_get_opiconfig(void);
+
+/**
+  * @brief  Read if download mode disabled from Efuse
+  *
+  * @return
+  * - true for efuse disable download mode.
+  * - false for efuse doesn't disable download mode.
+  */
+bool ets_efuse_download_modes_disabled(void);
+
+/**
+  * @brief  Read if legacy spi flash boot mode disabled from Efuse
+  *
+  * @return
+  * - true for efuse disable legacy spi flash boot mode.
+  * - false for efuse doesn't disable legacy spi flash boot mode.
+  */
+bool ets_efuse_legacy_spi_boot_mode_disabled(void);
+
+/**
+  * @brief  Read if uart print control value from Efuse
+  *
+  * @return
+  * - 0 for uart force print.
+  * - 1 for uart print when GPIO8 is low when digital reset.
+  *   2 for uart print when GPIO8 is high when digital reset.
+  *   3 for uart force slient
+  */
+uint32_t ets_efuse_get_uart_print_control(void);
+
+/**
+  * @brief  Read which channel will used by ROM to print
+  *
+  * @return
+  * - 0 for UART0.
+  * - 1 for UART1.
+  */
+uint32_t ets_efuse_get_uart_print_channel(void);
+
+/**
+  * @brief  Read if usb download mode disabled from Efuse
+  *
+  * (Also returns true if security download mode is enabled, as this mode
+  * disables USB download.)
+  *
+  * @return
+  * - true for efuse disable usb download mode.
+  * - false for efuse doesn't disable usb download mode.
+  */
+bool ets_efuse_usb_download_mode_disabled(void);
+
+/**
+  * @brief  Read if tiny basic mode disabled from Efuse
+  *
+  * @return
+  * - true for efuse disable tiny basic mode.
+  * - false for efuse doesn't disable tiny basic mode.
+  */
+bool ets_efuse_tiny_basic_mode_disabled(void);
+
+/**
+  * @brief  Read if usb module disabled from Efuse
+  *
+  * @return
+  * - true for efuse disable usb module.
+  * - false for efuse doesn't disable usb module.
+  */
+bool ets_efuse_usb_module_disabled(void);
+
+/**
+  * @brief  Read if security download modes enabled from Efuse
+  *
+  * @return
+  * - true for efuse enable security download mode.
+  * - false for efuse doesn't enable security download mode.
+  */
+bool ets_efuse_security_download_modes_enabled(void);
+
+/**
+ * @brief Return true if secure boot is enabled in EFuse
+ */
+bool ets_efuse_secure_boot_enabled(void);
+
+/**
+ * @brief Return true if secure boot aggressive revoke is enabled in EFuse
+ */
+bool ets_efuse_secure_boot_aggressive_revoke_enabled(void);
+
+/**
+ * @brief Return true if cache encryption (flash, etc) is enabled from boot via EFuse
+ */
+bool ets_efuse_cache_encryption_enabled(void);
+
+/**
+ * @brief Return true if EFuse indicates an external phy needs to be used for USB
+ */
+bool ets_efuse_usb_use_ext_phy(void);
+
+/**
+ * @brief Return true if EFuse indicates USB device persistence is disabled
+ */
+bool ets_efuse_usb_force_nopersist(void);
+
+/**
+ * @brief Return true if OPI pins GPIO33-37 are powered by VDDSPI, otherwise by VDD33CPU
+ */
+bool ets_efuse_flash_opi_5pads_power_sel_vddspi(void);
+
+/**
+ * @brief Return true if EFuse indicates an opi flash is attached.
+ */
+bool ets_efuse_flash_opi_mode(void);
+
+/**
+ * @brief Return true if EFuse indicates to send a flash resume command.
+ */
+bool ets_efuse_force_send_resume(void);
+
+/**
+  * @brief  return the time in us ROM boot need wait flash to power on from Efuse
+  *
+  * @return
+  * - uint32_t the time in us.
+  */
+uint32_t ets_efuse_get_flash_delay_us(void);
+
+#define EFUSE_SPICONFIG_SPI_DEFAULTS 0
+#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1
+
+#define EFUSE_SPICONFIG_RET_SPICLK_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT        0
+#define EFUSE_SPICONFIG_RET_SPICLK(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPIQ_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT          6
+#define EFUSE_SPICONFIG_RET_SPIQ(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPID_MASK           0x3f
+#define EFUSE_SPICONFIG_RET_SPID_SHIFT          12
+#define EFUSE_SPICONFIG_RET_SPID(ret)           (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK)
+
+#define EFUSE_SPICONFIG_RET_SPICS0_MASK         0x3f
+#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT        18
+#define EFUSE_SPICONFIG_RET_SPICS0(ret)         (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK)
+
+
+#define EFUSE_SPICONFIG_RET_SPIHD_MASK          0x3f
+#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT         24
+#define EFUSE_SPICONFIG_RET_SPIHD(ret)          (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK)
+
+/**
+ * @brief Enable JTAG temporarily by writing a JTAG HMAC "key" into
+ * the JTAG_CTRL registers.
+ *
+ * Works if JTAG has been "soft" disabled by burning the EFUSE_SOFT_DIS_JTAG efuse.
+ *
+ * Will enable the HMAC module to generate a "downstream" HMAC value from a key already saved in efuse, and then write the JTAG HMAC "key" which will enable JTAG if the two keys match.
+ *
+ * @param jtag_hmac_key Pointer to a 32 byte array containing a valid key. Supplied by user.
+ * @param key_block Index of a key block containing the source for this key.
+ *
+ * @return ETS_FAILED if HMAC operation fails or invalid parameter, ETS_OK otherwise. ETS_OK doesn't necessarily mean that JTAG was enabled.
+ */
+int ets_jtag_enable_temporarily(const uint8_t *jtag_hmac_key, ets_efuse_block_t key_block);
+
+/**
+  * @brief  A crc8 algorithm used for MAC addresses in efuse
+  *
+  * @param  unsigned char const *p : Pointer to original data.
+  *
+  * @param  unsigned int len : Data length in byte.
+  *
+  * @return unsigned char: Crc value.
+  */
+unsigned char esp_crc8(unsigned char const *p, unsigned int len);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_EFUSE_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/esp_flash.h b/components/esp_rom/include/esp8684/rom/esp_flash.h
new file mode 100644
index 0000000000000000000000000000000000000000..2ab679af68670889def97af67043886fa7582d9c
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/esp_flash.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Note: Most of esp_flash APIs in ROM are compatible with headers in ESP-IDF, this function
+   just adds ROM-specific parts
+*/
+
+struct spi_flash_chip_t;
+typedef struct esp_flash_t esp_flash_t;
+
+/* Structure to wrap "global" data used by esp_flash in ROM */
+typedef struct {
+    /* Default SPI flash chip, ie main chip attached to the MCU
+       This chip is used if the 'chip' argument passed to esp_flash_xxx API functions is ever NULL
+    */
+    esp_flash_t *default_chip;
+
+    /* Global API OS notification start/end/chip_check functions
+
+       These are used by ROM if no other host functions are configured.
+    */
+    struct {
+        esp_err_t (*start)(esp_flash_t *chip);
+        esp_err_t (*end)(esp_flash_t *chip, esp_err_t err);
+        esp_err_t (*chip_check)(esp_flash_t **inout_chip);
+    } api_funcs;
+} esp_flash_rom_global_data_t;
+
+/** Access a pointer to the global data used by the ROM spi_flash driver
+ */
+esp_flash_rom_global_data_t *esp_flash_get_rom_global_data(void);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_rom/include/esp8684/rom/ets_sys.h b/components/esp_rom/include/esp8684/rom/ets_sys.h
new file mode 100644
index 0000000000000000000000000000000000000000..893404cbf45f9e78030ca976b425460ddbdbed33
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/ets_sys.h
@@ -0,0 +1,555 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_ETS_SYS_H_
+#define _ROM_ETS_SYS_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup ets_sys_apis, ets system related apis
+  * @brief ets system apis
+  */
+
+/** @addtogroup ets_sys_apis
+  * @{
+  */
+
+/************************************************************************
+  *                                NOTE
+  *   Many functions in this header files can't be run in FreeRTOS.
+  *   Please see the comment of the Functions.
+  *   There are also some functions that doesn't work on FreeRTOS
+  *   without listed in the header, such as:
+  *   xtos functions start with "_xtos_" in ld file.
+  *
+  ***********************************************************************
+  */
+
+/** \defgroup ets_apis, Espressif Task Scheduler related apis
+  * @brief ets apis
+  */
+
+/** @addtogroup ets_apis
+  * @{
+  */
+
+typedef enum {
+    ETS_OK     = 0, /**< return successful in ets*/
+    ETS_FAILED = 1  /**< return failed in ets*/
+} ETS_STATUS;
+
+typedef ETS_STATUS ets_status_t;
+
+typedef uint32_t ETSSignal;
+typedef uint32_t ETSParam;
+
+typedef struct ETSEventTag ETSEvent;    /**< Event transmit/receive in ets*/
+
+struct ETSEventTag {
+    ETSSignal sig;  /**< Event signal, in same task, different Event with different signal*/
+    ETSParam  par;  /**< Event parameter, sometimes without usage, then will be set as 0*/
+};
+
+typedef void (*ETSTask)(ETSEvent *e);       /**< Type of the Task processer*/
+typedef void (* ets_idle_cb_t)(void *arg);  /**< Type of the system idle callback*/
+
+/**
+  * @brief  Start the Espressif Task Scheduler, which is an infinit loop. Please do not add code after it.
+  *
+  * @param  none
+  *
+  * @return none
+  */
+void ets_run(void);
+
+/**
+  * @brief  Set the Idle callback, when Tasks are processed, will call the callback before CPU goto sleep.
+  *
+  * @param  ets_idle_cb_t func : The callback function.
+  *
+  * @param  void *arg : Argument of the callback.
+  *
+  * @return None
+  */
+void ets_set_idle_cb(ets_idle_cb_t func, void *arg);
+
+/**
+  * @brief  Init a task with processer, priority, queue to receive Event, queue length.
+  *
+  * @param  ETSTask task : The task processer.
+  *
+  * @param  uint8_t prio : Task priority, 0-31, bigger num with high priority, one priority with one task.
+  *
+  * @param  ETSEvent *queue : Queue belongs to the task, task always receives Events, Queue is circular used.
+  *
+  * @param  uint8_t qlen : Queue length.
+  *
+  * @return None
+  */
+void ets_task(ETSTask task, uint8_t prio, ETSEvent *queue, uint8_t qlen);
+
+/**
+  * @brief  Post an event to an Task.
+  *
+  * @param  uint8_t prio : Priority of the Task.
+  *
+  * @param  ETSSignal sig : Event signal.
+  *
+  * @param  ETSParam  par : Event parameter
+  *
+  * @return ETS_OK     : post successful
+  * @return ETS_FAILED : post failed
+  */
+ETS_STATUS ets_post(uint8_t prio, ETSSignal sig, ETSParam par);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_boot_apis, Boot routing related apis
+  * @brief ets boot apis
+  */
+
+/** @addtogroup ets_apis
+  * @{
+  */
+
+extern const char *const exc_cause_table[40];   ///**< excption cause that defined by the core.*/
+
+/**
+  * @brief  Set Pro cpu Entry code, code can be called in PRO CPU when booting is not completed.
+  *         When Pro CPU booting is completed, Pro CPU will call the Entry code if not NULL.
+  *
+  * @param  uint32_t start : the PRO Entry code address value in uint32_t
+  *
+  * @return None
+  */
+void ets_set_user_start(uint32_t start);
+
+/**
+  * @brief  Set Pro cpu Startup code, code can be called when booting is not completed, or in Entry code.
+  *         When Entry code completed, CPU will call the Startup code if not NULL, else call ets_run.
+  *
+  * @param  uint32_t callback : the Startup code address value in uint32_t
+  *
+  * @return None     : post successful
+  */
+void ets_set_startup_callback(uint32_t callback);
+
+/**
+  * @brief  Set App cpu Entry code, code can be called in PRO CPU.
+  *         When APP booting is completed, APP CPU will call the Entry code if not NULL.
+  *
+  * @param  uint32_t start : the APP Entry code address value in uint32_t, stored in register APPCPU_CTRL_REG_D.
+  *
+  * @return None
+  */
+void ets_set_appcpu_boot_addr(uint32_t start);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_printf_apis, ets_printf related apis used in ets
+  * @brief ets printf apis
+  */
+
+/** @addtogroup ets_printf_apis
+  * @{
+  */
+
+/**
+  * @brief  Printf the strings to uart or other devices, similar with printf, simple than printf.
+  *         Can not print float point data format, or longlong data format.
+  *         So we maybe only use this in ROM.
+  *
+  * @param  const char *fmt : See printf.
+  *
+  * @param  ... : See printf.
+  *
+  * @return int : the length printed to the output device.
+  */
+int ets_printf(const char *fmt, ...);
+
+/**
+  * @brief  Set the uart channel of ets_printf(uart_tx_one_char).
+  *         ROM will set it base on the efuse and gpio setting, however, this can be changed after booting.
+  *
+  * @param  uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None
+  */
+void ets_set_printf_channel(uint8_t uart_no);
+
+/**
+  * @brief Get the uart channel of ets_printf(uart_tx_one_char).
+  *
+  * @return uint8_t uart channel used by ets_printf(uart_tx_one_char).
+  */
+uint8_t ets_get_printf_channel(void);
+
+/**
+  * @brief  Output a char to uart, which uart to output(which is in uart module in ROM) is not in scope of the function.
+  *         Can not print float point data format, or longlong data format
+  *
+  * @param  char c : char to output.
+  *
+  * @return None
+  */
+void ets_write_char_uart(char c);
+
+/**
+  * @brief  Ets_printf have two output functions: putc1 and putc2, both of which will be called if need ouput.
+  *         To install putc1, which is defaulted installed as ets_write_char_uart in none silent boot mode, as NULL in silent mode.
+  *
+  * @param  void (*)(char) p: Output function to install.
+  *
+  * @return None
+  */
+void ets_install_putc1(void (*p)(char c));
+
+/**
+  * @brief  Ets_printf have two output functions: putc1 and putc2, both of which will be called if need ouput.
+  *         To install putc2, which is defaulted installed as NULL.
+  *
+  * @param  void (*)(char) p: Output function to install.
+  *
+  * @return None
+  */
+void ets_install_putc2(void (*p)(char c));
+
+/**
+  * @brief  Install putc1 as ets_write_char_uart.
+  *         In silent boot mode(to void interfere the UART attached MCU), we can call this function, after booting ok.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_install_uart_printf(void);
+
+#define ETS_PRINTF(...) ets_printf(...)
+
+#define ETS_ASSERT(v) do { \
+    if (!(v)) {             \
+        ets_printf("%s %u \n", __FILE__, __LINE__); \
+        while (1) {};   \
+    }                   \
+} while (0);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_timer_apis, ets_timer related apis used in ets
+  * @brief ets timer apis
+  */
+
+/** @addtogroup ets_timer_apis
+  * @{
+  */
+typedef void ETSTimerFunc(void *timer_arg);/**< timer handler*/
+
+typedef struct _ETSTIMER_ {
+    struct _ETSTIMER_    *timer_next;   /**< timer linker*/
+    uint32_t              timer_expire; /**< abstruct time when timer expire*/
+    uint32_t              timer_period; /**< timer period, 0 means timer is not periodic repeated*/
+    ETSTimerFunc         *timer_func;   /**< timer handler*/
+    void                 *timer_arg;    /**< timer handler argument*/
+} ETSTimer;
+
+/**
+  * @brief  Init ets timer, this timer range is 640 us to 429496 ms
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_timer_init(void);
+
+/**
+  * @brief  In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_timer_deinit(void);
+
+/**
+  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  uint32_t tmout : Timer value in ms, range is 1 to 429496.
+  *
+  * @param  bool repeat : Timer is periodic repeated.
+  *
+  * @return None
+  */
+void ets_timer_arm(ETSTimer *timer, uint32_t tmout, bool repeat);
+
+/**
+  * @brief  Arm an ets timer, this timer range is 640 us to 429496 ms.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  uint32_t tmout : Timer value in us, range is 1 to 429496729.
+  *
+  * @param  bool repeat : Timer is periodic repeated.
+  *
+  * @return None
+  */
+void ets_timer_arm_us(ETSTimer *ptimer, uint32_t us, bool repeat);
+
+/**
+  * @brief  Disarm an ets timer.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @return None
+  */
+void ets_timer_disarm(ETSTimer *timer);
+
+/**
+  * @brief  Set timer callback and argument.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @param  ETSTimerFunc *pfunction : Timer callback.
+  *
+  * @param  void *parg : Timer callback argument.
+  *
+  * @return None
+  */
+void ets_timer_setfn(ETSTimer *ptimer, ETSTimerFunc *pfunction, void *parg);
+
+/**
+  * @brief  Unset timer callback and argument to NULL.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  ETSTimer *timer : Timer struct pointer.
+  *
+  * @return None
+  */
+void ets_timer_done(ETSTimer *ptimer);
+
+/**
+  * @brief  CPU do while loop for some time.
+  *         In FreeRTOS task, please call FreeRTOS apis.
+  *
+  * @param  uint32_t us : Delay time in us.
+  *
+  * @return None
+  */
+void ets_delay_us(uint32_t us);
+
+/**
+  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
+  *         Call this function when CPU frequency is changed.
+  *
+  * @param  uint32_t ticks_per_us : CPU ticks per us.
+  *
+  * @return None
+  */
+void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+/**
+  * @brief  Set the real CPU ticks per us to the ets, so that ets_delay_us will be accurate.
+  *
+  * @note This function only sets the tick rate for the current CPU. It is located in ROM,
+  *       so the deep sleep stub can use it even if IRAM is not initialized yet.
+  *
+  * @param  uint32_t ticks_per_us : CPU ticks per us.
+  *
+  * @return None
+  */
+void ets_update_cpu_frequency_rom(uint32_t ticks_per_us);
+
+/**
+  * @brief  Get the real CPU ticks per us to the ets.
+  *         This function do not return real CPU ticks per us, just the record in ets. It can be used to check with the real CPU frequency.
+  *
+  * @param  None
+  *
+  * @return uint32_t : CPU ticks per us record in ets.
+  */
+uint32_t ets_get_cpu_frequency(void);
+
+/**
+  * @brief  Get xtal_freq value, If value not stored in RTC_STORE5, than store.
+  *
+  * @param  None
+  *
+  * @return uint32_t : if stored in efuse(not 0)
+  *                         clock = ets_efuse_get_xtal_freq() * 1000000;
+  *                    else if analog_8M in efuse
+  *                         clock = ets_get_xtal_scale() * 625 / 16 * ets_efuse_get_8M_clock();
+  *                    else clock = 40M.
+  */
+uint32_t ets_get_xtal_freq(void);
+
+/**
+  * @brief  Get the apb divior by xtal frequency.
+  *         When any types of reset happen, the default value is 2.
+  *
+  * @param  None
+  *
+  * @return uint32_t : 1 or 2.
+  */
+uint32_t ets_get_xtal_div(void);
+
+/**
+  * @brief  Get apb_freq value, If value not stored in RTC_STORE5, than store.
+  *
+  * @param  None
+  *
+  * @return uint32_t : if rtc store the value (RTC_STORE5 high 16 bits and low 16 bits with same value), read from rtc register.
+  *                         clock = (REG_READ(RTC_STORE5) & 0xffff) << 12;
+  *                    else store ets_get_detected_xtal_freq() in.
+  */
+uint32_t ets_get_apb_freq(void);
+
+/**
+  * @}
+  */
+
+/** \defgroup ets_intr_apis, ets interrupt configure related apis
+  * @brief ets intr apis
+  */
+
+/** @addtogroup ets_intr_apis
+  * @{
+  */
+
+typedef void (* ets_isr_t)(void *);/**< interrupt handler type*/
+
+/**
+  * @brief  Attach a interrupt handler to a CPU interrupt number.
+  *         This function equals to _xtos_set_interrupt_handler_arg(i, func, arg).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  int i : CPU interrupt number.
+  *
+  * @param  ets_isr_t func : Interrupt handler.
+  *
+  * @param  void *arg : argument of the handler.
+  *
+  * @return None
+  */
+void ets_isr_attach(int i, ets_isr_t func, void *arg);
+
+/**
+  * @brief  Mask the interrupts which show in mask bits.
+  *         This function equals to _xtos_ints_off(mask).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
+  *
+  * @return None
+  */
+void ets_isr_mask(uint32_t mask);
+
+/**
+  * @brief  Unmask the interrupts which show in mask bits.
+  *         This function equals to _xtos_ints_on(mask).
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  uint32_t mask : BIT(i) means mask CPU interrupt number i.
+  *
+  * @return None
+  */
+void ets_isr_unmask(uint32_t unmask);
+
+/**
+  * @brief  Lock the interrupt to level 2.
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_intr_lock(void);
+
+/**
+  * @brief  Unlock the interrupt to level 0.
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_intr_unlock(void);
+
+/**
+  * @brief  Unlock the interrupt to level 0, and CPU will go into power save mode(wait interrupt).
+  *         This function direct set the CPU registers.
+  *         In FreeRTOS, please call FreeRTOS apis, never call this api.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void ets_waiti0(void);
+
+/**
+  * @brief  Attach an CPU interrupt to a hardware source.
+  *         We have 4 steps to use an interrupt:
+  *         1.Attach hardware interrupt source to CPU.  intr_matrix_set(0, ETS_WIFI_MAC_INTR_SOURCE, ETS_WMAC_INUM);
+  *         2.Set interrupt handler.                    xt_set_interrupt_handler(ETS_WMAC_INUM, func, NULL);
+  *         3.Enable interrupt for CPU.                 xt_ints_on(1 << ETS_WMAC_INUM);
+  *         4.Enable interrupt in the module.
+  *
+  * @param  int cpu_no : The CPU which the interrupt number belongs.
+  *
+  * @param  uint32_t model_num : The interrupt hardware source number, please see the interrupt hardware source table.
+  *
+  * @param  uint32_t intr_num : The interrupt number CPU, please see the interrupt cpu using table.
+  *
+  * @return None
+  */
+void intr_matrix_set(int cpu_no, uint32_t model_num, uint32_t intr_num);
+
+/**
+  * @}
+  */
+
+#ifndef MAC2STR
+#define MAC2STR(a) (a)[0], (a)[1], (a)[2], (a)[3], (a)[4], (a)[5]
+#define MACSTR "%02x:%02x:%02x:%02x:%02x:%02x"
+#endif
+
+#define ETS_MEM_BAR() asm volatile ( "" : : : "memory" )
+
+typedef enum {
+    OK = 0,
+    FAIL,
+    PENDING,
+    BUSY,
+    CANCEL,
+} STATUS;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_ETS_SYS_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/gpio.h b/components/esp_rom/include/esp8684/rom/gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..5da855075823430e2811fb4d3fdb8c37502d8d85
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/gpio.h
@@ -0,0 +1,303 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_GPIO_H_
+#define _ROM_GPIO_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_attr.h"
+#include "soc/gpio_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup gpio_apis, uart configuration and communication related apis
+  * @brief gpio apis
+  */
+
+/** @addtogroup gpio_apis
+  * @{
+  */
+
+#define GPIO_REG_READ(reg)              READ_PERI_REG(reg)
+#define GPIO_REG_WRITE(reg, val)        WRITE_PERI_REG(reg, val)
+#define GPIO_ID_PIN0                    0
+#define GPIO_ID_PIN(n)                  (GPIO_ID_PIN0+(n))
+#define GPIO_PIN_ADDR(i)                (GPIO_PIN0_REG + i*4)
+
+#define GPIO_FUNC_IN_HIGH               0x38
+#define GPIO_FUNC_IN_LOW                0x3C
+
+#define GPIO_ID_IS_PIN_REGISTER(reg_id) \
+    ((reg_id >= GPIO_ID_PIN0) && (reg_id <= GPIO_ID_PIN(GPIO_PIN_COUNT-1)))
+
+#define GPIO_REGID_TO_PINIDX(reg_id) ((reg_id) - GPIO_ID_PIN0)
+
+typedef enum {
+    GPIO_PIN_INTR_DISABLE = 0,
+    GPIO_PIN_INTR_POSEDGE = 1,
+    GPIO_PIN_INTR_NEGEDGE = 2,
+    GPIO_PIN_INTR_ANYEDGE = 3,
+    GPIO_PIN_INTR_LOLEVEL = 4,
+    GPIO_PIN_INTR_HILEVEL = 5
+} GPIO_INT_TYPE;
+
+#define GPIO_OUTPUT_SET(gpio_no, bit_value) \
+        ((gpio_no < 32) ? gpio_output_set(bit_value<<gpio_no, (bit_value ? 0 : 1)<<gpio_no, 1<<gpio_no,0) : \
+                         gpio_output_set_high(bit_value<<(gpio_no - 32), (bit_value ? 0 : 1)<<(gpio_no - 32), 1<<(gpio_no -32),0))
+#define GPIO_DIS_OUTPUT(gpio_no)    ((gpio_no < 32) ? gpio_output_set(0,0,0, 1<<gpio_no) : gpio_output_set_high(0,0,0, 1<<(gpio_no - 32)))
+#define GPIO_INPUT_GET(gpio_no)     ((gpio_no < 32) ? ((gpio_input_get()>>gpio_no)&BIT0) : ((gpio_input_get_high()>>(gpio_no - 32))&BIT0))
+
+/* GPIO interrupt handler, registered through gpio_intr_handler_register */
+typedef void (* gpio_intr_handler_fn_t)(uint32_t intr_mask, bool high, void *arg);
+
+/**
+  * @brief Initialize GPIO. This includes reading the GPIO Configuration DataSet
+  *        to initialize "output enables" and pin configurations for each gpio pin.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void gpio_init(void);
+
+/**
+  * @brief Change GPIO(0-31) pin output by setting, clearing, or disabling pins, GPIO0<->BIT(0).
+  *         There is no particular ordering guaranteed; so if the order of writes is significant,
+  *         calling code should divide a single call into multiple calls.
+  *
+  * @param  uint32_t set_mask : the gpios that need high level.
+  *
+  * @param  uint32_t clear_mask : the gpios that need low level.
+  *
+  * @param  uint32_t enable_mask : the gpios that need be changed.
+  *
+  * @param  uint32_t disable_mask : the gpios that need diable output.
+  *
+  * @return None
+  */
+void gpio_output_set(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
+
+/**
+  * @brief Change GPIO(32-39) pin output by setting, clearing, or disabling pins, GPIO32<->BIT(0).
+  *         There is no particular ordering guaranteed; so if the order of writes is significant,
+  *         calling code should divide a single call into multiple calls.
+  *
+  * @param  uint32_t set_mask : the gpios that need high level.
+  *
+  * @param  uint32_t clear_mask : the gpios that need low level.
+  *
+  * @param  uint32_t enable_mask : the gpios that need be changed.
+  *
+  * @param  uint32_t disable_mask : the gpios that need diable output.
+  *
+  * @return None
+  */
+void gpio_output_set_high(uint32_t set_mask, uint32_t clear_mask, uint32_t enable_mask, uint32_t disable_mask);
+
+/**
+  * @brief Sample the value of GPIO input pins(0-31) and returns a bitmask.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO0.
+  */
+uint32_t gpio_input_get(void);
+
+/**
+  * @brief Sample the value of GPIO input pins(32-39) and returns a bitmask.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO input pins, BIT(0) for GPIO32.
+  */
+uint32_t gpio_input_get_high(void);
+
+/**
+  * @brief Register an application-specific interrupt handler for GPIO pin interrupts.
+  *        Once the interrupt handler is called, it will not be called again until after a call to gpio_intr_ack.
+  *        Please do not call this function in SDK.
+  *
+  * @param gpio_intr_handler_fn_t fn : gpio application-specific interrupt handler
+  *
+  * @param void *arg : gpio application-specific interrupt handler argument.
+  *
+  * @return None
+  */
+void gpio_intr_handler_register(gpio_intr_handler_fn_t fn, void *arg);
+
+/**
+  * @brief Get gpio interrupts which happens but not processed.
+  *        Please do not call this function in SDK.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO0.
+  */
+uint32_t gpio_intr_pending(void);
+
+/**
+  * @brief Get gpio interrupts which happens but not processed.
+  *        Please do not call this function in SDK.
+  *
+  * @param None
+  *
+  * @return uint32_t : bitmask for GPIO pending interrupts, BIT(0) for GPIO32.
+  */
+uint32_t gpio_intr_pending_high(void);
+
+/**
+  * @brief Ack gpio interrupts to process pending interrupts.
+  *        Please do not call this function in SDK.
+  *
+  * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO0.
+  *
+  * @return None
+  */
+void gpio_intr_ack(uint32_t ack_mask);
+
+/**
+  * @brief Ack gpio interrupts to process pending interrupts.
+  *        Please do not call this function in SDK.
+  *
+  * @param uint32_t ack_mask: bitmask for GPIO ack interrupts, BIT(0) for GPIO32.
+  *
+  * @return None
+  */
+void gpio_intr_ack_high(uint32_t ack_mask);
+
+/**
+  * @brief Set GPIO to wakeup the ESP32.
+  *        Please do not call this function in SDK.
+  *
+  * @param uint32_t i: gpio number.
+  *
+  * @param GPIO_INT_TYPE intr_state : only GPIO_PIN_INTR_LOLEVEL\GPIO_PIN_INTR_HILEVEL can be used
+  *
+  * @return None
+  */
+void gpio_pin_wakeup_enable(uint32_t i, GPIO_INT_TYPE intr_state);
+
+/**
+  * @brief disable GPIOs to wakeup the ESP32.
+  *        Please do not call this function in SDK.
+  *
+  * @param None
+  *
+  * @return None
+  */
+void gpio_pin_wakeup_disable(void);
+
+/**
+  * @brief set gpio input to a signal, one gpio can input to several signals.
+  *
+  * @param uint32_t gpio : gpio number, 0~0x2f
+  *                        gpio == 0x3C, input 0 to signal
+  *                        gpio == 0x3A, input nothing to signal
+  *                        gpio == 0x38, input 1 to signal
+  *
+  * @param uint32_t signal_idx : signal index.
+  *
+  * @param bool inv : the signal is inv or not
+  *
+  * @return None
+  */
+void gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
+
+/**
+  * @brief set signal output to gpio, one signal can output to several gpios.
+  *
+  * @param uint32_t gpio : gpio number, 0~0x2f
+  *
+  * @param uint32_t signal_idx : signal index.
+  *                        signal_idx == 0x100, cancel output put to the gpio
+  *
+  * @param bool out_inv : the signal output is invert or not
+  *
+  * @param bool oen_inv : the signal output enable is invert or not
+  *
+  * @return None
+  */
+void gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, bool oen_inv);
+
+/**
+  * @brief Select pad as a gpio function from IOMUX.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @return None
+  */
+void gpio_pad_select_gpio(uint32_t gpio_num);
+
+/**
+  * @brief Set pad driver capability.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @param uint32_t drv : 0-3
+  *
+  * @return None
+  */
+void gpio_pad_set_drv(uint32_t gpio_num, uint32_t drv);
+
+/**
+  * @brief Pull up the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @return None
+  */
+void gpio_pad_pullup(uint32_t gpio_num);
+
+/**
+  * @brief Pull down the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @return None
+  */
+void gpio_pad_pulldown(uint32_t gpio_num);
+
+/**
+  * @brief Unhold the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @return None
+  */
+void gpio_pad_unhold(uint32_t gpio_num);
+
+/**
+  * @brief Hold the pad from gpio number.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @return None
+  */
+void gpio_pad_hold(uint32_t gpio_num);
+
+/**
+  * @brief enable gpio pad input.
+  *
+  * @param uint32_t gpio_num : gpio number, 0~0x2f
+  *
+  * @return None
+  */
+void gpio_pad_input_enable(uint32_t gpio_num);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_GPIO_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/libc_stubs.h b/components/esp_rom/include/esp8684/rom/libc_stubs.h
new file mode 100644
index 0000000000000000000000000000000000000000..708ef694267eeb5074ceddcf4387086987477d42
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/libc_stubs.h
@@ -0,0 +1,83 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ROM_LIBC_STUBS_H_
+#define _ROM_LIBC_STUBS_H_
+
+#include <sys/lock.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdarg.h>
+#include <reent.h>
+#include <errno.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ESP32-C3 ROM code contains implementations of some of C library functions.
+Whenever a function in ROM needs to use a syscall, it calls a pointer to the corresponding syscall
+implementation defined in the following struct.
+
+The table itself, by default, is not allocated in RAM. A global pointer syscall_table_ptr is used to
+set the address
+
+So, before using any of the C library functions (except for pure functions and memcpy/memset functions),
+application must allocate syscall table structure for each CPU being used, and populate it with pointers
+to actual implementations of corresponding syscalls.
+*/
+
+struct syscall_stub_table
+{
+    struct _reent* (*__getreent)(void);
+    void* (*_malloc_r)(struct _reent *r, size_t);
+    void (*_free_r)(struct _reent *r, void*);
+    void* (*_realloc_r)(struct _reent *r, void*, size_t);
+    void* (*_calloc_r)(struct _reent *r, size_t, size_t);
+    void (*_abort)(void);
+    int (*_system_r)(struct _reent *r, const char*);
+    int (*_rename_r)(struct _reent *r, const char*, const char*);
+    clock_t (*_times_r)(struct _reent *r, struct tms *);
+    int (*_gettimeofday_r) (struct _reent *r, struct timeval *, void *);
+    void (*_raise_r)(struct _reent *r);
+    int (*_unlink_r)(struct _reent *r, const char*);
+    int (*_link_r)(struct _reent *r, const char*, const char*);
+    int (*_stat_r)(struct _reent *r, const char*, struct stat *);
+    int (*_fstat_r)(struct _reent *r, int, struct stat *);
+    void* (*_sbrk_r)(struct _reent *r, ptrdiff_t);
+    int (*_getpid_r)(struct _reent *r);
+    int (*_kill_r)(struct _reent *r, int, int);
+    void (*_exit_r)(struct _reent *r, int);
+    int (*_close_r)(struct _reent *r, int);
+    int (*_open_r)(struct _reent *r, const char *, int, int);
+    int (*_write_r)(struct _reent *r, int, const void *, int);
+    int (*_lseek_r)(struct _reent *r, int, int, int);
+    int (*_read_r)(struct _reent *r, int, void *, int);
+    void (*_retarget_lock_init)(_LOCK_T *lock);
+    void (*_retarget_lock_init_recursive)(_LOCK_T *lock);
+    void (*_retarget_lock_close)(_LOCK_T lock);
+    void (*_retarget_lock_close_recursive)(_LOCK_T lock);
+    void (*_retarget_lock_acquire)(_LOCK_T lock);
+    void (*_retarget_lock_acquire_recursive)(_LOCK_T lock);
+    int (*_retarget_lock_try_acquire)(_LOCK_T lock);
+    int (*_retarget_lock_try_acquire_recursive)(_LOCK_T lock);
+    void (*_retarget_lock_release)(_LOCK_T lock);
+    void (*_retarget_lock_release_recursive)(_LOCK_T lock);
+    int (*_printf_float)(struct _reent *data, void *pdata, FILE * fp, int (*pfunc) (struct _reent *, FILE *, const char *, size_t len), va_list * ap);
+    int (*_scanf_float) (struct _reent *rptr, void *pdata, FILE *fp, va_list *ap);
+    void (*__assert_func) (const char *file, int line, const char * func, const char *failedexpr) __attribute__((noreturn));
+    void (*__sinit) (struct _reent *r);
+    void (*_cleanup_r) (struct _reent* r);
+};
+
+extern struct syscall_stub_table *syscall_table_ptr;
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif /* _ROM_LIBC_STUBS_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/lldesc.h b/components/esp_rom/include/esp8684/rom/lldesc.h
new file mode 100644
index 0000000000000000000000000000000000000000..99457ebc93240ca7831fd46e15d309aa07c21fd2
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/lldesc.h
@@ -0,0 +1,168 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_LLDESC_H_
+#define _ROM_LLDESC_H_
+
+#include <stdint.h>
+
+#include "sys/queue.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define LLDESC_TX_MBLK_SIZE                 268 /* */
+#define LLDESC_RX_SMBLK_SIZE                64  /* small block size, for small mgmt frame */
+#define LLDESC_RX_MBLK_SIZE                 524 /* rx is large sinec we want to contain mgmt frame in one block*/
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_SIZE    64  /* it is a small buffer which is a cycle link*/
+#define LLDESC_RX_AMPDU_LEN_MBLK_SIZE      256 /*for ampdu entry*/
+#ifdef ESP_MAC_5
+#define LLDESC_TX_MBLK_NUM                  116  /* 64K / 256 */
+#define LLDESC_RX_MBLK_NUM                  82 /* 64K / 512 MAX 172*/
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM     4
+#define LLDESC_RX_AMPDU_LEN_MLBK_NUM       12
+#else
+#ifdef SBUF_RXTX
+#define LLDESC_TX_MBLK_NUM_MAX    (2 * 48) /* 23K / 260 - 8 */
+#define LLDESC_RX_MBLK_NUM_MAX    (2 * 48) /* 23K / 524 */
+#define LLDESC_TX_MBLK_NUM_MIN    (2 * 16) /* 23K / 260 - 8 */
+#define LLDESC_RX_MBLK_NUM_MIN    (2 * 16) /* 23K / 524 */
+#endif
+#define LLDESC_TX_MBLK_NUM      10      //(2 * 32) /* 23K / 260 - 8 */
+
+#ifdef IEEE80211_RX_AMPDU
+#define LLDESC_RX_MBLK_NUM      30
+#else
+#define LLDESC_RX_MBLK_NUM      10
+#endif /*IEEE80211_RX_AMPDU*/
+
+#define LLDESC_RX_AMPDU_ENTRY_MBLK_NUM  4
+#define LLDESC_RX_AMPDU_LEN_MLBK_NUM    8
+#endif /* !ESP_MAC_5 */
+/*
+ *  SLC2 DMA Desc struct, aka lldesc_t
+ *
+ * --------------------------------------------------------------
+ * | own | EoF | sub_sof | 5'b0   | length [11:0] | size [11:0] |
+ * --------------------------------------------------------------
+ * |            buf_ptr [31:0]                                  |
+ * --------------------------------------------------------------
+ * |            next_desc_ptr [31:0]                            |
+ * --------------------------------------------------------------
+ */
+
+/* this bitfield is start from the LSB!!! */
+typedef struct lldesc_s {
+    volatile uint32_t size  : 12,
+             length: 12,
+             offset: 5, /* h/w reserved 5bit, s/w use it as offset in buffer */
+             sosf  : 1, /* start of sub-frame */
+             eof   : 1, /* end of frame */
+             owner : 1; /* hw or sw */
+    volatile const uint8_t *buf;       /* point to buffer data */
+    union {
+        volatile uint32_t empty;
+        STAILQ_ENTRY(lldesc_s) qe;  /* pointing to the next desc */
+    };
+} lldesc_t;
+
+typedef struct tx_ampdu_entry_s {
+    uint32_t sub_len  : 12,
+             dili_num : 7,
+             : 1,
+             null_byte: 2,
+             data     : 1,
+             enc      : 1,
+             seq      : 8;
+} tx_ampdu_entry_t;
+
+typedef struct lldesc_chain_s {
+    lldesc_t *head;
+    lldesc_t *tail;
+} lldesc_chain_t;
+
+#ifdef SBUF_RXTX
+enum sbuf_mask_s  {
+    SBUF_MOVE_NO = 0,
+    SBUF_MOVE_TX2RX,
+    SBUF_MOVE_RX2TX,
+} ;
+
+#define SBUF_MOVE_STEP 8
+#endif
+#define LLDESC_SIZE  sizeof(struct lldesc_s)
+
+/* SLC Descriptor  */
+#define LLDESC_OWNER_MASK                  0x80000000
+#define LLDESC_OWNER_SHIFT                         31
+#define LLDESC_SW_OWNED                             0
+#define LLDESC_HW_OWNED                             1
+
+#define LLDESC_EOF_MASK                    0x40000000
+#define LLDESC_EOF_SHIFT                           30
+
+#define LLDESC_SOSF_MASK                   0x20000000
+#define LLDESC_SOSF_SHIFT                          29
+
+#define LLDESC_LENGTH_MASK                 0x00fff000
+#define LLDESC_LENGTH_SHIFT                        12
+
+#define LLDESC_SIZE_MASK                   0x00000fff
+#define LLDESC_SIZE_SHIFT                           0
+
+#define LLDESC_ADDR_MASK                    0x000fffff
+
+void lldesc_build_chain(uint8_t *descptr, uint32_t desclen, uint8_t *mblkptr, uint32_t buflen, uint32_t blksz, uint8_t owner,
+                        lldesc_t **head,
+#ifdef TO_HOST_RESTART
+                        lldesc_t **one_before_tail,
+#endif
+                        lldesc_t **tail);
+
+lldesc_t *lldesc_num2link(lldesc_t *head, uint16_t nblks);
+
+lldesc_t *lldesc_set_owner(lldesc_t *head, uint16_t nblks, uint8_t owner);
+
+static inline uint32_t lldesc_get_chain_length(lldesc_t *head)
+{
+    lldesc_t *ds = head;
+    uint32_t len = 0;
+
+    while (ds) {
+        len += ds->length;
+        ds = STAILQ_NEXT(ds, qe);
+    }
+
+    return len;
+}
+
+static inline void lldesc_config(lldesc_t *ds, uint8_t owner, uint8_t eof, uint8_t sosf, uint16_t len)
+{
+    ds->owner  = owner;
+    ds->eof    = eof;
+    ds->sosf   = sosf;
+    ds->length = len;
+}
+
+#define LLDESC_CONFIG(_desc, _owner, _eof, _sosf, _len)        do { \
+        (_desc)->owner  = (_owner); \
+        (_desc)->eof    = (_eof);   \
+        (_desc)->sosf   = (_sosf);  \
+        (_desc)->length = (_len);   \
+} while(0)
+
+#define LLDESC_FROM_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
+
+#define LLDESC_MAC_RX_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, (ds)->size)
+
+#define LLDESC_TO_HOST_CLEANUP(ds) LLDESC_CONFIG((ds), LLDESC_HW_OWNED, 0, 0, 0)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_LLDESC_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/md5_hash.h b/components/esp_rom/include/esp8684/rom/md5_hash.h
new file mode 100644
index 0000000000000000000000000000000000000000..63ce15857b55ce38ac7f622ba9f8319e3a628227
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/md5_hash.h
@@ -0,0 +1,38 @@
+/*
+ * MD5 internal definitions
+ * Copyright (c) 2003-2005, Jouni Malinen <j@w1.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Alternatively, this software may be distributed under the terms of BSD
+ * license.
+ *
+ * See README and COPYING for more details.
+ */
+
+#ifndef _ROM_MD5_HASH_H_
+#define _ROM_MD5_HASH_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct MD5Context {
+    uint32_t buf[4];
+    uint32_t bits[2];
+    uint8_t in[64];
+};
+
+void MD5Init(struct MD5Context *context);
+void MD5Update(struct MD5Context *context, unsigned char const *buf, unsigned len);
+void MD5Final(unsigned char digest[16], struct MD5Context *context);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_MD5_HASH_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/miniz.h b/components/esp_rom/include/esp8684/rom/miniz.h
new file mode 100644
index 0000000000000000000000000000000000000000..0c8efbc41ae374bad49a44c983eb10a46710c6d9
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/miniz.h
@@ -0,0 +1,765 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef MINIZ_HEADER_INCLUDED
+#define MINIZ_HEADER_INCLUDED
+
+#include <stdlib.h>
+
+// Defines to completely disable specific portions of miniz.c:
+// If all macros here are defined the only functionality remaining will be CRC-32, adler-32, tinfl, and tdefl.
+
+// Define MINIZ_NO_STDIO to disable all usage and any functions which rely on stdio for file I/O.
+#define MINIZ_NO_STDIO
+
+// If MINIZ_NO_TIME is specified then the ZIP archive functions will not be able to get the current time, or
+// get/set file times, and the C run-time funcs that get/set times won't be called.
+// The current downside is the times written to your archives will be from 1979.
+#define MINIZ_NO_TIME
+
+// Define MINIZ_NO_ARCHIVE_APIS to disable all ZIP archive API's.
+#define MINIZ_NO_ARCHIVE_APIS
+
+// Define MINIZ_NO_ARCHIVE_APIS to disable all writing related ZIP archive API's.
+#define MINIZ_NO_ARCHIVE_WRITING_APIS
+
+// Define MINIZ_NO_ZLIB_APIS to remove all ZLIB-style compression/decompression API's.
+#define MINIZ_NO_ZLIB_APIS
+
+// Define MINIZ_NO_ZLIB_COMPATIBLE_NAME to disable zlib names, to prevent conflicts against stock zlib.
+#define MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+
+// Define MINIZ_NO_MALLOC to disable all calls to malloc, free, and realloc.
+// Note if MINIZ_NO_MALLOC is defined then the user must always provide custom user alloc/free/realloc
+// callbacks to the zlib and archive API's, and a few stand-alone helper API's which don't provide custom user
+// functions (such as tdefl_compress_mem_to_heap() and tinfl_decompress_mem_to_heap()) won't work.
+#define MINIZ_NO_MALLOC
+
+#if defined(__TINYC__) && (defined(__linux) || defined(__linux__))
+// TODO: Work around "error: include file 'sys\utime.h' when compiling with tcc on Linux
+#define MINIZ_NO_TIME
+#endif
+
+#if !defined(MINIZ_NO_TIME) && !defined(MINIZ_NO_ARCHIVE_APIS)
+#include <time.h>
+#endif
+
+//Hardcoded options for Xtensa - JD
+#define MINIZ_X86_OR_X64_CPU 0
+#define MINIZ_LITTLE_ENDIAN 1
+#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 0
+#define MINIZ_HAS_64BIT_REGISTERS 0
+#define TINFL_USE_64BIT_BITBUF 0
+
+
+#if defined(_M_IX86) || defined(_M_X64) || defined(__i386__) || defined(__i386) || defined(__i486__) || defined(__i486) || defined(i386) || defined(__ia64__) || defined(__x86_64__)
+// MINIZ_X86_OR_X64_CPU is only used to help set the below macros.
+#define MINIZ_X86_OR_X64_CPU 1
+#endif
+
+#if (__BYTE_ORDER__==__ORDER_LITTLE_ENDIAN__) || MINIZ_X86_OR_X64_CPU
+// Set MINIZ_LITTLE_ENDIAN to 1 if the processor is little endian.
+#define MINIZ_LITTLE_ENDIAN 1
+#endif
+
+#if MINIZ_X86_OR_X64_CPU
+// Set MINIZ_USE_UNALIGNED_LOADS_AND_STORES to 1 on CPU's that permit efficient integer loads and stores from unaligned addresses.
+#define MINIZ_USE_UNALIGNED_LOADS_AND_STORES 1
+#endif
+
+#if defined(_M_X64) || defined(_WIN64) || defined(__MINGW64__) || defined(_LP64) || defined(__LP64__) || defined(__ia64__) || defined(__x86_64__)
+// Set MINIZ_HAS_64BIT_REGISTERS to 1 if operations on 64-bit integers are reasonably fast (and don't involve compiler generated calls to helper functions).
+#define MINIZ_HAS_64BIT_REGISTERS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ------------------- zlib-style API Definitions.
+
+// For more compatibility with zlib, miniz.c uses unsigned long for some parameters/struct members. Beware: mz_ulong can be either 32 or 64-bits!
+typedef unsigned long mz_ulong;
+
+// mz_free() internally uses the MZ_FREE() macro (which by default calls free() unless you've modified the MZ_MALLOC macro) to release a block allocated from the heap.
+void mz_free(void *p);
+
+#define MZ_ADLER32_INIT (1)
+// mz_adler32() returns the initial adler-32 value to use when called with ptr==NULL.
+mz_ulong mz_adler32(mz_ulong adler, const unsigned char *ptr, size_t buf_len);
+
+#define MZ_CRC32_INIT (0)
+// mz_crc32() returns the initial CRC-32 value to use when called with ptr==NULL.
+mz_ulong mz_crc32(mz_ulong crc, const unsigned char *ptr, size_t buf_len);
+
+// Compression strategies.
+enum { MZ_DEFAULT_STRATEGY = 0, MZ_FILTERED = 1, MZ_HUFFMAN_ONLY = 2, MZ_RLE = 3, MZ_FIXED = 4 };
+
+// Method
+#define MZ_DEFLATED 8
+
+#ifndef MINIZ_NO_ZLIB_APIS
+
+// Heap allocation callbacks.
+// Note that mz_alloc_func parameter types purpsosely differ from zlib's: items/size is size_t, not unsigned long.
+typedef void *(*mz_alloc_func)(void *opaque, size_t items, size_t size);
+typedef void (*mz_free_func)(void *opaque, void *address);
+typedef void *(*mz_realloc_func)(void *opaque, void *address, size_t items, size_t size);
+
+#define MZ_VERSION          "9.1.15"
+#define MZ_VERNUM           0x91F0
+#define MZ_VER_MAJOR        9
+#define MZ_VER_MINOR        1
+#define MZ_VER_REVISION     15
+#define MZ_VER_SUBREVISION  0
+
+// Flush values. For typical usage you only need MZ_NO_FLUSH and MZ_FINISH. The other values are for advanced use (refer to the zlib docs).
+enum { MZ_NO_FLUSH = 0, MZ_PARTIAL_FLUSH = 1, MZ_SYNC_FLUSH = 2, MZ_FULL_FLUSH = 3, MZ_FINISH = 4, MZ_BLOCK = 5 };
+
+// Return status codes. MZ_PARAM_ERROR is non-standard.
+enum { MZ_OK = 0, MZ_STREAM_END = 1, MZ_NEED_DICT = 2, MZ_ERRNO = -1, MZ_STREAM_ERROR = -2, MZ_DATA_ERROR = -3, MZ_MEM_ERROR = -4, MZ_BUF_ERROR = -5, MZ_VERSION_ERROR = -6, MZ_PARAM_ERROR = -10000 };
+
+// Compression levels: 0-9 are the standard zlib-style levels, 10 is best possible compression (not zlib compatible, and may be very slow), MZ_DEFAULT_COMPRESSION=MZ_DEFAULT_LEVEL.
+enum { MZ_NO_COMPRESSION = 0, MZ_BEST_SPEED = 1, MZ_BEST_COMPRESSION = 9, MZ_UBER_COMPRESSION = 10, MZ_DEFAULT_LEVEL = 6, MZ_DEFAULT_COMPRESSION = -1 };
+
+// Window bits
+#define MZ_DEFAULT_WINDOW_BITS 15
+
+struct mz_internal_state;
+
+// Compression/decompression stream struct.
+typedef struct mz_stream_s {
+    const unsigned char *next_in;     // pointer to next byte to read
+    unsigned int avail_in;            // number of bytes available at next_in
+    mz_ulong total_in;                // total number of bytes consumed so far
+
+    unsigned char *next_out;          // pointer to next byte to write
+    unsigned int avail_out;           // number of bytes that can be written to next_out
+    mz_ulong total_out;               // total number of bytes produced so far
+
+    char *msg;                        // error msg (unused)
+    struct mz_internal_state *state;  // internal state, allocated by zalloc/zfree
+
+    mz_alloc_func zalloc;             // optional heap allocation function (defaults to malloc)
+    mz_free_func zfree;               // optional heap free function (defaults to free)
+    void *opaque;                     // heap alloc function user pointer
+
+    int data_type;                    // data_type (unused)
+    mz_ulong adler;                   // adler32 of the source or uncompressed data
+    mz_ulong reserved;                // not used
+} mz_stream;
+
+typedef mz_stream *mz_streamp;
+
+// Returns the version string of miniz.c.
+const char *mz_version(void);
+
+// mz_deflateInit() initializes a compressor with default options:
+// Parameters:
+//  pStream must point to an initialized mz_stream struct.
+//  level must be between [MZ_NO_COMPRESSION, MZ_BEST_COMPRESSION].
+//  level 1 enables a specially optimized compression function that's been optimized purely for performance, not ratio.
+//  (This special func. is currently only enabled when MINIZ_USE_UNALIGNED_LOADS_AND_STORES and MINIZ_LITTLE_ENDIAN are defined.)
+// Return values:
+//  MZ_OK on success.
+//  MZ_STREAM_ERROR if the stream is bogus.
+//  MZ_PARAM_ERROR if the input parameters are bogus.
+//  MZ_MEM_ERROR on out of memory.
+int mz_deflateInit(mz_streamp pStream, int level);
+
+// mz_deflateInit2() is like mz_deflate(), except with more control:
+// Additional parameters:
+//   method must be MZ_DEFLATED
+//   window_bits must be MZ_DEFAULT_WINDOW_BITS (to wrap the deflate stream with zlib header/adler-32 footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate/no header or footer)
+//   mem_level must be between [1, 9] (it's checked but ignored by miniz.c)
+int mz_deflateInit2(mz_streamp pStream, int level, int method, int window_bits, int mem_level, int strategy);
+
+// Quickly resets a compressor without having to reallocate anything. Same as calling mz_deflateEnd() followed by mz_deflateInit()/mz_deflateInit2().
+int mz_deflateReset(mz_streamp pStream);
+
+// mz_deflate() compresses the input to output, consuming as much of the input and producing as much output as possible.
+// Parameters:
+//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
+//   flush may be MZ_NO_FLUSH, MZ_PARTIAL_FLUSH/MZ_SYNC_FLUSH, MZ_FULL_FLUSH, or MZ_FINISH.
+// Return values:
+//   MZ_OK on success (when flushing, or if more input is needed but not available, and/or there's more output to be written but the output buffer is full).
+//   MZ_STREAM_END if all input has been consumed and all output bytes have been written. Don't call mz_deflate() on the stream anymore.
+//   MZ_STREAM_ERROR if the stream is bogus.
+//   MZ_PARAM_ERROR if one of the parameters is invalid.
+//   MZ_BUF_ERROR if no forward progress is possible because the input and/or output buffers are empty. (Fill up the input buffer or free up some output space and try again.)
+int mz_deflate(mz_streamp pStream, int flush);
+
+// mz_deflateEnd() deinitializes a compressor:
+// Return values:
+//  MZ_OK on success.
+//  MZ_STREAM_ERROR if the stream is bogus.
+int mz_deflateEnd(mz_streamp pStream);
+
+// mz_deflateBound() returns a (very) conservative upper bound on the amount of data that could be generated by deflate(), assuming flush is set to only MZ_NO_FLUSH or MZ_FINISH.
+mz_ulong mz_deflateBound(mz_streamp pStream, mz_ulong source_len);
+
+// Single-call compression functions mz_compress() and mz_compress2():
+// Returns MZ_OK on success, or one of the error codes from mz_deflate() on failure.
+int mz_compress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
+int mz_compress2(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len, int level);
+
+// mz_compressBound() returns a (very) conservative upper bound on the amount of data that could be generated by calling mz_compress().
+mz_ulong mz_compressBound(mz_ulong source_len);
+
+// Initializes a decompressor.
+int mz_inflateInit(mz_streamp pStream);
+
+// mz_inflateInit2() is like mz_inflateInit() with an additional option that controls the window size and whether or not the stream has been wrapped with a zlib header/footer:
+// window_bits must be MZ_DEFAULT_WINDOW_BITS (to parse zlib header/footer) or -MZ_DEFAULT_WINDOW_BITS (raw deflate).
+int mz_inflateInit2(mz_streamp pStream, int window_bits);
+
+// Decompresses the input stream to the output, consuming only as much of the input as needed, and writing as much to the output as possible.
+// Parameters:
+//   pStream is the stream to read from and write to. You must initialize/update the next_in, avail_in, next_out, and avail_out members.
+//   flush may be MZ_NO_FLUSH, MZ_SYNC_FLUSH, or MZ_FINISH.
+//   On the first call, if flush is MZ_FINISH it's assumed the input and output buffers are both sized large enough to decompress the entire stream in a single call (this is slightly faster).
+//   MZ_FINISH implies that there are no more source bytes available beside what's already in the input buffer, and that the output buffer is large enough to hold the rest of the decompressed data.
+// Return values:
+//   MZ_OK on success. Either more input is needed but not available, and/or there's more output to be written but the output buffer is full.
+//   MZ_STREAM_END if all needed input has been consumed and all output bytes have been written. For zlib streams, the adler-32 of the decompressed data has also been verified.
+//   MZ_STREAM_ERROR if the stream is bogus.
+//   MZ_DATA_ERROR if the deflate stream is invalid.
+//   MZ_PARAM_ERROR if one of the parameters is invalid.
+//   MZ_BUF_ERROR if no forward progress is possible because the input buffer is empty but the inflater needs more input to continue, or if the output buffer is not large enough. Call mz_inflate() again
+//   with more input data, or with more room in the output buffer (except when using single call decompression, described above).
+int mz_inflate(mz_streamp pStream, int flush);
+
+// Deinitializes a decompressor.
+int mz_inflateEnd(mz_streamp pStream);
+
+// Single-call decompression.
+// Returns MZ_OK on success, or one of the error codes from mz_inflate() on failure.
+int mz_uncompress(unsigned char *pDest, mz_ulong *pDest_len, const unsigned char *pSource, mz_ulong source_len);
+
+// Returns a string description of the specified error code, or NULL if the error code is invalid.
+const char *mz_error(int err);
+
+// Redefine zlib-compatible names to miniz equivalents, so miniz.c can be used as a drop-in replacement for the subset of zlib that miniz.c supports.
+// Define MINIZ_NO_ZLIB_COMPATIBLE_NAMES to disable zlib-compatibility if you use zlib in the same project.
+#ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+typedef unsigned char Byte;
+typedef unsigned int uInt;
+typedef mz_ulong uLong;
+typedef Byte Bytef;
+typedef uInt uIntf;
+typedef char charf;
+typedef int intf;
+typedef void *voidpf;
+typedef uLong uLongf;
+typedef void *voidp;
+typedef void *const voidpc;
+#define Z_NULL                0
+#define Z_NO_FLUSH            MZ_NO_FLUSH
+#define Z_PARTIAL_FLUSH       MZ_PARTIAL_FLUSH
+#define Z_SYNC_FLUSH          MZ_SYNC_FLUSH
+#define Z_FULL_FLUSH          MZ_FULL_FLUSH
+#define Z_FINISH              MZ_FINISH
+#define Z_BLOCK               MZ_BLOCK
+#define Z_OK                  MZ_OK
+#define Z_STREAM_END          MZ_STREAM_END
+#define Z_NEED_DICT           MZ_NEED_DICT
+#define Z_ERRNO               MZ_ERRNO
+#define Z_STREAM_ERROR        MZ_STREAM_ERROR
+#define Z_DATA_ERROR          MZ_DATA_ERROR
+#define Z_MEM_ERROR           MZ_MEM_ERROR
+#define Z_BUF_ERROR           MZ_BUF_ERROR
+#define Z_VERSION_ERROR       MZ_VERSION_ERROR
+#define Z_PARAM_ERROR         MZ_PARAM_ERROR
+#define Z_NO_COMPRESSION      MZ_NO_COMPRESSION
+#define Z_BEST_SPEED          MZ_BEST_SPEED
+#define Z_BEST_COMPRESSION    MZ_BEST_COMPRESSION
+#define Z_DEFAULT_COMPRESSION MZ_DEFAULT_COMPRESSION
+#define Z_DEFAULT_STRATEGY    MZ_DEFAULT_STRATEGY
+#define Z_FILTERED            MZ_FILTERED
+#define Z_HUFFMAN_ONLY        MZ_HUFFMAN_ONLY
+#define Z_RLE                 MZ_RLE
+#define Z_FIXED               MZ_FIXED
+#define Z_DEFLATED            MZ_DEFLATED
+#define Z_DEFAULT_WINDOW_BITS MZ_DEFAULT_WINDOW_BITS
+#define alloc_func            mz_alloc_func
+#define free_func             mz_free_func
+#define internal_state        mz_internal_state
+#define z_stream              mz_stream
+#define deflateInit           mz_deflateInit
+#define deflateInit2          mz_deflateInit2
+#define deflateReset          mz_deflateReset
+#define deflate               mz_deflate
+#define deflateEnd            mz_deflateEnd
+#define deflateBound          mz_deflateBound
+#define compress              mz_compress
+#define compress2             mz_compress2
+#define compressBound         mz_compressBound
+#define inflateInit           mz_inflateInit
+#define inflateInit2          mz_inflateInit2
+#define inflate               mz_inflate
+#define inflateEnd            mz_inflateEnd
+#define uncompress            mz_uncompress
+#define crc32                 mz_crc32
+#define adler32               mz_adler32
+#define MAX_WBITS             15
+#define MAX_MEM_LEVEL         9
+#define zError                mz_error
+#define ZLIB_VERSION          MZ_VERSION
+#define ZLIB_VERNUM           MZ_VERNUM
+#define ZLIB_VER_MAJOR        MZ_VER_MAJOR
+#define ZLIB_VER_MINOR        MZ_VER_MINOR
+#define ZLIB_VER_REVISION     MZ_VER_REVISION
+#define ZLIB_VER_SUBREVISION  MZ_VER_SUBREVISION
+#define zlibVersion           mz_version
+#define zlib_version          mz_version()
+#endif // #ifndef MINIZ_NO_ZLIB_COMPATIBLE_NAMES
+
+#endif // MINIZ_NO_ZLIB_APIS
+
+// ------------------- Types and macros
+
+typedef unsigned char mz_uint8;
+typedef signed short mz_int16;
+typedef unsigned short mz_uint16;
+typedef unsigned int mz_uint32;
+typedef unsigned int mz_uint;
+typedef long long mz_int64;
+typedef unsigned long long mz_uint64;
+typedef int mz_bool;
+
+#define MZ_FALSE (0)
+#define MZ_TRUE (1)
+
+// An attempt to work around MSVC's spammy "warning C4127: conditional expression is constant" message.
+#ifdef _MSC_VER
+#define MZ_MACRO_END while (0, 0)
+#else
+#define MZ_MACRO_END while (0)
+#endif
+
+// ------------------- ZIP archive reading/writing
+
+#ifndef MINIZ_NO_ARCHIVE_APIS
+
+enum {
+    MZ_ZIP_MAX_IO_BUF_SIZE = 64 * 1024,
+    MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE = 260,
+    MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE = 256
+};
+
+typedef struct {
+    mz_uint32 m_file_index;
+    mz_uint32 m_central_dir_ofs;
+    mz_uint16 m_version_made_by;
+    mz_uint16 m_version_needed;
+    mz_uint16 m_bit_flag;
+    mz_uint16 m_method;
+#ifndef MINIZ_NO_TIME
+    time_t m_time;
+#endif
+    mz_uint32 m_crc32;
+    mz_uint64 m_comp_size;
+    mz_uint64 m_uncomp_size;
+    mz_uint16 m_internal_attr;
+    mz_uint32 m_external_attr;
+    mz_uint64 m_local_header_ofs;
+    mz_uint32 m_comment_size;
+    char m_filename[MZ_ZIP_MAX_ARCHIVE_FILENAME_SIZE];
+    char m_comment[MZ_ZIP_MAX_ARCHIVE_FILE_COMMENT_SIZE];
+} mz_zip_archive_file_stat;
+
+typedef size_t (*mz_file_read_func)(void *pOpaque, mz_uint64 file_ofs, void *pBuf, size_t n);
+typedef size_t (*mz_file_write_func)(void *pOpaque, mz_uint64 file_ofs, const void *pBuf, size_t n);
+
+struct mz_zip_internal_state_tag;
+typedef struct mz_zip_internal_state_tag mz_zip_internal_state;
+
+typedef enum {
+    MZ_ZIP_MODE_INVALID = 0,
+    MZ_ZIP_MODE_READING = 1,
+    MZ_ZIP_MODE_WRITING = 2,
+    MZ_ZIP_MODE_WRITING_HAS_BEEN_FINALIZED = 3
+} mz_zip_mode;
+
+typedef struct mz_zip_archive_tag {
+    mz_uint64 m_archive_size;
+    mz_uint64 m_central_directory_file_ofs;
+    mz_uint m_total_files;
+    mz_zip_mode m_zip_mode;
+
+    mz_uint m_file_offset_alignment;
+
+    mz_alloc_func m_pAlloc;
+    mz_free_func m_pFree;
+    mz_realloc_func m_pRealloc;
+    void *m_pAlloc_opaque;
+
+    mz_file_read_func m_pRead;
+    mz_file_write_func m_pWrite;
+    void *m_pIO_opaque;
+
+    mz_zip_internal_state *m_pState;
+
+} mz_zip_archive;
+
+typedef enum {
+    MZ_ZIP_FLAG_CASE_SENSITIVE                = 0x0100,
+    MZ_ZIP_FLAG_IGNORE_PATH                   = 0x0200,
+    MZ_ZIP_FLAG_COMPRESSED_DATA               = 0x0400,
+    MZ_ZIP_FLAG_DO_NOT_SORT_CENTRAL_DIRECTORY = 0x0800
+} mz_zip_flags;
+
+// ZIP archive reading
+
+// Inits a ZIP archive reader.
+// These functions read and validate the archive's central directory.
+mz_bool mz_zip_reader_init(mz_zip_archive *pZip, mz_uint64 size, mz_uint32 flags);
+mz_bool mz_zip_reader_init_mem(mz_zip_archive *pZip, const void *pMem, size_t size, mz_uint32 flags);
+
+#ifndef MINIZ_NO_STDIO
+mz_bool mz_zip_reader_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint32 flags);
+#endif
+
+// Returns the total number of files in the archive.
+mz_uint mz_zip_reader_get_num_files(mz_zip_archive *pZip);
+
+// Returns detailed information about an archive file entry.
+mz_bool mz_zip_reader_file_stat(mz_zip_archive *pZip, mz_uint file_index, mz_zip_archive_file_stat *pStat);
+
+// Determines if an archive file entry is a directory entry.
+mz_bool mz_zip_reader_is_file_a_directory(mz_zip_archive *pZip, mz_uint file_index);
+mz_bool mz_zip_reader_is_file_encrypted(mz_zip_archive *pZip, mz_uint file_index);
+
+// Retrieves the filename of an archive file entry.
+// Returns the number of bytes written to pFilename, or if filename_buf_size is 0 this function returns the number of bytes needed to fully store the filename.
+mz_uint mz_zip_reader_get_filename(mz_zip_archive *pZip, mz_uint file_index, char *pFilename, mz_uint filename_buf_size);
+
+// Attempts to locates a file in the archive's central directory.
+// Valid flags: MZ_ZIP_FLAG_CASE_SENSITIVE, MZ_ZIP_FLAG_IGNORE_PATH
+// Returns -1 if the file cannot be found.
+int mz_zip_reader_locate_file(mz_zip_archive *pZip, const char *pName, const char *pComment, mz_uint flags);
+
+// Extracts a archive file to a memory buffer using no memory allocation.
+mz_bool mz_zip_reader_extract_to_mem_no_alloc(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
+mz_bool mz_zip_reader_extract_file_to_mem_no_alloc(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags, void *pUser_read_buf, size_t user_read_buf_size);
+
+// Extracts a archive file to a memory buffer.
+mz_bool mz_zip_reader_extract_to_mem(mz_zip_archive *pZip, mz_uint file_index, void *pBuf, size_t buf_size, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_mem(mz_zip_archive *pZip, const char *pFilename, void *pBuf, size_t buf_size, mz_uint flags);
+
+// Extracts a archive file to a dynamically allocated heap buffer.
+void *mz_zip_reader_extract_to_heap(mz_zip_archive *pZip, mz_uint file_index, size_t *pSize, mz_uint flags);
+void *mz_zip_reader_extract_file_to_heap(mz_zip_archive *pZip, const char *pFilename, size_t *pSize, mz_uint flags);
+
+// Extracts a archive file using a callback function to output the file's data.
+mz_bool mz_zip_reader_extract_to_callback(mz_zip_archive *pZip, mz_uint file_index, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_callback(mz_zip_archive *pZip, const char *pFilename, mz_file_write_func pCallback, void *pOpaque, mz_uint flags);
+
+#ifndef MINIZ_NO_STDIO
+// Extracts a archive file to a disk file and sets its last accessed and modified times.
+// This function only extracts files, not archive directory records.
+mz_bool mz_zip_reader_extract_to_file(mz_zip_archive *pZip, mz_uint file_index, const char *pDst_filename, mz_uint flags);
+mz_bool mz_zip_reader_extract_file_to_file(mz_zip_archive *pZip, const char *pArchive_filename, const char *pDst_filename, mz_uint flags);
+#endif
+
+// Ends archive reading, freeing all allocations, and closing the input archive file if mz_zip_reader_init_file() was used.
+mz_bool mz_zip_reader_end(mz_zip_archive *pZip);
+
+// ZIP archive writing
+
+#ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
+
+// Inits a ZIP archive writer.
+mz_bool mz_zip_writer_init(mz_zip_archive *pZip, mz_uint64 existing_size);
+mz_bool mz_zip_writer_init_heap(mz_zip_archive *pZip, size_t size_to_reserve_at_beginning, size_t initial_allocation_size);
+
+#ifndef MINIZ_NO_STDIO
+mz_bool mz_zip_writer_init_file(mz_zip_archive *pZip, const char *pFilename, mz_uint64 size_to_reserve_at_beginning);
+#endif
+
+// Converts a ZIP archive reader object into a writer object, to allow efficient in-place file appends to occur on an existing archive.
+// For archives opened using mz_zip_reader_init_file, pFilename must be the archive's filename so it can be reopened for writing. If the file can't be reopened, mz_zip_reader_end() will be called.
+// For archives opened using mz_zip_reader_init_mem, the memory block must be growable using the realloc callback (which defaults to realloc unless you've overridden it).
+// Finally, for archives opened using mz_zip_reader_init, the mz_zip_archive's user provided m_pWrite function cannot be NULL.
+// Note: In-place archive modification is not recommended unless you know what you're doing, because if execution stops or something goes wrong before
+// the archive is finalized the file's central directory will be hosed.
+mz_bool mz_zip_writer_init_from_reader(mz_zip_archive *pZip, const char *pFilename);
+
+// Adds the contents of a memory buffer to an archive. These functions record the current local time into the archive.
+// To add a directory entry, call this method with an archive name ending in a forwardslash with empty buffer.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_writer_add_mem(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, mz_uint level_and_flags);
+mz_bool mz_zip_writer_add_mem_ex(mz_zip_archive *pZip, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags, mz_uint64 uncomp_size, mz_uint32 uncomp_crc32);
+
+#ifndef MINIZ_NO_STDIO
+// Adds the contents of a disk file to an archive. This function also records the disk file's modified time into the archive.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_writer_add_file(mz_zip_archive *pZip, const char *pArchive_name, const char *pSrc_filename, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
+#endif
+
+// Adds a file to an archive by fully cloning the data from another archive.
+// This function fully clones the source file's compressed data (no recompression), along with its full filename, extra data, and comment fields.
+mz_bool mz_zip_writer_add_from_zip_reader(mz_zip_archive *pZip, mz_zip_archive *pSource_zip, mz_uint file_index);
+
+// Finalizes the archive by writing the central directory records followed by the end of central directory record.
+// After an archive is finalized, the only valid call on the mz_zip_archive struct is mz_zip_writer_end().
+// An archive must be manually finalized by calling this function for it to be valid.
+mz_bool mz_zip_writer_finalize_archive(mz_zip_archive *pZip);
+mz_bool mz_zip_writer_finalize_heap_archive(mz_zip_archive *pZip, void **pBuf, size_t *pSize);
+
+// Ends archive writing, freeing all allocations, and closing the output file if mz_zip_writer_init_file() was used.
+// Note for the archive to be valid, it must have been finalized before ending.
+mz_bool mz_zip_writer_end(mz_zip_archive *pZip);
+
+// Misc. high-level helper functions:
+
+// mz_zip_add_mem_to_archive_file_in_place() efficiently (but not atomically) appends a memory blob to a ZIP archive.
+// level_and_flags - compression level (0-10, see MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc.) logically OR'd with zero or more mz_zip_flags, or just set to MZ_DEFAULT_COMPRESSION.
+mz_bool mz_zip_add_mem_to_archive_file_in_place(const char *pZip_filename, const char *pArchive_name, const void *pBuf, size_t buf_size, const void *pComment, mz_uint16 comment_size, mz_uint level_and_flags);
+
+// Reads a single file from an archive into a heap block.
+// Returns NULL on failure.
+void *mz_zip_extract_archive_file_to_heap(const char *pZip_filename, const char *pArchive_name, size_t *pSize, mz_uint zip_flags);
+
+#endif // #ifndef MINIZ_NO_ARCHIVE_WRITING_APIS
+
+#endif // #ifndef MINIZ_NO_ARCHIVE_APIS
+
+// ------------------- Low-level Decompression API Definitions
+
+// Decompression flags used by tinfl_decompress().
+// TINFL_FLAG_PARSE_ZLIB_HEADER: If set, the input has a valid zlib header and ends with an adler32 checksum (it's a valid zlib stream). Otherwise, the input is a raw deflate stream.
+// TINFL_FLAG_HAS_MORE_INPUT: If set, there are more input bytes available beyond the end of the supplied input buffer. If clear, the input buffer contains all remaining input.
+// TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF: If set, the output buffer is large enough to hold the entire decompressed stream. If clear, the output buffer is at least the size of the dictionary (typically 32KB).
+// TINFL_FLAG_COMPUTE_ADLER32: Force adler-32 checksum computation of the decompressed bytes.
+enum {
+    TINFL_FLAG_PARSE_ZLIB_HEADER = 1,
+    TINFL_FLAG_HAS_MORE_INPUT = 2,
+    TINFL_FLAG_USING_NON_WRAPPING_OUTPUT_BUF = 4,
+    TINFL_FLAG_COMPUTE_ADLER32 = 8
+};
+
+// High level decompression functions:
+// tinfl_decompress_mem_to_heap() decompresses a block in memory to a heap block allocated via malloc().
+// On entry:
+//  pSrc_buf, src_buf_len: Pointer and size of the Deflate or zlib source data to decompress.
+// On return:
+//  Function returns a pointer to the decompressed data, or NULL on failure.
+//  *pOut_len will be set to the decompressed data's size, which could be larger than src_buf_len on uncompressible data.
+//  The caller must call mz_free() on the returned block when it's no longer needed.
+void *tinfl_decompress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
+
+// tinfl_decompress_mem_to_mem() decompresses a block in memory to another block in memory.
+// Returns TINFL_DECOMPRESS_MEM_TO_MEM_FAILED on failure, or the number of bytes written on success.
+#define TINFL_DECOMPRESS_MEM_TO_MEM_FAILED ((size_t)(-1))
+size_t tinfl_decompress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
+
+// tinfl_decompress_mem_to_callback() decompresses a block in memory to an internal 32KB buffer, and a user provided callback function will be called to flush the buffer.
+// Returns 1 on success or 0 on failure.
+typedef int (*tinfl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser);
+int tinfl_decompress_mem_to_callback(const void *pIn_buf, size_t *pIn_buf_size, tinfl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+struct tinfl_decompressor_tag; typedef struct tinfl_decompressor_tag tinfl_decompressor;
+
+// Max size of LZ dictionary.
+#define TINFL_LZ_DICT_SIZE 32768
+
+// Return status.
+typedef enum {
+    TINFL_STATUS_BAD_PARAM = -3,
+    TINFL_STATUS_ADLER32_MISMATCH = -2,
+    TINFL_STATUS_FAILED = -1,
+    TINFL_STATUS_DONE = 0,
+    TINFL_STATUS_NEEDS_MORE_INPUT = 1,
+    TINFL_STATUS_HAS_MORE_OUTPUT = 2
+} tinfl_status;
+
+// Initializes the decompressor to its initial state.
+#define tinfl_init(r) do { (r)->m_state = 0; } MZ_MACRO_END
+#define tinfl_get_adler32(r) (r)->m_check_adler32
+
+// Main low-level decompressor coroutine function. This is the only function actually needed for decompression. All the other functions are just high-level helpers for improved usability.
+// This is a universal API, i.e. it can be used as a building block to build any desired higher level decompression API. In the limit case, it can be called once per every byte input or output.
+tinfl_status tinfl_decompress(tinfl_decompressor *r, const mz_uint8 *pIn_buf_next, size_t *pIn_buf_size, mz_uint8 *pOut_buf_start, mz_uint8 *pOut_buf_next, size_t *pOut_buf_size, const mz_uint32 decomp_flags);
+
+// Internal/private bits follow.
+enum {
+    TINFL_MAX_HUFF_TABLES = 3, TINFL_MAX_HUFF_SYMBOLS_0 = 288, TINFL_MAX_HUFF_SYMBOLS_1 = 32, TINFL_MAX_HUFF_SYMBOLS_2 = 19,
+    TINFL_FAST_LOOKUP_BITS = 10, TINFL_FAST_LOOKUP_SIZE = 1 << TINFL_FAST_LOOKUP_BITS
+};
+
+typedef struct {
+    mz_uint8 m_code_size[TINFL_MAX_HUFF_SYMBOLS_0];
+    mz_int16 m_look_up[TINFL_FAST_LOOKUP_SIZE], m_tree[TINFL_MAX_HUFF_SYMBOLS_0 * 2];
+} tinfl_huff_table;
+
+#if MINIZ_HAS_64BIT_REGISTERS
+#define TINFL_USE_64BIT_BITBUF 1
+#endif
+
+#if TINFL_USE_64BIT_BITBUF
+typedef mz_uint64 tinfl_bit_buf_t;
+#define TINFL_BITBUF_SIZE (64)
+#else
+typedef mz_uint32 tinfl_bit_buf_t;
+#define TINFL_BITBUF_SIZE (32)
+#endif
+
+struct tinfl_decompressor_tag {
+    mz_uint32 m_state, m_num_bits, m_zhdr0, m_zhdr1, m_z_adler32, m_final, m_type, m_check_adler32, m_dist, m_counter, m_num_extra, m_table_sizes[TINFL_MAX_HUFF_TABLES];
+    tinfl_bit_buf_t m_bit_buf;
+    size_t m_dist_from_out_buf_start;
+    tinfl_huff_table m_tables[TINFL_MAX_HUFF_TABLES];
+    mz_uint8 m_raw_header[4], m_len_codes[TINFL_MAX_HUFF_SYMBOLS_0 + TINFL_MAX_HUFF_SYMBOLS_1 + 137];
+};
+
+// ------------------- Low-level Compression API Definitions
+
+// Set TDEFL_LESS_MEMORY to 1 to use less memory (compression will be slightly slower, and raw/dynamic blocks will be output more frequently).
+#define TDEFL_LESS_MEMORY 1
+
+// tdefl_init() compression flags logically OR'd together (low 12 bits contain the max. number of probes per dictionary search):
+// TDEFL_DEFAULT_MAX_PROBES: The compressor defaults to 128 dictionary probes per dictionary search. 0=Huffman only, 1=Huffman+LZ (fastest/crap compression), 4095=Huffman+LZ (slowest/best compression).
+enum {
+    TDEFL_HUFFMAN_ONLY = 0, TDEFL_DEFAULT_MAX_PROBES = 128, TDEFL_MAX_PROBES_MASK = 0xFFF
+};
+
+// TDEFL_WRITE_ZLIB_HEADER: If set, the compressor outputs a zlib header before the deflate data, and the Adler-32 of the source data at the end. Otherwise, you'll get raw deflate data.
+// TDEFL_COMPUTE_ADLER32: Always compute the adler-32 of the input data (even when not writing zlib headers).
+// TDEFL_GREEDY_PARSING_FLAG: Set to use faster greedy parsing, instead of more efficient lazy parsing.
+// TDEFL_NONDETERMINISTIC_PARSING_FLAG: Enable to decrease the compressor's initialization time to the minimum, but the output may vary from run to run given the same input (depending on the contents of memory).
+// TDEFL_RLE_MATCHES: Only look for RLE matches (matches with a distance of 1)
+// TDEFL_FILTER_MATCHES: Discards matches <= 5 chars if enabled.
+// TDEFL_FORCE_ALL_STATIC_BLOCKS: Disable usage of optimized Huffman tables.
+// TDEFL_FORCE_ALL_RAW_BLOCKS: Only use raw (uncompressed) deflate blocks.
+// The low 12 bits are reserved to control the max # of hash probes per dictionary lookup (see TDEFL_MAX_PROBES_MASK).
+enum {
+    TDEFL_WRITE_ZLIB_HEADER             = 0x01000,
+    TDEFL_COMPUTE_ADLER32               = 0x02000,
+    TDEFL_GREEDY_PARSING_FLAG           = 0x04000,
+    TDEFL_NONDETERMINISTIC_PARSING_FLAG = 0x08000,
+    TDEFL_RLE_MATCHES                   = 0x10000,
+    TDEFL_FILTER_MATCHES                = 0x20000,
+    TDEFL_FORCE_ALL_STATIC_BLOCKS       = 0x40000,
+    TDEFL_FORCE_ALL_RAW_BLOCKS          = 0x80000
+};
+
+// High level compression functions:
+// tdefl_compress_mem_to_heap() compresses a block in memory to a heap block allocated via malloc().
+// On entry:
+//  pSrc_buf, src_buf_len: Pointer and size of source block to compress.
+//  flags: The max match finder probes (default is 128) logically OR'd against the above flags. Higher probes are slower but improve compression.
+// On return:
+//  Function returns a pointer to the compressed data, or NULL on failure.
+//  *pOut_len will be set to the compressed data's size, which could be larger than src_buf_len on uncompressible data.
+//  The caller must free() the returned block when it's no longer needed.
+void *tdefl_compress_mem_to_heap(const void *pSrc_buf, size_t src_buf_len, size_t *pOut_len, int flags);
+
+// tdefl_compress_mem_to_mem() compresses a block in memory to another block in memory.
+// Returns 0 on failure.
+size_t tdefl_compress_mem_to_mem(void *pOut_buf, size_t out_buf_len, const void *pSrc_buf, size_t src_buf_len, int flags);
+
+// Compresses an image to a compressed PNG file in memory.
+// On entry:
+//  pImage, w, h, and num_chans describe the image to compress. num_chans may be 1, 2, 3, or 4.
+//  The image pitch in bytes per scanline will be w*num_chans. The leftmost pixel on the top scanline is stored first in memory.
+//  level may range from [0,10], use MZ_NO_COMPRESSION, MZ_BEST_SPEED, MZ_BEST_COMPRESSION, etc. or a decent default is MZ_DEFAULT_LEVEL
+//  If flip is true, the image will be flipped on the Y axis (useful for OpenGL apps).
+// On return:
+//  Function returns a pointer to the compressed data, or NULL on failure.
+//  *pLen_out will be set to the size of the PNG image file.
+//  The caller must mz_free() the returned heap block (which will typically be larger than *pLen_out) when it's no longer needed.
+void *tdefl_write_image_to_png_file_in_memory_ex(const void *pImage, int w, int h, int num_chans, size_t *pLen_out, mz_uint level, mz_bool flip);
+void *tdefl_write_image_to_png_file_in_memory(const void *pImage, int w, int h, int num_chans, size_t *pLen_out);
+
+// Output stream interface. The compressor uses this interface to write compressed data. It'll typically be called TDEFL_OUT_BUF_SIZE at a time.
+typedef mz_bool (*tdefl_put_buf_func_ptr)(const void *pBuf, int len, void *pUser);
+
+// tdefl_compress_mem_to_output() compresses a block to an output stream. The above helpers use this function internally.
+mz_bool tdefl_compress_mem_to_output(const void *pBuf, size_t buf_len, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+enum { TDEFL_MAX_HUFF_TABLES = 3, TDEFL_MAX_HUFF_SYMBOLS_0 = 288, TDEFL_MAX_HUFF_SYMBOLS_1 = 32, TDEFL_MAX_HUFF_SYMBOLS_2 = 19, TDEFL_LZ_DICT_SIZE = 32768, TDEFL_LZ_DICT_SIZE_MASK = TDEFL_LZ_DICT_SIZE - 1, TDEFL_MIN_MATCH_LEN = 3, TDEFL_MAX_MATCH_LEN = 258 };
+
+// TDEFL_OUT_BUF_SIZE MUST be large enough to hold a single entire compressed output block (using static/fixed Huffman codes).
+#if TDEFL_LESS_MEMORY
+enum { TDEFL_LZ_CODE_BUF_SIZE = 24 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 12, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
+#else
+enum { TDEFL_LZ_CODE_BUF_SIZE = 64 * 1024, TDEFL_OUT_BUF_SIZE = (TDEFL_LZ_CODE_BUF_SIZE * 13 ) / 10, TDEFL_MAX_HUFF_SYMBOLS = 288, TDEFL_LZ_HASH_BITS = 15, TDEFL_LEVEL1_HASH_SIZE_MASK = 4095, TDEFL_LZ_HASH_SHIFT = (TDEFL_LZ_HASH_BITS + 2) / 3, TDEFL_LZ_HASH_SIZE = 1 << TDEFL_LZ_HASH_BITS };
+#endif
+
+// The low-level tdefl functions below may be used directly if the above helper functions aren't flexible enough. The low-level functions don't make any heap allocations, unlike the above helper functions.
+typedef enum {
+    TDEFL_STATUS_BAD_PARAM = -2,
+    TDEFL_STATUS_PUT_BUF_FAILED = -1,
+    TDEFL_STATUS_OKAY = 0,
+    TDEFL_STATUS_DONE = 1,
+} tdefl_status;
+
+// Must map to MZ_NO_FLUSH, MZ_SYNC_FLUSH, etc. enums
+typedef enum {
+    TDEFL_NO_FLUSH = 0,
+    TDEFL_SYNC_FLUSH = 2,
+    TDEFL_FULL_FLUSH = 3,
+    TDEFL_FINISH = 4
+} tdefl_flush;
+
+// tdefl's compression state structure.
+typedef struct {
+    tdefl_put_buf_func_ptr m_pPut_buf_func;
+    void *m_pPut_buf_user;
+    mz_uint m_flags, m_max_probes[2];
+    int m_greedy_parsing;
+    mz_uint m_adler32, m_lookahead_pos, m_lookahead_size, m_dict_size;
+    mz_uint8 *m_pLZ_code_buf, *m_pLZ_flags, *m_pOutput_buf, *m_pOutput_buf_end;
+    mz_uint m_num_flags_left, m_total_lz_bytes, m_lz_code_buf_dict_pos, m_bits_in, m_bit_buffer;
+    mz_uint m_saved_match_dist, m_saved_match_len, m_saved_lit, m_output_flush_ofs, m_output_flush_remaining, m_finished, m_block_index, m_wants_to_finish;
+    tdefl_status m_prev_return_status;
+    const void *m_pIn_buf;
+    void *m_pOut_buf;
+    size_t *m_pIn_buf_size, *m_pOut_buf_size;
+    tdefl_flush m_flush;
+    const mz_uint8 *m_pSrc;
+    size_t m_src_buf_left, m_out_buf_ofs;
+    mz_uint8 m_dict[TDEFL_LZ_DICT_SIZE + TDEFL_MAX_MATCH_LEN - 1];
+    mz_uint16 m_huff_count[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+    mz_uint16 m_huff_codes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+    mz_uint8 m_huff_code_sizes[TDEFL_MAX_HUFF_TABLES][TDEFL_MAX_HUFF_SYMBOLS];
+    mz_uint8 m_lz_code_buf[TDEFL_LZ_CODE_BUF_SIZE];
+    mz_uint16 m_next[TDEFL_LZ_DICT_SIZE];
+    mz_uint16 m_hash[TDEFL_LZ_HASH_SIZE];
+    mz_uint8 m_output_buf[TDEFL_OUT_BUF_SIZE];
+} tdefl_compressor;
+
+// Initializes the compressor.
+// There is no corresponding deinit() function because the tdefl API's do not dynamically allocate memory.
+// pBut_buf_func: If NULL, output data will be supplied to the specified callback. In this case, the user should call the tdefl_compress_buffer() API for compression.
+// If pBut_buf_func is NULL the user should always call the tdefl_compress() API.
+// flags: See the above enums (TDEFL_HUFFMAN_ONLY, TDEFL_WRITE_ZLIB_HEADER, etc.)
+tdefl_status tdefl_init(tdefl_compressor *d, tdefl_put_buf_func_ptr pPut_buf_func, void *pPut_buf_user, int flags);
+
+// Compresses a block of data, consuming as much of the specified input buffer as possible, and writing as much compressed data to the specified output buffer as possible.
+tdefl_status tdefl_compress(tdefl_compressor *d, const void *pIn_buf, size_t *pIn_buf_size, void *pOut_buf, size_t *pOut_buf_size, tdefl_flush flush);
+
+// tdefl_compress_buffer() is only usable when the tdefl_init() is called with a non-NULL tdefl_put_buf_func_ptr.
+// tdefl_compress_buffer() always consumes the entire input buffer.
+tdefl_status tdefl_compress_buffer(tdefl_compressor *d, const void *pIn_buf, size_t in_buf_size, tdefl_flush flush);
+
+tdefl_status tdefl_get_prev_return_status(tdefl_compressor *d);
+mz_uint32 tdefl_get_adler32(tdefl_compressor *d);
+
+// Can't use tdefl_create_comp_flags_from_zip_params if MINIZ_NO_ZLIB_APIS isn't defined, because it uses some of its macros.
+#ifndef MINIZ_NO_ZLIB_APIS
+// Create tdefl_compress() flags given zlib-style compression parameters.
+// level may range from [0,10] (where 10 is absolute max compression, but may be much slower on some files)
+// window_bits may be -15 (raw deflate) or 15 (zlib)
+// strategy may be either MZ_DEFAULT_STRATEGY, MZ_FILTERED, MZ_HUFFMAN_ONLY, MZ_RLE, or MZ_FIXED
+mz_uint tdefl_create_comp_flags_from_zip_params(int level, int window_bits, int strategy);
+#endif // #ifndef MINIZ_NO_ZLIB_APIS
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // MINIZ_HEADER_INCLUDED
diff --git a/components/esp_rom/include/esp8684/rom/newlib.h b/components/esp_rom/include/esp8684/rom/newlib.h
new file mode 100644
index 0000000000000000000000000000000000000000..e812d1319b928d1be0aa7c127f74a6921e9478b3
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/newlib.h
@@ -0,0 +1,42 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <sys/lock.h>
+#include <sys/reent.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Global variables used by newlib in ROM
+
+   Note that any of these symbols which are used by both ROM & IDF will have duplicate copies
+   in each "side" of the memory. However they're all pointers, and the pointers will be to the same
+   thing, so it's not a big memory waste and functionality is the same.
+
+   Some variables which look like they should be here, but aren't:
+
+   - __sf_fake_stdin, __sf_fake_stdout, __sf_fake_stderr - These are defined in ROM because ROM includes findfp.c,
+   but only used if _REENT_INIT or _REENT_INIT_PTR are ever called and ROM doesn't use these macros anywhere unless
+   printf() or similar is called without initializing reent first. ESP-IDF sets up its own minimal reent structures.
+
+   - __lock___sinit_recursive_mutex, etc. - these are combined into common_recursive_mutex & common_mutex to save space
+*/
+typedef struct {
+    _LOCK_T common_recursive_mutex;
+    _LOCK_T common_mutex;
+    struct _reent *global_reent;
+} esp_rom_newlib_global_data_t;
+
+/* Called from IDF newlib component setup
+   to initialize common data shared between ROM and IDF
+*/
+void esp_rom_newlib_init_global_data(const esp_rom_newlib_global_data_t *data);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_rom/include/esp8684/rom/rom_layout.h b/components/esp_rom/include/esp8684/rom/rom_layout.h
new file mode 100644
index 0000000000000000000000000000000000000000..9142867ae8d4a8a4c8d69e0ed5797e86ed64cf57
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/rom_layout.h
@@ -0,0 +1,78 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SUPPORT_BTDM            1
+#define SUPPORT_WIFI            1
+
+/* Structure and functions for returning ROM global layout
+ *
+ * This is for address symbols defined in the linker script, which may change during ECOs.
+ */
+typedef struct {
+    void *dram0_stack_shared_mem_start;
+    void *dram0_rtos_reserved_start;
+    void *stack_sentry;
+    void *stack;
+    void *stack_sentry_app;
+    void *stack_app;
+
+    /* BTDM data */
+    void *data_start_btdm;
+    void *data_end_btdm;
+    void *bss_start_btdm;
+    void *bss_end_btdm;
+    void *data_start_btdm_rom;
+    void *data_end_btdm_rom;
+    void *data_start_interface_btdm;
+    void *data_end_interface_btdm;
+    void *bss_start_interface_btdm;
+    void *bss_end_interface_btdm;
+
+    /* Other DRAM ranges */
+#if SUPPORT_BTDM || SUPPORT_WIFI
+    void *dram_start_phyrom;
+    void *dram_end_phyrom;
+#endif
+#if SUPPORT_WIFI
+    void *dram_start_coexist;
+    void *dram_end_coexist;
+    void *dram_start_net80211;
+    void *dram_end_net80211;
+    void *dram_start_pp;
+    void *dram_end_pp;
+    void *data_start_interface_coexist;
+    void *data_end_interface_coexist;
+    void *bss_start_interface_coexist;
+    void *bss_end_interface_coexist;
+    void *data_start_interface_net80211;
+    void *data_end_interface_net80211;
+    void *bss_start_interface_net80211;
+    void *bss_end_interface_net80211;
+    void *data_start_interface_pp;
+    void *data_end_interface_pp;
+    void *bss_start_interface_pp;
+    void *bss_end_interface_pp;
+#endif
+    void *dram_start_usbdev_rom;
+    void *dram_end_usbdev_rom;
+    void *dram_start_uart_rom;
+    void *dram_end_uart_rom;
+
+} ets_rom_layout_t;
+
+extern const ets_rom_layout_t * const ets_rom_layout_p;
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/components/esp_rom/include/esp8684/rom/rsa_pss.h b/components/esp_rom/include/esp8684/rom/rsa_pss.h
new file mode 100644
index 0000000000000000000000000000000000000000..366ffb7bcd13d73b9a52db071a5ad9437a62a06c
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/rsa_pss.h
@@ -0,0 +1,38 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_RSA_PSS_H_
+#define _ROM_RSA_PSS_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ETS_SIG_LEN 384 /* Bytes */
+#define ETS_DIGEST_LEN 32 /* SHA-256, bytes */
+
+typedef struct {
+    uint8_t n[384]; /* Public key modulus */
+    uint32_t e;     /* Public key exponent */
+    uint8_t rinv[384];
+    uint32_t mdash;
+} ets_rsa_pubkey_t;
+
+bool ets_rsa_pss_verify(const ets_rsa_pubkey_t *key, const uint8_t *sig, const uint8_t *digest, uint8_t *verified_digest);
+
+void ets_mgf1_sha256(const uint8_t *mgfSeed, size_t seedLen, size_t maskLen, uint8_t *mask);
+
+bool ets_emsa_pss_verify(const uint8_t *encoded_message, const uint8_t *mhash);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/components/esp_rom/include/esp8684/rom/rtc.h b/components/esp_rom/include/esp8684/rom/rtc.h
new file mode 100644
index 0000000000000000000000000000000000000000..258a1ecbec1dca4b436b5ff4cf3413b7ad1ab7a0
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/rtc.h
@@ -0,0 +1,231 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_RTC_H_
+#define _ROM_RTC_H_
+
+#include "ets_sys.h"
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup rtc_apis, rtc registers and memory related apis
+  * @brief rtc apis
+  */
+
+/** @addtogroup rtc_apis
+  * @{
+  */
+
+/**************************************************************************************
+  *                                       Note:                                       *
+  *       Some Rtc memory and registers are used, in ROM or in internal library.      *
+  *          Please do not use reserved or used rtc memory or registers.              *
+  *                                                                                   *
+  *************************************************************************************
+  *                          RTC  Memory & Store Register usage
+  *************************************************************************************
+  *     rtc memory addr         type    size            usage
+  *     0x3f421000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
+  *     0x3f421000+SIZE_CP      Slow    8192-SIZE_CP
+  *
+  *     0x3ff80000(0x40070000)  Fast    8192            deep sleep entry code
+  *
+  *************************************************************************************
+  *     RTC store registers     usage
+  *     RTC_CNTL_STORE0_REG     Reserved
+  *     RTC_CNTL_STORE1_REG     RTC_SLOW_CLK calibration value
+  *     RTC_CNTL_STORE2_REG     Boot time, low word
+  *     RTC_CNTL_STORE3_REG     Boot time, high word
+  *     RTC_CNTL_STORE4_REG     External XTAL frequency
+  *     RTC_CNTL_STORE5_REG     APB bus frequency
+  *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
+  *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
+  *************************************************************************************
+  */
+
+#define RTC_SLOW_CLK_CAL_REG    RTC_CNTL_STORE1_REG
+#define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
+#define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
+#define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
+#define RTC_APB_FREQ_REG        RTC_CNTL_STORE5_REG
+#define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
+#define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
+#define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
+
+#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
+
+
+typedef enum {
+    AWAKE = 0,             //<CPU ON
+    LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
+    DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
+} SLEEP_MODE;
+
+typedef enum {
+    NO_MEAN                =  0,
+    POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
+    RTC_SW_SYS_RESET       =  3,    /**<3, Software reset digital core*/
+    DEEPSLEEP_RESET        =  5,    /**<3, Deep Sleep reset digital core*/
+    SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core*/
+    TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
+    TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
+    RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
+    INTRUSION_RESET        = 10,    /**<10, Instrusion tested to reset CPU*/
+    TG0WDT_CPU_RESET       = 11,    /**<11, Time Group0 reset CPU*/
+    RTC_SW_CPU_RESET       = 12,    /**<12, Software reset CPU*/
+    RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
+    RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
+    RTCWDT_RTC_RESET       = 16,    /**<16, RTC Watch dog reset digital core and rtc module*/
+    TG1WDT_CPU_RESET       = 17,    /**<11, Time Group1 reset CPU*/
+    SUPER_WDT_RESET        = 18,    /**<11, super watchdog reset digital core and rtc module*/
+} RESET_REASON;
+
+typedef enum {
+    NO_SLEEP        = 0,
+    EXT_EVENT0_TRIG = BIT0,
+    EXT_EVENT1_TRIG = BIT1,
+    GPIO_TRIG       = BIT2,
+    TIMER_EXPIRE    = BIT3,
+    SDIO_TRIG       = BIT4,
+    MAC_TRIG        = BIT5,
+    UART0_TRIG      = BIT6,
+    UART1_TRIG      = BIT7,
+    TOUCH_TRIG      = BIT8,
+    SAR_TRIG        = BIT9,
+    BT_TRIG         = BIT10,
+    RISCV_TRIG      = BIT11,
+    XTAL_DEAD_TRIG  = BIT12,
+    RISCV_TRAP_TRIG = BIT13,
+    USB_TRIG        = BIT14
+} WAKEUP_REASON;
+
+typedef enum {
+    DISEN_WAKEUP       = NO_SLEEP,
+    EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
+    EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
+    GPIO_TRIG_EN       = GPIO_TRIG,
+    TIMER_EXPIRE_EN    = TIMER_EXPIRE,
+    SDIO_TRIG_EN       = SDIO_TRIG,
+    MAC_TRIG_EN        = MAC_TRIG,
+    UART0_TRIG_EN      = UART0_TRIG,
+    UART1_TRIG_EN      = UART1_TRIG,
+    TOUCH_TRIG_EN      = TOUCH_TRIG,
+    SAR_TRIG_EN        = SAR_TRIG,
+    BT_TRIG_EN         = BT_TRIG,
+    RISCV_TRIG_EN      = RISCV_TRIG,
+    XTAL_DEAD_TRIG_EN  = XTAL_DEAD_TRIG,
+    RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG,
+    USB_TRIG_EN        = USB_TRIG
+} WAKEUP_ENABLE;
+
+/**
+  * @brief  Get the reset reason for CPU.
+  *
+  * @param  int cpu_no : CPU no.
+  *
+  * @return RESET_REASON
+  */
+RESET_REASON rtc_get_reset_reason(int cpu_no);
+
+/**
+  * @brief  Get the wakeup cause for CPU.
+  *
+  * @param  int cpu_no : CPU no.
+  *
+  * @return WAKEUP_REASON
+  */
+WAKEUP_REASON rtc_get_wakeup_cause(void);
+
+/**
+  * @brief Get CRC for Fast RTC Memory.
+  *
+  * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
+  *
+  * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
+  *
+  * @return uint32_t : CRC32 result
+  */
+uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
+
+/**
+  * @brief Suppress ROM log by setting specific RTC control register.
+  * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+static inline void rtc_suppress_rom_log(void)
+{
+    /* To disable logging in the ROM, only the least significant bit of the register is used,
+     * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
+     * you need to write to this register in the same format.
+     * Namely, the upper 16 bits and lower should be the same.
+     */
+    REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
+}
+
+/**
+  * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void set_rtc_memory_crc(void);
+
+/**
+  * @brief Fetch entry from RTC memory and RTC STORE reg
+  *
+  * @param uint32_t * entry_addr : the address to save entry
+  *
+  * @param RESET_REASON reset_reason : reset reason this time
+  *
+  * @return None
+  */
+void rtc_boot_control(uint32_t *entry_addr, RESET_REASON reset_reason);
+
+/**
+  * @brief Software Reset digital core.
+  *
+  * It is not recommended to use this function in esp-idf, use
+  * esp_restart() instead.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void software_reset(void);
+
+/**
+  * @brief Software Reset digital core.
+  *
+  * It is not recommended to use this function in esp-idf, use
+  * esp_restart() instead.
+  *
+  * @param  int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
+  *
+  * @return None
+  */
+void software_reset_cpu(int cpu_no);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_RTC_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/secure_boot.h b/components/esp_rom/include/esp8684/rom/secure_boot.h
new file mode 100644
index 0000000000000000000000000000000000000000..1b21ee8f113712d3c0839a4e63710458490b5654
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/secure_boot.h
@@ -0,0 +1,123 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_SECURE_BOOT_H_
+#define _ROM_SECURE_BOOT_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ets_sys.h"
+#include "rsa_pss.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ets_secure_boot_sig_block;
+struct ets_secure_boot_signature_t;
+
+typedef struct ets_secure_boot_sig_block ets_secure_boot_sig_block_t;
+typedef struct ets_secure_boot_signature ets_secure_boot_signature_t;
+typedef struct ets_secure_boot_key_digests ets_secure_boot_key_digests_t;
+
+/* Anti-FI measure: use full words for success/fail, instead of
+   0/non-zero
+*/
+typedef enum {
+    SB_SUCCESS = 0x3A5A5AA5,
+    SB_FAILED = 0x7533885E,
+} ets_secure_boot_status_t;
+
+
+/* Verify and stage-load the bootloader image
+   (reconfigures cache to map, loads trusted key digests from efuse,
+   copies the bootloader into the staging buffer.)
+
+   If allow_key_revoke is true and aggressive revoke efuse is set,
+   any failed signature has its associated key revoked in efuse.
+
+   If result is SB_SUCCESS, the "simple hash" of the bootloader
+   is copied into verified_hash.
+*/
+ets_secure_boot_status_t ets_secure_boot_verify_stage_bootloader(uint8_t *verified_hash, bool allow_key_revoke);
+
+/* Verify bootloader image (reconfigures cache to map),
+   with key digests provided as parameters.)
+
+   Can be used to verify secure boot status before enabling
+   secure boot permanently.
+
+   If stage_load parameter is true, bootloader is copied into staging
+   buffer in RAM at the same time.
+
+   If result is SB_SUCCESS, the "simple hash" of the bootloader is
+   copied into verified_hash.
+*/
+ets_secure_boot_status_t ets_secure_boot_verify_bootloader_with_keys(uint8_t *verified_hash, const ets_secure_boot_key_digests_t *trusted_keys, bool stage_load);
+
+/* Read key digests from efuse. Any revoked/missing digests will be
+   marked as NULL
+*/
+ETS_STATUS ets_secure_boot_read_key_digests(ets_secure_boot_key_digests_t *trusted_keys);
+
+/* Verify supplied signature against supplied digest, using
+   supplied trusted key digests.
+
+   Doesn't reconfigure cache or any other hardware access except for RSA peripheral.
+
+   If result is SB_SUCCESS, the image_digest value is copied into verified_digest.
+*/
+ets_secure_boot_status_t ets_secure_boot_verify_signature(const ets_secure_boot_signature_t *sig, const uint8_t *image_digest, const ets_secure_boot_key_digests_t *trusted_keys, uint8_t *verified_digest);
+
+/* Revoke a public key digest in efuse.
+   @param index Digest to revoke. Must be 0, 1 or 2.
+ */
+void ets_secure_boot_revoke_public_key_digest(int index);
+
+#define CRC_SIGN_BLOCK_LEN 1196
+#define SIG_BLOCK_PADDING 4096
+#define ETS_SECURE_BOOT_V2_SIGNATURE_MAGIC 0xE7
+
+/* Secure Boot V2 signature block
+
+   (Up to 3 in a signature sector are appended to the image)
+ */
+struct ets_secure_boot_sig_block {
+    uint8_t magic_byte;
+    uint8_t version;
+    uint8_t _reserved1;
+    uint8_t _reserved2;
+    uint8_t image_digest[32];
+    ets_rsa_pubkey_t key;
+    uint8_t signature[384];
+    uint32_t block_crc;
+    uint8_t _padding[16];
+};
+
+_Static_assert(sizeof(ets_secure_boot_sig_block_t) == 1216, "invalid sig block size");
+
+#define SECURE_BOOT_NUM_BLOCKS 1
+
+/* V2 Secure boot signature sector (up to 3 blocks) */
+struct ets_secure_boot_signature {
+    ets_secure_boot_sig_block_t block[SECURE_BOOT_NUM_BLOCKS];
+    uint8_t _padding[4096 - (sizeof(ets_secure_boot_sig_block_t) * SECURE_BOOT_NUM_BLOCKS)];
+};
+
+_Static_assert(sizeof(ets_secure_boot_signature_t) == 4096, "invalid sig sector size");
+
+#define MAX_KEY_DIGESTS 1
+
+struct ets_secure_boot_key_digests {
+    const void *key_digests[MAX_KEY_DIGESTS];
+    bool allow_key_revoke;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SECURE_BOOT_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/sha.h b/components/esp_rom/include/esp8684/rom/sha.h
new file mode 100644
index 0000000000000000000000000000000000000000..06fa47873b87635d672387a199ce20489daf0d79
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/sha.h
@@ -0,0 +1,53 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef _ROM_SHA_H_
+#define _ROM_SHA_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ets_sys.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    SHA1 = 0,
+    SHA2_224,
+    SHA2_256,
+    SHA_TYPE_MAX
+} SHA_TYPE;
+
+typedef struct SHAContext {
+    bool start;
+    bool in_hardware;               // Is this context currently in peripheral? Needs to be manually cleared if multiple SHAs are interleaved
+    SHA_TYPE type;
+    uint32_t state[16];             // For SHA1/SHA224/SHA256, used 8, other used 16
+    unsigned char buffer[128];      // For SHA1/SHA224/SHA256, used 64, other used 128
+    uint32_t total_bits[4];
+} SHA_CTX;
+
+void ets_sha_enable(void);
+
+void ets_sha_disable(void);
+
+ets_status_t ets_sha_init(SHA_CTX *ctx, SHA_TYPE type);
+
+ets_status_t ets_sha_starts(SHA_CTX *ctx, uint16_t sha512_t);
+
+void ets_sha_get_state(SHA_CTX *ctx);
+
+void ets_sha_process(SHA_CTX *ctx, const unsigned char *input);
+
+void ets_sha_update(SHA_CTX *ctx, const unsigned char *input, uint32_t input_bytes, bool update_ctx);
+
+ets_status_t ets_sha_finish(SHA_CTX *ctx, unsigned char *output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SHA_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/spi_flash.h b/components/esp_rom/include/esp8684/rom/spi_flash.h
new file mode 100644
index 0000000000000000000000000000000000000000..ce536e4ff234b63c788d51e8ccf8c57f9dda58ba
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/spi_flash.h
@@ -0,0 +1,566 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_SPI_FLASH_H_
+#define _ROM_SPI_FLASH_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "esp_attr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup spi_flash_apis, spi flash operation related apis
+  * @brief spi_flash apis
+  */
+
+/** @addtogroup spi_flash_apis
+  * @{
+  */
+
+#define PERIPHS_SPI_FLASH_CMD                 SPI_MEM_CMD_REG(1)
+#define PERIPHS_SPI_FLASH_ADDR                SPI_MEM_ADDR_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL                SPI_MEM_CTRL_REG(1)
+#define PERIPHS_SPI_FLASH_CTRL1               SPI_MEM_CTRL1_REG(1)
+#define PERIPHS_SPI_FLASH_STATUS              SPI_MEM_RD_STATUS_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG              SPI_MEM_USER_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG1             SPI_MEM_USER1_REG(1)
+#define PERIPHS_SPI_FLASH_USRREG2             SPI_MEM_USER2_REG(1)
+#define PERIPHS_SPI_FLASH_C0                  SPI_MEM_W0_REG(1)
+#define PERIPHS_SPI_FLASH_C1                  SPI_MEM_W1_REG(1)
+#define PERIPHS_SPI_FLASH_C2                  SPI_MEM_W2_REG(1)
+#define PERIPHS_SPI_FLASH_C3                  SPI_MEM_W3_REG(1)
+#define PERIPHS_SPI_FLASH_C4                  SPI_MEM_W4_REG(1)
+#define PERIPHS_SPI_FLASH_C5                  SPI_MEM_W5_REG(1)
+#define PERIPHS_SPI_FLASH_C6                  SPI_MEM_W6_REG(1)
+#define PERIPHS_SPI_FLASH_C7                  SPI_MEM_W7_REG(1)
+#define PERIPHS_SPI_FLASH_TX_CRC              SPI_MEM_TX_CRC_REG(1)
+
+#define SPI0_R_QIO_DUMMY_CYCLELEN             5
+#define SPI0_R_QIO_ADDR_BITSLEN               23
+#define SPI0_R_FAST_DUMMY_CYCLELEN            7
+#define SPI0_R_DIO_DUMMY_CYCLELEN             3
+#define SPI0_R_FAST_ADDR_BITSLEN              23
+#define SPI0_R_SIO_ADDR_BITSLEN               23
+
+#define SPI1_R_QIO_DUMMY_CYCLELEN             5
+#define SPI1_R_QIO_ADDR_BITSLEN               23
+#define SPI1_R_FAST_DUMMY_CYCLELEN            7
+#define SPI1_R_DIO_DUMMY_CYCLELEN             3
+#define SPI1_R_DIO_ADDR_BITSLEN               23
+#define SPI1_R_FAST_ADDR_BITSLEN              23
+#define SPI1_R_SIO_ADDR_BITSLEN               23
+
+#define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN   23
+
+#define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN   SPI_MEM_WRSR_2B
+
+//SPI address register
+#define ESP_ROM_SPIFLASH_BYTES_LEN            24
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM  32
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM   16
+#define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS  0xf
+
+//SPI status register
+#define  ESP_ROM_SPIFLASH_BUSY_FLAG           BIT0
+#define  ESP_ROM_SPIFLASH_WRENABLE_FLAG       BIT1
+#define  ESP_ROM_SPIFLASH_BP0                 BIT2
+#define  ESP_ROM_SPIFLASH_BP1                 BIT3
+#define  ESP_ROM_SPIFLASH_BP2                 BIT4
+#define  ESP_ROM_SPIFLASH_WR_PROTECT          (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
+#define  ESP_ROM_SPIFLASH_QE                  BIT9
+
+#define FLASH_ID_GD25LQ32C  0xC86016
+
+typedef enum {
+    ESP_ROM_SPIFLASH_QIO_MODE = 0,
+    ESP_ROM_SPIFLASH_QOUT_MODE,
+    ESP_ROM_SPIFLASH_DIO_MODE,
+    ESP_ROM_SPIFLASH_DOUT_MODE,
+    ESP_ROM_SPIFLASH_FASTRD_MODE,
+    ESP_ROM_SPIFLASH_SLOWRD_MODE
+} esp_rom_spiflash_read_mode_t;
+
+typedef enum {
+    ESP_ROM_SPIFLASH_RESULT_OK,
+    ESP_ROM_SPIFLASH_RESULT_ERR,
+    ESP_ROM_SPIFLASH_RESULT_TIMEOUT
+} esp_rom_spiflash_result_t;
+
+typedef struct {
+    uint32_t device_id;
+    uint32_t chip_size;    // chip size in bytes
+    uint32_t block_size;
+    uint32_t sector_size;
+    uint32_t page_size;
+    uint32_t status_mask;
+} esp_rom_spiflash_chip_t;
+
+typedef struct {
+    uint8_t  data_length;
+    uint8_t  read_cmd0;
+    uint8_t  read_cmd1;
+    uint8_t  write_cmd;
+    uint16_t data_mask;
+    uint16_t data;
+} esp_rom_spiflash_common_cmd_t;
+
+/**
+  * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write).
+  *
+  * @param  uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv);
+
+/**
+  * @brief Select SPI Flash to QIO mode when WP pad is read from Flash.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t wp_gpio_num: WP gpio number.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @return None
+  */
+void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi);
+
+/**
+  * @brief Set SPI Flash pad drivers.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint8_t wp_gpio_num: WP gpio number.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @param  uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid
+  *            drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp.
+  *                        Values usually read from falsh by rom code, function usually callde by rom code.
+  *                        if value with bit(3) set, the value is valid, bit[2:0] is the real value.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs);
+
+/**
+  * @brief Select SPI Flash function for pads.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @return None
+  */
+void esp_rom_spiflash_select_padsfunc(uint32_t ishspi);
+
+/**
+  * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode.
+  *    Please do not call this function in SDK.
+  *
+  * @param  uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
+  *              else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
+  *
+  * @param  uint8_t legacy: In legacy mode, more SPI command is used in line.
+  *
+  * @return None
+  */
+void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy);
+
+/**
+  * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR).
+  *    Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t *status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status);
+
+/**
+  * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2).
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t *status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status);
+
+/**
+  * @brief Write status to Falsh status register.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t status_value : Value to .
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value);
+
+/**
+  * @brief Use a command to Read Flash status register.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file.
+  *
+  * @param  uint32_t*status : The pointer to which to return the Flash status value.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd);
+
+/**
+  * @brief Config SPI Flash read mode when init.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD.
+  *
+  * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode);
+
+/**
+  * @brief Config SPI Flash clock divisor.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t freqdiv: clock divisor.
+  *
+  * @param  uint8_t spi: 0 for SPI0, 1 for SPI1.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : config error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi);
+
+/**
+  * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD.
+  *        Please do not call this function in SDK.
+  *
+  * @param  esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command.
+  *
+  * @return uint16_t  0 : do not send command any more.
+  *                   1 : go to the next command.
+  *                   n > 1 : skip (n - 1) commands.
+  */
+uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd);
+
+/**
+  * @brief Unlock SPI write protect.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void);
+
+/**
+  * @brief SPI write protect.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Lock error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_lock(void);
+
+/**
+  * @brief Update SPI Flash parameter.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t deviceId : Device ID read from SPI, the low 32 bit.
+  *
+  * @param  uint32_t chip_size : The Flash size.
+  *
+  * @param  uint32_t block_size : The Flash block size.
+  *
+  * @param  uint32_t sector_size : The Flash sector size.
+  *
+  * @param  uint32_t page_size : The Flash page size.
+  *
+  * @param  uint32_t status_mask : The Mask used when read status from Flash(use single CMD).
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Update error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size,
+        uint32_t sector_size, uint32_t page_size, uint32_t status_mask);
+
+/**
+  * @brief Erase whole flash chip.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void);
+
+/**
+  * @brief Erase a 64KB block of flash
+  *        Uses SPI flash command D8H.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t block_num : Which block to erase.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num);
+
+/**
+  * @brief Erase a sector of flash.
+  *        Uses SPI flash command 20H.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t sector_num : Which sector to erase.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num);
+
+/**
+  * @brief Erase some sectors.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t start_addr : Start addr to erase, should be sector aligned.
+  *
+  * @param  uint32_t area_len : Length to erase, should be sector aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Erase error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len);
+
+/**
+  * @brief Write Data to Flash, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t dest_addr : Address to write, should be 4 bytes aligned.
+  *
+  * @param  const uint32_t *src : The pointer to data which is to write.
+  *
+  * @param  uint32_t len : Length to write, should be 4 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len);
+
+/**
+  * @brief Read Data from Flash, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t src_addr : Address to read, should be 4 bytes aligned.
+  *
+  * @param  uint32_t *dest : The buf to read the data.
+  *
+  * @param  uint32_t len : Length to read, should be 4 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Read error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len);
+
+/**
+  * @brief SPI1 go into encrypto mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void esp_rom_spiflash_write_encrypted_enable(void);
+
+/**
+  * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint32_t flash_addr : Address to write, should be 32 bytes aligned.
+  *
+  * @param  uint32_t *data : The pointer to data which is to write.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data);
+
+/**
+  * @brief SPI1 go out of encrypto mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return None
+  */
+void esp_rom_spiflash_write_encrypted_disable(void);
+
+/**
+  * @brief Write data to flash with transparent encryption.
+  * @note Sectors to be written should already be erased.
+  *
+  * @note Please do not call this function in SDK.
+  *
+  * @param  uint32_t flash_addr : Address to write, should be 32 byte aligned.
+  *
+  * @param  uint32_t *data : The pointer to data to write. Note, this pointer must
+  *                          be 32 bit aligned and the content of the data will be
+  *                          modified by the encryption function.
+  *
+  * @param  uint32_t len : Length to write, should be 32 bytes aligned.
+  *
+  * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully.
+  *         ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error.
+  *         ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout.
+  */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len);
+
+
+/* TODO: figure out how to map these to their new names */
+typedef enum {
+    SPI_ENCRYPT_DESTINATION_FLASH,
+} SpiEncryptDest;
+
+typedef esp_rom_spiflash_result_t SpiFlashOpResult;
+
+SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len);
+SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len);
+void SPI_Write_Encrypt_Enable(void);
+void SPI_Write_Encrypt_Disable(void);
+
+/** @brief Wait until SPI flash write operation is complete
+ *
+ * @note Please do not call this function in SDK.
+ *
+ * Reads the Write In Progress bit of the SPI flash status register,
+ * repeats until this bit is zero (indicating write complete).
+ *
+ * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete
+ *         ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status.
+ */
+esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi);
+
+
+/** @brief Enable Quad I/O pin functions
+ *
+ * @note Please do not call this function in SDK.
+ *
+ * Sets the HD & WP pin functions for Quad I/O modes, based on the
+ * efuse SPI pin configuration.
+ *
+ * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O.
+ *
+ * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig().
+ * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored.
+ * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored.
+ * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used
+ *   to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
+ *   Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
+ */
+void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig);
+
+
+typedef void (* spi_flash_func_t)(void);
+typedef SpiFlashOpResult (* spi_flash_op_t)(void);
+typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t);
+typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int);
+typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int);
+typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t);
+typedef SpiFlashOpResult (* spi_flash_wren_t)(void*);
+
+typedef struct {
+    uint8_t pp_addr_bit_len;
+    uint8_t se_addr_bit_len;
+    uint8_t be_addr_bit_len;
+    uint8_t rd_addr_bit_len;
+    uint32_t read_sub_len;
+    uint32_t write_sub_len;
+    spi_flash_op_t unlock;
+    spi_flash_erase_t erase_sector;
+    spi_flash_erase_t erase_block;
+    spi_flash_rd_t read;
+    spi_flash_wr_t write;
+    spi_flash_ewr_t encrypt_write;
+    spi_flash_func_t check_sus;
+    spi_flash_wren_t wren;
+    spi_flash_op_t wait_idle;
+} spiflash_legacy_funcs_t;
+
+
+extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs;
+
+/** @brief Global ROM spiflash data, as used by legacy
+    SPI flash functions
+*/
+typedef struct {
+    esp_rom_spiflash_chip_t chip;
+    uint8_t dummy_len_plus[3];
+    uint8_t sig_matrix;
+} spiflash_legacy_data_t;
+
+extern spiflash_legacy_data_t *rom_spiflash_legacy_data;
+
+/* Defines to make the C3 ROM legacvy data access compatible with previous chips */
+#define g_rom_flashchip (rom_spiflash_legacy_data->chip)
+#define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus)
+
+/**
+ * @brief Clear WEL bit unconditionally.
+ *
+ * @return always ESP_ROM_SPIFLASH_RESULT_OK
+ */
+esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void);
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_SPI_FLASH_H_ */
diff --git a/components/esp_rom/include/esp8684/rom/tjpgd.h b/components/esp_rom/include/esp8684/rom/tjpgd.h
new file mode 100644
index 0000000000000000000000000000000000000000..2a3f7f01c77f37801174a247ef892fad54661b8e
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/tjpgd.h
@@ -0,0 +1,104 @@
+/*
+ * SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*----------------------------------------------------------------------------/
+/ TJpgDec - Tiny JPEG Decompressor include file               (C)ChaN, 2012
+/----------------------------------------------------------------------------*/
+#ifndef _TJPGDEC
+#define _TJPGDEC
+/*---------------------------------------------------------------------------*/
+/* System Configurations */
+
+#define JD_SZBUF        512 /* Size of stream input buffer */
+#define JD_FORMAT       0   /* Output pixel format 0:RGB888 (3 BYTE/pix), 1:RGB565 (1 WORD/pix) */
+#define JD_USE_SCALE    1   /* Use descaling feature for output */
+#define JD_TBLCLIP      1   /* Use table for saturation (might be a bit faster but increases 1K bytes of code size) */
+
+/*---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int             INT;
+typedef unsigned int    UINT;
+
+/* These types must be 8-bit integer */
+typedef char            CHAR;
+typedef unsigned char   UCHAR;
+typedef unsigned char   BYTE;
+
+/* These types must be 16-bit integer */
+typedef short           SHORT;
+typedef unsigned short  USHORT;
+typedef unsigned short  WORD;
+typedef unsigned short  WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long            LONG;
+typedef unsigned long   ULONG;
+typedef unsigned long   DWORD;
+
+
+/* Error code */
+typedef enum {
+    JDR_OK = 0, /* 0: Succeeded */
+    JDR_INTR,   /* 1: Interrupted by output function */
+    JDR_INP,    /* 2: Device error or wrong termination of input stream */
+    JDR_MEM1,   /* 3: Insufficient memory pool for the image */
+    JDR_MEM2,   /* 4: Insufficient stream input buffer */
+    JDR_PAR,    /* 5: Parameter error */
+    JDR_FMT1,   /* 6: Data format error (may be damaged data) */
+    JDR_FMT2,   /* 7: Right format but not supported */
+    JDR_FMT3    /* 8: Not supported JPEG standard */
+} JRESULT;
+
+
+
+/* Rectangular structure */
+typedef struct {
+    WORD left, right, top, bottom;
+} JRECT;
+
+
+
+/* Decompressor object structure */
+typedef struct JDEC JDEC;
+struct JDEC {
+    UINT dctr;              /* Number of bytes available in the input buffer */
+    BYTE *dptr;             /* Current data read ptr */
+    BYTE *inbuf;            /* Bit stream input buffer */
+    BYTE dmsk;              /* Current bit in the current read byte */
+    BYTE scale;             /* Output scaling ratio */
+    BYTE msx, msy;          /* MCU size in unit of block (width, height) */
+    BYTE qtid[3];           /* Quantization table ID of each component */
+    SHORT dcv[3];           /* Previous DC element of each component */
+    WORD nrst;              /* Restart inverval */
+    UINT width, height;     /* Size of the input image (pixel) */
+    BYTE *huffbits[2][2];   /* Huffman bit distribution tables [id][dcac] */
+    WORD *huffcode[2][2];   /* Huffman code word tables [id][dcac] */
+    BYTE *huffdata[2][2];   /* Huffman decoded data tables [id][dcac] */
+    LONG *qttbl[4];         /* Dequaitizer tables [id] */
+    void *workbuf;          /* Working buffer for IDCT and RGB output */
+    BYTE *mcubuf;           /* Working buffer for the MCU */
+    void *pool;             /* Pointer to available memory pool */
+    UINT sz_pool;           /* Size of momory pool (bytes available) */
+    UINT (*infunc)(JDEC *, BYTE *, UINT); /* Pointer to jpeg stream input function */
+    void *device;           /* Pointer to I/O device identifiler for the session */
+};
+
+
+
+/* TJpgDec API functions */
+JRESULT jd_prepare (JDEC *, UINT(*)(JDEC *, BYTE *, UINT), void *, UINT, void *);
+JRESULT jd_decomp (JDEC *, UINT(*)(JDEC *, void *, JRECT *), BYTE);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TJPGDEC */
diff --git a/components/esp_rom/include/esp8684/rom/uart.h b/components/esp_rom/include/esp8684/rom/uart.h
new file mode 100644
index 0000000000000000000000000000000000000000..e72fec0b3b35c4096d39d9d179f38adafaae64e4
--- /dev/null
+++ b/components/esp_rom/include/esp8684/rom/uart.h
@@ -0,0 +1,432 @@
+/*
+ * SPDX-FileCopyrightText: 2020-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _ROM_UART_H_
+#define _ROM_UART_H_
+
+#include "esp_types.h"
+#include "esp_attr.h"
+#include "ets_sys.h"
+#include "soc/soc.h"
+#include "soc/uart_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \defgroup uart_apis, uart configuration and communication related apis
+  * @brief uart apis
+  */
+
+/** @addtogroup uart_apis
+  * @{
+  */
+
+#define RX_BUFF_SIZE                     0x400
+#define TX_BUFF_SIZE                     100
+
+//uart int enalbe register ctrl bits
+#define UART_RCV_INTEN                   BIT0
+#define UART_TRX_INTEN                   BIT1
+#define UART_LINE_STATUS_INTEN           BIT2
+
+//uart int identification ctrl bits
+#define UART_INT_FLAG_MASK               0x0E
+
+//uart fifo ctrl bits
+#define UART_CLR_RCV_FIFO                BIT1
+#define UART_CLR_TRX_FIFO                BIT2
+#define UART_RCVFIFO_TRG_LVL_BITS        BIT6
+
+//uart line control bits
+#define  UART_DIV_LATCH_ACCESS_BIT       BIT7
+
+//uart line status bits
+#define  UART_RCV_DATA_RDY_FLAG          BIT0
+#define  UART_RCV_OVER_FLOW_FLAG         BIT1
+#define  UART_RCV_PARITY_ERR_FLAG        BIT2
+#define  UART_RCV_FRAME_ERR_FLAG         BIT3
+#define  UART_BRK_INT_FLAG               BIT4
+#define  UART_TRX_FIFO_EMPTY_FLAG        BIT5
+#define  UART_TRX_ALL_EMPTY_FLAG         BIT6   // include fifo and shift reg
+#define  UART_RCV_ERR_FLAG               BIT7
+
+//send and receive message frame head
+#define FRAME_FLAG                       0x7E
+
+typedef enum {
+    UART_LINE_STATUS_INT_FLAG  = 0x06,
+    UART_RCV_FIFO_INT_FLAG     = 0x04,
+    UART_RCV_TMOUT_INT_FLAG    = 0x0C,
+    UART_TXBUFF_EMPTY_INT_FLAG = 0x02
+} UartIntType;   //consider bit0 for int_flag
+
+typedef enum {
+    RCV_ONE_BYTE      = 0x0,
+    RCV_FOUR_BYTE     = 0x1,
+    RCV_EIGHT_BYTE    = 0x2,
+    RCV_FOURTEEN_BYTE = 0x3
+} UartRcvFifoTrgLvl;
+
+typedef enum {
+    FIVE_BITS  = 0x0,
+    SIX_BITS   = 0x1,
+    SEVEN_BITS = 0x2,
+    EIGHT_BITS = 0x3
+} UartBitsNum4Char;
+
+typedef enum {
+    ONE_STOP_BIT      = 1,
+    ONE_HALF_STOP_BIT = 2,
+    TWO_STOP_BIT      = 3
+} UartStopBitsNum;
+
+typedef enum {
+    NONE_BITS = 0,
+    ODD_BITS  = 2,
+    EVEN_BITS = 3
+
+} UartParityMode;
+
+typedef enum {
+    STICK_PARITY_DIS = 0,
+    STICK_PARITY_EN  = 2
+} UartExistParity;
+
+typedef enum {
+    BIT_RATE_9600   = 9600,
+    BIT_RATE_19200  = 19200,
+    BIT_RATE_38400  = 38400,
+    BIT_RATE_57600  = 57600,
+    BIT_RATE_115200 = 115200,
+    BIT_RATE_230400 = 230400,
+    BIT_RATE_460800 = 460800,
+    BIT_RATE_921600 = 921600
+} UartBautRate;
+
+typedef enum {
+    NONE_CTRL,
+    HARDWARE_CTRL,
+    XON_XOFF_CTRL
+} UartFlowCtrl;
+
+typedef enum {
+    EMPTY,
+    UNDER_WRITE,
+    WRITE_OVER
+} RcvMsgBuffState;
+
+typedef struct {
+    uint8_t *pRcvMsgBuff;
+    uint8_t *pWritePos;
+    uint8_t *pReadPos;
+    uint8_t  TrigLvl;
+    RcvMsgBuffState BuffState;
+} RcvMsgBuff;
+
+typedef struct {
+    uint32_t  TrxBuffSize;
+    uint8_t  *pTrxBuff;
+} TrxMsgBuff;
+
+typedef enum {
+    BAUD_RATE_DET,
+    WAIT_SYNC_FRM,
+    SRCH_MSG_HEAD,
+    RCV_MSG_BODY,
+    RCV_ESC_CHAR,
+} RcvMsgState;
+
+typedef struct {
+    UartBautRate     baut_rate;
+    UartBitsNum4Char data_bits;
+    UartExistParity  exist_parity;
+    UartParityMode   parity;    // chip size in byte
+    UartStopBitsNum  stop_bits;
+    UartFlowCtrl     flow_ctrl;
+    uint8_t          buff_uart_no;  //indicate which uart use tx/rx buffer
+    RcvMsgBuff       rcv_buff;
+//    TrxMsgBuff       trx_buff;
+    RcvMsgState      rcv_state;
+    int              received;
+} UartDevice;
+
+/**
+  * @brief Init uart device struct value and reset uart0/uart1 rx.
+  *        Please do not call this function in SDK.
+  *
+  * @param  rxBuffer, must be a pointer to RX_BUFF_SIZE bytes or NULL
+  *
+  * @return None
+  */
+void uartAttach(void *rxBuffer);
+
+/**
+  * @brief Init uart0 or uart1 for UART download booting mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, else for UART1.
+  *
+  * @param  uint32_t clock : clock used by uart module, to adjust baudrate.
+  *
+  * @return None
+  */
+void Uart_Init(uint8_t uart_no, uint32_t clock);
+
+/**
+  * @brief Modify uart baudrate.
+  *        This function will reset RX/TX fifo for uart.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @param  uint32_t DivLatchValue : (clock << 4)/baudrate.
+  *
+  * @return None
+  */
+void uart_div_modify(uint8_t uart_no, uint32_t DivLatchValue);
+
+/**
+  * @brief Init uart0 or uart1 for UART download booting mode.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module, easy to detect, wait until detected;
+  *                           1, two UART modules, hard to detect, detect and return.
+  *
+  * @return None
+  */
+int uart_baudrate_detect(uint8_t uart_no, uint8_t is_sync);
+
+/**
+  * @brief Switch printf channel of uart_tx_one_char.
+  *        Please do not call this function when printf.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None
+  */
+void uart_tx_switch(uint8_t uart_no);
+
+/**
+  * @brief Switch message exchange channel for UART download booting.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None
+  */
+void uart_buff_switch(uint8_t uart_no);
+
+/**
+  * @brief Output a char to printf channel, wait until fifo not full.
+  *
+  * @param  None
+  *
+  * @return OK.
+  */
+STATUS uart_tx_one_char(uint8_t TxChar);
+
+/**
+  * @brief Output a char to message exchange channel, wait until fifo not full.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return OK.
+  */
+STATUS uart_tx_one_char2(uint8_t TxChar);
+
+/**
+  * @brief Wait until uart tx full empty.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return None.
+  */
+void uart_tx_flush(uint8_t uart_no);
+
+/**
+  * @brief Wait until uart tx full empty and the last char send ok.
+  *
+  * @param  uart_no : 0 for UART0, 1 for UART1
+  *
+  * The function defined in ROM code has a bug, so we define the correct version
+  * here for compatibility.
+  */
+void uart_tx_wait_idle(uint8_t uart_no);
+
+/**
+  * @brief Get an input char from message channel.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pRxChar : the pointer to store the char.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS uart_rx_one_char(uint8_t *pRxChar);
+
+/**
+  * @brief Get an input char from message channel, wait until successful.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return char : input char value.
+  */
+char uart_rx_one_char_block(void);
+
+/**
+  * @brief Get an input string line from message channel.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pString : the pointer to store the string.
+  *
+  * @param  uint8_t MaxStrlen : the max string length, incude '\0'.
+  *
+  * @return OK.
+  */
+STATUS UartRxString(uint8_t *pString, uint8_t MaxStrlen);
+
+/**
+  * @brief Process uart recevied information in the interrupt handler.
+  *        Please do not call this function in SDK.
+  *
+  * @param  void *para : the message receive buffer.
+  *
+  * @return None
+  */
+void uart_rx_intr_handler(void *para);
+
+/**
+  * @brief Get an char from receive buffer.
+  *        Please do not call this function in SDK.
+  *
+  * @param  RcvMsgBuff *pRxBuff : the pointer to the struct that include receive buffer.
+  *
+  * @param  uint8_t *pRxByte : the pointer to store the char.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS uart_rx_readbuff( RcvMsgBuff *pRxBuff, uint8_t *pRxByte);
+
+/**
+  * @brief Get all chars from receive buffer.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pCmdLn : the pointer to store the string.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS UartGetCmdLn(uint8_t *pCmdLn);
+
+/**
+  * @brief Get uart configuration struct.
+  *        Please do not call this function in SDK.
+  *
+  * @param  None
+  *
+  * @return UartDevice * : uart configuration struct pointer.
+  */
+UartDevice *GetUartDevice(void);
+
+/**
+  * @brief Send an packet to download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *p : the pointer to output string.
+  *
+  * @param  int len : the string length.
+  *
+  * @return None.
+  */
+void send_packet(uint8_t *p, int len);
+
+/**
+  * @brief Receive an packet from download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *p : the pointer to input string.
+  *
+  * @param  int len : If string length > len, the string will be truncated.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module;
+  *                           1, two UART modules.
+  *
+  * @return int : the length of the string.
+  */
+int recv_packet(uint8_t *p, int len, uint8_t is_sync);
+
+/**
+  * @brief Send an packet to download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pData : the pointer to input string.
+  *
+  * @param  uint16_t DataLen : the string length.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS SendMsg(uint8_t *pData, uint16_t DataLen);
+
+/**
+  * @brief Receive an packet from download tool, with SLIP escaping.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t *pData : the pointer to input string.
+  *
+  * @param  uint16_t MaxDataLen : If string length > MaxDataLen, the string will be truncated.
+  *
+  * @param  uint8_t is_sync : 0, only one UART module;
+  *                           1, two UART modules.
+  *
+  * @return OK for successful.
+  *         FAIL for failed.
+  */
+STATUS RcvMsg(uint8_t *pData, uint16_t MaxDataLen, uint8_t is_sync);
+
+/**
+  * @brief Check if this UART is in download connection.
+  *        Please do not call this function in SDK.
+  *
+  * @param  uint8_t uart_no : 0 for UART0, 1 for UART1.
+  *
+  * @return ETS_NO_BOOT = 0 for no.
+  *         SEL_UART_BOOT = BIT(1) for yes.
+  */
+uint8_t UartConnCheck(uint8_t uart_no);
+
+/**
+  * @brief Initialize the USB ACM UART
+  * Needs to be fed a buffer of at least 128 bytes, plus any rx buffer you may want to have.
+  *
+  * @param cdc_acm_work_mem Pointer to work mem for CDC-ACM code
+  * @param cdc_acm_work_mem_len Length of work mem
+  */
+void Uart_Init_USB(void *cdc_acm_work_mem, int cdc_acm_work_mem_len);
+
+
+/**
+  * @brief Install handler to reset the chip when a RTS change has been detected on the CDC-ACM 'UART'.
+  */
+void uart_usb_enable_reset_on_rts(void);
+
+
+extern UartDevice UartDev;
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ROM_UART_H_ */
diff --git a/components/esp_rom/include/esp_rom_md5.h b/components/esp_rom/include/esp_rom_md5.h
index 0deaca471482ce12c8e539ef3e95bccd94b878ed..390806bdd533e1cc24e527906c873c1b2f4ae783 100644
--- a/components/esp_rom/include/esp_rom_md5.h
+++ b/components/esp_rom/include/esp_rom_md5.h
@@ -1,16 +1,8 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #pragma once
 
@@ -19,11 +11,66 @@ extern "C" {
 #endif
 
 #include <stdint.h>
+#include "sdkconfig.h"
 
 /**
  * The MD5 functions calculate a 128-bit cryptographic digest for any number of input bytes.
  */
+#define ESP_ROM_MD5_DIGEST_LEN 16
+
+#if CONFIG_IDF_TARGET_ESP8684
+/**
+ * \brief          MD5 context structure
+ *
+ * \warning        MD5 is considered a weak message digest and its use
+ *                 constitutes a security risk. We recommend considering
+ *                 stronger message digests instead.
+ *
+ */
+typedef struct mbedtls_md5_context {
+    uint32_t total[2];          /*!< number of bytes processed  */
+    uint32_t state[4];          /*!< intermediate digest state  */
+    unsigned char buffer[64];   /*!< data block being processed */
+} md5_context_t;
+/* Functions extracted from ROM, do not use it as an public API */
+void esp_rom_mbedtls_md5_starts_ret(md5_context_t *context);
+void esp_rom_mbedtls_md5_update_ret(md5_context_t *context, const void *buf, uint32_t len);
+void esp_rom_mbedtls_md5_finish_ret(md5_context_t *context, uint8_t *digest);
 
+/**
+ * @brief Initialize the MD5 context
+ *
+ * @param context Context object allocated by user
+ */
+static inline void esp_rom_md5_init(md5_context_t *context)
+{
+    esp_rom_mbedtls_md5_starts_ret(context);
+}
+
+/**
+ * @brief Running MD5 algorithm over input data
+ *
+ * @param context MD5 context which has been initialized by `MD5Init`
+ * @param buf Input buffer
+ * @param len Buffer length in bytes
+ */
+static inline void esp_rom_md5_update(md5_context_t *context, const void *buf, uint32_t len)
+{
+    esp_rom_mbedtls_md5_update_ret(context, buf, len);
+}
+
+/**
+ * @brief Extract the MD5 result, and erase the context
+ *
+ * @param digest Where to store the 128-bit digest value
+ * @param context MD5 context
+ */
+static inline void esp_rom_md5_final(uint8_t *digest, md5_context_t *context)
+{
+    esp_rom_mbedtls_md5_finish_ret(context, digest);
+}
+
+#else //#if !CONFIG_IDF_TARGET_ESP8684
 /**
  * @brief Type defined for MD5 context
  *
@@ -34,8 +81,6 @@ typedef struct MD5Context {
     uint8_t in[64];
 } md5_context_t;
 
-#define ESP_ROM_MD5_DIGEST_LEN 16
-
 /**
  * @brief Initialize the MD5 context
  *
@@ -60,6 +105,8 @@ void esp_rom_md5_update(md5_context_t *context, const void *buf, uint32_t len);
  */
 void esp_rom_md5_final(uint8_t *digest, md5_context_t *context);
 
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/esp_rom/patches/esp_rom_sys.c b/components/esp_rom/patches/esp_rom_sys.c
index 4b87d2d0811e3154e6e5cb3ba67ed86dcfb6fe1f..be489a77dac5b41198cdb2fe82376cba1c0e691c 100644
--- a/components/esp_rom/patches/esp_rom_sys.c
+++ b/components/esp_rom/patches/esp_rom_sys.c
@@ -1,16 +1,8 @@
-// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2010-2021 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
 #include <stdint.h>
 #include <stdbool.h>
@@ -34,7 +26,7 @@ IRAM_ATTR void esp_rom_install_channel_putc(int channel, void (*putc)(char c))
     }
 }
 
-#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2
+#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP8684
 IRAM_ATTR void esp_rom_install_uart_printf(void)
 {
     extern void ets_install_uart_printf(void);