From 0054609fdee38ad6560f48a7dee69f899599c18f Mon Sep 17 00:00:00 2001
From: Sergiusz Bazanski <q3k@q3k.org>
Date: Sat, 27 Jul 2019 01:50:01 +0200
Subject: [PATCH] fix indentation
---
epicardium/main.c | 4 +-
l0dables/lib/hardware.c | 86 ++++++++++++++++++++---------------------
l0dables/lib/l0dable.ld | 14 +++----
3 files changed, 52 insertions(+), 52 deletions(-)
diff --git a/epicardium/main.c b/epicardium/main.c
index 384ee3db..269cf1d0 100644
--- a/epicardium/main.c
+++ b/epicardium/main.c
@@ -118,8 +118,8 @@ int main(void)
core1_start(info.isr_vector);
}
} else {
- LOG_INFO("startup", "Starting pycardium on core1 ...");
- core1_start((void *)0x10080000);
+ LOG_INFO("startup", "Starting pycardium on core1 ...");
+ core1_start((void *)0x10080000);
}
diff --git a/l0dables/lib/hardware.c b/l0dables/lib/hardware.c
index 1e08e5ed..7a481afa 100644
--- a/l0dables/lib/hardware.c
+++ b/l0dables/lib/hardware.c
@@ -19,56 +19,56 @@ uint32_t SystemCoreClock = HIRC_FREQ >> 1;
void SystemCoreClockUpdate(void)
{
- uint32_t base_freq, div, clk_src;
+ uint32_t base_freq, div, clk_src;
- // Determine the clock source and frequency
- clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
- switch (clk_src)
- {
- case MXC_S_GCR_CLKCN_CLKSEL_HIRC:
- base_freq = HIRC_FREQ;
- break;
- case MXC_S_GCR_CLKCN_CLKSEL_XTAL32M:
- base_freq = XTAL32M_FREQ;
- break;
- case MXC_S_GCR_CLKCN_CLKSEL_LIRC8:
- base_freq = LIRC8_FREQ;
- break;
- case MXC_S_GCR_CLKCN_CLKSEL_HIRC96:
- base_freq = HIRC96_FREQ;
- break;
- case MXC_S_GCR_CLKCN_CLKSEL_HIRC8:
- base_freq = HIRC8_FREQ;
- break;
- case MXC_S_GCR_CLKCN_CLKSEL_XTAL32K:
- base_freq = XTAL32K_FREQ;
- break;
- default:
- // Values 001 and 111 are reserved, and should never be encountered.
- base_freq = HIRC_FREQ;
- break;
- }
- // Clock divider is retrieved to compute system clock
- div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
+ // Determine the clock source and frequency
+ clk_src = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_CLKSEL);
+ switch (clk_src)
+ {
+ case MXC_S_GCR_CLKCN_CLKSEL_HIRC:
+ base_freq = HIRC_FREQ;
+ break;
+ case MXC_S_GCR_CLKCN_CLKSEL_XTAL32M:
+ base_freq = XTAL32M_FREQ;
+ break;
+ case MXC_S_GCR_CLKCN_CLKSEL_LIRC8:
+ base_freq = LIRC8_FREQ;
+ break;
+ case MXC_S_GCR_CLKCN_CLKSEL_HIRC96:
+ base_freq = HIRC96_FREQ;
+ break;
+ case MXC_S_GCR_CLKCN_CLKSEL_HIRC8:
+ base_freq = HIRC8_FREQ;
+ break;
+ case MXC_S_GCR_CLKCN_CLKSEL_XTAL32K:
+ base_freq = XTAL32K_FREQ;
+ break;
+ default:
+ // Values 001 and 111 are reserved, and should never be encountered.
+ base_freq = HIRC_FREQ;
+ break;
+ }
+ // Clock divider is retrieved to compute system clock
+ div = (MXC_GCR->clkcn & MXC_F_GCR_CLKCN_PSC) >> MXC_F_GCR_CLKCN_PSC_POS;
- SystemCoreClock = base_freq >> div;
+ SystemCoreClock = base_freq >> div;
}
__weak void SystemInit() {
- // Enable FPU.
- SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
- __DSB();
- __ISB();
+ // Enable FPU.
+ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
+ __DSB();
+ __ISB();
- // Enable ICache1 Clock
- MXC_GCR->perckcn1 &= ~(1 << 22);
+ // Enable ICache1 Clock
+ MXC_GCR->perckcn1 &= ~(1 << 22);
- // Invalidate cache and wait until ready
- MXC_ICC1->invalidate = 1;
- while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY));
+ // Invalidate cache and wait until ready
+ MXC_ICC1->invalidate = 1;
+ while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY));
- // Enable Cache
- MXC_ICC1->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
+ // Enable Cache
+ MXC_ICC1->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
- SystemCoreClockUpdate();
+ SystemCoreClockUpdate();
}
diff --git a/l0dables/lib/l0dable.ld b/l0dables/lib/l0dable.ld
index 8c96d669..f09e39f6 100644
--- a/l0dables/lib/l0dable.ld
+++ b/l0dables/lib/l0dable.ld
@@ -45,10 +45,10 @@ SECTIONS {
. = ALIGN(4);
*(.data*)
- . = ALIGN(4);
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP(*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
@@ -79,7 +79,7 @@ SECTIONS {
CARD10_STACK_LIMIT = .;
} :data
- /* Limit based on current limitations of l0dable setup - only uses core1 RAM. */
+ /* Limit based on current limitations of l0dable setup - only uses core1 RAM. */
ASSERT(. < 0x40000, "Exceeded available RAM")
/DISCARD/ :
@@ -90,7 +90,7 @@ SECTIONS {
*(.ARM.attributes)
/* Original interpreter path from gcc/ld - nuke. */
*(.interp)
- /* Dynamic linking section - nuke, we're not a .so and nothing is going to link against us. */
- *(.dynamic)
+ /* Dynamic linking section - nuke, we're not a .so and nothing is going to link against us. */
+ *(.dynamic)
}
}
--
GitLab