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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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SPI-XIP Master Controller Protection Register. More...
Macros | |
| #define | MXC_F_RPU_SPIXIPMC_DMA0ACN_POS 0 |
| SPIXIPMC_DMA0ACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_DMA0ACN_POS)) |
| SPIXIPMC_DMA0ACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_DMA1ACN_POS 1 |
| SPIXIPMC_DMA1ACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_DMA1ACN_POS)) |
| SPIXIPMC_DMA1ACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_USBACN_POS 2 |
| SPIXIPMC_USBACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_USBACN_POS)) |
| SPIXIPMC_USBACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_SYS0ACN_POS 3 |
| SPIXIPMC_SYS0ACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SYS0ACN_POS)) |
| SPIXIPMC_SYS0ACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_SYS1ACN_POS 4 |
| SPIXIPMC_SYS1ACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SYS1ACN_POS)) |
| SPIXIPMC_SYS1ACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_SDMADACN_POS 5 |
| SPIXIPMC_SDMADACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDMADACN_POS)) |
| SPIXIPMC_SDMADACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_SDMAIACN_POS 6 |
| SPIXIPMC_SDMAIACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDMAIACN_POS)) |
| SPIXIPMC_SDMAIACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS 7 |
| SPIXIPMC_CRYPTOACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS)) |
| SPIXIPMC_CRYPTOACN Mask. | |
| #define | MXC_F_RPU_SPIXIPMC_SDIOACN_POS 8 |
| SPIXIPMC_SDIOACN Position. | |
| #define | MXC_F_RPU_SPIXIPMC_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDIOACN_POS)) |
| SPIXIPMC_SDIOACN Mask. | |