40 #ifndef _PWRSEQ_REGS_H_ 41 #define _PWRSEQ_REGS_H_ 50 #if defined (__ICCARM__) 51 #pragma system_include 54 #if defined (__CC_ARM) 65 #define __I volatile const 71 #define __R volatile const 94 __R uint32_t rsv_0x14_0x2f[7];
97 __R uint32_t rsv_0x38_0x3f[2];
111 #define MXC_R_PWRSEQ_LPCN ((uint32_t)0x00000000UL) 112 #define MXC_R_PWRSEQ_LPWKST0 ((uint32_t)0x00000004UL) 113 #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) 114 #define MXC_R_PWRSEQ_LPWKST1 ((uint32_t)0x0000000CUL) 115 #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) 116 #define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) 117 #define MXC_R_PWRSEQ_LPPWEN ((uint32_t)0x00000034UL) 118 #define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) 119 #define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) 120 #define MXC_R_PWRSEQ_BURETVEC ((uint32_t)0x00000048UL) 121 #define MXC_R_PWRSEQ_BUAOD ((uint32_t)0x0000004CUL) 130 #define MXC_F_PWRSEQ_LPCN_RAMRET_POS 0 131 #define MXC_F_PWRSEQ_LPCN_RAMRET ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCN_RAMRET_POS)) 132 #define MXC_V_PWRSEQ_LPCN_RAMRET_DIS ((uint32_t)0x0UL) 133 #define MXC_S_PWRSEQ_LPCN_RAMRET_DIS (MXC_V_PWRSEQ_LPCN_RAMRET_DIS << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 134 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN1 ((uint32_t)0x1UL) 135 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN1 (MXC_V_PWRSEQ_LPCN_RAMRET_EN1 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 136 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN2 ((uint32_t)0x2UL) 137 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN2 (MXC_V_PWRSEQ_LPCN_RAMRET_EN2 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 138 #define MXC_V_PWRSEQ_LPCN_RAMRET_EN3 ((uint32_t)0x3UL) 139 #define MXC_S_PWRSEQ_LPCN_RAMRET_EN3 (MXC_V_PWRSEQ_LPCN_RAMRET_EN3 << MXC_F_PWRSEQ_LPCN_RAMRET_POS) 141 #define MXC_F_PWRSEQ_LPCN_BLKDET_POS 6 142 #define MXC_F_PWRSEQ_LPCN_BLKDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BLKDET_POS)) 144 #define MXC_F_PWRSEQ_LPCN_BCKGRND_POS 9 145 #define MXC_F_PWRSEQ_LPCN_BCKGRND ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BCKGRND_POS)) 147 #define MXC_F_PWRSEQ_LPCN_FWKM_POS 10 148 #define MXC_F_PWRSEQ_LPCN_FWKM ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_FWKM_POS)) 150 #define MXC_F_PWRSEQ_LPCN_BGOFF_POS 11 151 #define MXC_F_PWRSEQ_LPCN_BGOFF ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_BGOFF_POS)) 153 #define MXC_F_PWRSEQ_LPCN_VCOREMD_POS 20 154 #define MXC_F_PWRSEQ_LPCN_VCOREMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VCOREMD_POS)) 156 #define MXC_F_PWRSEQ_LPCN_VREGIMD_POS 21 157 #define MXC_F_PWRSEQ_LPCN_VREGIMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VREGIMD_POS)) 159 #define MXC_F_PWRSEQ_LPCN_VDDAMD_POS 22 160 #define MXC_F_PWRSEQ_LPCN_VDDAMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDAMD_POS)) 162 #define MXC_F_PWRSEQ_LPCN_VDDIOMD_POS 23 163 #define MXC_F_PWRSEQ_LPCN_VDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOMD_POS)) 165 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS 24 166 #define MXC_F_PWRSEQ_LPCN_VDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDIOHMD_POS)) 168 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS 25 169 #define MXC_F_PWRSEQ_LPCN_PORVDDIOMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOMD_POS)) 171 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS 26 172 #define MXC_F_PWRSEQ_LPCN_PORVDDIOHMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PORVDDIOHMD_POS)) 174 #define MXC_F_PWRSEQ_LPCN_VDDBMD_POS 27 175 #define MXC_F_PWRSEQ_LPCN_VDDBMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VDDBMD_POS)) 177 #define MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS 28 178 #define MXC_F_PWRSEQ_LPCN_VRXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VRXOUTMD_POS)) 180 #define MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS 29 181 #define MXC_F_PWRSEQ_LPCN_VTXOUTMD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_VTXOUTMD_POS)) 183 #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS 30 184 #define MXC_F_PWRSEQ_LPCN_PDOWNDSLEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCN_PDOWNDSLEN_POS)) 195 #define MXC_F_PWRSEQ_LPWKST0_WAKEST_POS 0 196 #define MXC_F_PWRSEQ_LPWKST0_WAKEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPWKST0_WAKEST_POS)) 207 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS 0 208 #define MXC_F_PWRSEQ_LPWKEN0_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_WAKEEN_POS)) 219 #define MXC_F_PWRSEQ_LPWKST1_WAKEST_POS 0 220 #define MXC_F_PWRSEQ_LPWKST1_WAKEST ((uint32_t)(0x3FFFFUL << MXC_F_PWRSEQ_LPWKST1_WAKEST_POS)) 231 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS 0 232 #define MXC_F_PWRSEQ_LPWKEN1_WAKEEN ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN1_WAKEEN_POS)) 242 #define MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS 0 243 #define MXC_F_PWRSEQ_LPPWST_USBLSWKST ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWST_USBLSWKST_POS)) 245 #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS 2 246 #define MXC_F_PWRSEQ_LPPWST_USBVBUSWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_USBVBUSWKST_POS)) 248 #define MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS 3 249 #define MXC_F_PWRSEQ_LPPWST_SDMAWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_SDMAWKST_POS)) 251 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS 4 252 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0WKST_POS)) 254 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS 5 255 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1WKST_POS)) 257 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS 6 258 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2WKST_POS)) 260 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS 7 261 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3WKST_POS)) 263 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS 8 264 #define MXC_F_PWRSEQ_LPPWST_AINCOMP0ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP0ST_POS)) 266 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS 9 267 #define MXC_F_PWRSEQ_LPPWST_AINCOMP1ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP1ST_POS)) 269 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS 10 270 #define MXC_F_PWRSEQ_LPPWST_AINCOMP2ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP2ST_POS)) 272 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS 11 273 #define MXC_F_PWRSEQ_LPPWST_AINCOMP3ST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_AINCOMP3ST_POS)) 275 #define MXC_F_PWRSEQ_LPPWST_BBMODEST_POS 16 276 #define MXC_F_PWRSEQ_LPPWST_BBMODEST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BBMODEST_POS)) 278 #define MXC_F_PWRSEQ_LPPWST_RSTWKST_POS 17 279 #define MXC_F_PWRSEQ_LPPWST_RSTWKST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RSTWKST_POS)) 289 #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS 0 290 #define MXC_F_PWRSEQ_LPPWEN_USBLSWKEN ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWEN_USBLSWKEN_POS)) 292 #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS 2 293 #define MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_USBVBUSWKEN_POS)) 295 #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS 3 296 #define MXC_F_PWRSEQ_LPPWEN_SDMAWKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_SDMAWKEN_POS)) 298 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS 4 299 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP0WKEN_POS)) 301 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS 5 302 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP1WKEN_POS)) 304 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS 6 305 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP2WKEN_POS)) 307 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS 7 308 #define MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWEN_AINCOMP3WKEN_POS)) 318 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS 0 319 #define MXC_F_PWRSEQ_LPMEMSD_SRAM0SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM0SD_POS)) 321 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS 1 322 #define MXC_F_PWRSEQ_LPMEMSD_SRAM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM1SD_POS)) 324 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS 2 325 #define MXC_F_PWRSEQ_LPMEMSD_SRAM2SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM2SD_POS)) 327 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS 3 328 #define MXC_F_PWRSEQ_LPMEMSD_SRAM3SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM3SD_POS)) 330 #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS 4 331 #define MXC_F_PWRSEQ_LPMEMSD_SRAM4SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM4SD_POS)) 333 #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS 5 334 #define MXC_F_PWRSEQ_LPMEMSD_SRAM5SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRAM5SD_POS)) 336 #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS 7 337 #define MXC_F_PWRSEQ_LPMEMSD_ICACHESD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHESD_POS)) 339 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS 8 340 #define MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICACHEXIPSD_POS)) 342 #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS 9 343 #define MXC_F_PWRSEQ_LPMEMSD_SRCCSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCCSD_POS)) 345 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS 10 346 #define MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_CRYPTOSD_POS)) 348 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS 11 349 #define MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFOSD_POS)) 351 #define MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS 12 352 #define MXC_F_PWRSEQ_LPMEMSD_ROMSD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROMSD_POS)) 354 #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS 13 355 #define MXC_F_PWRSEQ_LPMEMSD_ROM1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1SD_POS)) 357 #define MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS 14 358 #define MXC_F_PWRSEQ_LPMEMSD_IC1SD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_IC1SD_POS)) 368 #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS 0 369 #define MXC_F_PWRSEQ_LPVDDPD_VREGOBPD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGOBPD_POS)) 371 #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS 1 372 #define MXC_F_PWRSEQ_LPVDDPD_VREGODPD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VREGODPD_POS)) 374 #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS 8 375 #define MXC_F_PWRSEQ_LPVDDPD_VDD2PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD2PD_POS)) 377 #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS 9 378 #define MXC_F_PWRSEQ_LPVDDPD_VDD3PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD3PD_POS)) 380 #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS 10 381 #define MXC_F_PWRSEQ_LPVDDPD_VDD4PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD4PD_POS)) 383 #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS 11 384 #define MXC_F_PWRSEQ_LPVDDPD_VDD5PD ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_VDD5PD_POS)) __IO uint32_t lpvddpd
0x44: PWRSEQ LPVDDPD Register
Definition: pwrseq_regs.h:99
__IO uint32_t buaod
0x4C: PWRSEQ BUAOD Register
Definition: pwrseq_regs.h:101
__IO uint32_t lpmemsd
0x40: PWRSEQ LPMEMSD Register
Definition: pwrseq_regs.h:98
__IO uint32_t buretvec
0x48: PWRSEQ BURETVEC Register
Definition: pwrseq_regs.h:100
__IO uint32_t lpwken1
0x10: PWRSEQ LPWKEN1 Register
Definition: pwrseq_regs.h:93
__IO uint32_t lppwen
0x34: PWRSEQ LPPWEN Register
Definition: pwrseq_regs.h:96
__IO uint32_t lpwken0
0x08: PWRSEQ LPWKEN0 Register
Definition: pwrseq_regs.h:91
__IO uint32_t lppwst
0x30: PWRSEQ LPPWST Register
Definition: pwrseq_regs.h:95
__IO uint32_t lpwkst0
0x04: PWRSEQ LPWKST0 Register
Definition: pwrseq_regs.h:90
__IO uint32_t lpcn
0x00: PWRSEQ LPCN Register
Definition: pwrseq_regs.h:89
__IO uint32_t lpwkst1
0x0C: PWRSEQ LPWKST1 Register
Definition: pwrseq_regs.h:92
Structure type to access the PWRSEQ Registers.
Definition: pwrseq_regs.h:88