MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation
max32665.h
1 /*******************************************************************************
2  * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included
12  * in all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
18  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Except as contained in this notice, the name of Maxim Integrated
23  * Products, Inc. shall not be used except as stated in the Maxim Integrated
24  * Products, Inc. Branding Policy.
25  *
26  * The mere transfer of this software does not imply any licenses
27  * of trade secrets, proprietary technology, copyrights, patents,
28  * trademarks, maskwork rights, or any other form of intellectual
29  * property whatsoever. Maxim Integrated Products, Inc. retains all
30  * ownership rights.
31  *
32  * $Date: 2020-08-06 16:55:44 -0500 (Thu, 06 Aug 2020) $
33  * $Revision: 54746 $
34  *
35  ******************************************************************************/
36 
37 #ifndef _MAX32665_REGS_H_
38 #define _MAX32665_REGS_H_
39 
40 #ifndef TARGET_NUM
41 #define TARGET_NUM 32665
42 #endif
43 
44 #define MXC_NUMCORES 2
45 
46 #include <stdint.h>
47 
48 #ifndef FALSE
49 #define FALSE (0)
50 #endif
51 
52 #ifndef TRUE
53 #define TRUE (1)
54 #endif
55 
56 #if !defined ( __GNUC__ )
57  #define CMSIS_VECTAB_VIRTUAL
58  #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "nvic_table.h"
59 #endif
60 
61 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
62 #if defined ( __GNUC__ )
63 
64 #define __weak __attribute__((weak))
65 
66 #elif defined ( __CC_ARM)
67 
68 #define inline __inline
69 #pragma anon_unions
70 
71 #elif defined ( __CROSSWORKS_MAXQ30 )
72 
73 #define __weak
74 
75 #endif
76 
77 typedef enum {
78  NonMaskableInt_IRQn = -14,
79  HardFault_IRQn = -13,
80  MemoryManagement_IRQn = -12,
81  BusFault_IRQn = -11,
82  UsageFault_IRQn = -10,
83  SVCall_IRQn = -5,
84  DebugMonitor_IRQn = -4,
85  PendSV_IRQn = -2,
86  SysTick_IRQn = -1,
87 
88  /* Device-specific interrupt sources (external to ARM core) */
89  /* table entry number */
90  /* |||| */
91  /* |||| table offset address */
92  /* vvvv vvvvvv */
93 
94  PF_IRQn = 0, /* 0x10 0x0040 16: Power Fail */
95  WDT0_IRQn, /* 0x11 0x0044 17: Watchdog 0 */
96  USB_IRQn, /* 0x12 0x0048 18: USB */
97  RTC_IRQn, /* 0x13 0x004C 19: RTC */
98  TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */
99  TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */
100  TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */
101  TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */
102  TMR3_IRQn, /* 0x18 0x0060 24: Timer 3*/
103  TMR4_IRQn, /* 0x19 0x0064 25: Timer 4*/
104  TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 */
105  RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */
106  RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */
107  I2C0_IRQn, /* 0x1D 0x0074 29: I2C0 */
108  UART0_IRQn, /* 0x1E 0x0078 30: UART 0 */
109  UART1_IRQn, /* 0x1F 0x007C 31: UART 1 */
110  SPI17Y1_IRQn, /* 0x20 0x0080 32: SPI17Y1 */
111  SPI17Y2_IRQn, /* 0x21 0x0084 33: SPI17Y2 */
112  RSV18_IRQn, /* 0x22 0x0088 34: Reserved */
113  RSV19_IRQn, /* 0x23 0x008C 35: Reserved */
114  ADC_IRQn, /* 0x24 0x0090 36: ADC */
115  RSV21_IRQn, /* 0x25 0x0094 37: Reserved */
116  RSV22_IRQn, /* 0x26 0x0098 38: Reserved */
117  FLC0_IRQn, /* 0x27 0x009C 39: Flash Controller 0 */
118  GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */
119  GPIO1_IRQn, /* 0x29 0x00A4 41: GPIO1 */
120  RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */
121  TPU_IRQn, /* 0x2B 0x00AC 43: Crypto */
122  DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */
123  DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */
124  DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */
125  DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */
126  RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */
127  RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */
128  UART2_IRQn, /* 0x32 0x00C8 50: UART 2 */
129  RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */
130  I2C1_IRQn, /* 0x34 0x00D0 52: I2C1 */
131  RSV36_IRQn, /* 0x35 0x00D4 53: Reserved */
132  SPIXFC_IRQn, /* 0x36 0x00D8 54: SPI execute in place */
133  BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */
134  BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */
135  BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */
136  BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */
137  BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/
138  BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/
139  BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */
140  BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */
141  BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */
142  BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */
143  BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */
144  BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */
145  BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/
146  BTLE_IQ_DATA_VALID_IRQn,/* 0x44 0x0110 68: BTLE IQ Data Valid */
147  WUT_IRQn, /* 0x45 0x0114 69: WUT Wakeup */
148  GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */
149  RSV55_IRQn, /* 0x47 0x011C 71: Reserved */
150  SPI17Y0_IRQn, /* 0x48 0x0120 72: SPI17Y0 AHB*/
151  WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */
152  RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */
153  PT_IRQn, /* 0x4B 0x012C 75: Pulse train */
154  SDMA_IRQn, /* 0x4C 0x0130 76: Smart DMA 0 */
155  RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */
156  I2C2_IRQn, /* 0x4E 0x0138 78: I2C 2 */
157  RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */
158  RSV64_IRQn, /* 0x50 0x0140 80: Reserved */
159  RSV65_IRQn, /* 0x51 0x0144 81: Reserved */
160  SDHC_IRQn, /* 0x52 0x0148 82: SDIO/SDHC */
161  OWM_IRQn, /* 0x53 0x014C 83: One Wire Master */
162  DMA4_IRQn, /* 0x54 0x0150 84: DMA4 */
163  DMA5_IRQn, /* 0x55 0x0154 85: DMA5 */
164  DMA6_IRQn, /* 0x56 0x0158 86: DMA6 */
165  DMA7_IRQn, /* 0x57 0x015C 87: DMA7 */
166  DMA8_IRQn, /* 0x58 0x0160 88: DMA8 */
167  DMA9_IRQn, /* 0x59 0x0164 89: DMA9 */
168  DMA10_IRQn, /* 0x5A 0x0168 90: DMA10 */
169  DMA11_IRQn, /* 0x5B 0x016C 91: DMA11 */
170  DMA12_IRQn, /* 0x5C 0x0170 92: DMA12 */
171  DMA13_IRQn, /* 0x5D 0x0174 93: DMA13 */
172  DMA14_IRQn, /* 0x5E 0x0178 94: DMA14 */
173  DMA15_IRQn, /* 0x5F 0x017C 95: DMA15 */
174  USBDMA_IRQn, /* 0x60 0x0180 96: USB DMA */
175  WDT2_IRQn, /* 0x61 0x0184 97: Watchdog Timer 2 */
176  ECC_IRQn, /* 0x62 0x0188 98: Error Correction */
177  DVS_IRQn, /* 0x63 0x018C 99: DVS Controller */
178  SIMO_IRQn, /* 0x64 0x0190 100: SIMO Controller */
179  SCA_IRQn, /* 0x65 0x0194 101: SCA */
180  AUDIO_IRQn, /* 0x66 0x0198 102: Audio subsystem */
181  FLC1_IRQn, /* 0x67 0x019C 103: Flash Control 1 */
182  UART3_IRQn, /* 0x68 0x01A0 104: UART 3 */
183  UART4_IRQn, /* 0x69 0x01A4 105: UART 4 */
184  UART5_IRQn, /* 0x6A 0x01A8 106: UART 5 */
185  CameraIF_IRQn, /* 0x6B 0x01AC 107: Camera IF */
186  I3C_IRQn, /* 0x6C 0x01B0 108: I3C */
187  HTMR0_IRQn, /* 0x6D 0x01B4 109: HTimer0 */
188  HTMR1_IRQn, /* 0x6E 0x01B8 110: HTimer1 */
189  MXC_IRQ_EXT_COUNT
190 } IRQn_Type;
191 
192 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
193 
194 
195 /* ================================================================================ */
196 /* ================ Processor and Core Peripheral Section ================ */
197 /* ================================================================================ */
198 
199 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
200 #define __CM4_REV 0x0100
201 #define __MPU_PRESENT 1
202 #define __NVIC_PRIO_BITS 3
203 #define __Vendor_SysTickConfig 0
204 #define __FPU_PRESENT 1
206 #ifndef __CROSSWORKS
207 #include <core_cm4.h>
208 #else
209 #include "max32665_sdma.h"
210 #endif
211 
212 #include "system_max32665.h"
215 /* ================================================================================ */
216 /* ================== Device Specific Memory Section ================== */
217 /* ================================================================================ */
218 
219 #define MXC_ROM_MEM_BASE 0x00000000UL
220 #define MXC_ROM_MEM_SIZE 0x00020000UL
221 #define MXC_XIP_MEM_BASE 0x08000000UL
222 #define MXC_XIP_MEM_SIZE 0x08000000UL
223 #define MXC_FLASH0_MEM_BASE 0x10000000UL
224 #define MXC_FLASH1_MEM_BASE 0x10080000UL
225 #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE
226 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
227 #define MXC_FLASH_MEM_SIZE 0x00080000UL
228 #define MXC_INFO0_MEM_BASE 0x10800000UL
229 #define MXC_INFO1_MEM_BASE 0x10804000UL
230 #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE
231 #define MXC_INFO_MEM_SIZE 0x00004000UL
232 #define MXC_SRAM_MEM_BASE 0x20000000UL
233 #define MXC_SRAM_MEM_SIZE 0x0008C000UL
234 #define MXC_XIP_DATA_MEM_BASE 0x80000000UL
235 #define MXC_XIP_DATA_MEM_SIZE 0x20000000UL
236 
237 /* ================================================================================ */
238 /* ================ Device Specific Peripheral Section ================ */
239 /* ================================================================================ */
240 
241 /*
242  Base addresses and configuration settings for all MAX32665 peripheral modules.
243 */
244 
245 /******************************************************************************/
246 /* Global control */
247 #define MXC_BASE_GCR ((uint32_t)0x40000000UL)
248 #define MXC_GCR ((mxc_gcr_regs_t*)MXC_BASE_GCR)
249 
250 /******************************************************************************/
251 /* Non-battery backed SI Registers */
252 #define MXC_BASE_SIR ((uint32_t)0x40000400UL)
253 #define MXC_SIR ((mxc_sir_regs_t*)MXC_BASE_SIR)
254 
255 /******************************************************************************/
256 /* Non-battery backed Function Control */
257 #define MXC_BASE_FCR ((uint32_t)0x40000800UL)
258 #define MXC_FCR ((mxc_fcr_regs_t*)MXC_BASE_FCR)
259 
260 /******************************************************************************/
261 /* Trust Protection Unit */
262 #define MXC_BASE_TPU ((uint32_t)0x40001000UL)
263 #define MXC_TPU ((mxc_tpu_regs_t*)MXC_BASE_TPU)
264 
265 /******************************************************************************/
266 /* Watchdog */
267 #define MXC_BASE_WDT0 ((uint32_t)0x40003000UL)
268 #define MXC_WDT0 ((mxc_wdt_regs_t*)MXC_BASE_WDT0)
269 #define MXC_BASE_WDT1 ((uint32_t)0x40003400UL)
270 #define MXC_WDT1 ((mxc_wdt_regs_t*)MXC_BASE_WDT1)
271 #define MXC_BASE_WDT2 ((uint32_t)0x40003800UL)
272 #define MXC_WDT2 ((mxc_wdt_regs_t*)MXC_BASE_WDT2)
273 
274 /******************************************************************************/
275 /* Security Monitor */
276 #define MXC_BASE_SMON ((uint32_t)0x40004000UL)
277 #define MXC_SMON ((mxc_smon_regs_t*)MXC_BASE_SMON)
278 
279 
280 /******************************************************************************/
281 /* SIMO */
282 #define MXC_BASE_SIMO ((uint32_t)0x40004400UL)
283 #define MXC_SIMO ((mxc_simo_regs_t*)MXC_BASE_SIMO)
284 
285 
286 /******************************************************************************/
287 /* DVS*/
288 #define MXC_BASE_DVS ((uint32_t)0x40004800UL)
289 #define MXC_DVS ((mxc_dvs_regs_t*)MXC_BASE_DVS)
290 
291 
292 /******************************************************************************/
293 /* Security Monitor */
294 #define MXC_BASE_SMON ((uint32_t)0x40004000UL)
295 #define MXC_SMON ((mxc_smon_regs_t*)MXC_BASE_SMON)
296 
297 /******************************************************************************/
298 /* Real Time Clock */
299 #define MXC_BASE_RTC ((uint32_t)0x40006000UL)
300 #define MXC_RTC ((mxc_rtc_regs_t*)MXC_BASE_RTC)
301 
302 /******************************************************************************/
303 /* Wakeup Timer */
304 #define MXC_BASE_WUT ((uint32_t)0x40006400UL)
305 #define MXC_WUT ((mxc_wut_regs_t*)MXC_BASE_WUT)
306 
307 
308 /******************************************************************************/
309 /* Power Sequencer */
310 #define MXC_BASE_PWRSEQ ((uint32_t)0x40006800UL)
311 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t*)MXC_BASE_PWRSEQ)
312 /******************************************************************************/
313 /* Power Sequencer */
314 #define MXC_BASE_MCR ((uint32_t)0x40006C00UL)
315 #define MXC_MCR ((mxc_mcr_regs_t*)MXC_BASE_MCR)
316 
317 /******************************************************************************/
318 /* GPIO */
319 #define MXC_CFG_GPIO_INSTANCES (2)
320 #define MXC_CFG_GPIO_PINS_PORT (32)
321 
322 #define MXC_BASE_GPIO0 ((uint32_t)0x40008000UL)
323 #define MXC_GPIO0 ((mxc_gpio_regs_t*)MXC_BASE_GPIO0)
324 #define MXC_BASE_GPIO1 ((uint32_t)0x40009000UL)
325 #define MXC_GPIO1 ((mxc_gpio_regs_t*)MXC_BASE_GPIO1)
326 
327 #define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : \
328  (p) == MXC_GPIO1 ? 1 : -1)
329 
330 #define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : \
331  (i) == 1 ? MXC_GPIO1 : 0)
332 
333 #define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : \
334  (i) == 1 ? GPIO1_IRQn : (IRQn_Type) 0)
335 
336 /******************************************************************************/
337 /* Timer */
338 #define MXC_CFG_TMR_INSTANCES (6)
339 
340 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
341 #define MXC_TMR0 ((mxc_tmr_regs_t*)MXC_BASE_TMR0)
342 #define MXC_BASE_TMR1 ((uint32_t)0x40011000UL)
343 #define MXC_TMR1 ((mxc_tmr_regs_t*)MXC_BASE_TMR1)
344 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
345 #define MXC_TMR2 ((mxc_tmr_regs_t*)MXC_BASE_TMR2)
346 #define MXC_BASE_TMR3 ((uint32_t)0x40013000UL)
347 #define MXC_TMR3 ((mxc_tmr_regs_t*)MXC_BASE_TMR3)
348 #define MXC_BASE_TMR4 ((uint32_t)0x40014000UL)
349 #define MXC_TMR4 ((mxc_tmr_regs_t*)MXC_BASE_TMR4)
350 #define MXC_BASE_TMR5 ((uint32_t)0x40015000UL)
351 #define MXC_TMR5 ((mxc_tmr_regs_t*)MXC_BASE_TMR5)
352 
353 #define MXC_TMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? TMR0_IRQn : \
354  (i) == 1 ? TMR1_IRQn : \
355  (i) == 2 ? TMR2_IRQn : \
356  (i) == 3 ? TMR3_IRQn : \
357  (i) == 4 ? TMR4_IRQn : \
358  (i) == 5 ? TMR5_IRQn : 0)
359 
360 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
361  (i) == 1 ? MXC_BASE_TMR1 : \
362  (i) == 2 ? MXC_BASE_TMR2 : \
363  (i) == 3 ? MXC_BASE_TMR3 : \
364  (i) == 4 ? MXC_BASE_TMR4 : \
365  (i) == 5 ? MXC_BASE_TMR5 : 0)
366 
367 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
368  (i) == 1 ? MXC_TMR1 : \
369  (i) == 2 ? MXC_TMR2 : \
370  (i) == 3 ? MXC_TMR3 : \
371  (i) == 4 ? MXC_TMR4 : \
372  (i) == 5 ? MXC_TMR5 : 0)
373 
374 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
375  (p) == MXC_TMR1 ? 1 : \
376  (p) == MXC_TMR2 ? 2 : \
377  (p) == MXC_TMR3 ? 3 : \
378  (p) == MXC_TMR4 ? 4 : \
379  (p) == MXC_TMR5 ? 5 : -1)
380 
381 /******************************************************************************/
382 /* High Speed Timer */
383 #define MXC_BASE_HTMR0 ((uint32_t)0x4001B000UL)
384 #define MXC_HTMR0 ((mxc_htmr_regs_t*)MXC_BASE_HTMR0)
385 #define MXC_BASE_HTMR1 ((uint32_t)0x4001C000UL)
386 #define MXC_HTMR1 ((mxc_htmr_regs_t*)MXC_BASE_HTMR1)
387 
388 
389 /******************************************************************************/
390 /* I2C */
391 #define MXC_I2C_INSTANCES (3)
392 
393 #define MXC_BASE_I2C0_BUS0 ((uint32_t)0x4001D000UL)
394 #define MXC_I2C0_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS0)
395 #define MXC_BASE_I2C1_BUS0 ((uint32_t)0x4001E000UL)
396 #define MXC_I2C1_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS0)
397 #define MXC_BASE_I2C2_BUS0 ((uint32_t)0x4001F000UL)
398 #define MXC_I2C2_BUS0 ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS0)
399 
400 #define MXC_BASE_I2C0_BUS1 ((uint32_t)0x4011D000UL)
401 #define MXC_I2C0_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C0_BUS1)
402 #define MXC_BASE_I2C1_BUS1 ((uint32_t)0x4011E000UL)
403 #define MXC_I2C1_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C1_BUS1)
404 #define MXC_BASE_I2C2_BUS1 ((uint32_t)0x4011F000UL)
405 #define MXC_I2C2_BUS1 ((mxc_i2c_regs_t*)MXC_BASE_I2C2_BUS1)
406 
407 
408 #define MXC_I2C_GET_IRQ(i) (IRQn_Type)((i) == 0x0 ? I2C0_IRQn : \
409  (i) == 0x1 ? I2C1_IRQn : \
410  (i) == 0x2 ? I2C2_IRQn : \
411  (i) == 0x8000 ? I2C0_IRQn : \
412  (i) == 0x8001 ? I2C1_IRQn : \
413  (i) == 0x8002 ? I2C2_IRQn : 0)
414 
415 #define MXC_I2C_GET_BASE(i) ((i) == 0x0 ? MXC_BASE_I2C0_BUS0 : \
416  (i) == 0x1 ? MXC_BASE_I2C1_BUS0 : \
417  (i) == 0x2 ? MXC_BASE_I2C2_BUS0 : \
418  (i) == 0x8000 ? MXC_BASE_I2C0_BUS1 : \
419  (i) == 0x8001 ? MXC_BASE_I2C1_BUS1 : \
420  (i) == 0x8002 ? MXC_BASE_I2C2_BUS1 : 0)
421 
422 #define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0_BUS0 ? 0x0 : \
423  (p) == MXC_I2C1_BUS0 ? 0x1 : \
424  (p) == MXC_I2C2_BUS0 ? 0x2 : \
425  (p) == MXC_I2C0_BUS1 ? 0x8000 : \
426  (p) == MXC_I2C1_BUS1 ? 0x8001 : \
427  (p) == MXC_I2C2_BUS1 ? 0x8002 : -1)
428 
429 #define MXC_I2C_GET_I2C(p) ((p) == 0x0 ? MXC_I2C0_BUS0 : \
430  (p) == 0x1 ? MXC_I2C1_BUS0 : \
431  (p) == 0x2 ? MXC_I2C2_BUS0 : \
432  (p) == 0x8000 ? MXC_I2C0_BUS1 : \
433  (p) == 0x8001 ? MXC_I2C1_BUS1 : \
434  (p) == 0x8002? MXC_I2C2_BUS1 : 0)
435 #define MXC_I2C_FIFO_DEPTH (8)
436 
437 /******************************************************************************/
438 /* SPI Execute in Place */
439 #define MXC_BASE_SPIXF ((uint32_t)0x40026000UL)
440 #define MXC_SPIXF ((mxc_spixf_regs_t*)MXC_BASE_SPIXF)
441 
442 #define MXC_BASE_SPIXF_FIFO ((uint32_t)0x400BC000UL)
443 #define MXC_SPIXF_FIFO ((mxc_spixf_fifo_regs_t*)MXC_BASE_SPIXF_FIFO)
444 /******************************************************************************/
445 /* SPI Execute in Place Master */
446 
447 #define MXC_CFG_SPIXFC_FIFO_DEPTH (16)
448 
449 #define MXC_BASE_SPIXFC ((uint32_t)0x40027000UL)
450 #define MXC_SPIXFC ((mxc_spixfc_regs_t*)MXC_BASE_SPIXFC)
451 
452 /******************************************************************************/
453 /* DMA */
454 #define MXC_DMA_CHANNELS (16)
455 #define MXC_DMA_INSTANCES (2)
456 
457 #define MXC_BASE_DMA0 ((uint32_t)0x40028000UL)
458 #define MXC_DMA0 ((mxc_dma_regs_t*)MXC_BASE_DMA0)
459 #define MXC_BASE_DMA1 ((uint32_t)0x40035000UL)
460 #define MXC_DMA1 ((mxc_dma_regs_t*)MXC_BASE_DMA1)
461 
462 // TODO: remove this when creating drivers to accept two instance of these.
463 #define MXC_DMA MXC_DMA0
464 
465 #define MXC_DMA_GET_BASE(i) ((i) == 0 ? MXC_BASE_DMA0 : \
466  (i) == 1 ? MXC_BASE_DMA1 : 0)
467 
468 #define MXC_DMA_GET_DMA(i) ((i) == 0 ? MXC_DMA0 : \
469  (i) == 1 ? MXC_DMA1 : 0)
470 
471 #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : \
472  (p) == MXC_DMA1 ? 1 : -1)
473 /******************************************************************************/
474 /* FLC */
475 #define MXC_FLC_INSTANCES (2)
476 
477 #define MXC_BASE_FLC0 ((uint32_t)0x40029000UL)
478 #define MXC_FLC0 ((mxc_flc_regs_t*)MXC_BASE_FLC0)
479 #define MXC_BASE_FLC1 ((uint32_t)0x40029400UL)
480 #define MXC_FLC1 ((mxc_flc_regs_t*)MXC_BASE_FLC1)
481 
482 // TODO: remove this when creating drivers to accept two instance of these.
483 // #define MXC_FLC MXC_FLC0
484 
485 
486 #define MXC_FLC_GET_IRQ(i) (IRQn_Type)((i) == 0 ? FLC0_IRQn : \
487  (i) == 1 ? FLC1_IRQn :0)
488 
489 #define MXC_FLC_GET_BASE(i) ((i) == 0 ? MXC_BASE_FLC0 : \
490  (i) == 1 ? MXC_BASE_FLC1 : 0)
491 
492 #define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC0 : \
493  (i) == 1 ? MXC_FLC1 : 0)
494 
495 #define MXC_FLC_GET_IDX(p) ((p) == MXC_FLC0 ? 0 : \
496  (p) == MXC_FLC1 ? 1 : -1)
497 /******************************************************************************/
498 /* Instruction Cache */
499 #define MXC_ICC_INSTANCES (2)
500 
501 #define MXC_BASE_ICC0 ((uint32_t)0x4002A000UL)
502 #define MXC_ICC0 ((mxc_icc_regs_t*)MXC_BASE_ICC0)
503 #define MXC_BASE_ICC1 ((uint32_t)0x4002A800UL)
504 #define MXC_ICC1 ((mxc_icc_regs_t*)MXC_BASE_ICC1)
505 
506 // TODO: remove this when creating drivers to accept two instance of these.
507 #define MXC_ICC MXC_ICC0
508 
509 
510 #define MXC_ICC_GET_BASE(i) ((i) == 0 ? MXC_BASE_ICC0 : \
511  (i) == 1 ? MXC_BASE_ICC1 : 0)
512 
513 #define MXC_ICC_GET_ICC(i) ((i) == 0 ? MXC_ICC0 : \
514  (i) == 1 ? MXC_ICC1 : 0)
515 
516 #define MXC_ICC_GET_IDX(p) ((p) == MXC_ICC0 ? 0 : \
517  (p) == MXC_ICC1 ? 1 : -1)
518 /******************************************************************************/
519 /* Instruction Cache XIP */
520 #define MXC_BASE_SFCC ((uint32_t)0x4002F000UL)
521 #define MXC_SFCC ((mxc_icc_regs_t*)MXC_BASE_SFCC)
522 
523 /******************************************************************************/
524 /* Data Cache */
525 #define MXC_BASE_SRCC ((uint32_t)0x40033000UL)
526 #define MXC_SRCC ((mxc_srcc_regs_t*)MXC_BASE_SRCC)
527 
528 /******************************************************************************/
529 /* ADC */
530 #define MXC_BASE_ADC ((uint32_t)0x40034000UL)
531 #define MXC_ADC ((mxc_adc_regs_t*)MXC_BASE_ADC)
532 #define MXC_ADC_MAX_CLOCK 8000000 // Maximum ADC clock in Hz
533 
534 /******************************************************************************/
535 /* USB */
536 #define MXC_BASE_USBHS ((uint32_t)0x400B1000UL)
537 #define MXC_USBHS ((mxc_usbhs_regs_t*)MXC_BASE_USBHS)
538 #define MXC_USBHS_NUM_EP 12 /* HW must have at least EP 0 CONTROL + 11 IN/OUT */
539 #define MXC_USBHS_NUM_DMA 8 /* HW must have at least this many DMA channels */
540 #define MXC_USBHS_MAX_PACKET 512
541 
542 /******************************************************************************/
543 /* Smart DMA */
544 #define MXC_BASE_SDMA ((uint32_t)0x40036000UL)
545 #define MXC_SDMA ((mxc_sdma_regs_t*)MXC_BASE_SDMA)
546 
547 /******************************************************************************/
548 /* SPI XIP Data */
549 #define MXC_BASE_SPIXR ((uint32_t)0x4003A000UL)
550 #define MXC_SPIXR ((mxc_spixr_regs_t*)MXC_BASE_SPIXR)
551 
552 /*******************************************************************************/
553 /* Pulse Train Generation */
554 
555 #define MXC_CFG_PT_INSTANCES (16)
556 
557 #define MXC_BASE_PTG_BUS0 ((uint32_t)0x4003C000UL)
558 #define MXC_PTG_BUS0 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS0)
559 #define MXC_BASE_PT0_BUS0 ((uint32_t)0x4003C020UL)
560 #define MXC_PT0_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS0)
561 #define MXC_BASE_PT1_BUS0 ((uint32_t)0x4003C040UL)
562 #define MXC_PT1_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS0)
563 #define MXC_BASE_PT2_BUS0 ((uint32_t)0x4003C060UL)
564 #define MXC_PT2_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS0)
565 #define MXC_BASE_PT3_BUS0 ((uint32_t)0x4003C080UL)
566 #define MXC_PT3_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS0)
567 #define MXC_BASE_PT4_BUS0 ((uint32_t)0x4003C0A0UL)
568 #define MXC_PT4_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS0)
569 #define MXC_BASE_PT5_BUS0 ((uint32_t)0x4003C0C0UL)
570 #define MXC_PT5_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS0)
571 #define MXC_BASE_PT6_BUS0 ((uint32_t)0x4003C0E0UL)
572 #define MXC_PT6_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS0)
573 #define MXC_BASE_PT7_BUS0 ((uint32_t)0x4003C100UL)
574 #define MXC_PT7_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS0)
575 #define MXC_BASE_PT8_BUS0 ((uint32_t)0x4003C120UL)
576 #define MXC_PT8_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS0)
577 #define MXC_BASE_PT9_BUS0 ((uint32_t)0x4003C140UL)
578 #define MXC_PT9_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS0)
579 #define MXC_BASE_PT10_BUS0 ((uint32_t)0x4003C160UL)
580 #define MXC_PT10_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS0)
581 #define MXC_BASE_PT11_BUS0 ((uint32_t)0x4003C180UL)
582 #define MXC_PT11_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS0)
583 #define MXC_BASE_PT12_BUS0 ((uint32_t)0x4003C1A0UL)
584 #define MXC_PT12_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS0)
585 #define MXC_BASE_PT13_BUS0 ((uint32_t)0x4003C1C0UL)
586 #define MXC_PT13_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS0)
587 #define MXC_BASE_PT14_BUS0 ((uint32_t)0x4003C1E0UL)
588 #define MXC_PT14_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS0)
589 #define MXC_BASE_PT15_BUS0 ((uint32_t)0x4003C200UL)
590 #define MXC_PT15_BUS0 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS0)
591 
592 
593 #define MXC_BASE_PTG_BUS1 ((uint32_t)0x4013C000UL)
594 #define MXC_PTG_BUS1 ((mxc_ptg_regs_t *)MXC_BASE_PTG_BUS1)
595 #define MXC_BASE_PT0_BUS1 ((uint32_t)0x4013C020UL)
596 #define MXC_PT0_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT0_BUS1)
597 #define MXC_BASE_PT1_BUS1 ((uint32_t)0x4013C040UL)
598 #define MXC_PT1_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT1_BUS1)
599 #define MXC_BASE_PT2_BUS1 ((uint32_t)0x4013C060UL)
600 #define MXC_PT2_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT2_BUS1)
601 #define MXC_BASE_PT3_BUS1 ((uint32_t)0x4013C080UL)
602 #define MXC_PT3_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT3_BUS1)
603 #define MXC_BASE_PT4_BUS1 ((uint32_t)0x4013C0A0UL)
604 #define MXC_PT4_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT4_BUS1)
605 #define MXC_BASE_PT5_BUS1 ((uint32_t)0x4013C0C0UL)
606 #define MXC_PT5_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT5_BUS1)
607 #define MXC_BASE_PT6_BUS1 ((uint32_t)0x4013C0E0UL)
608 #define MXC_PT6_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT6_BUS1)
609 #define MXC_BASE_PT7_BUS1 ((uint32_t)0x4013C100UL)
610 #define MXC_PT7_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT7_BUS1)
611 #define MXC_BASE_PT8_BUS1 ((uint32_t)0x4013C120UL)
612 #define MXC_PT8_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT8_BUS1)
613 #define MXC_BASE_PT9_BUS1 ((uint32_t)0x4013C140UL)
614 #define MXC_PT9_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT9_BUS1)
615 #define MXC_BASE_PT10_BUS1 ((uint32_t)0x4013C160UL)
616 #define MXC_PT10_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT10_BUS1)
617 #define MXC_BASE_PT11_BUS1 ((uint32_t)0x4013C180UL)
618 #define MXC_PT11_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT11_BUS1)
619 #define MXC_BASE_PT12_BUS1 ((uint32_t)0x4013C1A0UL)
620 #define MXC_PT12_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT12_BUS1)
621 #define MXC_BASE_PT13_BUS1 ((uint32_t)0x4013C1C0UL)
622 #define MXC_PT13_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT13_BUS1)
623 #define MXC_BASE_PT14_BUS1 ((uint32_t)0x4013C1E0UL)
624 #define MXC_PT14_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT14_BUS1)
625 #define MXC_BASE_PT15_BUS1 ((uint32_t)0x4013C200UL)
626 #define MXC_PT15_BUS1 ((mxc_pt_regs_t *)MXC_BASE_PT15_BUS1)
627 
628 #define MXC_PT_GET_BASE(i) ((i) == 0x0 ? MXC_BASE_PT0_BUS0 : \
629  (i) == 0x1 ? MXC_BASE_PT1_BUS0 : \
630  (i) == 0x2 ? MXC_BASE_PT2_BUS0 : \
631  (i) == 0x3 ? MXC_BASE_PT3_BUS0 : \
632  (i) == 0x4 ? MXC_BASE_PT4_BUS0 : \
633  (i) == 0x5 ? MXC_BASE_PT5_BUS0 : \
634  (i) == 0x6 ? MXC_BASE_PT6_BUS0 : \
635  (i) == 0x7 ? MXC_BASE_PT7_BUS0 : \
636  (i) == 0x8 ? MXC_BASE_PT8_BUS0 : \
637  (i) == 0x9 ? MXC_BASE_PT9_BUS0 : \
638  (i) == 0xA ? MXC_BASE_PT10_BUS0 : \
639  (i) == 0xB ? MXC_BASE_PT11_BUS0 : \
640  (i) == 0xC ? MXC_BASE_PT12_BUS0 : \
641  (i) == 0xD ? MXC_BASE_PT13_BUS0 : \
642  (i) == 0xE ? MXC_BASE_PT14_BUS0 : \
643  (i) == 0xF ? MXC_BASE_PT15_BUS0 : \
644  (i) == 0x8000 ? MXC_BASE_PT0_BUS1 : \
645  (i) == 0x8001 ? MXC_BASE_PT1_BUS1 : \
646  (i) == 0x8002 ? MXC_BASE_PT2_BUS1 : \
647  (i) == 0x8003 ? MXC_BASE_PT3_BUS1 : \
648  (i) == 0x8004 ? MXC_BASE_PT4_BUS1 : \
649  (i) == 0x8005 ? MXC_BASE_PT5_BUS1 : \
650  (i) == 0x8006 ? MXC_BASE_PT6_BUS1 : \
651  (i) == 0x8007 ? MXC_BASE_PT7_BUS1 : \
652  (i) == 0x8008 ? MXC_BASE_PT8_BUS1 : \
653  (i) == 0x8009 ? MXC_BASE_PT9_BUS1 : \
654  (i) == 0x800A ? MXC_BASE_PT10_BUS1 : \
655  (i) == 0x800B ? MXC_BASE_PT11_BUS1 : \
656  (i) == 0x800C ? MXC_BASE_PT12_BUS1 : \
657  (i) == 0x800D ? MXC_BASE_PT13_BUS1 : \
658  (i) == 0x800E ? MXC_BASE_PT14_BUS1 : \
659  (i) == 0x800F ? MXC_BASE_PT15_BUS1 : 0)
660 
661 #define MXC_PT_GET_PT(i) ((i) == 0x0 ? MXC_PT0_BUS0 : \
662  (i) == 0x1 ? MXC_PT1_BUS0 : \
663  (i) == 0x2 ? MXC_PT2_BUS0 : \
664  (i) == 0x3 ? MXC_PT3_BUS0 : \
665  (i) == 0x4 ? MXC_PT4_BUS0 : \
666  (i) == 0x5 ? MXC_PT5_BUS0 : \
667  (i) == 0x6 ? MXC_PT6_BUS0 : \
668  (i) == 0x7 ? MXC_PT7_BUS0 : \
669  (i) == 0x8 ? MXC_PT8_BUS0 : \
670  (i) == 0x9 ? MXC_PT9_BUS0 : \
671  (i) == 0xA ? MXC_PT10_BUS0 : \
672  (i) == 0xB ? MXC_PT11_BUS0 : \
673  (i) == 0xC ? MXC_PT12_BUS0 : \
674  (i) == 0xD ? MXC_PT13_BUS0 : \
675  (i) == 0xE ? MXC_PT14_BUS0 : \
676  (i) == 0xF ? MXC_PT15_BUS0 : \
677  (i) == 0x8000 ? MXC_PT0_BUS1 : \
678  (i) == 0x8001 ? MXC_PT1_BUS1 : \
679  (i) == 0x8002 ? MXC_PT2_BUS1 : \
680  (i) == 0x8003 ? MXC_PT3_BUS1 : \
681  (i) == 0x8004 ? MXC_PT4_BUS1 : \
682  (i) == 0x8005 ? MXC_PT5_BUS1 : \
683  (i) == 0x8006 ? MXC_PT6_BUS1 : \
684  (i) == 0x8007 ? MXC_PT7_BUS1 : \
685  (i) == 0x8008 ? MXC_PT8_BUS1 : \
686  (i) == 0x8009 ? MXC_PT9_BUS1 : \
687  (i) == 0x800A ? MXC_PT10_BUS1 : \
688  (i) == 0x800B ? MXC_PT11_BUS1 : \
689  (i) == 0x800C ? MXC_PT12_BUS1 : \
690  (i) == 0x800D ? MXC_PT13_BUS1 : \
691  (i) == 0x800E ? MXC_PT14_BUS1 : \
692  (i) == 0x800F ? MXC_PT15_BUS1 : 0)
693 
694 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0_BUS0 ? 0x0 : \
695  (p) == MXC_PT1_BUS0 ? 0x1 : \
696  (p) == MXC_PT2_BUS0 ? 0x2 : \
697  (p) == MXC_PT3_BUS0 ? 0x3 : \
698  (p) == MXC_PT4_BUS0 ? 0x4 : \
699  (p) == MXC_PT5_BUS0 ? 0x5 : \
700  (p) == MXC_PT6_BUS0 ? 0x6 : \
701  (p) == MXC_PT7_BUS0 ? 0x7 : \
702  (p) == MXC_PT8_BUS0 ? 0x8 : \
703  (p) == MXC_PT9_BUS0 ? 0x9 : \
704  (p) == MXC_PT10_BUS0 ? 0xA : \
705  (p) == MXC_PT11_BUS0 ? 0xB : \
706  (p) == MXC_PT12_BUS0 ? 0xC : \
707  (p) == MXC_PT13_BUS0 ? 0xD : \
708  (p) == MXC_PT14_BUS0 ? 0xE : \
709  (p) == MXC_PT15_BUS0 ? 0xF : \
710  (p) == MXC_PT0_BUS1 ? 0x8000 : \
711  (p) == MXC_PT1_BUS1 ? 0x8001 : \
712  (p) == MXC_PT2_BUS1 ? 0x8002 : \
713  (p) == MXC_PT3_BUS1 ? 0x8003 : \
714  (p) == MXC_PT4_BUS1 ? 0x8004 : \
715  (p) == MXC_PT5_BUS1 ? 0x8005 : \
716  (p) == MXC_PT6_BUS1 ? 0x8006 : \
717  (p) == MXC_PT7_BUS1 ? 0x8007 : \
718  (p) == MXC_PT8_BUS1 ? 0x8008 : \
719  (p) == MXC_PT9_BUS1 ? 0x8009 : \
720  (p) == MXC_PT10_BUS1 ? 0x800A : \
721  (p) == MXC_PT11_BUS1 ? 0x800B : \
722  (p) == MXC_PT12_BUS1 ? 0x800C : \
723  (p) == MXC_PT13_BUS1 ? 0x800D : \
724  (p) == MXC_PT14_BUS1 ? 0x800E : \
725  (p) == MXC_PT15_BUS1 ? 0x800F : -1)
726 
727 #define MXC_PT_GET_BUS(i) (((i) & 0x00100000UL)>>20)
728 
729 #define MXC_PTG_GET_PTG(i) (MXC_PT_GET_BUS((i)) == 0 ? MXC_PTG_BUS0 : \
730  MXC_PT_GET_BUS((i)) == 1 ? MXC_PTG_BUS1 : 0)
731 
732 /******************************************************************************/
733 /* One Wire Master */
734 #define MXC_BASE_OWM ((uint32_t)0x4003D000UL)
735 #define MXC_OWM ((mxc_owm_regs_t*)MXC_BASE_OWM)
736 
737 /******************************************************************************/
738 /* Semaphore */
739 #define MXC_CFG_SEMA_INSTANCES (8)
740 
741 #define MXC_BASE_SEMA ((uint32_t)0x4003E000UL)
742 #define MXC_SEMA ((mxc_sema_regs_t*)MXC_BASE_SEMA)
743 
744 /******************************************************************************/
745 /* UART / Serial Port Interface */
746 
747 #define MXC_UART_INSTANCES (3)
748 #define MXC_UART_FIFO_DEPTH (32)
749 
750 #define MXC_BASE_UART0 ((uint32_t)0x40042000UL)
751 #define MXC_UART0 ((mxc_uart_regs_t*)MXC_BASE_UART0)
752 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
753 #define MXC_UART1 ((mxc_uart_regs_t*)MXC_BASE_UART1)
754 #define MXC_BASE_UART2 ((uint32_t)0x40044000UL)
755 #define MXC_UART2 ((mxc_uart_regs_t*)MXC_BASE_UART2)
756 
757 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
758  (i) == 1 ? UART1_IRQn : \
759  (i) == 2 ? UART2_IRQn : 0)
760 
761 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
762  (i) == 1 ? MXC_BASE_UART1 : \
763  (i) == 2 ? MXC_BASE_UART2 : 0)
764 
765 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
766  (i) == 1 ? MXC_UART1 : \
767  (i) == 2 ? MXC_UART2 : 0)
768 
769 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
770  (p) == MXC_UART1 ? 1 : \
771  (p) == MXC_UART2 ? 2 : -1)
772 
773 /******************************************************************************/
774 /* SPI17Y */
775 
776 #define MXC_SPI17Y_INSTANCES (3)
777 #define MXC_SPI17Y_SS_INSTANCES (4)
778 #define MXC_SPI17Y_FIFO_DEPTH (32)
779 
780 #define MXC_BASE_SPI17Y0 ((uint32_t)0x400BE000UL)
781 #define MXC_SPI17Y0 ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y0)
782 #define MXC_BASE_SPI17Y1 ((uint32_t)0x40046000UL)
783 #define MXC_SPI17Y1 ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y1)
784 #define MXC_BASE_SPI17Y2 ((uint32_t)0x40047000UL)
785 #define MXC_SPI17Y2 ((mxc_spi17y_regs_t*)MXC_BASE_SPI17Y2)
786 
787 
788 #define MXC_SPI17Y_GET_IDX(p) ((p) == MXC_SPI17Y0 ? 0 : \
789  (p) == MXC_SPI17Y1 ? 1 : \
790  (p) == MXC_SPI17Y2 ? 2 : -1)
791 
792 #define MXC_SPI17Y_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI17Y0 : \
793  (i) == 1 ? MXC_BASE_SPI17Y1 : \
794  (i) == 2 ? MXC_BASE_SPI17Y2 : 0)
795 
796 #define MXC_SPI17Y_GET_SPI17Y(i) ((i) == 0 ? MXC_SPI17Y0 : \
797  (i) == 1 ? MXC_SPI17Y1 : \
798  (i) == 2 ? MXC_SPI17Y2 : 0)
799 
800 #define MXC_SPI17Y_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI17Y0_IRQn : \
801  (i) == 1 ? SPI17Y1_IRQn : \
802  (i) == 2 ? SPI17Y2_IRQn : 0)
803 
804 
805 /******************************************************************************/
806 /* TRNG */
807 #define MXC_BASE_TRNG ((uint32_t)0x4004D000UL)
808 #define MXC_TRNG ((mxc_trng_regs_t*)MXC_BASE_TRNG)
809 
810 /******************************************************************************/
811 /* SDHC */
812 #define MXC_BASE_SDHC ((uint32_t)0x400B6000UL)
813 #define MXC_SDHC ((mxc_sdhc_regs_t*)MXC_BASE_SDHC)
814 
815 /******************************************************************************/
816 /* RPU */
817 #define MXC_BASE_RPU ((uint32_t)0x40002000UL)
818 #define MXC_RPU ((mxc_rpu_regs_t*)MXC_BASE_RPU)
819 #define MXC_RPU_NUM_BUS_MASTERS 9
820 
821 /******************************************************************************/
822 /* Audio Subsystem */
823 #define MXC_BASE_AUDIO ((uint32_t)0x4004C000UL)
824 #define MXC_AUDIO ((mxc_audio_regs_t*)MXC_BASE_AUDIO)
825 
826 /******************************************************************************/
827 /* Bluetooth Low Energy */
828 #define MXC_BASE_BTLE (0x40050000UL)
829 #define MXC_BTLE ((mxc_btle_regs_t*)MXC_BASE_BTLE)
830 #define MXC_BASE_BTLE_DBB_CTRL (MXC_BASE_BTLE + 0x1000)
831 #define MXC_BASE_BTLE_DBB_TX (MXC_BASE_BTLE + 0x2000)
832 #define MXC_BASE_BTLE_DBB_RX (MXC_BASE_BTLE + 0x3000)
833 #define MXC_BASE_BTLE_DBB_EXT_RFFE (MXC_BASE_BTLE + 0x8000)
834 
835 // Base address definitions needed for DBB register definitions in BTLE stack
836 #define DBB_CTRL_BASE MXC_BASE_BTLE_DBB_CTRL
837 #define DBB_TX_BASE MXC_BASE_BTLE_DBB_TX
838 #define DBB_RX_BASE MXC_BASE_BTLE_DBB_RX
839 #define DBB_EXT_RFFE_BASE MXC_BASE_BTLE_DBB_EXT_RFFE
840 
841 
842 /******************************************************************************/
843 /* Bit Shifting */
844 
845 #define MXC_F_BIT_0 (1 << 0)
846 #define MXC_F_BIT_1 (1 << 1)
847 #define MXC_F_BIT_2 (1 << 2)
848 #define MXC_F_BIT_3 (1 << 3)
849 #define MXC_F_BIT_4 (1 << 4)
850 #define MXC_F_BIT_5 (1 << 5)
851 #define MXC_F_BIT_6 (1 << 6)
852 #define MXC_F_BIT_7 (1 << 7)
853 #define MXC_F_BIT_8 (1 << 8)
854 #define MXC_F_BIT_9 (1 << 9)
855 #define MXC_F_BIT_10 (1 << 10)
856 #define MXC_F_BIT_11 (1 << 11)
857 #define MXC_F_BIT_12 (1 << 12)
858 #define MXC_F_BIT_13 (1 << 13)
859 #define MXC_F_BIT_14 (1 << 14)
860 #define MXC_F_BIT_15 (1 << 15)
861 #define MXC_F_BIT_16 (1 << 16)
862 #define MXC_F_BIT_17 (1 << 17)
863 #define MXC_F_BIT_18 (1 << 18)
864 #define MXC_F_BIT_19 (1 << 19)
865 #define MXC_F_BIT_20 (1 << 20)
866 #define MXC_F_BIT_21 (1 << 21)
867 #define MXC_F_BIT_22 (1 << 22)
868 #define MXC_F_BIT_23 (1 << 23)
869 #define MXC_F_BIT_24 (1 << 24)
870 #define MXC_F_BIT_25 (1 << 25)
871 #define MXC_F_BIT_26 (1 << 26)
872 #define MXC_F_BIT_27 (1 << 27)
873 #define MXC_F_BIT_28 (1 << 28)
874 #define MXC_F_BIT_29 (1 << 29)
875 #define MXC_F_BIT_30 (1 << 30)
876 #define MXC_F_BIT_31 (1 << 31)
877 
878 /******************************************************************************/
879 /* Bit Banding */
880 
881 
882 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + \
883  (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
884 
885 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
886 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
887 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
888 
889 #define MXC_SETFIELD(reg, mask, setting) (reg = (reg & ~mask) | (setting & mask))
890 
891 /******************************************************************************/
892 /* SCB CPACR */
893 
894 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
895 #define SCB_CPACR_CP10_Pos 20
896 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos)
897 #define SCB_CPACR_CP11_Pos 22
898 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos)
900 #endif /* _MAX32665_REGS_H_ */