50 #if defined (__ICCARM__) 51 #pragma system_include 54 #if defined (__CC_ARM) 65 #define __I volatile const 71 #define __R volatile const 106 __R uint32_t rsv_0x44;
118 #define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) 119 #define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) 120 #define MXC_R_I2C_INT_FL0 ((uint32_t)0x00000008UL) 121 #define MXC_R_I2C_INT_EN0 ((uint32_t)0x0000000CUL) 122 #define MXC_R_I2C_INT_FL1 ((uint32_t)0x00000010UL) 123 #define MXC_R_I2C_INT_EN1 ((uint32_t)0x00000014UL) 124 #define MXC_R_I2C_FIFO_LEN ((uint32_t)0x00000018UL) 125 #define MXC_R_I2C_RX_CTRL0 ((uint32_t)0x0000001CUL) 126 #define MXC_R_I2C_RX_CTRL1 ((uint32_t)0x00000020UL) 127 #define MXC_R_I2C_TX_CTRL0 ((uint32_t)0x00000024UL) 128 #define MXC_R_I2C_TX_CTRL1 ((uint32_t)0x00000028UL) 129 #define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) 130 #define MXC_R_I2C_MASTER_CTRL ((uint32_t)0x00000030UL) 131 #define MXC_R_I2C_CLK_LO ((uint32_t)0x00000034UL) 132 #define MXC_R_I2C_CLK_HI ((uint32_t)0x00000038UL) 133 #define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) 134 #define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) 135 #define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) 136 #define MXC_R_I2C_SLAVE_ADDR ((uint32_t)0x0000004CUL) 145 #define MXC_F_I2C_CTRL_I2C_EN_POS 0 146 #define MXC_F_I2C_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_I2C_EN_POS)) 148 #define MXC_F_I2C_CTRL_MST_POS 1 149 #define MXC_F_I2C_CTRL_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) 151 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 152 #define MXC_F_I2C_CTRL_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) 154 #define MXC_F_I2C_CTRL_RX_MODE_POS 3 155 #define MXC_F_I2C_CTRL_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_POS)) 157 #define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 158 #define MXC_F_I2C_CTRL_RX_MODE_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) 160 #define MXC_F_I2C_CTRL_SCL_OUT_POS 6 161 #define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) 163 #define MXC_F_I2C_CTRL_SDA_OUT_POS 7 164 #define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) 166 #define MXC_F_I2C_CTRL_SCL_POS 8 167 #define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) 169 #define MXC_F_I2C_CTRL_SDA_POS 9 170 #define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) 172 #define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 173 #define MXC_F_I2C_CTRL_SW_OUT_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SW_OUT_EN_POS)) 175 #define MXC_F_I2C_CTRL_READ_POS 11 176 #define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) 178 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS 12 179 #define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) 181 #define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 182 #define MXC_F_I2C_CTRL_SCL_PP_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) 184 #define MXC_F_I2C_CTRL_HS_MODE_POS 15 185 #define MXC_F_I2C_CTRL_HS_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_MODE_POS)) 195 #define MXC_F_I2C_STATUS_BUS_POS 0 196 #define MXC_F_I2C_STATUS_BUS ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUS_POS)) 198 #define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 199 #define MXC_F_I2C_STATUS_RX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EMPTY_POS)) 201 #define MXC_F_I2C_STATUS_RX_FULL_POS 2 202 #define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) 204 #define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 205 #define MXC_F_I2C_STATUS_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EMPTY_POS)) 207 #define MXC_F_I2C_STATUS_TX_FULL_POS 4 208 #define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) 210 #define MXC_F_I2C_STATUS_CLK_MODE_POS 5 211 #define MXC_F_I2C_STATUS_CLK_MODE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CLK_MODE_POS)) 221 #define MXC_F_I2C_INT_FL0_DONE_POS 0 222 #define MXC_F_I2C_INT_FL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DONE_POS)) 224 #define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 225 #define MXC_F_I2C_INT_FL0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_MODE_POS)) 227 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS 2 228 #define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) 230 #define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 231 #define MXC_F_I2C_INT_FL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) 233 #define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 234 #define MXC_F_I2C_INT_FL0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RX_THRESH_POS)) 236 #define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 237 #define MXC_F_I2C_INT_FL0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_THRESH_POS)) 239 #define MXC_F_I2C_INT_FL0_STOP_POS 6 240 #define MXC_F_I2C_INT_FL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_POS)) 242 #define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 243 #define MXC_F_I2C_INT_FL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) 245 #define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 246 #define MXC_F_I2C_INT_FL0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ARB_ER_POS)) 248 #define MXC_F_I2C_INT_FL0_TO_ER_POS 9 249 #define MXC_F_I2C_INT_FL0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TO_ER_POS)) 251 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS 10 252 #define MXC_F_I2C_INT_FL0_ADDR_NACK_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) 254 #define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 255 #define MXC_F_I2C_INT_FL0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DATA_ER_POS)) 257 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS 12 258 #define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) 260 #define MXC_F_I2C_INT_FL0_START_ER_POS 13 261 #define MXC_F_I2C_INT_FL0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_START_ER_POS)) 263 #define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 264 #define MXC_F_I2C_INT_FL0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_STOP_ER_POS)) 266 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS 15 267 #define MXC_F_I2C_INT_FL0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) 269 #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS 22 270 #define MXC_F_I2C_INT_FL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_RD_ADDR_MATCH_POS)) 272 #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS 23 273 #define MXC_F_I2C_INT_FL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL0_WR_ADDR_MATCH_POS)) 283 #define MXC_F_I2C_INT_EN0_DONE_POS 0 284 #define MXC_F_I2C_INT_EN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DONE_POS)) 286 #define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 287 #define MXC_F_I2C_INT_EN0_RX_MODE ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_MODE_POS)) 289 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS 2 290 #define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) 292 #define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 293 #define MXC_F_I2C_INT_EN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) 295 #define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 296 #define MXC_F_I2C_INT_EN0_RX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RX_THRESH_POS)) 298 #define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 299 #define MXC_F_I2C_INT_EN0_TX_THRESH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_THRESH_POS)) 301 #define MXC_F_I2C_INT_EN0_STOP_POS 6 302 #define MXC_F_I2C_INT_EN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_POS)) 304 #define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 305 #define MXC_F_I2C_INT_EN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) 307 #define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 308 #define MXC_F_I2C_INT_EN0_ARB_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ARB_ER_POS)) 310 #define MXC_F_I2C_INT_EN0_TO_ER_POS 9 311 #define MXC_F_I2C_INT_EN0_TO_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TO_ER_POS)) 313 #define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 314 #define MXC_F_I2C_INT_EN0_ADDR_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) 316 #define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 317 #define MXC_F_I2C_INT_EN0_DATA_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DATA_ER_POS)) 319 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS 12 320 #define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) 322 #define MXC_F_I2C_INT_EN0_START_ER_POS 13 323 #define MXC_F_I2C_INT_EN0_START_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_START_ER_POS)) 325 #define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 326 #define MXC_F_I2C_INT_EN0_STOP_ER ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_STOP_ER_POS)) 328 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS 15 329 #define MXC_F_I2C_INT_EN0_TX_LOCK_OUT ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) 331 #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS 22 332 #define MXC_F_I2C_INT_EN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_RD_ADDR_MATCH_POS)) 334 #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS 23 335 #define MXC_F_I2C_INT_EN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN0_WR_ADDR_MATCH_POS)) 345 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS 0 346 #define MXC_F_I2C_INT_FL1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) 348 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS 1 349 #define MXC_F_I2C_INT_FL1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) 351 #define MXC_F_I2C_INT_FL1_START_POS 2 352 #define MXC_F_I2C_INT_FL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS)) 362 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS 0 363 #define MXC_F_I2C_INT_EN1_RX_OVERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) 365 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS 1 366 #define MXC_F_I2C_INT_EN1_TX_UNDERFLOW ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) 368 #define MXC_F_I2C_INT_EN1_START_POS 2 369 #define MXC_F_I2C_INT_EN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INT_EN1_START_POS)) 379 #define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 380 #define MXC_F_I2C_FIFO_LEN_RX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) 382 #define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 383 #define MXC_F_I2C_FIFO_LEN_TX_LEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) 393 #define MXC_F_I2C_RX_CTRL0_DNR_POS 0 394 #define MXC_F_I2C_RX_CTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_DNR_POS)) 396 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 397 #define MXC_F_I2C_RX_CTRL0_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) 399 #define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 400 #define MXC_F_I2C_RX_CTRL0_RX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) 410 #define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 411 #define MXC_F_I2C_RX_CTRL1_RX_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) 413 #define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 414 #define MXC_F_I2C_RX_CTRL1_RX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) 424 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS 0 425 #define MXC_F_I2C_TX_CTRL0_TX_PRELOAD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) 427 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS 1 428 #define MXC_F_I2C_TX_CTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) 430 #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS 2 431 #define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS)) 433 #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS 3 434 #define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS)) 436 #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS 4 437 #define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS)) 439 #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS 5 440 #define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS)) 442 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 443 #define MXC_F_I2C_TX_CTRL0_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) 445 #define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 446 #define MXC_F_I2C_TX_CTRL0_TX_THRESH ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) 456 #define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 457 #define MXC_F_I2C_TX_CTRL1_TX_READY ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_READY_POS)) 459 #define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 460 #define MXC_F_I2C_TX_CTRL1_TX_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) 462 #define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 463 #define MXC_F_I2C_TX_CTRL1_TX_FIFO ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) 473 #define MXC_F_I2C_FIFO_DATA_POS 0 474 #define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) 484 #define MXC_F_I2C_MASTER_CTRL_START_POS 0 485 #define MXC_F_I2C_MASTER_CTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_START_POS)) 487 #define MXC_F_I2C_MASTER_CTRL_RESTART_POS 1 488 #define MXC_F_I2C_MASTER_CTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_RESTART_POS)) 490 #define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 491 #define MXC_F_I2C_MASTER_CTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_STOP_POS)) 493 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS 7 494 #define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) 496 #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS 8 497 #define MXC_F_I2C_MASTER_CTRL_MASTER_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) 499 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS 11 500 #define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP ((uint32_t)(0x1UL << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) 510 #define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 511 #define MXC_F_I2C_CLK_LO_CLK_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_LO_CLK_LO_POS)) 521 #define MXC_F_I2C_CLK_HI_CKH_POS 0 522 #define MXC_F_I2C_CLK_HI_CKH ((uint32_t)(0x1FFUL << MXC_F_I2C_CLK_HI_CKH_POS)) 532 #define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 533 #define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) 535 #define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 536 #define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) 546 #define MXC_F_I2C_TIMEOUT_TO_POS 0 547 #define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) 557 #define MXC_F_I2C_DMA_TX_EN_POS 0 558 #define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) 560 #define MXC_F_I2C_DMA_RX_EN_POS 1 561 #define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) 571 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS 0 572 #define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) 574 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS 15 575 #define MXC_F_I2C_SLAVE_ADDR_EX_ADDR ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) __IO uint32_t int_en0
0x0C: I2C INT_EN0 Register
Definition: i2c_regs.h:92
__IO uint32_t master_ctrl
0x30: I2C MASTER_CTRL Register
Definition: i2c_regs.h:101
__IO uint32_t hs_clk
0x3C: I2C HS_CLK Register
Definition: i2c_regs.h:104
__IO uint32_t dma
0x48: I2C DMA Register
Definition: i2c_regs.h:107
__IO uint32_t int_fl0
0x08: I2C INT_FL0 Register
Definition: i2c_regs.h:91
__IO uint32_t fifo_len
0x18: I2C FIFO_LEN Register
Definition: i2c_regs.h:95
__IO uint32_t rx_ctrl1
0x20: I2C RX_CTRL1 Register
Definition: i2c_regs.h:97
__IO uint32_t clk_hi
0x38: I2C CLK_HI Register
Definition: i2c_regs.h:103
__IO uint32_t status
0x04: I2C STATUS Register
Definition: i2c_regs.h:90
__IO uint32_t fifo
0x2C: I2C FIFO Register
Definition: i2c_regs.h:100
__IO uint32_t rx_ctrl0
0x1C: I2C RX_CTRL0 Register
Definition: i2c_regs.h:96
__IO uint32_t slave_addr
0x4C: I2C SLAVE_ADDR Register
Definition: i2c_regs.h:108
__IO uint32_t timeout
0x40: I2C TIMEOUT Register
Definition: i2c_regs.h:105
Structure type to access the I2C Registers.
Definition: i2c_regs.h:88
__IO uint32_t tx_ctrl1
0x28: I2C TX_CTRL1 Register
Definition: i2c_regs.h:99
__IO uint32_t ctrl
0x00: I2C CTRL Register
Definition: i2c_regs.h:89
__IO uint32_t clk_lo
0x34: I2C CLK_LO Register
Definition: i2c_regs.h:102
__IO uint32_t int_fl1
0x10: I2C INT_FL1 Register
Definition: i2c_regs.h:93
__IO uint32_t tx_ctrl0
0x24: I2C TX_CTRL0 Register
Definition: i2c_regs.h:98
__IO uint32_t int_en1
0x14: I2C INT_EN1 Register
Definition: i2c_regs.h:94