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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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DMA Interrupt Register. More...
Macros | |
#define | MXC_F_DMA_INTR_CH0_IPEND_POS 0 |
INTR_CH0_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH0_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS)) |
INTR_CH0_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH1_IPEND_POS 1 |
INTR_CH1_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH1_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS)) |
INTR_CH1_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH2_IPEND_POS 2 |
INTR_CH2_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH2_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS)) |
INTR_CH2_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH3_IPEND_POS 3 |
INTR_CH3_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH3_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS)) |
INTR_CH3_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH4_IPEND_POS 4 |
INTR_CH4_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH4_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS)) |
INTR_CH4_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH5_IPEND_POS 5 |
INTR_CH5_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH5_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS)) |
INTR_CH5_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH6_IPEND_POS 6 |
INTR_CH6_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH6_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS)) |
INTR_CH6_IPEND Mask. | |
#define | MXC_F_DMA_INTR_CH7_IPEND_POS 7 |
INTR_CH7_IPEND Position. | |
#define | MXC_F_DMA_INTR_CH7_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS)) |
INTR_CH7_IPEND Mask. | |