MAX32665 SDK Documentation  0.2
Software Development Kit Overview and API Documentation
mxc_sys.h
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36 
42 #ifndef _MXC_SYS_H_
43 #define _MXC_SYS_H_
44 
45 #include "mxc_config.h"
46 #include "uart_regs.h"
47 #include "i2c_regs.h"
48 #include "ptg_regs.h"
49 #include "pt_regs.h"
50 #include "gcr_regs.h"
51 #include "tmr_regs.h"
52 #include "gpio.h"
53 #include "sdhc_regs.h"
54 #include "flc_regs.h"
55 #include "spixfc_regs.h"
56 #include "spi17y_regs.h"
57 #include "htmr_regs.h"
58 #include "wdt_regs.h"
59 #include "dma.h"
60 
61 #ifdef __cplusplus
62 extern "C" {
63 #endif
64 
66 typedef enum {
67  SYS_RESET_DMA = MXC_F_GCR_RSTR0_DMA_POS,
68  SYS_RESET_WDT = MXC_F_GCR_RSTR0_WDT0_POS,
69  SYS_RESET_GPIO0 = MXC_F_GCR_RSTR0_GPIO0_POS,
70  SYS_RESET_GPIO1 = MXC_F_GCR_RSTR0_GPIO1_POS,
71  SYS_RESET_TIMER0 = MXC_F_GCR_RSTR0_TIMER0_POS,
72  SYS_RESET_TIMER1 = MXC_F_GCR_RSTR0_TIMER1_POS,
73  SYS_RESET_TIMER2 = MXC_F_GCR_RSTR0_TIMER2_POS,
74  SYS_RESET_TIMER3 = MXC_F_GCR_RSTR0_TIMER3_POS,
75  SYS_RESET_TIMER4 = MXC_F_GCR_RSTR0_TIMER4_POS,
76  SYS_RESET_TIMER5 = MXC_F_GCR_RSTR0_TIMER5_POS,
77  SYS_RESET_UART0 = MXC_F_GCR_RSTR0_UART0_POS,
78  SYS_RESET_UART1 = MXC_F_GCR_RSTR0_UART1_POS,
79  SYS_RESET_SPI1 = MXC_F_GCR_RSTR0_SPI1_POS,
80  SYS_RESET_SPI2 = MXC_F_GCR_RSTR0_SPI2_POS,
81  SYS_RESET_I2C0 = MXC_F_GCR_RSTR0_I2C0_POS,
82  SYS_RESET_RTC = MXC_F_GCR_RSTR0_RTC_POS,
83  SYS_RESET_CRYPTO = MXC_F_GCR_RSTR0_CRYPTO_POS,
84  SYS_RESET_USB = MXC_F_GCR_RSTR0_USB_POS,
85  SYS_RESET_TRNG = MXC_F_GCR_RSTR0_TRNG_POS,
86  SYS_RESET_ADC = MXC_F_GCR_RSTR0_ADC_POS,
87  SYS_RESET_UART2 = MXC_F_GCR_RSTR0_UART2_POS,
88  SYS_RESET_SRST = MXC_F_GCR_RSTR0_SRST_POS,
89  SYS_RESET_PRST = MXC_F_GCR_RSTR0_PRST_POS,
90  SYS_RESET_SYSTEM = MXC_F_GCR_RSTR0_SYSTEM_POS,
91  /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
92  SYS_RESET_I2C1 = (MXC_F_GCR_RSTR1_I2C1_POS + 32),
93  SYS_RESET_PT = (MXC_F_GCR_RSTR1_PT_POS + 32),
94  SYS_RESET_SPIXIP = (MXC_F_GCR_RSTR1_SPIXIP_POS + 32),
95  SYS_RESET_XSPIM = (MXC_F_GCR_RSTR1_XSPIM_POS + 32),
96  SYS_RESET_SDHC = (MXC_F_GCR_RSTR1_SDHC_POS + 32),
97  SYS_RESET_OWIRE = (MXC_F_GCR_RSTR1_OWIRE_POS + 32),
98  SYS_RESET_HTR0 = (MXC_F_GCR_RSTR1_HTMR0_POS + 32),
99  SYS_RESET_HTMR1 = (MXC_F_GCR_RSTR1_HTMR1_POS + 32),
100  SYS_RESET_WDT1 = (MXC_F_GCR_RSTR1_WDT1_POS + 32),
101  SYS_RESET_SPI0 = (MXC_F_GCR_RSTR1_SPI0_POS + 32),
102  SYS_RESET_SPIXMEM = (MXC_F_GCR_RSTR1_SPIXMEM_POS + 32),
103  SYS_RESET_SMPHR = (MXC_F_GCR_RSTR1_SMPHR_POS + 32)
104 } sys_reset_t;
105 
107 typedef enum {
108  SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PERCKCN0_GPIO0D_POS,
109  SYS_PERIPH_CLOCK_GPIO1 = MXC_F_GCR_PERCKCN0_GPIO1D_POS,
110  SYS_PERIPH_CLOCK_USB = MXC_F_GCR_PERCKCN0_USBD_POS,
111  SYS_PERIPH_CLOCK_DMA = MXC_F_GCR_PERCKCN0_DMAD_POS,
112  SYS_PERIPH_CLOCK_SPI1 = MXC_F_GCR_PERCKCN0_SPI1D_POS,
113  SYS_PERIPH_CLOCK_SPI2 = MXC_F_GCR_PERCKCN0_SPI2D_POS,
114  SYS_PERIPH_CLOCK_UART0 = MXC_F_GCR_PERCKCN0_UART0D_POS,
115  SYS_PERIPH_CLOCK_UART1 = MXC_F_GCR_PERCKCN0_UART1D_POS,
116  SYS_PERIPH_CLOCK_I2C0 = MXC_F_GCR_PERCKCN0_I2C0D_POS,
117  SYS_PERIPH_CLOCK_TPU = MXC_F_GCR_PERCKCN0_CRYPTOD_POS,
118  SYS_PERIPH_CLOCK_T0 = MXC_F_GCR_PERCKCN0_TIMER0D_POS,
119  SYS_PERIPH_CLOCK_T1 = MXC_F_GCR_PERCKCN0_TIMER1D_POS,
120  SYS_PERIPH_CLOCK_T2 = MXC_F_GCR_PERCKCN0_TIMER2D_POS,
121  SYS_PERIPH_CLOCK_T3 = MXC_F_GCR_PERCKCN0_TIMER3D_POS,
122  SYS_PERIPH_CLOCK_T4 = MXC_F_GCR_PERCKCN0_TIMER4D_POS,
123  SYS_PERIPH_CLOCK_T5 = MXC_F_GCR_PERCKCN0_TIMER5D_POS,
124  SYS_PERIPH_CLOCK_ADC = MXC_F_GCR_PERCKCN0_ADCD_POS,
125  SYS_PERIPH_CLOCK_I2C1 = MXC_F_GCR_PERCKCN0_I2C1D_POS,
126  SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PERCKCN0_PTD_POS,
127  SYS_PERIPH_CLOCK_SPIXIP = MXC_F_GCR_PERCKCN0_SPIXIPD_POS,
128  SYS_PERIPH_CLOCK_SPIXFC = MXC_F_GCR_PERCKCN0_SPIMD_POS,
129  /* PERCKCN1 Below this line we add 32 to separate PERCKCN0 and PERCKCN1 */
130  SYS_PERIPH_CLOCK_BTLE =(MXC_F_GCR_PERCKCN1_BTLED_POS + 32),
131  SYS_PERIPH_CLOCK_UART2 =(MXC_F_GCR_PERCKCN1_UART2D_POS + 32),
132  SYS_PERIPH_CLOCK_TRNG =(MXC_F_GCR_PERCKCN1_TRNGD_POS + 32),
133  SYS_PERIPH_CLOCK_SCACHE =(MXC_F_GCR_PERCKCN1_SCACHED_POS + 32),
134  SYS_PERIPH_CLOCK_SDMA =(MXC_F_GCR_PERCKCN1_SDMAD_POS + 32),
135  SYS_PERIPH_CLOCK_SMPHR =(MXC_F_GCR_PERCKCN1_SMPHRD_POS + 32),
136  SYS_PERIPH_CLOCK_SDHC =(MXC_F_GCR_PERCKCN1_SDHCD_POS + 32),
137  SYS_PERIPH_CLOCK_ICACHEXIP =(MXC_F_GCR_PERCKCN1_ICACHEXIPD_POS + 32),
138  SYS_PERIPH_CLOCK_OWIRE =(MXC_F_GCR_PERCKCN1_OWIRED_POS + 32),
139  SYS_PERIPH_CLOCK_SPI0 =(MXC_F_GCR_PERCKCN1_SPI0D_POS + 32),
140  SYS_PERIPH_CLOCK_SPIXIPD =(MXC_F_GCR_PERCKCN1_SPIXIPDD_POS + 32),
141  SYS_PERIPH_CLOCK_DMA1 =(MXC_F_GCR_PERCKCN1_DMA1_POS + 32),
142  SYS_PERIPH_CLOCK_AUDIO =(MXC_F_GCR_PERCKCN1_AUDIO_POS + 32),
143  SYS_PERIPH_CLOCK_I2C2 =(MXC_F_GCR_PERCKCN1_I2C2_POS + 32),
144  SYS_PERIPH_CLOCK_HTMR0 =(MXC_F_GCR_PERCKCN1_HTMR0_POS + 32),
145  SYS_PERIPH_CLOCK_HTMR1 =(MXC_F_GCR_PERCKCN1_HTMR1_POS + 32),
146  SYS_PERIPH_CLOCK_WDT0 =(MXC_F_GCR_PERCKCN1_WDT0_POS + 32),
147  SYS_PERIPH_CLOCK_WDT1 =(MXC_F_GCR_PERCKCN1_WDT1_POS + 32),
148  SYS_PERIPH_CLOCK_WDT2 =(MXC_F_GCR_PERCKCN1_WDT2_POS + 32),
149  SYS_PERIPH_CLOCK_CPU1 =(MXC_F_GCR_PERCKCN1_CPU1_POS + 32)
150 } sys_periph_clock_t;
151 
152 typedef enum {
153  SYS_CLOCK_HIRC96 = MXC_V_GCR_CLKCN_CLKSEL_HIRC96,
154  SYS_CLOCK_HIRC8 = MXC_V_GCR_CLKCN_CLKSEL_HIRC8,
155  SYS_CLOCK_HIRC = MXC_V_GCR_CLKCN_CLKSEL_HIRC,
156  SYS_CLOCK_XTAL32M = MXC_V_GCR_CLKCN_CLKSEL_XTAL32M,
157  SYS_CLOCK_LIRC8K = MXC_V_GCR_CLKCN_CLKSEL_LIRC8,
158  SYS_CLOCK_XTAL32K = MXC_V_GCR_CLKCN_CLKSEL_XTAL32K
159 } sys_system_clock_t;
160 
161 #define SYS_SCACHE_CLK 1 // Enable SCACHE CLK
162 #define SYS_CRYPTO_CLK 1 // Enable CRYPTO CLK
163 
164 #define SYS_USN_CHECKSUM_LEN 16
165 
167 typedef enum {
168  MAP_A,
169  MAP_B
170 } sys_map_t;
172 typedef enum {
173  Disable,
174  Enable
175 } sys_control_t;
176 typedef void* sys_cfg_t;
177 
179 typedef struct
180 {
181  sys_map_t map;
182  sys_control_t ss0;
183  sys_control_t ss1;
184  sys_control_t ss2;
185  unsigned num_io;
187 
189 typedef struct
190 {
191  sys_map_t map;
192  sys_control_t flow;
194 
196 typedef struct
197 {
198  uint8_t scache_flag;
199  uint8_t crypto_flag;
201 
202 
204 typedef sys_cfg_t sys_cfg_i2c_t;
205 
207 typedef sys_cfg_t sys_cfg_sdhc_t;
208 
210 typedef sys_cfg_t sys_cfg_owm_t;
211 
213 typedef sys_cfg_t sys_cfg_scache_t;
214 
216 typedef sys_cfg_t sys_cfg_usbhs_t;
217 
219 typedef sys_cfg_t sys_cfg_rtc_t;
220 
222 typedef sys_cfg_t sys_cfg_tpu_t;
223 
225 typedef sys_cfg_t sys_cfg_tmr_t;
226 
228 typedef sys_cfg_t sys_cfg_adc_t;
229 
231 typedef sys_cfg_t sys_cfg_flc_t;
232 
234 typedef sys_cfg_t sys_cfg_trng_t;
235 
237 typedef sys_cfg_t sys_cfg_spixfc_t;
238 
240 typedef gpio_cfg_t sys_cfg_pt_t;
241 
243 typedef sys_cfg_t sys_cfg_ptg_t;
244 
246 typedef sys_cfg_t sys_cfg_htmr_t;
247 
249 typedef sys_cfg_t sys_cfg_sema_t;
250 
252 typedef sys_cfg_t sys_cfg_wdt_t;
253 
255 typedef unsigned int sys_pt_clk_scale;
256 
257 /***** Function Prototypes *****/
258 
266 int SYS_GetUSN(uint8_t *usn, uint8_t *checksum);
267 
273 int SYS_IsClockEnabled(sys_periph_clock_t clock);
274 
279 void SYS_ClockDisable(sys_periph_clock_t clock);
280 
285 void SYS_ClockEnable(sys_periph_clock_t clock);
286 
291 void SYS_RTCClockEnable(sys_cfg_rtc_t *sys_cfg);
292 
297 int SYS_RTCClockDisable(void);
298 
304 int SYS_ClockSourceEnable(sys_system_clock_t clock);
305 
311 int SYS_ClockSourceDisable(sys_system_clock_t clock);
312 
319 int SYS_Clock_Select(sys_system_clock_t clock, mxc_tmr_regs_t* tmr);
320 
327 int SYS_UART_Init(mxc_uart_regs_t *uart, const sys_cfg_uart_t* sys_cfg);
328 
336 
337 
344 int SYS_I2C_Init(mxc_i2c_regs_t *i2c, const sys_cfg_i2c_t* sys_cfg);
345 
351 int SYS_I2C_Shutdown(mxc_i2c_regs_t *i2c);
352 
358 unsigned SYS_I2C_GetFreq(mxc_i2c_regs_t *i2c);
359 
365 int SYS_PT_Config(mxc_pt_regs_t *pt, const sys_cfg_pt_t *cfg);
366 
371 void SYS_PT_Init(const sys_cfg_ptg_t* sys_cfg);
372 
376 void SYS_PT_Shutdown(void);
377 
382 unsigned SYS_PT_GetFreq(void);
383 
388 unsigned SYS_TMR_GetFreq(mxc_tmr_regs_t *tmr);
392 void SYS_Flash_Operation(void);
397 void SYS_Reset_Periph(sys_reset_t reset);
403 int SYS_SDHC_Init(const sys_cfg_sdhc_t* sys_cfg);
404 
409 int SYS_SDHC_Shutdown(void);
410 
415 int SYS_SEMA_Init(const sys_cfg_sema_t* sys_cfg);
416 
421 int SYS_SEMA_Shutdown(void);
422 
429 int SYS_SPIXFC_Init(mxc_spixfc_regs_t *spixfc, const sys_cfg_spixfc_t* sys_cfg);
430 
436 int SYS_SPIXFC_Shutdown(mxc_spixfc_regs_t *spixfc);
437 
438 
444 int SYS_SPIXFC_GetFreq(mxc_spixfc_regs_t *spixfc);
445 
446 
452 uint32_t SYS_OWM_Init(const sys_cfg_owm_t* sys_cfg);
453 
457 void SYS_OWM_Shutdown(void);
458 
463 uint32_t SYS_OWM_GetFreq(void);
464 
470 int SYS_SPIXR_Init(const sys_cfg_spixr_t* sys_cfg);
471 
475 void SYS_SPIXR_Shutdown(void);
476 
481 void SYS_SCACHE_Init(const sys_cfg_scache_t* sys_cfg);
482 
486 void SYS_SCACHE_Shutdown(void);
487 
488 
494 int SYS_SPI17Y_Init( mxc_spi17y_regs_t *spi, const sys_cfg_spi17y_t* sys_cfg);
495 
500 int SYS_SPI17Y_Shutdown(mxc_spi17y_regs_t *spi);
501 
506 void SYS_RTC_SqwavInit(const sys_cfg_rtc_t* sys_cfg);
507 
508 
513 int SYS_USBHS_Init(const sys_cfg_usbhs_t* sys_cfg);
514 
519 int SYS_USBHS_Shutdown(void);
523 void SYS_DMA_Init(void);
524 
528 void SYS_DMA_Shutdown(void);
529 
534 int SYS_TMR_Init(mxc_tmr_regs_t *tmr, const sys_cfg_tmr_t* sys_cfg);
535 
539 int SYS_TMR_Shutdown(mxc_tmr_regs_t *tmr);
540 
545 int SYS_TPU_Init(const sys_cfg_tpu_t* sys_cfg);
546 
550 int SYS_TPU_Shutdown(void);
551 
556 int SYS_ADC_Init(const sys_cfg_adc_t* sys_cfg);
557 
561 int SYS_ADC_Shutdown(void);
562 
566 int SYS_FLC_Init(const sys_cfg_flc_t* sys_cfg);
575 int SYS_FLC_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr);
576 
585 int SYS_FLC_GetPhysicalAddress( uint32_t addr, uint32_t *result);
586 
590 int SYS_FLC_Shutdown(void);
591 
596 int SYS_TRNG_Init(const sys_cfg_trng_t* sys_cfg);
597 
601 int SYS_TRNG_Shutdown(void);
602 
607 int SYS_HTMR_Init(mxc_htmr_regs_t *htmr);
608 
613 int SYS_HTMR_Shutdown(mxc_htmr_regs_t *htmr);
614 
620 int SYS_WDT_Init(mxc_wdt_regs_t *wdt, const sys_cfg_wdt_t* sys_cfg);
621 
626 uint32_t SYS_WUT_GetFreq(void);
627 
628 #ifdef __cplusplus
629 }
630 #endif
631 
632 #endif /* _MXC_SYS_H_*/
Structure type for configuring a GPIO port.
Definition: gpio.h:138
Structure type to access the WDT Registers.
Definition: wdt_regs.h:88
UART Configuration Object.
Definition: mxc_sys.h:189
SPIXR Configuration Object.
Definition: mxc_sys.h:196
Structure type to access the HTMR Registers.
Definition: htmr_regs.h:88
int SYS_UART_Shutdown(mxc_uart_regs_t *uart)
System level shutdown for UART module.
SPI17Y Configuration Object.
Definition: mxc_sys.h:179
Structure type to access the UART Registers.
Definition: uart_regs.h:88
Structure type to access the I2C Registers.
Definition: i2c_regs.h:88
Structure type to access the FLC Registers.
Definition: flc_regs.h:88
Structure type to access the SPI17Y Registers.
Definition: spi17y_regs.h:88
Structure type to access the TMR Registers.
Definition: tmr_regs.h:88
Structure type to access the PT Registers.
Definition: pt_regs.h:88
Structure type to access the SPIXFC Registers.
Definition: spixfc_regs.h:88