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MAX32665 SDK Documentation
0.2
Software Development Kit Overview and API Documentation
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Power Sequencer Protection Register. More...
Macros | |
| #define | MXC_F_RPU_PWRSEQ_DMA0ACN_POS 0 |
| PWRSEQ_DMA0ACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_DMA0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA0ACN_POS)) |
| PWRSEQ_DMA0ACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_DMA1ACN_POS 1 |
| PWRSEQ_DMA1ACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_DMA1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_DMA1ACN_POS)) |
| PWRSEQ_DMA1ACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_USBACN_POS 2 |
| PWRSEQ_USBACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_USBACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_USBACN_POS)) |
| PWRSEQ_USBACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_SYS0ACN_POS 3 |
| PWRSEQ_SYS0ACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_SYS0ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS0ACN_POS)) |
| PWRSEQ_SYS0ACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_SYS1ACN_POS 4 |
| PWRSEQ_SYS1ACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_SYS1ACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SYS1ACN_POS)) |
| PWRSEQ_SYS1ACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_SDMADACN_POS 5 |
| PWRSEQ_SDMADACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_SDMADACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMADACN_POS)) |
| PWRSEQ_SDMADACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_SDMAIACN_POS 6 |
| PWRSEQ_SDMAIACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_SDMAIACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDMAIACN_POS)) |
| PWRSEQ_SDMAIACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_CRYPTOACN_POS 7 |
| PWRSEQ_CRYPTOACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_CRYPTOACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_CRYPTOACN_POS)) |
| PWRSEQ_CRYPTOACN Mask. | |
| #define | MXC_F_RPU_PWRSEQ_SDIOACN_POS 8 |
| PWRSEQ_SDIOACN Position. | |
| #define | MXC_F_RPU_PWRSEQ_SDIOACN ((uint32_t)(0x1UL << MXC_F_RPU_PWRSEQ_SDIOACN_POS)) |
| PWRSEQ_SDIOACN Mask. | |