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 <span id="projectnumber">0.2</span>
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<div class="title">RPU_UART0<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> » <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div> </div>
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<p>UART0 Protection Register.
<a href="#details">More...</a></p>
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Macros</h2></td></tr>
<tr class="memitem:gac91a10f54ce8ca670dd985e70c792f60"><td class="memItemLeft" align="right" valign="top"><a id="gac91a10f54ce8ca670dd985e70c792f60"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gac91a10f54ce8ca670dd985e70c792f60">MXC_F_RPU_UART0_DMA0ACN_POS</a>   0</td></tr>
<tr class="memdesc:gac91a10f54ce8ca670dd985e70c792f60"><td class="mdescLeft"> </td><td class="mdescRight">UART0_DMA0ACN Position. <br /></td></tr>
<tr class="separator:gac91a10f54ce8ca670dd985e70c792f60"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga259231c9fdc4ee5742ca4790663aef98"><td class="memItemLeft" align="right" valign="top"><a id="ga259231c9fdc4ee5742ca4790663aef98"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga259231c9fdc4ee5742ca4790663aef98">MXC_F_RPU_UART0_DMA0ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_DMA0ACN_POS))</td></tr>
<tr class="memdesc:ga259231c9fdc4ee5742ca4790663aef98"><td class="mdescLeft"> </td><td class="mdescRight">UART0_DMA0ACN Mask. <br /></td></tr>
<tr class="separator:ga259231c9fdc4ee5742ca4790663aef98"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5f4898e494ac7114e1fe37b9770c49c5"><td class="memItemLeft" align="right" valign="top"><a id="ga5f4898e494ac7114e1fe37b9770c49c5"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga5f4898e494ac7114e1fe37b9770c49c5">MXC_F_RPU_UART0_DMA1ACN_POS</a>   1</td></tr>
<tr class="memdesc:ga5f4898e494ac7114e1fe37b9770c49c5"><td class="mdescLeft"> </td><td class="mdescRight">UART0_DMA1ACN Position. <br /></td></tr>
<tr class="separator:ga5f4898e494ac7114e1fe37b9770c49c5"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gac573088d6bc80992f2954adfc3c1fd06">MXC_F_RPU_UART0_DMA1ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_DMA1ACN_POS))</td></tr>
<tr class="memdesc:gac573088d6bc80992f2954adfc3c1fd06"><td class="mdescLeft"> </td><td class="mdescRight">UART0_DMA1ACN Mask. <br /></td></tr>
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<tr class="memitem:ga4ef2dab23320eb30070b8aae40e118fc"><td class="memItemLeft" align="right" valign="top"><a id="ga4ef2dab23320eb30070b8aae40e118fc"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga4ef2dab23320eb30070b8aae40e118fc">MXC_F_RPU_UART0_USBACN_POS</a>   2</td></tr>
<tr class="memdesc:ga4ef2dab23320eb30070b8aae40e118fc"><td class="mdescLeft"> </td><td class="mdescRight">UART0_USBACN Position. <br /></td></tr>
<tr class="separator:ga4ef2dab23320eb30070b8aae40e118fc"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga58606600b22c9a8af7b0c3a30f6a9270"><td class="memItemLeft" align="right" valign="top"><a id="ga58606600b22c9a8af7b0c3a30f6a9270"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga58606600b22c9a8af7b0c3a30f6a9270">MXC_F_RPU_UART0_USBACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_USBACN_POS))</td></tr>
<tr class="memdesc:ga58606600b22c9a8af7b0c3a30f6a9270"><td class="mdescLeft"> </td><td class="mdescRight">UART0_USBACN Mask. <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gabc70702897811f9fed5c7c720c39d7a1">MXC_F_RPU_UART0_SYS0ACN_POS</a>   3</td></tr>
<tr class="memdesc:gabc70702897811f9fed5c7c720c39d7a1"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SYS0ACN Position. <br /></td></tr>
<tr class="separator:gabc70702897811f9fed5c7c720c39d7a1"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga3244c065baba0c2c4f2266fede5a6394">MXC_F_RPU_UART0_SYS0ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SYS0ACN_POS))</td></tr>
<tr class="memdesc:ga3244c065baba0c2c4f2266fede5a6394"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SYS0ACN Mask. <br /></td></tr>
<tr class="separator:ga3244c065baba0c2c4f2266fede5a6394"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gae893b5d1213e1e94a24c9b56ed26a39b">MXC_F_RPU_UART0_SYS1ACN_POS</a>   4</td></tr>
<tr class="memdesc:gae893b5d1213e1e94a24c9b56ed26a39b"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SYS1ACN Position. <br /></td></tr>
<tr class="separator:gae893b5d1213e1e94a24c9b56ed26a39b"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gab2d75648fcc1b1054b59cab44adf5bff">MXC_F_RPU_UART0_SYS1ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SYS1ACN_POS))</td></tr>
<tr class="memdesc:gab2d75648fcc1b1054b59cab44adf5bff"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SYS1ACN Mask. <br /></td></tr>
<tr class="separator:gab2d75648fcc1b1054b59cab44adf5bff"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gac66a3f1fdcf74768933c415610bc1aea">MXC_F_RPU_UART0_SDMADACN_POS</a>   5</td></tr>
<tr class="memdesc:gac66a3f1fdcf74768933c415610bc1aea"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SDMADACN Position. <br /></td></tr>
<tr class="separator:gac66a3f1fdcf74768933c415610bc1aea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga58132e72fcf3d6524e2eeb6221a2e133"><td class="memItemLeft" align="right" valign="top"><a id="ga58132e72fcf3d6524e2eeb6221a2e133"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga58132e72fcf3d6524e2eeb6221a2e133">MXC_F_RPU_UART0_SDMADACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SDMADACN_POS))</td></tr>
<tr class="memdesc:ga58132e72fcf3d6524e2eeb6221a2e133"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SDMADACN Mask. <br /></td></tr>
<tr class="separator:ga58132e72fcf3d6524e2eeb6221a2e133"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gae3a485e9b25a902296acb37735b3919b">MXC_F_RPU_UART0_SDMAIACN_POS</a>   6</td></tr>
<tr class="memdesc:gae3a485e9b25a902296acb37735b3919b"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SDMAIACN Position. <br /></td></tr>
<tr class="separator:gae3a485e9b25a902296acb37735b3919b"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga96283394db993675cd0554c5f2aba21e"><td class="memItemLeft" align="right" valign="top"><a id="ga96283394db993675cd0554c5f2aba21e"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga96283394db993675cd0554c5f2aba21e">MXC_F_RPU_UART0_SDMAIACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SDMAIACN_POS))</td></tr>
<tr class="memdesc:ga96283394db993675cd0554c5f2aba21e"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SDMAIACN Mask. <br /></td></tr>
<tr class="separator:ga96283394db993675cd0554c5f2aba21e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga1d03a9fb644e7d0a4773cb7b43e05db8"><td class="memItemLeft" align="right" valign="top"><a id="ga1d03a9fb644e7d0a4773cb7b43e05db8"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga1d03a9fb644e7d0a4773cb7b43e05db8">MXC_F_RPU_UART0_CRYPTOACN_POS</a>   7</td></tr>
<tr class="memdesc:ga1d03a9fb644e7d0a4773cb7b43e05db8"><td class="mdescLeft"> </td><td class="mdescRight">UART0_CRYPTOACN Position. <br /></td></tr><tr class="separator:ga1d03a9fb644e7d0a4773cb7b43e05db8"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga420a8893e5c8e66ff47d7c42e6dc6711"><td class="memItemLeft" align="right" valign="top"><a id="ga420a8893e5c8e66ff47d7c42e6dc6711"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga420a8893e5c8e66ff47d7c42e6dc6711">MXC_F_RPU_UART0_CRYPTOACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_CRYPTOACN_POS))</td></tr>
<tr class="memdesc:ga420a8893e5c8e66ff47d7c42e6dc6711"><td class="mdescLeft"> </td><td class="mdescRight">UART0_CRYPTOACN Mask. <br /></td></tr>
<tr class="separator:ga420a8893e5c8e66ff47d7c42e6dc6711"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa343cea179696abf1cd95405567fa7d9"><td class="memItemLeft" align="right" valign="top"><a id="gaa343cea179696abf1cd95405567fa7d9"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#gaa343cea179696abf1cd95405567fa7d9">MXC_F_RPU_UART0_SDIOACN_POS</a>   8</td></tr>
<tr class="memdesc:gaa343cea179696abf1cd95405567fa7d9"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SDIOACN Position. <br /></td></tr>
<tr class="separator:gaa343cea179696abf1cd95405567fa7d9"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5a0bf04464ab4a155810e9f73cd14441"><td class="memItemLeft" align="right" valign="top"><a id="ga5a0bf04464ab4a155810e9f73cd14441"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__UART0.html#ga5a0bf04464ab4a155810e9f73cd14441">MXC_F_RPU_UART0_SDIOACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_UART0_SDIOACN_POS))</td></tr>
<tr class="memdesc:ga5a0bf04464ab4a155810e9f73cd14441"><td class="mdescLeft"> </td><td class="mdescRight">UART0_SDIOACN Mask. <br /></td></tr>
<tr class="separator:ga5a0bf04464ab4a155810e9f73cd14441"><td class="memSeparator" colspan="2"> </td></tr>
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<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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