Add a config option to indicate that a flashlight LED was soldered onto
the harmonic board.

Can be used to build docs and directly open them in the users default
web-browser:

	./Documentation/build-docs.sh --open

See merge request !481

ci: Expose artifacts for debug builds

See merge request !482

See merge request !478

See merge request !480

The loop condition in the epic_sleep based sleep could underflow if an
interrupt introduced too much delay at the end.

The clock source of epicardium is not very stable and can drift multiple
percent. This has an effect on epic_sleep() and can lead to sleeps which
are longer than anticipated. With this change we slowly move towards our
sleep goal using multiple calls. This is less efficient but leads to
precise results.

This can be used by the second core to signal that the system can go to
a light sleep to recuce power consumption.

See merge request !475

feat(personal-state): Convert personal state to use the work queue

See merge request !479

This is in perparation of epicardium being allowed to change the system
clock source. By using the alternate clock source for the systick, we
can keep accurate (tick) time on pycardium.

This reduces the power consumption of the system by around .1 mA when
the personal state is not active.

change(uart): Use low power HIRC8 for uart clock

See merge request !477

Timer frequency is now held close to a value which can be achieved both
with a 48 MHz PCLK (96 MHz system clock) and a 7.5 MHz PCLK (15 MHz
system clock).

If even lower PCLKs should be supported, the frequency of the timer has
to be changed as well.

Disable core 1 interrupts during API calls

See merge request !474

Disable all maskable interrupts on core 1 during API calls.  This brings
two main advantages:

1. It means API calls are now always ISR-safe and can be used everywhere
   in core 1 code.  This is mostly interesting to l0dables as Pycardium
   should not need to do this.

2. It allows Epicardium to halt the clock for core 1 without fear as we
   have observed problems with doing this when core 1 is currently
   executing instructions that touch memory.  Now a synchronous call
   from core 1 will guarantee that it is currently waiting in a WFE and
   no other ISRs could be potentially running.

When interrupts are disabled during API calls on core 1, we can only
trigger a core 1 reset when there is no API call ongoing.  This means
that the lifecycle machinery needs to allow any running API calls to
complete before it has a chance to see its reset interrupt delivered.

This is complicated because we cannot synchronize on core 1 triggering
an API call - the best we can do is stop the dispatcher, check whether
our reset interrupt was delivered, and if not, give it another chance to
process an API call.

Additionally, "give it another chance to process an API call" means that
the IDLE task must run, because this is currently a prerequisite to
scheduling the dispatcher (see [1]).  The only way to facilitate this is
with a sleep that is long enough that it will eventually let core 0 go
idle.  It seems that an 8 tick delay does the job quite fine.

Thus, implement a busy loop which provides the above requirements and
with that makes Epicardium prepared for payloads which perform API calls
with interrupts disabled.

[1]: https://firmware.card10.badge.events.ccc.de/epicardium/overview.html#internals

This function is useful on its own for more complex lifecycle management
in Epicardium.  Split it out of core1_wait_ready() so it can be used.

Cleanup epicardium structure

See merge request !472

As a part of this, drop os/log.h.  Also add documentation for this.