adoped for the new display

badge/Badge_Top-PCB/Badge_Top-PCB.sch

 EESchema Schematic File Version 4
-LIBS:Badge_Top-PCB-cache
-EELAYER 26 0
+EELAYER 29 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8

badge/Badge_Top-PCB/Connections.sch

 EESchema Schematic File Version 4
-LIBS:Badge_Top-PCB-cache
-EELAYER 26 0
+EELAYER 29 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8

badge/Badge_Top-PCB/Display.sch

 EESchema Schematic File Version 4
-LIBS:Badge_Top-PCB-cache
-EELAYER 26 0
+EELAYER 29 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8
@@ -82,10 +81,6 @@ F 3 "" H 6150 3650 50  0001 C CNN
 $EndComp
 Wire Wire Line
 	6750 4300 6450 4300
-Wire Wire Line
-	6750 3800 6650 3800
-Wire Wire Line
-	6450 3700 6900 3700
 Wire Wire Line
 	6900 3300 6450 3300
 Wire Wire Line
@@ -107,7 +102,6 @@ Wire Wire Line
 	6800 2650 6800 2600
 Wire Wire Line
 	6800 2600 6650 2600
-Connection ~ 6650 2600
 Wire Wire Line
 	6650 2600 6650 2550
 Wire Wire Line
@@ -149,8 +143,6 @@ Wire Wire Line
 	4800 3900 4800 3700
 Text Notes 4600 3950 1    50   ~ 0
 Place next to Display
-Wire Wire Line
-	6650 2600 6650 3800
 Text Notes 3950 5750 0    50   ~ 0
 display: KD0096FM-1\nSource: http://www.startek-lcd.com/res/starteklcd/pdres/201902/20190223094535700.pdf
 $Comp
@@ -187,7 +179,6 @@ Wire Wire Line
 	7950 4650 7850 4650
 Wire Wire Line
 	6750 4500 6750 4300
-Connection ~ 6750 4300
 $Comp
 L Transistor_FET:2N7002 T1
 U 1 1 5D0832A3
@@ -199,8 +190,6 @@ F 3 "https://www.fairchildsemi.com/datasheets/2N/2N7002.pdf" H 7950 4450 50  000
 	1    7950 4450
 	-1   0    0    -1  
 $EndComp
-Wire Wire Line
-	6750 3800 6750 4300
 Wire Wire Line
 	6450 4200 6650 4200
 Wire Wire Line
@@ -234,43 +223,8 @@ Wire Wire Line
 Wire Wire Line
 	8300 4450 8450 4450
 Connection ~ 8300 4450
-$Comp
-L Device:R R24
-U 1 1 5D16F233
-P 7050 3200
-F 0 "R24" V 7130 3200 50  0000 C CNN
-F 1 "0" V 7050 3200 50  0000 C CNN
-F 2 "Resistor_SMD:R_0201_0603Metric" V 6980 3200 50  0001 C CNN
-F 3 "~" H 7050 3200 50  0001 C CNN
-	1    7050 3200
-	0    -1   -1   0   
-$EndComp
-Connection ~ 6650 3800
-Wire Wire Line
-	6650 3800 6450 3800
 Wire Wire Line
 	6800 2950 6800 3600
-$Comp
-L Device:R R23
-U 1 1 5D1701A6
-P 7050 3100
-F 0 "R23" V 7130 3100 50  0000 C CNN
-F 1 "0" V 7050 3100 50  0000 C CNN
-F 2 "Resistor_SMD:R_0201_0603Metric" V 6980 3100 50  0001 C CNN
-F 3 "~" H 7050 3100 50  0001 C CNN
-	1    7050 3100
-	0    -1   -1   0   
-$EndComp
-Wire Wire Line
-	6450 3100 6900 3100
-Wire Wire Line
-	6900 3200 6450 3200
-Wire Wire Line
-	7200 3200 7300 3200
-Wire Wire Line
-	7300 3200 7300 3100
-Wire Wire Line
-	7300 3100 7200 3100
 Text GLabel 7950 2750 2    50   Input ~ 0
 GPIO2
 $Comp
@@ -288,7 +242,6 @@ Wire Wire Line
 	7850 2750 7950 2750
 Text GLabel 7400 2550 2    50   Input ~ 0
 PMIC_GPIO
-Connection ~ 7300 3100
 Wire Wire Line
 	7400 2550 7300 2550
 Wire Wire Line
@@ -298,4 +251,17 @@ Wire Wire Line
 Connection ~ 7300 2750
 Wire Wire Line
 	7300 2750 7300 3100
+Wire Wire Line
+	6450 3100 7300 3100
+Wire Wire Line
+	6650 2600 6650 4000
+Connection ~ 6650 2600
+Connection ~ 6650 4000
+Wire Wire Line
+	6450 3800 6750 3800
+Wire Wire Line
+	6750 3800 6750 4300
+Connection ~ 6750 4300
+Wire Wire Line
+	6900 3700 6450 3700
 $EndSCHEMATC

badge/Badge_Top-PCB/EKG.sch

 EESchema Schematic File Version 4
-LIBS:Badge_Top-PCB-cache
-EELAYER 26 0
+EELAYER 29 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8

badge/Badge_Top-PCB/LED.sch

 EESchema Schematic File Version 4
-LIBS:Badge_Top-PCB-cache
-EELAYER 26 0
+EELAYER 29 0
 EELAYER END
 $Descr A4 11693 8268
 encoding utf-8