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Damien George authoredOn MCUs other than F4 the ORE (overrun error) flag needs to be cleared independently of clearing RXNE, even though both are wired to trigger the same RXNE IRQ. In the case that an overrun occurred it's necessary to explicitly clear the ORE flag or else the RXNE interrupt will keep firing.
Damien George authoredOn MCUs other than F4 the ORE (overrun error) flag needs to be cleared independently of clearing RXNE, even though both are wired to trigger the same RXNE IRQ. In the case that an overrun occurred it's necessary to explicitly clear the ORE flag or else the RXNE interrupt will keep firing.
.gdbinit 81 B
target remote localhost:3333
define reset
mon mww 0x40000004 0x80000000
end