stmhal: Add lots of constants to stm module.

stmhal/make-stmconst.py

+"""
+Read in the cmsis/devinc/stm32f405xx.h header, extract relevant constants,
+and create modstmconst.c.
+
+This is not part of the automatic build process because stm32f405xx.h isn't
+expected to change.  After generating the file, some manual intervention is
+needed to copy the new qstr definitions to qstrdefsport.h.
+"""
+
+import argparse
+import re
+
+# given a list of (name,regex) pairs, find the first one that matches the given line
+def re_match_first(regexs, line):
+    for name, regex in regexs:
+        match = re.match(regex, line)
+        if match:
+            return name, match
+    return None, None
+
+class LexerError(Exception):
+    def __init__(self, line):
+        self.line = line
+
+class Lexer:
+    re_io_reg = r'__IO uint(?P<bits>8|16|32)_t +(?P<reg>[A-Z0-9]+)'
+    re_comment = r'(?P<comment>[A-Za-z0-9 \-/_()]+)'
+    re_addr_offset = r'Address offset: (?P<offset>0x[0-9A-Z]{2,3})'
+    regexs = (
+        ('#define hex', re.compile(r'#define +(?P<id>[A-Z0-9_]+) +\(\(uint32_t\)(?P<hex>0x[0-9A-F]+)\)($| +/\*)')),
+        ('#define X', re.compile(r'#define +(?P<id>[A-Z0-9_]+) +(?P<id2>[A-Z0-9_]+)($| +/\*)')),
+        ('#define X+hex', re.compile(r'#define +(?P<id>[A-Z0-9_]+) +\((?P<id2>[A-Z0-9_]+) \+ (?P<hex>0x[0-9A-F]+)\)($| +/\*)')),
+        ('#define typedef', re.compile(r'#define +(?P<id>[A-Z0-9_]+) +\(\([A-Za-z0-9_]+_TypeDef \*\) (?P<id2>[A-Z0-9_]+)\)($| +/\*)')),
+        ('typedef struct', re.compile(r'typedef struct$')),
+        ('{', re.compile(r'{$')),
+        ('}', re.compile(r'}$')),
+        ('} TypeDef', re.compile(r'} *(?P<id>[A-Z][A-Za-z0-9_]+)_(?P<global>(Global)?)TypeDef;$')),
+        ('IO reg', re.compile(re_io_reg + r'; +/\*!< ' + re_comment + r', +' + re_addr_offset + r' *\*/')),
+        ('IO reg array', re.compile(re_io_reg + r'\[(?P<array>[2-8])\]; +/\*!< ' + re_comment + r', +' + re_addr_offset + r'-(0x[0-9A-Z]{2,3}) *\*/')),
+    )
+
+    def __init__(self, filename):
+        self.file = open(filename, 'rt')
+        self.line_number = 0
+
+    def next_match(self, strictly_next=False):
+        while True:
+            line = self.file.readline()
+            self.line_number += 1
+            if len(line) == 0:
+                return ('EOF', None)
+            match = re_match_first(Lexer.regexs, line.strip())
+            if strictly_next or match[0] is not None:
+                return match
+
+    def must_match(self, kind):
+        match = self.next_match(strictly_next=True)
+        if match[0] != kind:
+            raise LexerError(self.line_number)
+        return match
+
+def parse_file(filename):
+    lexer = Lexer(filename)
+
+    reg_defs = {}
+    consts = {}
+    periphs = []
+    while True:
+        m = lexer.next_match()
+        if m[0] == 'EOF':
+            break
+        elif m[0] == '#define hex':
+            d = m[1].groupdict()
+            consts[d['id']] = int(d['hex'], base=16)
+        elif m[0] == '#define X':
+            d = m[1].groupdict()
+            if d['id2'] in consts:
+                consts[d['id']] = consts[d['id2']]
+        elif m[0] == '#define X+hex':
+            d = m[1].groupdict()
+            if d['id2'] in consts:
+                consts[d['id']] = consts[d['id2']] + int(d['hex'], base=16)
+        elif m[0] == '#define typedef':
+            d = m[1].groupdict()
+            if d['id2'] in consts:
+                periphs.append((d['id'], consts[d['id2']]))
+        elif m[0] == 'typedef struct':
+            lexer.must_match('{')
+            m = lexer.next_match()
+            regs = []
+            while m[0] in ('IO reg', 'IO reg array'):
+                d = m[1].groupdict()
+                reg = d['reg']
+                offset = int(d['offset'], base=16)
+                bits = int(d['bits'])
+                comment = d['comment']
+                if m[0] == 'IO reg':
+                    regs.append((reg, offset, bits, comment))
+                else:
+                    for i in range(int(d['array'])):
+                        regs.append((reg + str(i), offset + i * bits // 8, bits, comment))
+                m = lexer.next_match()
+            if m[0] == '}':
+                pass
+            elif m[0] == '} TypeDef':
+                reg_defs[m[1].groupdict()['id']] = regs
+            else:
+                raise LexerError(lexer.line_number)
+
+    return periphs, reg_defs
+
+def print_periph(periph_name, periph_val, needed_qstrs):
+    qstr = periph_name.upper()
+    print('{ MP_OBJ_NEW_QSTR(MP_QSTR_%s), MP_OBJ_NEW_SMALL_INT(%#x) },' % (qstr, periph_val))
+    needed_qstrs.add(qstr)
+
+def print_regs(reg_name, reg_defs, needed_qstrs):
+    reg_name = reg_name.upper()
+    for r in reg_defs:
+        qstr = reg_name + '_' + r[0]
+        print('{ MP_OBJ_NEW_QSTR(MP_QSTR_%s), MP_OBJ_NEW_SMALL_INT(%#x) }, // %s-bits, %s' % (qstr, r[1], r[2], r[3]))
+        needed_qstrs.add(qstr)
+
+# This version of print regs groups registers together into submodules (eg GPIO submodule).
+# This makes the qstrs shorter, and makes the list of constants more manageable (since
+# they are not all in one big module) but it is then harder to compile the constants, and
+# is more cumbersome to access.
+# As such, we don't use this version.
+# And for the number of constants we have, this function seems to use about the same amount
+# of ROM as print_regs.
+def print_regs_as_submodules(reg_name, reg_defs, modules, needed_qstrs):
+    mod_name_lower = reg_name.lower() + '_'
+    mod_name_upper = mod_name_lower.upper()
+    modules.append((mod_name_lower, mod_name_upper))
+
+    print("""
+STATIC const mp_map_elem_t stm_%s_globals_table[] = {
+    { MP_OBJ_NEW_QSTR(MP_QSTR___name__), MP_OBJ_NEW_QSTR(MP_QSTR_%s) },
+""" % (mod_name_lower, mod_name_upper))
+    needed_qstrs.add(mod_name_upper)
+
+    for r in reg_defs:
+        print('    { MP_OBJ_NEW_QSTR(MP_QSTR_%s), MP_OBJ_NEW_SMALL_INT(%#x) }, // %s-bits, %s' % (r[0], r[1], r[2], r[3]))
+        needed_qstrs.add(r[0])
+
+    print("""};
+
+STATIC const mp_obj_dict_t stm_%s_globals = {
+    .base = {&mp_type_dict},
+    .map = {
+        .all_keys_are_qstrs = 1,
+        .table_is_fixed_array = 1,
+        .used = sizeof(stm_%s_globals_table) / sizeof(mp_map_elem_t),
+        .alloc = sizeof(stm_%s_globals_table) / sizeof(mp_map_elem_t),
+        .table = (mp_map_elem_t*)stm_%s_globals_table,
+    },
+};
+
+const mp_obj_module_t stm_%s_obj = {
+    .base = { &mp_type_module },
+    .name = MP_QSTR_%s,
+    .globals = (mp_obj_dict_t*)&stm_%s_globals,
+};
+""" % (mod_name_lower, mod_name_lower, mod_name_lower, mod_name_lower, mod_name_lower, mod_name_upper, mod_name_lower))
+
+def main():
+    cmd_parser = argparse.ArgumentParser(description='Extract ST constants from a C header file.')
+    cmd_parser.add_argument('file', nargs=1, help='input file')
+    args = cmd_parser.parse_args()
+
+    periphs, reg_defs = parse_file(args.file[0])
+
+    modules = []
+    needed_qstrs = set()
+
+    print("// Automatically generated from %s by make-stmconst.py" % args.file[0])
+    print("")
+
+    for periph_name, periph_val in periphs:
+        print_periph(periph_name, periph_val, needed_qstrs)
+
+    for reg in (
+        'ADC',
+        #'ADC_Common',
+        #'CAN_TxMailBox',
+        #'CAN_FIFOMailBox',
+        #'CAN_FilterRegister',
+        #'CAN',
+        'CRC',
+        'DAC',
+        'DBGMCU',
+        'DMA_Stream',
+        'DMA',
+        'EXTI',
+        'FLASH',
+        'GPIO',
+        'SYSCFG',
+        'I2C',
+        'IWDG',
+        'PWR',
+        'RCC',
+        'RTC',
+        #'SDIO',
+        'SPI',
+        'TIM',
+        'USART',
+        'WWDG',
+        'RNG',
+        ):
+        print_regs(reg, reg_defs[reg], needed_qstrs)
+        #print_regs_as_submodules(reg, reg_defs[reg], modules, needed_qstrs)
+
+    #print("#define MOD_STM_CONST_MODULES \\")
+    #for mod_lower, mod_upper in modules:
+    #    print("    { MP_OBJ_NEW_QSTR(MP_QSTR_%s), (mp_obj_t)&stm_%s_obj }, \\" % (mod_upper, mod_lower))
+
+    print("")
+
+    for qstr in sorted(needed_qstrs):
+        print('Q({})'.format(qstr))
+
+if __name__ == "__main__":
+    main()

stmhal/modstm.c

@@ -97,13 +97,7 @@ STATIC const mp_map_elem_t stm_module_globals_table[] = {
     { MP_OBJ_NEW_QSTR(MP_QSTR_mem16), (mp_obj_t)&stm_mem16_obj },
     { MP_OBJ_NEW_QSTR(MP_QSTR_mem32), (mp_obj_t)&stm_mem32_obj },
 
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIOA), MP_OBJ_NEW_SMALL_INT(GPIOA_BASE) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIOB), MP_OBJ_NEW_SMALL_INT(GPIOB_BASE) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIOC), MP_OBJ_NEW_SMALL_INT(GPIOC_BASE) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIOD), MP_OBJ_NEW_SMALL_INT(GPIOD_BASE) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_IDR), MP_OBJ_NEW_SMALL_INT(0x10) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_BSRRL), MP_OBJ_NEW_SMALL_INT(0x18) },
-    { MP_OBJ_NEW_QSTR(MP_QSTR_GPIO_BSRRH), MP_OBJ_NEW_SMALL_INT(0x1a) },
+#include "modstmconst.gen.c"
 };
 
 STATIC const mp_obj_dict_t stm_module_globals = {

stmhal/qstrdefsport.h

@@ -155,10 +155,254 @@ Q(mem)
 Q(mem8)
 Q(mem16)
 Q(mem32)
+
+// for stm constants
+Q(ADC)
+Q(ADC1)
+Q(ADC2)
+Q(ADC3)
+Q(ADC_CR1)
+Q(ADC_CR2)
+Q(ADC_DR)
+Q(ADC_HTR)
+Q(ADC_JDR1)
+Q(ADC_JDR2)
+Q(ADC_JDR3)
+Q(ADC_JDR4)
+Q(ADC_JOFR1)
+Q(ADC_JOFR2)
+Q(ADC_JOFR3)
+Q(ADC_JOFR4)
+Q(ADC_JSQR)
+Q(ADC_LTR)
+Q(ADC_SMPR1)
+Q(ADC_SMPR2)
+Q(ADC_SQR1)
+Q(ADC_SQR2)
+Q(ADC_SQR3)
+Q(ADC_SR)
+Q(CAN1)
+Q(CAN2)
+Q(CRC)
+Q(CRC_CR)
+Q(CRC_DR)
+Q(CRC_IDR)
+Q(DAC)
+Q(DAC_CR)
+Q(DAC_DHR12L1)
+Q(DAC_DHR12L2)
+Q(DAC_DHR12LD)
+Q(DAC_DHR12R1)
+Q(DAC_DHR12R2)
+Q(DAC_DHR12RD)
+Q(DAC_DHR8R1)
+Q(DAC_DHR8R2)
+Q(DAC_DHR8RD)
+Q(DAC_DOR1)
+Q(DAC_DOR2)
+Q(DAC_SR)
+Q(DAC_SWTRIGR)
+Q(DBGMCU_APB1FZ)
+Q(DBGMCU_APB2FZ)
+Q(DBGMCU_CR)
+Q(DBGMCU_IDCODE)
+Q(DMA1)
+Q(DMA2)
+Q(DMA_HIFCR)
+Q(DMA_HISR)
+Q(DMA_LIFCR)
+Q(DMA_LISR)
+Q(EXTI)
+Q(EXTI_EMR)
+Q(EXTI_FTSR)
+Q(EXTI_IMR)
+Q(EXTI_PR)
+Q(EXTI_RTSR)
+Q(EXTI_SWIER)
+Q(FLASH)
+Q(FLASH_ACR)
+Q(FLASH_CR)
+Q(FLASH_KEYR)
+Q(FLASH_OPTCR)
+Q(FLASH_OPTCR1)
+Q(FLASH_OPTKEYR)
+Q(FLASH_SR)
 Q(GPIOA)
 Q(GPIOB)
 Q(GPIOC)
 Q(GPIOD)
-Q(GPIO_IDR)
-Q(GPIO_BSRRL)
+Q(GPIOE)
+Q(GPIOF)
+Q(GPIOG)
+Q(GPIOH)
+Q(GPIOI)
+Q(GPIO_AFR0)
+Q(GPIO_AFR1)
 Q(GPIO_BSRRH)
+Q(GPIO_BSRRL)
+Q(GPIO_IDR)
+Q(GPIO_LCKR)
+Q(GPIO_MODER)
+Q(GPIO_ODR)
+Q(GPIO_OSPEEDR)
+Q(GPIO_OTYPER)
+Q(GPIO_PUPDR)
+Q(I2C1)
+Q(I2C2)
+Q(I2C3)
+Q(I2C_CCR)
+Q(I2C_CR1)
+Q(I2C_CR2)
+Q(I2C_DR)
+Q(I2C_FLTR)
+Q(I2C_OAR1)
+Q(I2C_OAR2)
+Q(I2C_SR1)
+Q(I2C_SR2)
+Q(I2C_TRISE)
+Q(IWDG)
+Q(IWDG_KR)
+Q(IWDG_PR)
+Q(IWDG_RLR)
+Q(IWDG_SR)
+Q(PWR)
+Q(PWR_CR)
+Q(PWR_CSR)
+Q(RCC)
+Q(RCC_AHB1ENR)
+Q(RCC_AHB1LPENR)
+Q(RCC_AHB1RSTR)
+Q(RCC_AHB2ENR)
+Q(RCC_AHB2LPENR)
+Q(RCC_AHB2RSTR)
+Q(RCC_AHB3ENR)
+Q(RCC_AHB3LPENR)
+Q(RCC_AHB3RSTR)
+Q(RCC_APB1ENR)
+Q(RCC_APB1LPENR)
+Q(RCC_APB1RSTR)
+Q(RCC_APB2ENR)
+Q(RCC_APB2LPENR)
+Q(RCC_APB2RSTR)
+Q(RCC_BDCR)
+Q(RCC_CFGR)
+Q(RCC_CIR)
+Q(RCC_CR)
+Q(RCC_PLLCFGR)
+Q(RCC_PLLI2SCFGR)
+Q(RCC_SSCGR)
+Q(RNG)
+Q(RNG_CR)
+Q(RNG_DR)
+Q(RNG_SR)
+Q(RTC)
+Q(RTC_ALRMAR)
+Q(RTC_ALRMBR)
+Q(RTC_BKP0R)
+Q(RTC_BKP10R)
+Q(RTC_BKP11R)
+Q(RTC_BKP12R)
+Q(RTC_BKP13R)
+Q(RTC_BKP14R)
+Q(RTC_BKP15R)
+Q(RTC_BKP16R)
+Q(RTC_BKP17R)
+Q(RTC_BKP18R)
+Q(RTC_BKP19R)
+Q(RTC_BKP1R)
+Q(RTC_BKP2R)
+Q(RTC_BKP3R)
+Q(RTC_BKP4R)
+Q(RTC_BKP5R)
+Q(RTC_BKP6R)
+Q(RTC_BKP7R)
+Q(RTC_BKP8R)
+Q(RTC_BKP9R)
+Q(RTC_CALIBR)
+Q(RTC_CALR)
+Q(RTC_CR)
+Q(RTC_DR)
+Q(RTC_ISR)
+Q(RTC_PRER)
+Q(RTC_SHIFTR)
+Q(RTC_SSR)
+Q(RTC_TAFCR)
+Q(RTC_TR)
+Q(RTC_TSDR)
+Q(RTC_TSSSR)
+Q(RTC_TSTR)
+Q(RTC_WPR)
+Q(RTC_WUTR)
+Q(SDIO)
+Q(SPI1)
+Q(SPI2)
+Q(SPI3)
+Q(SPI_CR1)
+Q(SPI_CR2)
+Q(SPI_CRCPR)
+Q(SPI_DR)
+Q(SPI_I2SCFGR)
+Q(SPI_I2SPR)
+Q(SPI_RXCRCR)
+Q(SPI_SR)
+Q(SPI_TXCRCR)
+Q(SYSCFG)
+Q(SYSCFG_CMPCR)
+Q(SYSCFG_EXTICR0)
+Q(SYSCFG_EXTICR1)
+Q(SYSCFG_EXTICR2)
+Q(SYSCFG_EXTICR3)
+Q(SYSCFG_MEMRMP)
+Q(SYSCFG_PMC)
+Q(TIM1)
+Q(TIM10)
+Q(TIM11)
+Q(TIM12)
+Q(TIM13)
+Q(TIM14)
+Q(TIM2)
+Q(TIM3)
+Q(TIM4)
+Q(TIM5)
+Q(TIM6)
+Q(TIM7)
+Q(TIM8)
+Q(TIM9)
+Q(TIM_ARR)
+Q(TIM_BDTR)
+Q(TIM_CCER)
+Q(TIM_CCMR1)
+Q(TIM_CCMR2)
+Q(TIM_CCR1)
+Q(TIM_CCR2)
+Q(TIM_CCR3)
+Q(TIM_CCR4)
+Q(TIM_CNT)
+Q(TIM_CR1)
+Q(TIM_CR2)
+Q(TIM_DCR)
+Q(TIM_DIER)
+Q(TIM_DMAR)
+Q(TIM_EGR)
+Q(TIM_OR)
+Q(TIM_PSC)
+Q(TIM_RCR)
+Q(TIM_SMCR)
+Q(TIM_SR)
+Q(UART4)
+Q(UART5)
+Q(USART1)
+Q(USART2)
+Q(USART3)
+Q(USART6)
+Q(USART_BRR)
+Q(USART_CR1)
+Q(USART_CR2)
+Q(USART_CR3)
+Q(USART_DR)
+Q(USART_GTPR)
+Q(USART_SR)
+Q(WWDG)
+Q(WWDG_CFR)
+Q(WWDG_CR)
+Q(WWDG_SR)