Pieter Conradie <Pieter.Conradie@psitek.com> Scripts for Atmel AT91SAM7S256 and AT91SAM9260

git-svn-id: svn://svn.berlios.de/openocd/trunk@2602 b42882b7-edfa-0310-969c-e2dbd0fdcd60

tcl/board/at91sam7sx.cfg

+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam7s
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-init { 
+        soft_reset_halt
+        # RSTC_CR : Reset peripherals
+        mww 0xfffffd00 0xa5000004
+        # disable watchdog
+	mww 0xfffffd44 0x00008000	
+	# enable user reset
+	mww 0xfffffd08 0xa5000001	
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601	
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e 	
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007	
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=73)
+	mww 0xffffff60 0x00490100	
+	sleep 100        
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+
+# For more information about the configuration files, take a look at:
+# openocd.texi

tcl/board/at91sam9260.cfg

+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 300
+jtag_ntrst_delay 10
+
+jtag_rclk 3
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+
+

tcl/board/atmel_at91sam7s-ek.cfg

+# Atmel AT91SAM7S-EK
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
+
+set CHIPNAME at91sam7s256
+
+source [find target/at91sam7sx.cfg]
+
+

tcl/board/atmel_at91sam9260-ek.cfg

+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+	
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
+        
+        mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
+}

tcl/board/unknown_at91sam9260.cfg

+# Thanks to Pieter Conradie for this script! 
+#
+# Unknown vendor board contains:
+#
+# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
+#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
+#
+# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
+# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
+##################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 22 to 42 kHz.
+        # JTAG Frequency must be 6 times slower.
+        jtag_rclk 3                        
+        halt
+	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+	
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x205dbf09         # CKGR_PLLAR: Set PLLA Register for 192.512MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000                    
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x09070806         # SMC_PULSE0
+	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
+	mww 0xffffec0c 0x00001003         # SMC_MODE0
+
+	flash probe 0                     # Identify flash bank 0
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
+        mww 0xfffff860 0xffff0000         # PIO_PUDR : Disable D15..D31 pull-ups
+        
+        mww 0xffffef1c 0x00010102         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
+                                          #            VDDIOMSEL set for +3V3 memory
+                                          #            Disable D0..D15 pull-ups
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2a2              # SDRAMC_TR : Set refresh timer count to 7us
+}
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x10000000 0x01000000 2 2 0
+
+