Duane Ellis <openocd@duaneellis.com> stm32 peripherals scripts

git-svn-id: svn://svn.berlios.de/openocd/trunk@846 b42882b7-edfa-0310-969c-e2dbd0fdcd60

src/Makefile.am

@@ -93,6 +93,7 @@ nobase_dist_pkglib_DATA = \
 	tcl/cpu/arm/arm920.tcl			\
 	tcl/cpu/arm/arm946.tcl			\
 	tcl/cpu/arm/arm966.tcl			\
+	tcl/cpu/arm/cortex_m3.tcl               \
 	tcl/memory.tcl				\
 	tcl/mmr_helpers.tcl			\
 	tcl/readable.tcl

src/tcl/chip/st/stm32/stm32_rcc.tcl

@@ -42,7 +42,7 @@ proc show_RCC_CFGR { } {
     show_mmr_bitfield 15 14 $val  ADCPRE { pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div1 pclk2_div2 pclk2_div4 pclk2_div8 pclk2_div16 }
     show_mmr_bitfield 16 16 $val  PLLSRC { HSI_div_2 HSE }
     show_mmr_bitfield 17 17 $val  PLLXTPRE { hse_div1 hse_div2 }
-    show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
+    show_mmr_bitfield 21 18 $val  PLLMUL { x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 x16 }
     show_mmr_bitfield 22 22 $val  USBPRE { div1 div1_5 }
     show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }
 }

src/tcl/cpu/arm/cortex_m3.tcl

+set CPU_TYPE   arm
+set CPU_NAME   cortex_m3
+set CPU_ARCH   armv7
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+set CPU_NBITS  32
+