Skip to content
Snippets Groups Projects
Select Git revision
  • dw-cmsisdap-path
  • max32xxx default protected
2 results
Search by author
  • Any Author
  • 9R 9R
  • Administrator root
  • Andreas Schildbach pink
  • Daniel Hoffend griffon
  • Definitely Not A Robot Doloo1ai
  • Dirk Jäckel Dirk Jäckel biafra
  • G G
  • Hauke Mehrtens hauke
  • Jan Morawek RFguy
  • Julian hdsjulian
  • Lila Fisch lilafisch
  • Martin Ling martinling
  • Mateusz Zalega msgctl
  • Michael Huebler mh
  • Ole Dreessen ole
  • Phileas Phileas pl
  • Philip Brechler Philip Brechler plaetzchen
  • Renze renze
  • Sabine Wolf Bine
  • Sec 42 sec
20 authors
  1. Aug 13, 2009
  3. Aug 07, 2009
  5. Aug 06, 2009
  7. Jul 27, 2009
  9. Jul 26, 2009
  11. Jul 24, 2009
  13. Jul 23, 2009
  15. Jul 21, 2009
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · d460a7cd
      ntfreak authored 
      Dump SP on poll, and show whether it's MSP or PSP.

Thread mode can use either stack pointer, so this is
part of the state that's not yet displayed.

Shrink some lines.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      d460a7cd
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · 4da019ed
      ntfreak authored 
      Clean up treatment of registers in ARMv7-M and Cortex-M3. 

 - At the arch level:
    * Just list registers and names; don't impose core-specific
      policy about how they are accessed.
    * Each register has a symbol.
    * Remove the register mode field (irrelevant to debugger)

 - At the core/implementation level:
    * Just map the registers to their relevant access methods;
      don't require the arch level to say how that should work
      (cores other than Cortex-M3 could do it differently).
    * Don't use undefined bits from register 20.
    * Use register IDs that are part of the ARMv7-M interface.

In short, there's now a real distinction between the arch
and core layers.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      4da019ed
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · eea04862
      ntfreak authored 
      Minor updates to the Thumb2 disassembly:

 - Bugfixes:
    * Distinguish branch from misc via "!=" not "=="
    * MRS register shift is 8 bits (vs MSR being 16)
 - Format tweaks:
    * CPS needed tab (not space)
    * add commma before some shifts
    * add space after comma in LDM/STM
    * use ".W" width spec on various instructions

git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      eea04862
    • ntfreak's avatar
      David Brownell <david-b@pacbell.net>: · cd0ca916
      ntfreak authored 
      Revert parts of the previous ARMv7-M register patch.
It turns out that part of the issue is a documentation
problem for the Cortex-M3 r1 parts. So for the rest,
simpler fixes are possible (in followup patch).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      cd0ca916
  17. Jul 20, 2009
  19. Jul 17, 2009
  21. Jul 16, 2009
    • oharboe's avatar
      microscopic whitespace cleanup · bd437719
      oharboe authored 
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2547 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      bd437719
    • oharboe's avatar
      microscopic white space fixes · 4deb8530
      oharboe authored 
      git-svn-id: svn://svn.berlios.de/openocd/trunk@2546 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      4deb8530
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 1af6b72f
      zwelch authored 
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:

Move the dap command handler implementations to arm_adi_v5.c,
leaving just thin wrappers in armv7m.c.  There should be no
change in functionality here.  (From Magnus.)

Minor style cleanup:  whitespace, line length, etc.  Update spec
references to use docs which are currently available.  (From Dave.)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2544 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      1af6b72f
    • zwelch's avatar
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>,... · 16e17ab1
      zwelch authored 
      Magnus Lundin <lundin@mlu.mine.nu>, Oyvind Harboe <oyvind.harboe@zylin.com>, David Brownell <david-b@pacbell.net>:

Some cleanup of the ARMv7-M support:

 - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and
   update the Cortex-M3 doc refs (DDI 0337C is no longer available).

 - Those registers aren't actually general, and some are incorrect (per all
   public docs anyway).  Update comments and code accordingly.

     * What the Core Debug facility exposes is *implementation-specific*
       not architectural.  These values aren't fully portable.  They match
       Cortex-M3 ... so no current implementation will make trouble, but
       the next v7m implementation might.

     * Four of the registers are actually not exposed that way.  Before
       Cortex-M3 r2p0 they are read/written through MRS/MSR instructions.
       In that newest silicon, they are four bytes in one register, not
       four separate registers.

 - Update the CM3 code to report when that one register is available,
   and not try to access it when it isn't.  Also declare the register
   numbers that an eventual MRS/MSR solution will need to be using.

 - Stop line wrapping the exception labels.

So for parts before r2p0 OpenOCD behavior is effectively unchanged, and
still buggy; but for those newer parts a few things might now be correct.

Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include
most LM3S parts and all STM32 parts.  Parts using r2p0 are available, and
include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx
parts which are now sampling.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2543 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      16e17ab1
  23. Jul 15, 2009