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20 authors
  1. Sep 30, 2009
  3. Sep 29, 2009
  5. Sep 28, 2009
  7. Sep 26, 2009
    • dbrownell's avatar
      Streamline Capture-IR handling and integrity test. · 2e210ee4
      dbrownell authored 
      Change the handling of the "-ircapture" and "-irmask" parameters
to be slightly more sensible, given that the JTAG spec describes
what is required, and that we already require that conformance in
one place.  IR scan returns some bitstring with LSBs "01".

 - First, provide and use default values that satisfy the IEEE spec.
   Existing TAP configs will override the defaults, but those parms
   are no longer required.

 - Second, warn if any TAP gets set up to violate the JTAG spec.
   It's likely a bug, but maybe not; else this should be an error.
   Improve the related diagnostics to say which TAP is affected.

And associated minor fixes/cleanups to comments and diagnostics.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2758 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      2e210ee4
  9. Sep 23, 2009
    • dbrownell's avatar
      When setting up an ETM, cache its ETM_CONFIG register. Then · 22045fa6
      dbrownell authored 
      only expose the registers which are actually present.  They
could be missing for two basic reasons:

 - This version might not support them at all; e.g. ETMv1.1
   doesn't have some control/status registers.  (My sample of
   ARM9 boards shows all with ETMv1.3 support, FWIW.)

 - The configuration on this chip may not populate as many
   registers as possible; e.g. only two data value comparators
   instead of eight.

Includes a bugfix in the "etm info" command:  only one of the
two registers is missing on older silicon, so show the first
one before bailing.

Update ETM usage docs to explain that those registers need to be
written to configure what is traced, and that some ETM configs
are not yet handled.  Also, give some examples of the kinds of
constrained trace which could be arranged.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2752 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      22045fa6
  11. Sep 22, 2009
  13. Sep 21, 2009
  15. Sep 20, 2009
  17. Sep 19, 2009
  19. Sep 17, 2009
    • dbrownell's avatar
      Minor fixes to NAND code and docs · 9536577c
      dbrownell authored 
      Erase logic:
 - command invocation
    + treat "nand erase N" (no offset/length) as "erase whole chip N"
    + catch a few more bogus parameter cases, like length == 0 (sigh)
 - nand_erase() should be static
 - on error
    + say which block failed, and if it was a bad block
    + don't give up after the first error; try to erase the rest
 - on success, say which nand device was erased (name isn't unique)

Device list ("nand list"):
 - say how many blocks there are
 - split summary into two lines
 - give example in the docs

Doc tweaks:
 - Use @option{...} for DaVinci's supported hardware ECC options

For the record, I've observed that _sometimes_ erasing bad blocks causes
failure reports, and that manufacturer bad block markers aren't always
erasable (even when erasing their blocks doesn't trigger an error report).


git-svn-id: svn://svn.berlios.de/openocd/trunk@2724 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      9536577c
    • oharboe's avatar
      srst_gates_jtag option. at91sam9260 needs retesting, and possibly... · 016e7ebb
      oharboe authored 
      srst_gates_jtag option. at91sam9260 needs retesting, and possibly srst_gates_jtag added to reset_config. Could i.MX27 be a case where srst does not pull trst, but really srst gates jtag clock?

git-svn-id: svn://svn.berlios.de/openocd/trunk@2720 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      016e7ebb
    • dbrownell's avatar
      The "arm9tdmi.c" file is more of a generic ARM9 support file: · cb7ad25c
      dbrownell authored 
       - update comments to say so.
 - update docs to clarify that the "arm9tdmi" command prefix
   is a misnomer.
 - bugfix some messages that wrongly assume only ARM9TDMI
   based processors use this code.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2719 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      cb7ad25c
    • dbrownell's avatar
      Doc update: mention how ARM's WFI instruction affects · e18bd3b5
      dbrownell authored 
      JTAG clocking by gating the core clock, and workarounds.
Most details are with the "halt" command, which is one
of the first places this issue will be noticed.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2718 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      e18bd3b5
  21. Sep 16, 2009
  23. Sep 12, 2009
  25. Sep 09, 2009
    • oharboe's avatar
      David Brownell <david-b@pacbell.net> · 8b2b0071
      oharboe authored 
      Fix docs on ARM11 MCR and MRC coprocessor commands:
correct read-vs-write; and describe the params.

(ARM920 and ARM926 have cp15-specific commands; this
approach is more generic.  MCR2, MRC2, MCRR, MCRR2,
MRRC, and MRRC2 instructions could also get exposed.)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2679 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      8b2b0071
  27. Sep 08, 2009
  29. Aug 30, 2009
  31. Aug 25, 2009
  33. Aug 18, 2009
  35. Aug 13, 2009
  37. Aug 07, 2009
  39. Jul 17, 2009
  41. Jul 15, 2009
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 309870e4
      zwelch authored 
      Initial support for disassembling Thumb2 code.  This works only for
Cortex-M3 cores so far.  Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.

 - Update the 16-bit Thumb decoder:
 
     * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
       by ARMv6.  (It already seems to treat CPY as MOV.)

     * Understand CB, CBNZ, WFI, IT, and other opcodes added by
       in Thumb2.

 - A new Thumb2 instruction decode routine is provided.
 
     * This has a different signature:  pass the target, not the
       instruction, so it can fetch a second halfword when needed.  
       The instruction size is likewise returned to the caller.

     * 32-bit instructions are recognized but not yet decoded.
   
 - Start using the current "UAL" syntax in some cases.  "SWI" is
   renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".

 - Define a new "cortex_m3 disassemble addr count" command to give
   access to this disassembly.

Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2530 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      309870e4
  43. Jul 14, 2009
  45. Jul 12, 2009
  47. Jul 08, 2009
  49. Jul 06, 2009