Florian Boor <florian.boor@kernelconcepts.de> fixes a segfault executing commands from the web interface using the
"Run Command" tab.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2601 b42882b7-edfa-0310-969c-e2dbd0fdcd60

SVF file, making OpenOCD compatible with files generated by
Altera Quatrus II 9.0.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2600 b42882b7-edfa-0310-969c-e2dbd0fdcd60

- remove enable-ft2232-highspeed configure option, high speed ftdi support is now detected during the configure stage
- warning now issued if high speed ftdi device found and openocd was built using an old driver

git-svn-id: svn://svn.berlios.de/openocd/trunk@2599 b42882b7-edfa-0310-969c-e2dbd0fdcd60

  ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch

GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler.  LDREX and STREX are not
issued by GCC without inline assembly.

This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled.  Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2598 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Fix small typo in ftd2xx type detection

git-svn-id: svn://svn.berlios.de/openocd/trunk@2597 b42882b7-edfa-0310-969c-e2dbd0fdcd60

 - spell "address" right
 - list bp/wp params as optional

And make those source lines wrap at sane margins.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2596 b42882b7-edfa-0310-969c-e2dbd0fdcd60

 - AIRCR_SYSRESETREQ is generic; use it on any system where
  SRST won't fly, not just on Stellaris-based ones.

 - Reformat and improve comments about the Stellaris quirk; and
  xref the only public docs (an email) about the issue.

It seems that *most* Stellaris chips have this problem.  Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2595 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Simplify dumping of register lists by only printing cached values
if they are marked as valid.  Most of the time, they are invalid;
so printing *any* value is just misleading.

Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2594 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Brian Findlay <findlaybrian@gmail.com> Board support for mini2440 (friendlyARM) samsung s3c2440 based board

git-svn-id: svn://svn.berlios.de/openocd/trunk@2593 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2592 b42882b7-edfa-0310-969c-e2dbd0fdcd60

https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html

1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H 
since version 0.16 

2. A speed value of 0 is used as a RTCK request indicator. This clashes with the 
valid clock division value 0 that provide the highest fixed clock frequency. 

3. The ft2232_speed_div function return the maximum selectable frequency (30MHz) 
when RTCK is activated. It should return 0. 

4. The ft2232_khz function return ERROR_OK when RTCK is requested even for 
devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers 
can detect this and try to fallback to a fixed frequency. 

5. FT2232H/FT4232H have a backward compatibility function that divide the clock 
by 5 to get the same frequency range as FT2232D. There is no code that disable 
this functionality. I can not find anything about if this is enabled or disabled by default. 
I think it is safest to actively disable it. 


git-svn-id: svn://svn.berlios.de/openocd/trunk@2591 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Change jtag_rclk behaviour so it can be called before the interface init function

git-svn-id: svn://svn.berlios.de/openocd/trunk@2590 b42882b7-edfa-0310-969c-e2dbd0fdcd60

 - remove endianness options; these chips hard-wire "little"
 - $_TARGETNAME updates:
    * don't pass $_TARGETNAME where a TAP label is required
    * flash config uses $_TARGETNAME (it might not be target #0)
    * simplify one $_TARGETNAME construction
 - update work area setup:
    * remove VM spec; these chips have no VM!
    * fix some wrong sizes (0x4000 == 16K, not 4K)
    * simplify: take defaults
 - comment fixups


git-svn-id: svn://svn.berlios.de/openocd/trunk@2589 b42882b7-edfa-0310-969c-e2dbd0fdcd60

issue with this is that the core debug support uses this
mechanism, then trashes its state over reset.  Users can
Work around that (for now) by re-assigning the desired
config after reset.

Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2588 b42882b7-edfa-0310-969c-e2dbd0fdcd60

David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register handling ... don't use parallel
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.

Minor updates for ARM9 vector_catch support:  it's an 8-bit value.  This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60

display them as 32 bits unless that's their true size.
(Removes some confusion.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60

OpenOCD was able to access only to chips attached to first EMIF
chipselect. This patch fixes chipselect management code and allows
OpenOCD to access to NAND devices attached to any EMIF CS line.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2585 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2584 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2583 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Xiaofan Chen <xiaofanc@gmail.com> Add config file for TI-Luminary LM3S1968 chip and EK-LM3S1968 board

git-svn-id: svn://svn.berlios.de/openocd/trunk@2582 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2580 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Add flash programming support for NXP LPC1700 cortex_m3 based family


git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2578 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Better explanation for the TAP "-ircapture" parameter.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2577 b42882b7-edfa-0310-969c-e2dbd0fdcd60

- fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9

git-svn-id: svn://svn.berlios.de/openocd/trunk@2576 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60

- revert patch from rev1507 as it was causing reset issues with arm9 cores

git-svn-id: svn://svn.berlios.de/openocd/trunk@2574 b42882b7-edfa-0310-969c-e2dbd0fdcd60

- Bring all the ftdi names inline in the cfg scripts. scripts will now work for either ftd2xx or libftdi drivers.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2573 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Fix ARM11 half-word bulk memory read and write.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2572 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2571 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2570 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2569 b42882b7-edfa-0310-969c-e2dbd0fdcd60

       A5.3.11 Data processing (shifted register)

The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes.  There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60

       A5.3.5 Load/store multiple
       A5.3.7 Load word

There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos.  Load word had two bitmask goofs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60

       A5.3.8 Load halfword, unallocated memory hints

It's mostly the usual sort of bitmasking goofage and getting the
width specs right.  In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60

       A5.3.5 Load/store multiple
       A5.3.7 Load word

There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos.  Load word had two bitmask goofs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60

ARMv7-M arch manual:

 A5.3.1 Data processing (modified immediate)
 A5.3.3 Data processing (plain binary immediate)
 A5.3.4 Branches and miscellaneous control

and other (immediate) encodings referenced there.  Several of
these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but
there were a few bugs too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60

with testcases covering several new encodings in these sections
of the ARMv7-M arch manual:

 A5.3.12 Data processing (register)
 A5.3.13 Miscellaneous operations
 A5.3.14 Multiply, and multiply accumulate
 A5.3.15 Long multiply, long multiply accumulate, and divide

The issues were mostly in '12 and '13; some new related 16-bit
opcodes had issues too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few checks for (rt == 0xf) even though that case
is handled with an early return at the top of the function.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60