- Aug 18, 2009
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oharboe authored
David Brownell <david-b@pacbell.net> Clean up ARM7/ARM9 EmbeddedICE register handling ... don't use parallel arrays (error prone) or assume all registers are 32-bits wide (they can have fewer bits); don't use spaces in register names, so they can be passed more easily to the "reg" command. Minor updates for ARM9 vector_catch support: it's an 8-bit value. This seems to help this core's vector_catch command work a bit better; but its behavior wih the register cache is still goofy. git-svn-id: svn://svn.berlios.de/openocd/trunk@2587 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
display them as 32 bits unless that's their true size. (Removes some confusion. git-svn-id: svn://svn.berlios.de/openocd/trunk@2586 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
OpenOCD was able to access only to chips attached to first EMIF chipselect. This patch fixes chipselect management code and allows OpenOCD to access to NAND devices attached to any EMIF CS line. git-svn-id: svn://svn.berlios.de/openocd/trunk@2585 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Aug 16, 2009
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2584 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2583 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
Xiaofan Chen <xiaofanc@gmail.com> Add config file for TI-Luminary LM3S1968 chip and EK-LM3S1968 board git-svn-id: svn://svn.berlios.de/openocd/trunk@2582 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2581 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2580 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Aug 13, 2009
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ntfreak authored
Add flash programming support for NXP LPC1700 cortex_m3 based family git-svn-id: svn://svn.berlios.de/openocd/trunk@2579 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Aug 07, 2009
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ntfreak authored
Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed. git-svn-id: svn://svn.berlios.de/openocd/trunk@2578 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
Better explanation for the TAP "-ircapture" parameter. git-svn-id: svn://svn.berlios.de/openocd/trunk@2577 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
- fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9 git-svn-id: svn://svn.berlios.de/openocd/trunk@2576 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2575 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Aug 06, 2009
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ntfreak authored
- revert patch from rev1507 as it was causing reset issues with arm9 cores git-svn-id: svn://svn.berlios.de/openocd/trunk@2574 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
- Bring all the ftdi names inline in the cfg scripts. scripts will now work for either ftd2xx or libftdi drivers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2573 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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zwelch authored
Fix ARM11 half-word bulk memory read and write. git-svn-id: svn://svn.berlios.de/openocd/trunk@2572 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 31, 2009
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ntfreak authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2571 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 27, 2009
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2570 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2569 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 26, 2009
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oharboe authored
A5.3.11 Data processing (shifted register) The usual kinds of problems; the most noteworthy were that the "S"et flags bit was mis-handled in these instructions. --- This is the last patch from a quickie set of tests covering all encodings of the instructions with 32-bit opcodes. There may be some corner cases left, plus the instructions that aren't yet handled, but the Thumb2 disassembler is no longer just "lightly" tested with GCC output ... the new code paths have mostly been verified. git-svn-id: svn://svn.berlios.de/openocd/trunk@2568 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2567 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
A5.3.8 Load halfword, unallocated memory hints It's mostly the usual sort of bitmasking goofage and getting the width specs right. In one case an older x86 GCC generated bad code unless I structred a conditional differently (sigh). git-svn-id: svn://svn.berlios.de/openocd/trunk@2566 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
A5.3.5 Load/store multiple A5.3.7 Load word There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM fixes are just using width specs to match UAL syntax, except for two opcode name typos. Load word had two bitmask goofs. git-svn-id: svn://svn.berlios.de/openocd/trunk@2565 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 24, 2009
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oharboe authored
ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2564 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. git-svn-id: svn://svn.berlios.de/openocd/trunk@2563 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
Andreas Fritiofson <andreas.fritiofson@gmail.com> I noticed there are a few checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. git-svn-id: svn://svn.berlios.de/openocd/trunk@2562 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 23, 2009
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2561 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2560 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2559 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2558 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 22, 2009
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oharboe authored
Jonathan Cameron <jic23@cam.ac.uk> fix regression from 1836 when the reset_config command was removed from pxa270.cfg git-svn-id: svn://svn.berlios.de/openocd/trunk@2557 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2556 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 21, 2009
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ntfreak authored
Dump SP on poll, and show whether it's MSP or PSP. Thread mode can use either stack pointer, so this is part of the state that's not yet displayed. Shrink some lines. git-svn-id: svn://svn.berlios.de/openocd/trunk@2555 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. git-svn-id: svn://svn.berlios.de/openocd/trunk@2554 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions git-svn-id: svn://svn.berlios.de/openocd/trunk@2553 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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ntfreak authored
Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). git-svn-id: svn://svn.berlios.de/openocd/trunk@2552 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 20, 2009
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ntfreak authored
- fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus git-svn-id: svn://svn.berlios.de/openocd/trunk@2551 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 19, 2009
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2550 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 17, 2009
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2549 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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- Jul 16, 2009
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oharboe authored
git-svn-id: svn://svn.berlios.de/openocd/trunk@2548 b42882b7-edfa-0310-969c-e2dbd0fdcd60
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