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20 authors
  1. Jun 18, 2009
  3. Jun 17, 2009
  5. Jun 16, 2009
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · a0c10dd2
      zwelch authored 
      Extend the internal JTAG event handlers to cover enable/disable,
and use those events to make sure that targets get "examined" if
they were disabled when the scan chain was first set up:

 - Remove "enum jtag_tap_event", merge with "enum jtag_event",
   so C code can now listen for TAP enable/disable events.

 - Report those events so they can trigger callbacks.

 - During startup, make target_examine() register a handler to
   catch ENABLE events for any then-disabled targets.

This fixes bugs like "can't halt target after enabling its TAP".

One class of unresolved bugs:  if the target has an ETM hooked
up to an ETB, nothing activates the ETB.  But starting up the
ETM without access to the ETB registers fails...


git-svn-id: svn://svn.berlios.de/openocd/trunk@2251 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      a0c10dd2
    • zwelch's avatar
      David Brownell <david-b@pacbell.net>: · 14f88aca
      zwelch authored 
      Fix some polling issues:

 - Don't background-poll disabled TAPs ... this was just a bug
   waiting to happen.  (And then it happened!)

 - Don't fail command line polls of disabled taps; that's not any
   kind of error, it's just that you can't do much.  But do show
   that tap-disabled status.

 - Spell "continuous" correctly in the variable name.  ;)

Not resolved by this patch:  the need for an interlock whereby
other code (like the JTAG layer) can block all other access to
the JTAG layer, e.g. while enabling or disabling TAPs.  And
that interlock needs to be timer-safe...


git-svn-id: svn://svn.berlios.de/openocd/trunk@2247 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      14f88aca
  7. Jun 13, 2009
  9. Jun 12, 2009
    • zwelch's avatar
      Further cleanup to MIPS target read/write memory function: · 7fdce0e8
      zwelch authored 
      - Move the mips32_..._read_mem calls to top-level of read_mem function.
- Change: Only perform mips_m4k_read_mem conversion when retval == ERROR_OK.  
   - Prevents pointless conversions of bogus read values after failures.
- Eliminate retval variable from mips_m4k_write_mem; return directly.
- Move declaration of retval variable to point of first use.
- Remove the now redundant switch statements testing size:
  - argument sanitizing already covers these cases.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2220 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      7fdce0e8
    • zwelch's avatar
      David Claffey <dnclaffey@gmail.com>: · c6e80f63
      zwelch authored 
      This patch helps fix MIPS big endian (elf32-tradbigmips) targets.
If "-endian big" is not set in target create, the endianess defaults to
little.  mw and md commands will still work, but binary file loads will
have the incorrect word order loaded into memory.

The EJTAG processor access data register (PrAcc) is little endian
regardless of the CPU endianness; it is always loaded LSB first. This
is confirmed by the fact that mips_ejtag_drscan_32() uses buf_set_u32()
to load the scan field; buf_set_u32() is a little-endian formatter. For
big endian targets, data buffers have to be modified so the LSB of each
u32 or u16 is at the lower (first) memory location.  If the drscan
out_value word order is set using buf_set_u32() then it makes sense to
also fixup the in_value with buf_get_u32(); a symmetry argument. This
has no affect on little endian hosts.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2219 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      c6e80f63
  11. Jun 11, 2009
  13. Jun 10, 2009
  15. Jun 09, 2009
  17. Jun 08, 2009
  19. Jun 07, 2009