add openocd sdk files

openocd/OpenULINK/ulink_firmware.hex

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+:1012C7000C80F70D80C0227F00907F99E0FE30E50B
+:1012D700027F01907F99E0FE30E603430702907F8B
+:1012E7009AE0FE30E703430704907F9BE0FE30E57A
+:1012F70003430708907F9AE0FE53067F8F05E4FFBC
+:10130700FCEE4FF582EC4DF58322E582547FF4FF26
+:10131700907F97E05FF0747F550AFF907F97E04FCB
+:10132700F022858222850A23850B24850C25850DCD
+:10133700262200227E567F021EBEFF011FEE4F703F
+:10134700F722750A05750B001213A6AE82AF837CD0
+:10135700007D00C3EC9EED9F501AC007C006C00574
+:10136700C004121339D004D005D006D0070CBC0036
+:10137700E20D80DF22AE82AF837C007D00C3EC9E4E
+:10138700ED9F501AC007C006C005C00412133BD01A
+:0F13970004D005D006D0070CBC00E20D80DF2289
+:03004300021B009D
+:101B0000020110000201630002016400020165008D
+:101B1000020166000201670002016800020169001B
+:101B200002016A0002016B0002016C0002019300D5
+:101B30000201BA000201BB000201BC000201BD00AB
+:101B40000201BE000201BF000201C0000201C1008B
+:081B50000201C2000201C30002
+:1013A6007A10E4FBFCE58225E0F582E58333F583DC
+:1013B600EB33FBEC33FCEB950AF5F0EC950B4006B2
+:0913C600FCABF0438201DADD22E8
+:0600A000E478FFF6D8FD34
+:10007E007900E94400601B7A009014617800759253
+:10008E0020E493F2A308B800020592D9F4DAF275CF
+:02009E0092FFCF
+:1000A6007800E84400600A7900759220E4F309D8E4
+:1000B600FC7800E84400600C7900902000E4F0A38E
+:0400C600D8FCD9FA8F
+:0D00710075814A1213CFE582600302006E14
+:0413CF007582002201
+:00000001FF

openocd/contrib/99-openocd.rules

+# Copy this file to /etc/udev/rules.d/
+
+ACTION!="add|change", GOTO="openocd_rules_end"
+SUBSYSTEM!="usb|tty|hidraw", GOTO="openocd_rules_end"
+
+# Please keep this list sorted by VID:PID
+
+# opendous and estick
+ATTRS{idVendor}=="03eb", ATTRS{idProduct}=="204f", MODE="664", GROUP="plugdev"
+
+# Original FT232/FT245 VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6001", MODE="664", GROUP="plugdev"
+
+# Original FT2232 VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", MODE="664", GROUP="plugdev"
+
+# Original FT4232 VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6011", MODE="664", GROUP="plugdev"
+
+# Original FT232H VID:PID
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6014", MODE="664", GROUP="plugdev"
+
+# DISTORTEC JTAG-lock-pick Tiny 2
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8220", MODE="664", GROUP="plugdev"
+
+# TUMPA, TUMPA Lite
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a98", MODE="664", GROUP="plugdev"
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="8a99", MODE="664", GROUP="plugdev"
+
+# XDS100v2
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="a6d0", MODE="664", GROUP="plugdev"
+
+# Xverve Signalyzer Tool (DT-USB-ST), Signalyzer LITE (DT-USB-SLITE)
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca0", MODE="664", GROUP="plugdev"
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bca1", MODE="664", GROUP="plugdev"
+
+# TI/Luminary Stellaris Evaluation Board FTDI (several)
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcd9", MODE="664", GROUP="plugdev"
+
+# TI/Luminary Stellaris In-Circuit Debug Interface FTDI (ICDI) Board
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bcda", MODE="664", GROUP="plugdev"
+
+# egnite Turtelizer 2
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="bdc8", MODE="664", GROUP="plugdev"
+
+# Section5 ICEbear
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c140", MODE="664", GROUP="plugdev"
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="664", GROUP="plugdev"
+
+# Amontec JTAGkey and JTAGkey-tiny
+ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="664", GROUP="plugdev"
+
+# TI ICDI
+ATTRS{idVendor}=="0451", ATTRS{idProduct}=="c32a", MODE="664", GROUP="plugdev"
+
+# STLink v1
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3744", MODE="664", GROUP="plugdev"
+
+# STLink v2
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="3748", MODE="664", GROUP="plugdev"
+
+# STLink v2-1
+ATTRS{idVendor}=="0483", ATTRS{idProduct}=="374b", MODE="664", GROUP="plugdev"
+
+# Hilscher NXHX Boards
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="0028", MODE="664", GROUP="plugdev"
+
+# Hitex STR9-comStick
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002c", MODE="664", GROUP="plugdev"
+
+# Hitex STM32-PerformanceStick
+ATTRS{idVendor}=="0640", ATTRS{idProduct}=="002d", MODE="664", GROUP="plugdev"
+
+# Amontec JTAGkey-HiSpeed
+ATTRS{idVendor}=="0fbb", ATTRS{idProduct}=="1000", MODE="664", GROUP="plugdev"
+
+# IAR J-Link USB
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0101", MODE="664", GROUP="plugdev"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0102", MODE="664", GROUP="plugdev"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0103", MODE="664", GROUP="plugdev"
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0104", MODE="664", GROUP="plugdev"
+
+# J-Link-OB (onboard)
+ATTRS{idVendor}=="1366", ATTRS{idProduct}=="0105", MODE="664", GROUP="plugdev"
+
+# Raisonance RLink
+ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="664", GROUP="plugdev"
+
+# Debug Board for Neo1973
+ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-USB-OCD
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0003", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-USB-OCD-TINY
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="0004", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-JTAG-EW
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="001e", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-USB-OCD-TINY-H
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002a", MODE="664", GROUP="plugdev"
+
+# Olimex ARM-USB-OCD-H
+ATTRS{idVendor}=="15ba", ATTRS{idProduct}=="002b", MODE="664", GROUP="plugdev"
+
+# USBprog with OpenOCD firmware
+ATTRS{idVendor}=="1781", ATTRS{idProduct}=="0c63", MODE="664", GROUP="plugdev"
+
+# TI/Luminary Stellaris In-Circuit Debug Interface (ICDI) Board
+ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="664", GROUP="plugdev"
+
+# Marvell Sheevaplug
+ATTRS{idVendor}=="9e88", ATTRS{idProduct}=="9e8f", MODE="664", GROUP="plugdev"
+
+# CMSIS-DAP compatible adapters
+ATTRS{product}=="*CMSIS-DAP*", MODE="664", GROUP="plugdev"
+
+LABEL="openocd_rules_end"

openocd/contrib/libdcc/README

+This code is an example of using the openocd debug message system.
+
+Before the message output is seen in the debug window, the functionality
+will need enabling:
+
+From the gdb prompt:
+monitor target_request debugmsgs enable
+monitor trace point 1
+
+From the Telnet prompt:
+target_request debugmsgs enable
+trace point 1
+
+To see how many times the trace point was hit:
+(monitor) trace point 1
+
+Spen
+spen@spen-soft.co.uk
+

openocd/contrib/libdcc/dcc_stdio.c

+/***************************************************************************
+ *   Copyright (C) 2008 by Dominic Rath                                    *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *   Copyright (C) 2008 by Frederik Kriewtz                                *
+ *   frederik@kriewitz.eu                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#include "dcc_stdio.h"
+
+#define TARGET_REQ_TRACEMSG					0x00
+#define TARGET_REQ_DEBUGMSG_ASCII			0x01
+#define TARGET_REQ_DEBUGMSG_HEXMSG(size)	(0x01 | ((size & 0xff) << 8))
+#define TARGET_REQ_DEBUGCHAR				0x02
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__)
+
+/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel
+ * DCRDR[7:0] is used by target for status
+ * DCRDR[15:8] is used by target for write buffer
+ * DCRDR[23:16] is used for by host for status
+ * DCRDR[31:24] is used for by host for write buffer */
+
+#define NVIC_DBG_DATA_R		(*((volatile unsigned short *)0xE000EDF8))
+
+#define	BUSY	1
+
+void dbg_write(unsigned long dcc_data)
+{
+	int len = 4;
+
+	while (len--)
+	{
+		/* wait for data ready */
+		while (NVIC_DBG_DATA_R & BUSY);
+
+		/* write our data and set write flag - tell host there is data*/
+		NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY);
+		dcc_data >>= 8;
+	}
+}
+
+#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__)
+
+void dbg_write(unsigned long dcc_data)
+{
+	unsigned long dcc_status;
+
+	do {
+		asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status));
+	} while (dcc_status & 0x2);
+
+	asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data));
+}
+
+#else
+ #error unsupported target
+#endif
+
+void dbg_trace_point(unsigned long number)
+{
+	dbg_write(TARGET_REQ_TRACEMSG | (number << 8));
+}
+
+void dbg_write_u32(const unsigned long *val, long len)
+{
+	dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dbg_write(*val);
+
+		val++;
+		len--;
+	}
+}
+
+void dbg_write_u16(const unsigned short *val, long len)
+{
+	unsigned long dcc_data;
+
+	dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dcc_data = val[0]
+			| ((len > 1) ? val[1] << 16: 0x0000);
+
+		dbg_write(dcc_data);
+
+		val += 2;
+		len -= 2;
+	}
+}
+
+void dbg_write_u8(const unsigned char *val, long len)
+{
+	unsigned long dcc_data;
+
+	dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dcc_data = val[0]
+			| ((len > 1) ? val[1] << 8 : 0x00)
+			| ((len > 2) ? val[2] << 16 : 0x00)
+			| ((len > 3) ? val[3] << 24 : 0x00);
+
+		dbg_write(dcc_data);
+
+		val += 4;
+		len -= 4;
+	}
+}
+
+void dbg_write_str(const char *msg)
+{
+	long len;
+	unsigned long dcc_data;
+
+	for (len = 0; msg[len] && (len < 65536); len++);
+
+	dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16));
+
+	while (len > 0)
+	{
+		dcc_data = msg[0]
+			| ((len > 1) ? msg[1] << 8 : 0x00)
+			| ((len > 2) ? msg[2] << 16 : 0x00)
+			| ((len > 3) ? msg[3] << 24 : 0x00);
+		dbg_write(dcc_data);
+
+		msg += 4;
+		len -= 4;
+	}
+}
+
+void dbg_write_char(char msg)
+{
+	dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16));
+}

openocd/contrib/libdcc/dcc_stdio.h

+/***************************************************************************
+ *   Copyright (C) 2008 by Dominic Rath                                    *
+ *   Dominic.Rath@gmx.de                                                   *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#ifndef DCC_STDIO_H
+#define DCC_STDIO_H
+
+void dbg_trace_point(unsigned long number);
+
+void dbg_write_u32(const unsigned long *val, long len);
+void dbg_write_u16(const unsigned short *val, long len);
+void dbg_write_u8(const unsigned char *val, long len);
+
+void dbg_write_str(const char *msg);
+void dbg_write_char(char msg);
+
+#endif	/* DCC_STDIO_H */

openocd/contrib/libdcc/example.c

+/***************************************************************************
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   spen@spen-soft.co.uk                                                  *
+ *   Copyright (C) 2008 by Frederik Kriewtz                                *
+ *   frederik@kriewitz.eu                                                  *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
+ ***************************************************************************/
+
+#include "dcc_stdio.h"
+
+/* enable openocd debugmsg at the gdb prompt:
+ * monitor target_request debugmsgs enable
+ *
+ * create a trace point:
+ * monitor trace point 1
+ *
+ * to show how often the trace point was hit:
+ * monitor trace point
+*/
+
+int main(void)
+{
+	dbg_write_str("hello world");
+
+	dbg_write_char('t');
+	dbg_write_char('e');
+	dbg_write_char('s');
+	dbg_write_char('t');
+	dbg_write_char('\n');
+
+	unsigned long test_u32 = 0x01234567;
+	dbg_write_u32(&test_u32, 1);
+
+	static const unsigned short test_u16[] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x0123, 0x4567, 0x89AB, 0xCDEF};
+	dbg_write_u16(test_u16, 8);
+
+	static const unsigned char test_u8[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0XDD, 0xEE, 0xFF};
+	dbg_write_u8(test_u8, 16);
+
+	while(1)
+	{
+		dbg_trace_point(0);
+	}
+}

openocd/scripts/bitsbytes.tcl

+#----------------------------------------
+# Purpose - Create some $BIT variables
+#           Create $K and $M variables
+#          and some bit field extraction variables.
+# Creat helper variables ...
+#    BIT0.. BIT31
+
+for { set x 0  } { $x < 32 } { set x [expr $x + 1]} {
+    set vn [format "BIT%d" $x]
+    global $vn
+    set $vn   [expr (1 << $x)]
+}
+
+# Create K bytes values
+#    __1K ... to __2048K
+for { set x 1  } { $x < 2048 } { set x [expr $x * 2]} {
+    set vn [format "__%dK" $x]
+    global $vn
+    set $vn   [expr (1024 * $x)]
+}
+
+# Create M bytes values
+#    __1M ... to __2048K
+for { set x 1  } { $x < 2048 } { set x [expr $x * 2]} {
+    set vn [format "__%dM" $x]
+    global $vn
+    set $vn [expr (1024 * 1024 * $x)]
+}
+
+proc create_mask { MSB LSB } {
+    return [expr (((1 << ($MSB - $LSB + 1))-1) << $LSB)]
+}
+
+# Cut Bits $MSB to $LSB out of this value.
+# Example: % format "0x%08x" [extract_bitfield 0x12345678 27 16]
+# Result:  0x02340000
+
+proc extract_bitfield { VALUE MSB LSB } {
+    return [expr [create_mask $MSB $LSB] & $VALUE]
+}
+
+
+# Cut bits $MSB to $LSB out of this value
+# and shift (normalize) them down to bit 0.
+#
+# Example: % format "0x%08x" [normalize_bitfield 0x12345678 27 16]
+# Result:  0x00000234
+#
+proc normalize_bitfield { VALUE MSB LSB } {
+    return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB]
+}
+
+proc show_normalize_bitfield { VALUE MSB LSB } {
+    set m [create_mask $MSB $LSB]
+    set mr [expr $VALUE & $m]
+    set sr [expr $mr >> $LSB]
+    echo [format "((0x%08x & 0x%08x) -> 0x%08x) >> %2d => (0x%x) %5d " $VALUE $m $mr $LSB $sr $sr]
+   return $sr
+}
+
+

openocd/scripts/board/actux3.cfg

+# board config file for AcTux3/XBA IXP42x board
+# Date:   2010-12-16
+# Author: Michael Schwingen <michael@schwingen.org>
+
+reset_config trst_and_srst separate
+
+adapter_nsrst_delay 100
+jtag_ntrst_delay 100
+
+source [find target/ixp42x.cfg]
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init { init_actux3 }
+
+proc init_actux3 { } {
+    ##########################################################################
+    # setup expansion bus CS
+    ##########################################################################
+    mww 0xc4000000  0xbd113842  ;#CS0  : Flash, write enabled @0x50000000
+    mww 0xc4000004  0x94d10013  ;#CS1
+    mww 0xc4000008  0x95960003  ;#CS2
+    mww 0xc400000c  0x00000000  ;#CS3
+    mww 0xc4000010  0x80900003  ;#CS4
+    mww 0xc4000014  0x9d520003  ;#CS5
+    mww 0xc4000018  0x81860001  ;#CS6
+    mww 0xc400001c  0x80900003  ;#CS7
+
+    ixp42x_init_sdram $::IXP42x_SDRAM_16MB_4Mx16_1BANK 2100 3
+
+    #mww 0xc4000020  0xffffee ;# CFG0: remove expansion bus boot flash mirror at 0x00000000
+
+    ixp42x_set_bigendian
+
+    flash probe 0
+}
+
+proc flash_boot { {FILE "/tftpboot/actux3/u-boot.bin"} } {
+    echo "writing bootloader: $FILE"
+    flash write_image erase $FILE 0x50000000 bin
+}
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x50000000 0x400000 2 2 $_TARGETNAME
+
+init
+reset init
+
+# setup to debug u-boot in flash
+proc uboot_debug {} {
+    gdb_breakpoint_override hard
+    xscale vector_catch 0xFF
+
+    xscale vector_table low  1 0xe59ff018
+    xscale vector_table low  2 0xe59ff018
+    xscale vector_table low  3 0xe59ff018
+    xscale vector_table low  4 0xe59ff018
+    xscale vector_table low  5 0xe59ff018
+    xscale vector_table low  6 0xe59ff018
+    xscale vector_table low  7 0xe59ff018
+
+    xscale vector_table high 1 0xe59ff018
+    xscale vector_table high 2 0xe59ff018
+    xscale vector_table high 3 0xe59ff018
+    xscale vector_table high 4 0xe59ff018
+    xscale vector_table high 5 0xe59ff018
+    xscale vector_table high 6 0xe59ff018
+    xscale vector_table high 7 0xe59ff018
+}

openocd/scripts/board/alphascale_asm9260_ek.cfg

+source [find target/alphascale_asm9260t.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configure clock"
+	# Enable SRAM clk
+	mww 0x80040024 0x4
+	# Enable IRQ clk
+	mww 0x80040034 0x100
+	# Enable DMA0,1 clk
+	mww 0x80040024 0x600
+	# Make sysre syspll is enabled
+	mww 0x80040238 0x750
+	#CPU = PLLCLK/2
+	mww 0x8004017C 0x2
+	#SYSAHBCLK = CPUCLK/2
+	mww 0x80040180 0x2
+	# Set PLL freq to 480MHz
+	mww 0x80040100 480
+	# normally we shoul waiting here until we get 0x1 (0x80040104)&0x1)==0x0)
+	sleep 100
+
+	# select PLL as main source
+	mww 0x80040120 0x1
+	# disable and enble main clk to update changes?
+	mww 0x80040124 0x0
+	mww 0x80040124 0x1
+
+	echo "Configure memory"
+	#enable EMI CLK
+	mww 0x80040024 0x40
+
+	# configure memory controller for internal SRAM
+	mww 0x80700000 0x1188
+	# change default emi clk delay
+	mww 0x8004034C 0xA0503
+	# make sure chip_select_register2_low has correct value (why?)
+	mww 0x8070001c 0x20000000
+	# set type to sdram and size to 32MB
+	mww 0x8070005c 0xa
+	# configure internal SDRAM timing
+	mww 0x80700004 0x024996d9
+	# configure Static Memory timing
+	mww 0x80700094 0x00542b4f
+
+	echo "Configure uart4"
+	# enable pinctrl clk
+	mww 0x80040024 0x2000000
+	# mux GPIO3_0 and GPIO3_1 to UART4
+	mww 0x80044060 0x2
+	mww 0x80044064 0x2
+	# configure UART4CLKDIV
+	mww 0x800401a8 0x1
+	# enable uart4 clk
+	mww 0x80040024 0x8000
+	# clear softrst and clkgate on uart4
+	mww 0x80010008 0xC0000000
+	# set bandrate 115200 12M
+	mww 0x80010030 0x00062070
+	# enable Rx&Tx
+	mww 0x80010024 0x301
+	# clear hw control
+	mww 0x80010028 0xc000
+}
+
+$_TARGETNAME configure -work-area-phys 0x21ffe000 -work-area-virt 0xc1ffe000 -work-area-size 0x1000
+$_TARGETNAME arm7_9 fast_memory_access enable
+$_TARGETNAME arm7_9 dcc_downloads enable

openocd/scripts/board/altera_sockit.cfg

+#
+# Cyclone V SocKit board
+# http://www.altera.com/b/arrow-sockit.html
+#
+# Software support page:
+# http://www.rocketboards.org/
+
+# openocd does not currently support the on-board USB Blaster II.
+# Install the JTAG header and use a USB Blaster instead.
+interface usb_blaster
+
+source [find target/altera_fpgasoc.cfg]
+
+# If the USB Blaster II were supported, these settings would be needed
+#usb_blaster_vid_pid 0x6810 0x09fb
+#usb_blaster_device_desc "USB-Blaster II"
+
+adapter_khz 100
+

openocd/scripts/board/am3517evm.cfg

+# DANGER!!!! early work in progress for this PCB/target.
+#
+# The most basic operations work well enough that it is
+# useful to have this in the repository for cooperation
+# alpha testing purposes.
+#
+# TI AM3517
+#
+# http://focus.ti.com/docs/prod/folders/print/am3517.html
+# http://processors.wiki.ti.com/index.php/Debug_Access_Port_(DAP)
+# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
+
+set CHIPTYPE "am35x"
+source [find target/amdm37x.cfg]
+
+# The TI-14 JTAG connector does not have srst.  CPU reset is handled in
+# hardware.
+reset_config trst_only
+
+# "amdm37x_dbginit am35x.cpu" needs to be run after init.
+

openocd/scripts/board/arm_evaluator7t.cfg

+# This board is from ARM and has an samsung s3c45101x01 chip
+
+source [find target/samsung_s3c4510.cfg]
+
+#
+# FIXME:
+#  Add (A) sdram configuration
+#  Add (B) flash cfi programing configuration
+#
+

openocd/scripts/board/asus-rt-n16.cfg

+#
+# http://wikidevi.com/wiki/ASUS_RT-N16
+#
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4718.cfg]
+
+# External 32MB NOR Flash (Macronix MX29GL256EHTI2I-90Q)
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 1 1 $_TARGETNAME x16_as_x8

openocd/scripts/board/asus-rt-n66u.cfg

+#
+# http://wikidevi.com/wiki/Asus_RT-N66U
+#
+
+echo "ATTENTION: you need to solder a 4.7-10k pullup resistor to pin 21 of flash IC"
+echo "to enable JTAG, see http://wl500g.info/album.php?albumid=28&attachmentid=8991 ,"
+echo "there is an unpopulated footprint near U8.\n"
+
+set partition_list {
+    CFE		{ Bootloader			0xbc000000 0x00040000 }
+    firmware	{ "Kernel+rootfs"		0xbc040000 0x01fa0000 }
+    nvram	{ "Config space"		0xbdfe0000 0x00020000 }
+}
+
+source [find target/bcm4706.cfg]
+
+# External 32MB NOR Flash (Spansion S29GL256P10TF101
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0xbc000000 0x02000000 2 2 $_TARGETNAME

openocd/scripts/board/at91cap7a-stk-sdram.cfg

+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
+#
+# use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME cap7
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x40700f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -event reset-start {
+	# start off real slow when we're running off internal RC oscillator
+	adapter_khz 32
+}
+
+proc peek32 {address} {
+	mem2array t 32 $address 1
+	return $t(0)
+}
+
+# Wait for an expression to be true with a timeout
+proc wait_state {expression} {
+	for {set i 0} {$i < 1000} {set i [expr $i + 1]} {
+		if {[uplevel 1 $expression] == 0} {
+			return
+		}
+	}
+	return -code 1 "Timed out"	
+}
+
+# Use a global variable here to be able to tinker interactively with
+# post reset jtag frequency.
+global post_reset_khz
+# Danger!!!! Even 16MHz kinda works with this target, but 
+# it needs to be as low as 2000kHz to be stable.
+set post_reset_khz 2000
+
+$_TARGETNAME configure -event reset-init {
+	echo "Configuring master clock"
+	# disable watchdog
+	mww 0xfffffd44 0xff008000
+	# enable user reset
+	mww 0xfffffd08 0xa5000001
+	# Enable main oscillator
+	mww 0xFFFFFc20  0x00000f01
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}  
+
+	# Set PLLA to 96MHz
+	mww 0xFFFFFc28 0x20072801
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}  
+
+	# Select prescaler
+	mww 0xFFFFFC30 0x00000004
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+
+	# Select master clock to 48MHz
+	mww 0xFFFFFC30 0x00000006
+	wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}  
+
+	echo "Master clock ok."
+	
+	# Now that we're up and running, crank up speed!
+	global post_reset_khz ;	adapter_khz $post_reset_khz
+	
+	echo "Configuring the SDRAM controller..."
+
+	# Configure EBI Chip select for SDRAM
+	mww 0xFFFFEF30 0x00000102
+
+	# Enable clock on EBI PIOs
+	mww 0xFFFFFC10 0x00000004
+
+	# Configure PIO for SDRAM
+	mww 0xFFFFF470 0xFFFF0000
+	mww 0xFFFFF474 0x00000000
+	mww 0xFFFFF404 0xFFFF0000
+
+	# Configure SDRAMC CR
+	mww 0xFFFFEA08 0xA63392F9
+ 
+	# NOP command
+	mww 0xFFFFEA00 0x1
+	mww 0x20000000 0
+
+	# Precharge All Banks command
+	mww 0xFFFFEA00 0x2
+	mww 0x20000000 0
+
+	# Set 1st CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000010 0x00000001
+
+	# Set 2nd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000020 0x00000002
+
+	# Set 3rd CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000030 0x00000003
+
+	# Set 4th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000040 0x00000004
+
+	# Set 5th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000050 0x00000005
+
+	# Set 6th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000060 0x00000006
+
+	# Set 7th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000070 0x00000007
+
+	# Set 8th CBR
+	mww 0xFFFFEA00 0x00000004
+	mww 0x20000080 0x00000008
+
+	# Set LMR operation
+	mww 0xFFFFEA00 0x00000003
+
+	# Perform LMR burst=1, lat=2
+	mww 0x20000020 0xCAFEDEDE
+
+	# Set Refresh Timer
+	mww 0xFFFFEA04 0x00000203
+
+	# Set Normal mode
+	mww 0xFFFFEA00 0x00000000
+	mww 0x20000000 0x00000000
+
+	#remap internal memory at address 0x0
+	mww 0xffffef00 0x3
+	
+	echo "SDRAM configuration ok."
+}
+
+$_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+arm7_9 dcc_downloads enable
+arm7_9 fast_memory_access enable
+
+#set _FLASHNAME $_CHIPNAME.flash
+#flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
+

openocd/scripts/board/at91eb40a.cfg

+#Script for AT91EB40a
+
+# FIXME use some standard target config, maybe create one from this
+#
+#	source [find target/...cfg]
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME at91eb40a
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x1f0f0f0f
+}
+
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#target configuration
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# speed up memory downloads
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+#flash driver
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x01000000 0x200000 2 2 $_TARGETNAME
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+	echo "Running reset init script for AT91EB40A"
+	# Reset script for AT91EB40a
+	reg cpsr 0x000000D3
+	mww 0xFFE00020 0x1
+	mww 0xFFE00024 0x00000000
+	mww 0xFFE00000 0x01002539
+	mww 0xFFFFF124 0xFFFFFFFF
+	mww 0xffff0010 0x100
+	mww 0xffff0034 0x100
+}
+
+# This target is pretty snappy...
+adapter_khz 16000

openocd/scripts/board/at91rm9200-dk.cfg

+#
+# This is for the "at91rm9200-DK" (not the EK) eval board.
+#
+# The two are probably very simular.... I have DK...
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_dk_init }
+
+#flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00200000 2 2 $_TARGETNAME
+
+
+proc at91rm9200_dk_init { } {
+    # Try to run at 1khz... Yea, that slow!
+    # Chip is really running @ 32khz
+    adapter_khz 8
+
+    mww 0xfffffc64 0xffffffff
+    ##  disable all clocks but system clock
+    mww 0xfffffc04 0xfffffffe
+    ##  disable all clocks to pioa and piob
+    mww 0xfffffc14 0xffffffc3
+    ##  master clock = slow cpu = slow
+    ##  (means the CPU is running at 32khz!)
+    mww 0xfffffc30 0
+    ##  main osc enable
+    mww 0xfffffc20 0x0000ff01
+    ##  program pllA
+    mww 0xfffffc28 0x20263e04
+    ##  program pllB
+    mww 0xfffffc2c 0x10483e0e
+    ##  let pll settle... sleep 100msec
+    sleep 100
+    ##  switch to fast clock
+    mww 0xfffffc30 0x202
+    ## Sleep some - (go read)
+    sleep 100
+
+    #========================================
+    # CPU now runs at 180mhz
+    # SYS runs at 60mhz.
+    adapter_khz 40000
+    #========================================
+
+
+    ##  set memc for all memories
+    mww 0xffffff60 0x02
+    ##  program smc controller
+    mww 0xffffff70 0x3284
+    ##  init sdram
+    mww 0xffffff98 0x7fffffd0
+    ##  all banks precharge
+    mww 0xffffff80 0x02
+    ##  touch sdram chip to make it work
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    mww 0xffffff90 0x04
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    mww 0x20000000 0
+    ##  sdram controller mode register
+    ##  Refresh, etc....
+    mww 0xffffff90 0x03
+    mww 0x20000080 0
+    mww 0xffffff94 0x1f4
+    mww 0x20000080 0
+    mww 0xffffff90 0x10
+    mww 0x20000000 0
+    mww 0xffffff00 0x01
+
+}

openocd/scripts/board/at91rm9200-ek.cfg

+#
+# Copyright 2010 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
+#
+# under GPLv2 Only
+#
+# This is for the "at91rm9200-ek" eval board.
+#
+#
+# It has atmel at91rm9200 chip.
+source [find target/at91rm9200.cfg]
+
+reset_config trst_and_srst
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91rm9200_ek_init }
+
+## flash bank <name> <driver> <base> <size> <chip_width> <bus_width> <target>
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
+
+# The chip may run @ 32khz, so set a really low JTAG speed
+adapter_khz 8
+
+proc at91rm9200_ek_init { } {
+	# Try to run at 1khz... Yea, that slow!
+	# Chip is really running @ 32khz
+	adapter_khz 8
+
+	mww 0xfffffc64 0xffffffff
+	## disable all clocks but system clock
+	mww 0xfffffc04 0xfffffffe
+	## disable all clocks to pioa and piob
+	mww 0xfffffc14 0xffffffc3
+	## master clock = slow cpu = slow
+	## (means the CPU is running at 32khz!)
+	mww 0xfffffc30 0
+	## main osc enable
+	mww 0xfffffc20 0x0000ff01
+	## MC_PUP
+	mww 0xFFFFFF50 0x00000000
+	## MC_PUER: Memory controller protection unit disable
+	mww 0xFFFFFF54 0x00000000
+	## EBI_CFGR
+	mww 0xFFFFFF64 0x00000000
+	## SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
+	mww 0xFFFFFF70 0x00003284
+
+	## Init Clocks
+	## CKGR_PLLAR
+	mww 0xFFFFFC28 0x2000BF05
+	## PLLAR: 179,712000 MHz for PCK
+	mww 0xFFFFFC28 0x20263E04
+	sleep 100
+	## PMC_MCKR
+	mww 0xFFFFFC30 0x00000100
+	sleep 100
+	## ;MCKR : PCK/3 = MCK Master Clock = 59,904000MHz from PLLA
+	mww 0xFFFFFC30 0x00000202
+	sleep 100
+
+	#========================================
+	# CPU now runs at 180mhz
+	# SYS runs at 60mhz.
+	adapter_khz 40000
+	#========================================
+
+	## Init SDRAM
+	## PIOC_ASR: Configure PIOC as peripheral (D16/D31)
+	mww 0xFFFFF870 0xFFFF0000
+	## PIOC_BSR:
+	mww 0xFFFFF874 0x00000000
+	## PIOC_PDR:
+	mww 0xFFFFF804 0xFFFF0000
+	## EBI_CSA : CS1=SDRAM
+	mww 0xFFFFFF60 0x00000002
+	## EBI_CFGR:
+	mww 0xFFFFFF64 0x00000000
+	## SDRC_CR :
+	mww 0xFFFFFF98 0x2188c155
+	## SDRC_MR : Precharge All
+	mww 0xFFFFFF90 0x00000002
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Refresh
+	mww 0xFFFFFF90 0x00000004
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Load Mode Register
+	mww 0xFFFFFF90 0x00000003
+	## access SDRAM
+	mww 0x20000080 0x00000000
+	## SDRC_TR : Write refresh rate
+	mww 0xFFFFFF94 0x000002E0
+	## access SDRAM
+	mww 0x20000000 0x00000000
+	## SDRC_MR : Normal Mode
+	mww 0xFFFFFF90 0x00000000
+	## access SDRAM
+	mww 0x20000000 0x00000000
+}

openocd/scripts/board/at91sam9261-ek.cfg

+################################################################################
+# Atmel AT91SAM9261-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9261.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9261_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9261.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9261ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9261ek_reset_init { } {
+
+	;# for ppla at 199 Mhz
+	set config(master_pll_div)	15
+	set config(master_pll_mul)	162
+
+	;# for ppla at 239 Mhz
+	;# set master_pll_div	1
+	;# set master_pll_mul	13
+
+	set val	[expr $::AT91_WDT_WDV]			;# Counter Value
+	set val	[expr ($val | $::AT91_WDT_WDDIS)]	;# Watchdog Disable
+	set val	[expr ($val | $::AT91_WDT_WDD)]		;# Delta Value
+	set val	[expr ($val | $::AT91_WDT_WDDBGHLT)]	;# Debug Halt
+	set val	[expr ($val | $::AT91_WDT_WDIDLEHLT)]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBICSA
+	set config(matrix_ebicsa_val) [expr ($::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC)]
+
+	;# SDRAMC_CR - Configuration register
+	set val [expr $::AT91_SDRAMC_NC_9]
+	set val [expr ($val | $::AT91_SDRAMC_NR_13)]
+	set val [expr ($val | $::AT91_SDRAMC_NB_4)]
+	set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
+	set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
+	set val [expr ($val | (2 <<  8))]		;# Write Recovery Delay
+	set val [expr ($val | (7 << 12))]		;# Row Cycle Delay
+	set val [expr ($val | (3 << 16))]		;# Row Precharge Delay
+	set val [expr ($val | (2 << 20))]		;# Row to Column Delay
+	set val [expr ($val | (5 << 24))]		;# Active to Precharge Delay
+	set val [expr ($val | (8 << 28))]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}

openocd/scripts/board/at91sam9263-ek.cfg

+################################################################################
+# Atmel AT91SAM9263-EK eval board
+################################################################################
+
+source [find mem_helper.tcl]
+source [find target/at91sam9263.cfg]
+uplevel #0 [list source [find chip/atmel/at91/hardware.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9263_matrix.cfg]]
+uplevel #0 [list source [find chip/atmel/at91/at91sam9_init.cfg]]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9263.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+scan_chain
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { at91sam9263ek_reset_init }
+$_TARGETNAME configure -event reset-start { at91sam9_reset_start }
+
+proc at91sam9263ek_reset_init { } {
+
+	set config(master_pll_div)	14
+	set config(master_pll_mul)	171
+
+	set val	[expr $::AT91_WDT_WDV]			;# Counter Value
+	set val	[expr ($val | $::AT91_WDT_WDDIS)]	;# Watchdog Disable
+	set val	[expr ($val | $::AT91_WDT_WDD)]		;# Delta Value
+	set val	[expr ($val | $::AT91_WDT_WDDBGHLT)]	;# Debug Halt
+	set val	[expr ($val | $::AT91_WDT_WDIDLEHLT)]	;# Idle Halt
+
+	set config(wdt_mr_val) $val
+
+	set config(sdram_piod) 1
+	;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
+	set config(matrix_ebicsa_addr)	$::AT91_MATRIX_EBI0CSA
+
+	set val	[expr $::AT91_MATRIX_EBI0_DBPUC]
+	set val [expr ($val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V)]
+	set val [expr ($val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC)]
+	set config(matrix_ebicsa_val) $val
+
+	;# SDRAMC_CR - Configuration register
+	set val [expr $::AT91_SDRAMC_NC_9]
+	set val [expr ($val | $::AT91_SDRAMC_NR_13)]
+	set val [expr ($val | $::AT91_SDRAMC_NB_4)]
+	set val [expr ($val | $::AT91_SDRAMC_CAS_3)]
+	set val [expr ($val | $::AT91_SDRAMC_DBW_32)]
+	set val [expr ($val | (1 <<  8))]		;# Write Recovery Delay
+	set val [expr ($val | (7 << 12))]		;# Row Cycle Delay
+	set val [expr ($val | (2 << 16))]		;# Row Precharge Delay
+	set val [expr ($val | (2 << 20))]		;# Row to Column Delay
+	set val [expr ($val | (5 << 24))]		;# Active to Precharge Delay
+	set val [expr ($val | (1 << 28))]		;# Exit Self Refresh to Active Delay
+
+	set config(sdram_cr_val) $val
+
+	set config(sdram_tr_val) 0x13c
+
+	set config(sdram_base) $::AT91_CHIPSELECT_1
+	at91sam9_reset_init $config
+}