core1startup.c

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 * $Date: 2018-08-10 17:11:51 -0500 (Fri, 10 Aug 2018) $
 * $Revision: 36872 $
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/**
 * @file    core1startup.c
 * @brief   Startup Code for MAX32665 Family CPU1
 * @details These functions are called at the startup of the second ARM core (CPU1/Core1)
 */
#include <string.h>
#include <stdio.h>
#include <stdlib.h>
#include "max32665.h"
#include "mxc_sys.h"
#include "gcr_regs.h"
#include "icc_regs.h"
#include "pwrseq_regs.h"

extern uint32_t __isr_vector_core1;

void PreInit_Core1(void) {
    return;
}

void SystemInit_Core1(void) {
    /* Configure the interrupt controller to use the application vector table in */
    /* the application space */
    SCB->VTOR = (unsigned long)__isr_vector_core1;

    /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */
    /* Grant full access, per "Table B3-24 CPACR bit assignments". */
    /* DDI0403D "ARMv7-M Architecture Reference Manual" */
    SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk;
    __DSB();
    __ISB();

    // Flush iCache
    // MXC_ICC1->invalidate = 1;
    // while(!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY));
    // Enable iCachez
    // MXC_ICC1->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_CACHE_EN;
    // while(!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_CACHE_RDY)); 
}