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 <span id="projectnumber">0.2</span>
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<div class="title">RPU_SPIXIPMC<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> » <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div> </div>
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<p>SPI-XIP Master Controller Protection Register.
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<table class="memberdecls">
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Macros</h2></td></tr>
<tr class="memitem:ga5ce2b6ddbaf7e59b39a2b44f862e7655"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5ce2b6ddbaf7e59b39a2b44f862e7655"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga5ce2b6ddbaf7e59b39a2b44f862e7655">MXC_F_RPU_SPIXIPMC_DMA0ACN_POS</a>   0</td></tr>
<tr class="memdesc:ga5ce2b6ddbaf7e59b39a2b44f862e7655"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_DMA0ACN Position. <br /></td></tr>
<tr class="separator:ga5ce2b6ddbaf7e59b39a2b44f862e7655"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga3b5950f60a389df10fdb1ca150c87e3f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga3b5950f60a389df10fdb1ca150c87e3f"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga3b5950f60a389df10fdb1ca150c87e3f">MXC_F_RPU_SPIXIPMC_DMA0ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_DMA0ACN_POS))</td></tr>
<tr class="memdesc:ga3b5950f60a389df10fdb1ca150c87e3f"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_DMA0ACN Mask. <br /></td></tr>
<tr class="separator:ga3b5950f60a389df10fdb1ca150c87e3f"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga816cd413caf31d69bc2b14db4a5b1387"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga816cd413caf31d69bc2b14db4a5b1387"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga816cd413caf31d69bc2b14db4a5b1387">MXC_F_RPU_SPIXIPMC_DMA1ACN_POS</a>   1</td></tr>
<tr class="memdesc:ga816cd413caf31d69bc2b14db4a5b1387"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_DMA1ACN Position. <br /></td></tr>
<tr class="separator:ga816cd413caf31d69bc2b14db4a5b1387"><td class="memSeparator" colspan="2"> </td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gaedc1fc10fc1cfc1c92770c1b3575d496">MXC_F_RPU_SPIXIPMC_DMA1ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_DMA1ACN_POS))</td></tr>
<tr class="memdesc:gaedc1fc10fc1cfc1c92770c1b3575d496"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_DMA1ACN Mask. <br /></td></tr>
<tr class="separator:gaedc1fc10fc1cfc1c92770c1b3575d496"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4b7a5013315f2e809aaa3097f36e1126"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga4b7a5013315f2e809aaa3097f36e1126"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga4b7a5013315f2e809aaa3097f36e1126">MXC_F_RPU_SPIXIPMC_USBACN_POS</a>   2</td></tr>
<tr class="memdesc:ga4b7a5013315f2e809aaa3097f36e1126"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_USBACN Position. <br /></td></tr>
<tr class="separator:ga4b7a5013315f2e809aaa3097f36e1126"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaa1a76dec2f9e5d65d60a193f4ab38be7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaa1a76dec2f9e5d65d60a193f4ab38be7"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gaa1a76dec2f9e5d65d60a193f4ab38be7">MXC_F_RPU_SPIXIPMC_USBACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_USBACN_POS))</td></tr>
<tr class="memdesc:gaa1a76dec2f9e5d65d60a193f4ab38be7"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_USBACN Mask. <br /></td></tr>
<tr class="separator:gaa1a76dec2f9e5d65d60a193f4ab38be7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaf8d9485347d095a426bdd280ebdc0d90"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaf8d9485347d095a426bdd280ebdc0d90"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gaf8d9485347d095a426bdd280ebdc0d90">MXC_F_RPU_SPIXIPMC_SYS0ACN_POS</a>   3</td></tr>
<tr class="memdesc:gaf8d9485347d095a426bdd280ebdc0d90"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SYS0ACN Position. <br /></td></tr>
<tr class="separator:gaf8d9485347d095a426bdd280ebdc0d90"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga8a4912d1832a6c5d4b878117fb0232ea"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga8a4912d1832a6c5d4b878117fb0232ea"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga8a4912d1832a6c5d4b878117fb0232ea">MXC_F_RPU_SPIXIPMC_SYS0ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SYS0ACN_POS))</td></tr>
<tr class="memdesc:ga8a4912d1832a6c5d4b878117fb0232ea"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SYS0ACN Mask. <br /></td></tr>
<tr class="separator:ga8a4912d1832a6c5d4b878117fb0232ea"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga660b2ef8c8ad8677786daa3b45fcdbad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga660b2ef8c8ad8677786daa3b45fcdbad"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga660b2ef8c8ad8677786daa3b45fcdbad">MXC_F_RPU_SPIXIPMC_SYS1ACN_POS</a>   4</td></tr>
<tr class="memdesc:ga660b2ef8c8ad8677786daa3b45fcdbad"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SYS1ACN Position. <br /></td></tr>
<tr class="separator:ga660b2ef8c8ad8677786daa3b45fcdbad"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaad3480699ff964c6b8618c8e90e4d2e0"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaad3480699ff964c6b8618c8e90e4d2e0"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gaad3480699ff964c6b8618c8e90e4d2e0">MXC_F_RPU_SPIXIPMC_SYS1ACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SYS1ACN_POS))</td></tr>
<tr class="memdesc:gaad3480699ff964c6b8618c8e90e4d2e0"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SYS1ACN Mask. <br /></td></tr>
<tr class="separator:gaad3480699ff964c6b8618c8e90e4d2e0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga72620f426935c7a907c78ea3a9852fca"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga72620f426935c7a907c78ea3a9852fca"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga72620f426935c7a907c78ea3a9852fca">MXC_F_RPU_SPIXIPMC_SDMADACN_POS</a>   5</td></tr>
<tr class="memdesc:ga72620f426935c7a907c78ea3a9852fca"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SDMADACN Position. <br /></td></tr>
<tr class="separator:ga72620f426935c7a907c78ea3a9852fca"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab763d50705bebda205c6f1dbb9dc3ee3"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab763d50705bebda205c6f1dbb9dc3ee3"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gab763d50705bebda205c6f1dbb9dc3ee3">MXC_F_RPU_SPIXIPMC_SDMADACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDMADACN_POS))</td></tr>
<tr class="memdesc:gab763d50705bebda205c6f1dbb9dc3ee3"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SDMADACN Mask. <br /></td></tr>
<tr class="separator:gab763d50705bebda205c6f1dbb9dc3ee3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaaffe93903f1f7bfcf80b17aa961fd0f7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaaffe93903f1f7bfcf80b17aa961fd0f7"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gaaffe93903f1f7bfcf80b17aa961fd0f7">MXC_F_RPU_SPIXIPMC_SDMAIACN_POS</a>   6</td></tr>
<tr class="memdesc:gaaffe93903f1f7bfcf80b17aa961fd0f7"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SDMAIACN Position. <br /></td></tr>
<tr class="separator:gaaffe93903f1f7bfcf80b17aa961fd0f7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gafd77d31cf7b7aaf53a5af3ec63123585"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gafd77d31cf7b7aaf53a5af3ec63123585"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gafd77d31cf7b7aaf53a5af3ec63123585">MXC_F_RPU_SPIXIPMC_SDMAIACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDMAIACN_POS))</td></tr>
<tr class="memdesc:gafd77d31cf7b7aaf53a5af3ec63123585"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SDMAIACN Mask. <br /></td></tr>
<tr class="separator:gafd77d31cf7b7aaf53a5af3ec63123585"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gab6e444e8f97aa164ce6d6e1e9061b49e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gab6e444e8f97aa164ce6d6e1e9061b49e"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gab6e444e8f97aa164ce6d6e1e9061b49e">MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS</a>   7</td></tr><tr class="memdesc:gab6e444e8f97aa164ce6d6e1e9061b49e"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_CRYPTOACN Position. <br /></td></tr>
<tr class="separator:gab6e444e8f97aa164ce6d6e1e9061b49e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga44a11431a568f92dc74c87e76aa4eff5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga44a11431a568f92dc74c87e76aa4eff5"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga44a11431a568f92dc74c87e76aa4eff5">MXC_F_RPU_SPIXIPMC_CRYPTOACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_CRYPTOACN_POS))</td></tr>
<tr class="memdesc:ga44a11431a568f92dc74c87e76aa4eff5"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_CRYPTOACN Mask. <br /></td></tr>
<tr class="separator:ga44a11431a568f92dc74c87e76aa4eff5"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gaddf7e9d7a4036f05855ac692e6f5a244"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="gaddf7e9d7a4036f05855ac692e6f5a244"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#gaddf7e9d7a4036f05855ac692e6f5a244">MXC_F_RPU_SPIXIPMC_SDIOACN_POS</a>   8</td></tr>
<tr class="memdesc:gaddf7e9d7a4036f05855ac692e6f5a244"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SDIOACN Position. <br /></td></tr>
<tr class="separator:gaddf7e9d7a4036f05855ac692e6f5a244"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5f27f60cde647cf697e129f77688fc8e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ga5f27f60cde647cf697e129f77688fc8e"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SPIXIPMC.html#ga5f27f60cde647cf697e129f77688fc8e">MXC_F_RPU_SPIXIPMC_SDIOACN</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SPIXIPMC_SDIOACN_POS))</td></tr>
<tr class="memdesc:ga5f27f60cde647cf697e129f77688fc8e"><td class="mdescLeft"> </td><td class="mdescRight">SPIXIPMC_SDIOACN Mask. <br /></td></tr>
<tr class="separator:ga5f27f60cde647cf697e129f77688fc8e"><td class="memSeparator" colspan="2"> </td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
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