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 <span id="projectnumber">0.2</span>
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<div class="title">RPU_SYSRAM5<div class="ingroups"><a class="el" href="group__rpu.html">Resource Protection Unit</a> » <a class="el" href="group__rpu__registers.html">RPU_Registers</a></div></div> </div>
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<p>SYSRAM5 Protection Register.
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Macros</h2></td></tr>
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<tr class="memdesc:gab6be376bca089b12c7d358cf23015a48"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA0ACNR Position. <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga70a44d1a8847a28037f2f2bbb6257534">MXC_F_RPU_SYSRAM5_DMA0ACNR</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_DMA0ACNR_POS))</td></tr>
<tr class="memdesc:ga70a44d1a8847a28037f2f2bbb6257534"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA0ACNR Mask. <br /></td></tr>
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<tr class="memdesc:ga6de5531a5eb9ec977dccfef92455bd1c"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA0ACNW Position. <br /></td></tr>
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<tr class="memdesc:gacfc0f2e108602ed862160ea85f6df049"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA0ACNW Mask. <br /></td></tr>
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<tr class="memdesc:ga3647519b015b9e23f1a6c1ee75ef0e65"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA1ACNR Position. <br /></td></tr>
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<tr class="memdesc:gac4a12798a5065bea40922f2d7b0bfef6"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA1ACNR Mask. <br /></td></tr>
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<tr class="memdesc:ga715360d30404ab450e2e747034072e13"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_DMA1ACNW Mask. <br /></td></tr>
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<tr class="memdesc:ga80e7d3775e6e1a68b2bed67d7c72a9c3"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_USBACNR Mask. <br /></td></tr>
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<tr class="memdesc:ga34b4ee20f9b57f39b114dfd78915bf7e"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_USBACNW Position. <br /></td></tr>
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#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga11cf9303cab3674150082cf9ce54a7c4">MXC_F_RPU_SYSRAM5_USBACNW</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_USBACNW_POS))</td></tr>
<tr class="memdesc:ga11cf9303cab3674150082cf9ce54a7c4"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_USBACNW Mask. <br /></td></tr>
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<tr class="memdesc:gab04225bd97e811c80e3d644f37e94899"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS0ACNR Position. <br /></td></tr>
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<tr class="memdesc:ga4c578a178264ab658ae1dfc1117a14ab"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS0ACNR Mask. <br /></td></tr>
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<tr class="memdesc:gaca68ff267b5df6af961e755e61047ee0"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS0ACNW Position. <br /></td></tr><tr class="separator:gaca68ff267b5df6af961e755e61047ee0"><td class="memSeparator" colspan="2"> </td></tr>
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<tr class="memdesc:ga7e32f6edd93e700318967acacc7a2a3b"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS0ACNW Mask. <br /></td></tr>
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<tr class="memdesc:gaa0ecf3c44bf12f307eccd1164141cd2e"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS1ACNR Position. <br /></td></tr>
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<tr class="memdesc:gafbb08a982cec1ff8b1447c0b83999fb4"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS1ACNR Mask. <br /></td></tr>
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<tr class="memdesc:ga5d6a4c854a5329d54f36425a7e836440"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS1ACNW Position. <br /></td></tr>
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<tr class="memdesc:ga66992b0f41011c377de7d8c1bb79825f"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SYS1ACNW Mask. <br /></td></tr>
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<tr class="memdesc:ga0f6d3479df5c894a9195c7dee119d818"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMADACNR Position. <br /></td></tr>
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<tr class="memdesc:ga25137e94f6e374d03632d791bf0ea806"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMADACNR Mask. <br /></td></tr>
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<tr class="memdesc:ga2b412d8bd32723dda6f40cea7118fe19"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMADACNW Position. <br /></td></tr>
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<tr class="memdesc:ga5c706e81eb14bedaee2094e4771591d8"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMADACNW Mask. <br /></td></tr>
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<tr class="memitem:ga39a2f95faff5bce1cd80f348ba048fe2"><td class="memItemLeft" align="right" valign="top"><a id="ga39a2f95faff5bce1cd80f348ba048fe2"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga39a2f95faff5bce1cd80f348ba048fe2">MXC_F_RPU_SYSRAM5_SDMAIACNR_POS</a>   12</td></tr>
<tr class="memdesc:ga39a2f95faff5bce1cd80f348ba048fe2"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMAIACNR Position. <br /></td></tr>
<tr class="separator:ga39a2f95faff5bce1cd80f348ba048fe2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae299959d3e5843b350af472f6d8ad43d"><td class="memItemLeft" align="right" valign="top"><a id="gae299959d3e5843b350af472f6d8ad43d"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#gae299959d3e5843b350af472f6d8ad43d">MXC_F_RPU_SYSRAM5_SDMAIACNR</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMAIACNR_POS))</td></tr>
<tr class="memdesc:gae299959d3e5843b350af472f6d8ad43d"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMAIACNR Mask. <br /></td></tr>
<tr class="separator:gae299959d3e5843b350af472f6d8ad43d"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga5bd555606e95c6c406948b7fdbc5882c"><td class="memItemLeft" align="right" valign="top"><a id="ga5bd555606e95c6c406948b7fdbc5882c"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga5bd555606e95c6c406948b7fdbc5882c">MXC_F_RPU_SYSRAM5_SDMAIACNW_POS</a>   13</td></tr>
<tr class="memdesc:ga5bd555606e95c6c406948b7fdbc5882c"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMAIACNW Position. <br /></td></tr>
<tr class="separator:ga5bd555606e95c6c406948b7fdbc5882c"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga0c30813013f0926b583f7b1bf45c15b3"><td class="memItemLeft" align="right" valign="top"><a id="ga0c30813013f0926b583f7b1bf45c15b3"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga0c30813013f0926b583f7b1bf45c15b3">MXC_F_RPU_SYSRAM5_SDMAIACNW</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDMAIACNW_POS))</td></tr>
<tr class="memdesc:ga0c30813013f0926b583f7b1bf45c15b3"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDMAIACNW Mask. <br /></td></tr>
<tr class="separator:ga0c30813013f0926b583f7b1bf45c15b3"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gae1a85fa07526cf275187fbf2f02a9b90"><td class="memItemLeft" align="right" valign="top"><a id="gae1a85fa07526cf275187fbf2f02a9b90"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#gae1a85fa07526cf275187fbf2f02a9b90">MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS</a>   14</td></tr>
<tr class="memdesc:gae1a85fa07526cf275187fbf2f02a9b90"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_CRYPTOACNR Position. <br /></td></tr>
<tr class="separator:gae1a85fa07526cf275187fbf2f02a9b90"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga506b5598208b5c636daa6e45942cf45e"><td class="memItemLeft" align="right" valign="top"><a id="ga506b5598208b5c636daa6e45942cf45e"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga506b5598208b5c636daa6e45942cf45e">MXC_F_RPU_SYSRAM5_CRYPTOACNR</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_CRYPTOACNR_POS))</td></tr>
<tr class="memdesc:ga506b5598208b5c636daa6e45942cf45e"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_CRYPTOACNR Mask. <br /></td></tr>
<tr class="separator:ga506b5598208b5c636daa6e45942cf45e"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gadd9e22a170d6cc90d1bb9474e6e30eb2"><td class="memItemLeft" align="right" valign="top"><a id="gadd9e22a170d6cc90d1bb9474e6e30eb2"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#gadd9e22a170d6cc90d1bb9474e6e30eb2">MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS</a>   15</td></tr>
<tr class="memdesc:gadd9e22a170d6cc90d1bb9474e6e30eb2"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_CRYPTOACNW Position. <br /></td></tr>
<tr class="separator:gadd9e22a170d6cc90d1bb9474e6e30eb2"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga4bb7f541ff406f68f2b29a18908ac839"><td class="memItemLeft" align="right" valign="top"><a id="ga4bb7f541ff406f68f2b29a18908ac839"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga4bb7f541ff406f68f2b29a18908ac839">MXC_F_RPU_SYSRAM5_CRYPTOACNW</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_CRYPTOACNW_POS))</td></tr>
<tr class="memdesc:ga4bb7f541ff406f68f2b29a18908ac839"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_CRYPTOACNW Mask. <br /></td></tr>
<tr class="separator:ga4bb7f541ff406f68f2b29a18908ac839"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac75cab82fdb6371b9451b8c2acd322c0"><td class="memItemLeft" align="right" valign="top"><a id="gac75cab82fdb6371b9451b8c2acd322c0"></a>#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#gac75cab82fdb6371b9451b8c2acd322c0">MXC_F_RPU_SYSRAM5_SDIOACNR_POS</a>   16</td></tr>
<tr class="memdesc:gac75cab82fdb6371b9451b8c2acd322c0"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDIOACNR Position. <br /></td></tr>
<tr class="separator:gac75cab82fdb6371b9451b8c2acd322c0"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:gac9e364df61edc6e0f379210fef654ee7"><td class="memItemLeft" align="right" valign="top"><a id="gac9e364df61edc6e0f379210fef654ee7"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#gac9e364df61edc6e0f379210fef654ee7">MXC_F_RPU_SYSRAM5_SDIOACNR</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDIOACNR_POS))</td></tr>
<tr class="memdesc:gac9e364df61edc6e0f379210fef654ee7"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDIOACNR Mask. <br /></td></tr>
<tr class="separator:gac9e364df61edc6e0f379210fef654ee7"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga32436212e12a5c55e6785c230d3684ed"><td class="memItemLeft" align="right" valign="top"><a id="ga32436212e12a5c55e6785c230d3684ed"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga32436212e12a5c55e6785c230d3684ed">MXC_F_RPU_SYSRAM5_SDIOACNW_POS</a>   17</td></tr>
<tr class="memdesc:ga32436212e12a5c55e6785c230d3684ed"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDIOACNW Position. <br /></td></tr>
<tr class="separator:ga32436212e12a5c55e6785c230d3684ed"><td class="memSeparator" colspan="2"> </td></tr>
<tr class="memitem:ga794bd6a83099d39aee394a5cfeaa279d"><td class="memItemLeft" align="right" valign="top"><a id="ga794bd6a83099d39aee394a5cfeaa279d"></a>
#define </td><td class="memItemRight" valign="bottom"><a class="el" href="group__RPU__SYSRAM5.html#ga794bd6a83099d39aee394a5cfeaa279d">MXC_F_RPU_SYSRAM5_SDIOACNW</a>   ((uint32_t)(0x1UL << MXC_F_RPU_SYSRAM5_SDIOACNW_POS))</td></tr>
<tr class="memdesc:ga794bd6a83099d39aee394a5cfeaa279d"><td class="mdescLeft"> </td><td class="mdescRight">SYSRAM5_SDIOACNW Mask. <br /></td></tr>
<tr class="separator:ga794bd6a83099d39aee394a5cfeaa279d"><td class="memSeparator" colspan="2"> </td></tr>
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