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badge fixer
non-destructive text micropython
Commits
4096fa39
Commit
4096fa39
authored
Jul 16, 2019
by
Damien George
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stm32/powerctrlboot: Increase SYSCLK to 32MHz for L0 MCUs.
parent
4c1ad1f6
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ports/stm32/powerctrlboot.c
+12
-2
12 additions, 2 deletions
ports/stm32/powerctrlboot.c
with
12 additions
and
2 deletions
ports/stm32/powerctrlboot.c
+
12
−
2
View file @
4096fa39
...
@@ -82,11 +82,21 @@ void SystemClock_Config(void) {
...
@@ -82,11 +82,21 @@ void SystemClock_Config(void) {
// Enable power control peripheral
// Enable power control peripheral
__HAL_RCC_PWR_CLK_ENABLE
();
__HAL_RCC_PWR_CLK_ENABLE
();
// Use the 16MHz internal oscillator
// Set flash latency to 1 because SYSCLK > 16MHz
FLASH
->
ACR
|=
FLASH_ACR_LATENCY
;
// Enable the 16MHz internal oscillator
RCC
->
CR
|=
RCC_CR_HSION
;
RCC
->
CR
|=
RCC_CR_HSION
;
while
(
!
(
RCC
->
CR
&
RCC_CR_HSIRDY
))
{
while
(
!
(
RCC
->
CR
&
RCC_CR_HSIRDY
))
{
}
}
const
uint32_t
sysclk_src
=
1
;
// Use HSI16 and the PLL to get a 32MHz SYSCLK
RCC
->
CFGR
=
1
<<
RCC_CFGR_PLLDIV_Pos
|
1
<<
RCC_CFGR_PLLMUL_Pos
;
RCC
->
CR
|=
RCC_CR_PLLON
;
while
(
!
(
RCC
->
CR
&
RCC_CR_PLLRDY
))
{
// Wait for PLL to lock
}
const
uint32_t
sysclk_src
=
3
;
// Select SYSCLK source
// Select SYSCLK source
RCC
->
CFGR
|=
sysclk_src
<<
RCC_CFGR_SW_Pos
;
RCC
->
CFGR
|=
sysclk_src
<<
RCC_CFGR_SW_Pos
;
...
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