Without the compiler enabled the mp_optimise_value is unused, and the
micropython.opt_level() function is not useful, so exclude these from the
build to save RAM and code size.

So that these tests test the runtime behaviour, not the compiler (which may
be executed offline).

The case of a return statement in the try suite of a try-except statement
was previously only tested by builtin_compile.py, and only then in the part
of this test which checked for the existence of the compile builtin.  So
this patch adds an explicit unit test for this case.

When pystack is enabled mp_obj_fun_bc_prepare_codestate() will always
return a valid pointer, and if there is no more pystack available then it
will raise an exception (a RuntimeError).  So having pystack enabled with
stackless enabled automatically gives strict stackless mode.  There is
therefore no need to have code for strict stackless mode when pystack is
enabled, and this patch optimises the VM for such a case.

Neither the ip nor sp variables are used again after the execution of the
RAISE_VARARGS opcode, so they don't need to be updated.

Some code in mp_iternext() was only tested by the native emitter, so the
tests added here test this function using just the bytecode emitter.

The VM expects that, if mp_resume() returns MP_VM_RETURN_EXCEPTION, then
the returned value is an exception instance (eg to add a traceback to it).
It's possible that a value passed to a generator's throw() is not an
exception so must be explicitly checked for if the thrown value is not
intercepted by the generator.

Thanks to @jepler for finding the bug.

Prior to this patch the code would crash if a key in a ** dict was anything
other than a str or qstr.  This is because mp_setup_code_state() assumes
that keys in kwargs are qstrs (for efficiency).

Thanks to @jepler for finding the bug.

Instead of using a dedicated variable in RAM it's simpler to use the
relevant bits in the DWT register.

If the board is configured to use a bootloader then that bootloader will
pass through the reset_mode.

The main() function has a predefined type in C which is not so useful for
embedded contexts.  This patch renames main() to stm32_main() so we can
define our own type signature for this function.  The type signature is
defined to have a single argument which is the "reset_mode" and is passed
through as r0 from Reset_Handler.  This allows, for example, a bootloader
to pass through information into the main application.

The Reset_Handler needs to copy the data section and zero the BSS, and
these operations should be as optimised as possible to reduce start up
time.  The versions provided in this patch are about 2x faster (on a Cortex
M4) than the previous implementations.

Rather than pin objects themselves.  The actual object is now pin_X_obj and
defines are provided so that pin_X is &pin_X_obj.  This makes it so that
code that uses pin objects doesn't need to know if they are literals or
objects (that need pointers taken) or something else.  They are just
entities that can be passed to the map_hal_pin_xxx functions.  This mirrors
how the core handles constant objects (eg mp_const_none which is
&mp_const_none_obj) and allows for the possibility of different
implementations of the pin layer.

For example, prior to this patch there was the following:

    extern const pin_obj_t pin_A0;
    #define pyb_pin_X1 pin_A0
    ...
    mp_hal_pin_high(&pin_A0);

and now there is:

    extern const pin_obj_t pin_A0_obj;
    #define pin_A0 (&pin_A0_obj)
    #define pyb_pin_X1 pin_A0
    ...
    mp_hal_pin_high(pin_A0);

This patch should have minimal effect on board configuration files.  The
only change that may be needed is if a board has .c files that configure
pins.

The H7 SD peripheral has direct connection to MDMA instead.

The relevant common.ld file should now be included explicitly by a
particular board.

This allows F767 MCUs to support a bootloader in the first sector.

This patch forces a board to explicitly define TEXT1_ADDR in order to
split the firmware into two separate pieces.  Otherwise the default is now
to produce only a single continuous firmware image with all ISR, text and
data together.

To make it clearer that these addresses are both for firmware text and that
they have a prescribed ordering.

This patch allows a particular board to independently specify the linker
scripts for 1) the MCU memory layout; 2) how the different firmware
sections are arranged in memory.  Right now all boards follow the same
layout with two separate firmware section, one for the ISR and one for the
text and data.  This leaves room for storage (filesystem data) to live
between the firmware sections.

The idea with this patch is to accommodate boards that don't have internal
flash storage and only need to have one continuous firmware section.  Thus
the common.ld script is renamed to common_ifs.ld to make explicit that it
is used for cases where the board has internal flash storage.

Explicitly writing out the implementation of sys_tick_has_passed makes
these bdev files independent of systick.c and more reusable as a general
component.  It also reduces the code size slightly.

The irq.h header is added to spibdev.c because it uses declarations in that
file (irq.h is usually included implicitly via mphalport.h but not always).

Taking the address assumes that the pin is an object (eg a struct), but it
could be a literal (eg an int).  Not taking the address makes this driver
more general for other uses.

genhdr/pins.h is an internal header file that defines all of the pin
objects and it's cleaner to have pin.h include it (where the struct's for
these objects are defined) rather than an explicit include by every user.

The HAL requires strict aliasing optimisation to be turned on to function
correctly (at least for the SD card driver on F4 MCUs).  This optimisation
was recently disabled with the addition of H7 support due to the H7 HAL
having errors with the strict aliasing optimisation enabled.  But this is
now fixed in the latest stm32lib and so the optimisation can now be
re-enabled.

Thanks to @chuckbook for finding that there was a problem with the SD card
on F4 MCUs with the strict aliasing optimisation disabled.

There's no uSD Transceiver on this NUCLEO board.

Found the timing for full (400 KHz) and FM+ (1MHz) in the HAL examples, and
used CubeMX to calculate the standard value (100KHz).

This API matches (as close as possible) how other pyb classes allow inplace
operations, such as pyb.SPI.recv(buf).