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20 authors
  1. Oct 07, 2009
  3. Oct 06, 2009
  5. Oct 05, 2009
    • dbrownell's avatar
      Improve jtag_validate_ircapture() diagnostics. · 7a57c316
      dbrownell authored 
      Bugfix the error message so it shows the disliked value, and add
a debug message showing each TAP's IR capture value, all N bits.

This just changes diagnostics ... it still ignores the parameters
given to us at TAP declaration time.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2801 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      7a57c316
    • dbrownell's avatar
      Add a new JTAG "setup" event; use for better DaVinci ICEpick support. · 7c7467b3
      dbrownell authored 
      The model is that this fires after scanchain verification, when it's
safe to call "jtag tapenable $TAPNAME".  So it will fire as part of
non-error paths of "init" and "reset" command processing.  However it
will *NOT* trigger during "jtag_reset" processing, which skips all
scan chain verification, or after verification errors.

ALSO:
 - switch DaVinci chips to use this new mechanism
 - log TAP activation/deactivation, since their IDCODEs aren't verified
 - unify "enum jtag_event" scripted event notifications
 - remove duplicative JTAG_TAP_EVENT_POST_RESET


git-svn-id: svn://svn.berlios.de/openocd/trunk@2800 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      7c7467b3
    • dbrownell's avatar
      Minor cleanup to ARM926 debug entry: · 16a7ad57
      dbrownell authored 
       - don't needlessly export this function
 - handle "case 0" debug method-of-entry better (silent by default)

The "case 0" is a valid debug entry mode so it doesn't deserve the
warning int now gets.  But it probably means that OpenOCD confused
itself somehow; or that it confused the ARM9EJS target.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2799 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      16a7ad57
  7. Oct 02, 2009
  9. Oct 01, 2009
  11. Sep 30, 2009
  13. Sep 29, 2009
  15. Sep 28, 2009
  17. Sep 27, 2009
    • dbrownell's avatar
      Update FT2232 driver so that it reliably enters TAP_RESET. · 817ea3f4
      dbrownell authored 
      When the OpenOCD server starts up it records its state as TAP_RESET,
even though it could be anything.  Then when it starts to examine
the scan chain, it calls jtag_add_tlr() which sees it doesn't have
any work to do, and so it does nothing.  This can make the next
operations fail because they start from the wrong TAP state...

Instead of caring about the current recorded state, always enter
TAP_RESET by forcing five clocks with TMS high.

(NOTE:  it seems most other JTAG adapter drivers have this same bug.)


git-svn-id: svn://svn.berlios.de/openocd/trunk@2763 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      817ea3f4
  19. Sep 26, 2009
  21. Sep 25, 2009
  23. Sep 24, 2009
  25. Sep 23, 2009
    • dbrownell's avatar
      Start handling the (second) SRST stage of reset better: · 23e22b6e
      dbrownell authored 
      make sure that when there are two or more targets, their
various pre/post event reports are correctly ordered.

Previously, only the first target always saw its "pre"
method before SRST was asserted or deasserted.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2753 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      23e22b6e
    • dbrownell's avatar
      When setting up an ETM, cache its ETM_CONFIG register. Then · 22045fa6
      dbrownell authored 
      only expose the registers which are actually present.  They
could be missing for two basic reasons:

 - This version might not support them at all; e.g. ETMv1.1
   doesn't have some control/status registers.  (My sample of
   ARM9 boards shows all with ETMv1.3 support, FWIW.)

 - The configuration on this chip may not populate as many
   registers as possible; e.g. only two data value comparators
   instead of eight.

Includes a bugfix in the "etm info" command:  only one of the
two registers is missing on older silicon, so show the first
one before bailing.

Update ETM usage docs to explain that those registers need to be
written to configure what is traced, and that some ETM configs
are not yet handled.  Also, give some examples of the kinds of
constrained trace which could be arranged.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2752 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      22045fa6
    • dbrownell's avatar
      Start cleaning up ETM register handling. On one ARM926 ETM+ETB · d9ce8a2f
      dbrownell authored 
      system, removes 20 non-existent registers ... but still includes
over 45 (!) ETM registers which don't even exist there ...

 - Integrate the various tables to get one struct per register
 - Get rid of needless per-register dynamic allocation
 - Double check list of registers:
    * Remove sixteen (!) non-registers for data comparators
    * Remove four registers that imply newer ETM than we support
    * Change some names to match current architecture specs
 - Handle more register info
    * some are write-only
    * some are read-only
    * record which versions have them, just in case
 - Reorganize the registers to facilitate removing the extras
    * group e.g. comparator/counter #N registers together
    * add and use lookup-by-ID


git-svn-id: svn://svn.berlios.de/openocd/trunk@2751 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      d9ce8a2f
    • dbrownell's avatar
      Initial ETM cleanups. Most of these are cosmetic: · a6d858eb
      dbrownell authored 
       - Add a header comment
 - Line up the ETM context struct, pack it a bit
 - Remove unused context_id (this doesn't support ETMv2 yet)
 - Make most functions static
 - Remove unused string table and other needless lines of code
 - Correct "tracemode" helptext

Also provide and use an etm_reg_lookup() to find entries in the ETM
register cache.  This will help cope with corrected contents of that
cache, which doesn't include entires for non-existent registers.


git-svn-id: svn://svn.berlios.de/openocd/trunk@2750 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      a6d858eb
    • oharboe's avatar
      Nico Coesel <ncoesel@dealogic.nl> fix warnings. . I'm wondering why these · 7393fcfc
      oharboe authored 
      didn't turn up earlier. Is everyone still using gcc 3.x? Or is the x86
version of gcc 4.x much more relaxed?

git-svn-id: svn://svn.berlios.de/openocd/trunk@2749 b42882b7-edfa-0310-969c-e2dbd0fdcd60
      7393fcfc