Optionally shave time off the armv4_5 run_algorithm() code:  let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.

Enable this by using BKPT to terminate execution instead of "branch
to here" loops.  Then pass zero as the exit address, except when
running on an ARMv4 core.  ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.

Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps.  Some other algorithms
could use this too (mostly flavors of flash operation).

git-svn-id: svn://svn.berlios.de/openocd/trunk@2680 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Fix docs on ARM11 MCR and MRC coprocessor commands:
correct read-vs-write; and describe the params.

(ARM920 and ARM926 have cp15-specific commands; this
approach is more generic.  MCR2, MRC2, MCRR, MCRR2,
MRRC, and MRRC2 instructions could also get exposed.)

git-svn-id: svn://svn.berlios.de/openocd/trunk@2679 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2677 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Provide an "armv7a disassemble" command.  Current omissions include
VFP (except as coprocessor instructions), Neon, and various Thumb2
opcodes that are not available in ARMv7-M processors.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2676 b42882b7-edfa-0310-969c-e2dbd0fdcd60

lean up some loose ends with the ARM disassembler

 - Add a header comment describing its current state and uses
   and referencing the now-generally-available V7 arch spec

 - Support some mode switch instructions:
    * Thumb to Jazelle (BXJ)
    * Thumb to ThumbEE (ENTERX)
    * ThumbEE to Thumb (LEAVEX)

 - Improve that recent warning fix (and associated whitespace goof)

 - Declare the rest of the internal code and data "static".  A
   compiler may use this, and it helps clarify the scope of these
   routines (e.g. what changes to them could affect).


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Mahr, Stefan <Stefan.Mahr@sphairon.com> removes the endianness swapping in mips_m4k.c Swapping is already done in target.c

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2671 b42882b7-edfa-0310-969c-e2dbd0fdcd60

 

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2669 b42882b7-edfa-0310-969c-e2dbd0fdcd60

By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2668 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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Abstract the orion_nand_fast_block_write() routine into a separate
routine -- arm_nandwrite() -- so that other ARM cores can reuse it.

Have davinci_nand do so.  This faster than byte-at-a-time ops by a
factor of three (!), even given the slowish interactions to support
hardware ECC (1-bit flavor in that test) each 512 bytes; those could
be read more efficiently by on-chip code.

NOTE that until there's a generic "ARM algorithm" structure, this
can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8)
cores, though the downloaded code itself would work just fine there.

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2656 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Via code review by Steve Grubb <sgrubb@redhat.com> 

Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2655 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be 'production_test' instead of 'production' here.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2654 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2653 b42882b7-edfa-0310-969c-e2dbd0fdcd60

Via code review by Steve Grubb <sgrubb@redhat.com> 

Also minor fixes for the message from "fill":  the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written

git-svn-id: svn://svn.berlios.de/openocd/trunk@2652 b42882b7-edfa-0310-969c-e2dbd0fdcd60

 - Itemize the list of private customization examples
  for openocd.cfg

 - Add "override defaults" as a customization, specifically
  for the work area (back it up or relocate it)

 - Highlight some work area location issues

git-svn-id: svn://svn.berlios.de/openocd/trunk@2651 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2650 b42882b7-edfa-0310-969c-e2dbd0fdcd60

David Brownell <david-b@pacbell.net> Be sure the built-in search paths always go *after* ones provided
on the command line ... matching comment in add_default_dirs().

Without this it's impossible to use a private config file which
happens to have the same name as an installed one.  Say, because
you're bugfixing a private copy...

git-svn-id: svn://svn.berlios.de/openocd/trunk@2649 b42882b7-edfa-0310-969c-e2dbd0fdcd60

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git-svn-id: svn://svn.berlios.de/openocd/trunk@2647 b42882b7-edfa-0310-969c-e2dbd0fdcd60

git-svn-id: svn://svn.berlios.de/openocd/trunk@2646 b42882b7-edfa-0310-969c-e2dbd0fdcd60

defining ntrst_delay is pointless; don't.

At least the LM3S3748 eval board doesn't need nsrst_delay
either; remove that too.

git-svn-id: svn://svn.berlios.de/openocd/trunk@2645 b42882b7-edfa-0310-969c-e2dbd0fdcd60

David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

 - ARMv5J "BXJ" (for Java/Jazelle)
 - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested.  This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

git-svn-id: svn://svn.berlios.de/openocd/trunk@2644 b42882b7-edfa-0310-969c-e2dbd0fdcd60

arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. 

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