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By enabling this bit, the processor halts when a debug event
such as breakpoint occurs.

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Abstract the orion_nand_fast_block_write() routine into a separate
routine -- arm_nandwrite() -- so that other ARM cores can reuse it.

Have davinci_nand do so.  This faster than byte-at-a-time ops by a
factor of three (!), even given the slowish interactions to support
hardware ECC (1-bit flavor in that test) each 512 bytes; those could
be read more efficiently by on-chip code.

NOTE that until there's a generic "ARM algorithm" structure, this
can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8)
cores, though the downloaded code itself would work just fine there.

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Via code review by Steve Grubb <sgrubb@redhat.com> 

Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.

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Dirk Behme <dirk.behme@googlemail.com> Fix typo in help text. It has to be 'production_test' instead of 'production' here.

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Via code review by Steve Grubb <sgrubb@redhat.com> 

Also minor fixes for the message from "fill":  the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written

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 - Itemize the list of private customization examples
  for openocd.cfg

 - Add "override defaults" as a customization, specifically
  for the work area (back it up or relocate it)

 - Highlight some work area location issues

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David Brownell <david-b@pacbell.net> Be sure the built-in search paths always go *after* ones provided
on the command line ... matching comment in add_default_dirs().

Without this it's impossible to use a private config file which
happens to have the same name as an installed one.  Say, because
you're bugfixing a private copy...

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defining ntrst_delay is pointless; don't.

At least the LM3S3748 eval board doesn't need nsrst_delay
either; remove that too.

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David Brownell <david-b@pacbell.net> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

 - ARMv5J "BXJ" (for Java/Jazelle)
 - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested.  This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

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arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. 

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Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org>  cortex-a8: Wait for the CPU to be halted/started

With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.

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Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org>  Print the value that the method didn't like

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Matt Hsu <matt@0xlab.org> and Holger Hans Peter Freyther <zecke@selfish.org> Only dap_ap_select when we are going to do a memory access
in the fast reg case.

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the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

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Matt Hsu <matt@0xlab.org> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function.

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